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add lwl lwr swl swr test cases

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This commit is contained in:
Paul Pan 2021-08-29 20:17:42 +08:00
parent cf9d3e8ed0
commit eea7b6bbda
8 changed files with 243 additions and 16 deletions
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19
resources/2021/soc_axi_func/testbench/tb2.sv
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@ -4,6 +4,7 @@
`define TRACE_REF_FILE "../../../../../../../cpu132_gettrace/golden_trace.txt"
`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
//`define CONFREG_OPEN_TRACE 1'b0
`define CONFREG_NUM_MONITOR soc_lite.u_confreg.num_monitor
`define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid
`define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data
@ -84,11 +85,11 @@ module tb2_top ();
assign debug_wb_rf_wen = soc_lite.debug_wb_rf_wen;
assign debug_wb_rf_wnum = soc_lite.debug_wb_rf_wnum;
assign debug_wb_rf_wdata = soc_lite.debug_wb_rf_wdata;
assign debug_wb1_pc = soc_lite.debug_wb1_pc;
assign debug_wb1_rf_wen = soc_lite.debug_wb1_rf_wen;
assign debug_wb1_rf_wnum = soc_lite.debug_wb1_rf_wnum;
assign debug_wb1_rf_wdata = soc_lite.debug_wb1_rf_wdata;
assign debug_wb_pc_A = soc_lite.debug_wb_pc_A;
assign debug_wb1_pc = soc_lite.u_cpu.debug_wb1_pc;
assign debug_wb1_rf_wen = soc_lite.u_cpu.debug_wb1_rf_wen;
assign debug_wb1_rf_wnum = soc_lite.u_cpu.debug_wb1_rf_wnum;
assign debug_wb1_rf_wdata = soc_lite.u_cpu.debug_wb1_rf_wdata;
assign debug_wb_pc_A = soc_lite.u_cpu.debug_wb_pc_A;
// open the trace file;
integer trace_ref;
@ -145,7 +146,7 @@ module tb2_top ();
#2;
if (!resetn) begin
debug_wb_err <= 1'b0;
end else if (!debug_end && `CONFREG_OPEN_TRACE) begin
end else if (!debug_end) begin
if (debug_wb_pc_A) begin
dbg_0_rf_wen <= debug_wb1_rf_wen;
dbg_0_pc <= debug_wb1_pc;
@ -177,7 +178,7 @@ module tb2_top ();
dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
end
if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0) begin
if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
if ( (dbg_0_pc !== ref_trace[0].ref_wb_pc )
|| (dbg_0_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|| (dbg_0_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
@ -198,7 +199,7 @@ module tb2_top ();
$finish;
end else ref_trace.pop_front();
end
if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0) begin
if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0 && `CONFREG_OPEN_TRACE) begin
if ( (dbg_1_pc !== ref_trace[0].ref_wb_pc )
|| (dbg_1_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|| (dbg_1_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
@ -266,7 +267,7 @@ module tb2_top ();
end
end
//妯℃嫙涓插彛鎵撳嵃
// Uart Display
logic uart_display;
logic [7:0] uart_data;
assign uart_display = `CONFREG_UART_DISPLAY;

46
resources/2021/soft/func/inst/inst_test.h
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@ -1290,3 +1290,49 @@
mtc0 v1, c0_cause; \
1: b 1b; \
nop
/*90*/
#define TEST_LWL(data, base_addr, offset, offset_align, ref, confuse) \
LI(t1, data); \
LI(t0, base_addr); \
LI(v1, ref); \
LI(v0, confuse); \
sw t1, offset_align(t0); \
lwl v0, offset(t0); \
bne v0, v1, inst_error; \
nop
/*91*/
#define TEST_LWR(data, base_addr, offset, offset_align, ref, confuse) \
LI(t1, data); \
LI(t0, base_addr); \
LI(v1, ref); \
LI(v0, confuse); \
sw t1, offset_align(t0); \
lwr v0, offset(t0); \
bne v0, v1, inst_error; \
nop
/*92*/
#define TEST_SWL(data, base_addr, offset, offset_align, ref, confuse) \
LI(t1, data); \
LI(t0, base_addr); \
LI(v0, confuse); \
LI(v1, ref); \
sw v0, offset_align(t0); \
swl t1, offset(t0); \
lw v0, offset_align(t0); \
bne v0, v1, inst_error; \
nop
/*93*/
#define TEST_SWR(data, base_addr, offset, offset_align, ref, confuse) \
LI(t1, data); \
LI(t0, base_addr); \
LI(v0, confuse); \
LI(v1, ref); \
sw v0, offset_align(t0); \
swr t1, offset(t0); \
lw v0, offset_align(t0); \
bne v0, v1, inst_error; \
nop

41
resources/2021/soft/func/inst/n90_lwl.S Normal file
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@ -0,0 +1,41 @@
#include <asm.h>
#include <regdef.h>
#include <inst_test.h>
LEAF(n90_lwl_test)
.set noreorder
addiu s0, s0 ,1
li s2, 0x0
###test inst
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xE8B6C7D8, 0xA5B6C7D8)
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xC7E8C7D8, 0xA5B6C7D8)
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0x22C7E8D8, 0xA5B6C7D8)
TEST_LWL(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xC822C7E8, 0xA5B6C7D8)
TEST_LWL(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x10B6C7D8, 0xA5B6C7D8)
TEST_LWL(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0x7C10C7D8, 0xA5B6C7D8)
TEST_LWL(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0x737C10D8, 0xA5B6C7D8)
TEST_LWL(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x71737C10, 0xA5B6C7D8)
TEST_LWL(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x20B6C7D8, 0xA5B6C7D8)
TEST_LWL(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0x2420C7D8, 0xA5B6C7D8)
TEST_LWL(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0x682420D8, 0xA5B6C7D8)
TEST_LWL(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x03682420, 0xA5B6C7D8)
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0xd3B6C7D8, 0xA5B6C7D8)
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xf5d3C7D8, 0xA5B6C7D8)
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0x59f5d3D8, 0xA5B6C7D8)
TEST_LWL(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n90_lwl_test)

41
resources/2021/soft/func/inst/n91_lwr.S Normal file
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@ -0,0 +1,41 @@
#include <asm.h>
#include <regdef.h>
#include <inst_test.h>
LEAF(n91_lwr_test)
.set noreorder
addiu s0, s0 ,1
li s2, 0x0
###test inst
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xA5c822c7, 0xA5B6C7D8)
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xA5B6c822, 0xA5B6C7D8)
TEST_LWR(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xA5B6C7c8, 0xA5B6C7D8)
TEST_LWR(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
TEST_LWR(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0xA571737c, 0xA5B6C7D8)
TEST_LWR(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0xA5B67173, 0xA5B6C7D8)
TEST_LWR(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0xA5B6C771, 0xA5B6C7D8)
TEST_LWR(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x03682420, 0xA5B6C7D8)
TEST_LWR(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0xA5036824, 0xA5B6C7D8)
TEST_LWR(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0xA5B60368, 0xA5B6C7D8)
TEST_LWR(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0xA5B6C703, 0xA5B6C7D8)
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xA56f59f5, 0xA5B6C7D8)
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xA5B66f59, 0xA5B6C7D8)
TEST_LWR(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0xA5B6C76f, 0xA5B6C7D8)
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n91_lwr_test)

41
resources/2021/soft/func/inst/n92_swl.S Normal file
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@ -0,0 +1,41 @@
#include <asm.h>
#include <regdef.h>
#include <inst_test.h>
LEAF(n92_swl_test)
.set noreorder
addiu s0, s0 ,1
li s2, 0x0
###test inst
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xA5B6C7c8, 0xA5B6C7D8)
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0xA5B6c822, 0xA5B6C7D8)
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xA5c822c7, 0xA5B6C7D8)
TEST_SWL(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
TEST_SWL(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0xA5B6C771, 0xA5B6C7D8)
TEST_SWL(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0xA5B67173, 0xA5B6C7D8)
TEST_SWL(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0xA571737c, 0xA5B6C7D8)
TEST_SWL(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
TEST_SWL(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0xA5B6C703, 0xA5B6C7D8)
TEST_SWL(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0xA5B60368, 0xA5B6C7D8)
TEST_SWL(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0xA5036824, 0xA5B6C7D8)
TEST_SWL(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x03682420, 0xA5B6C7D8)
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0xA5B6C76f, 0xA5B6C7D8)
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0xA5B66f59, 0xA5B6C7D8)
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xA56f59f5, 0xA5B6C7D8)
TEST_SWL(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n92_swl_test)

41
resources/2021/soft/func/inst/n93_swr.S Normal file
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@ -0,0 +1,41 @@
#include <asm.h>
#include <regdef.h>
#include <inst_test.h>
LEAF(n93_swr_test)
.set noreorder
addiu s0, s0 ,1
li s2, 0x0
###test inst
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066a8, 0x000066a8, 0xc822c7e8, 0xA5B6C7D8)
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066a9, 0x000066a8, 0x22c7e8D8, 0xA5B6C7D8)
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066aA, 0x000066a8, 0xc7e8C7D8, 0xA5B6C7D8)
TEST_SWR(0xc822c7e8, 0x800d34c0, 0x000066aB, 0x000066a8, 0xe8B6C7D8, 0xA5B6C7D8)
TEST_SWR(0x71737c10, 0x800df660, 0x000002e4, 0x000002e4, 0x71737c10, 0xA5B6C7D8)
TEST_SWR(0x71737c10, 0x800df660, 0x000002e5, 0x000002e4, 0x737c10D8, 0xA5B6C7D8)
TEST_SWR(0x71737c10, 0x800df660, 0x000002e6, 0x000002e4, 0x7c10C7D8, 0xA5B6C7D8)
TEST_SWR(0x71737c10, 0x800df660, 0x000002e7, 0x000002e4, 0x10B6C7D8, 0xA5B6C7D8)
TEST_SWR(0x03682420, 0x800d24e4, 0x00001680, 0x00001680, 0x03682420, 0xA5B6C7D8)
TEST_SWR(0x03682420, 0x800d24e4, 0x00001681, 0x00001680, 0x682420D8, 0xA5B6C7D8)
TEST_SWR(0x03682420, 0x800d24e4, 0x00001682, 0x00001680, 0x2420C7D8, 0xA5B6C7D8)
TEST_SWR(0x03682420, 0x800d24e4, 0x00001683, 0x00001680, 0x20B6C7D8, 0xA5B6C7D8)
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b0, 0x000001b0, 0x6f59f5d3, 0xA5B6C7D8)
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b1, 0x000001b0, 0x59f5d3D8, 0xA5B6C7D8)
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b2, 0x000001b0, 0xf5d3C7D8, 0xA5B6C7D8)
TEST_SWR(0x6f59f5d3, 0x800dabdc, 0x000001b3, 0x000001b0, 0xd3B6C7D8, 0xA5B6C7D8)
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n93_swr_test)

18
resources/2021/soft/func/start.S
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@ -2,7 +2,7 @@
#include <regdef.h>
#include <cpu_cde.h>
#define TEST_NUM 89
#define TEST_NUM 93
##s0, number
@ -651,6 +651,22 @@ kseg0_kseg1:
nop
jal wait_1s
nop
jal n90_lwl_test
nop
jal wait_1s
nop
jal n91_lwr_test
nop
jal wait_1s
nop
jal n92_swl_test
nop
jal wait_1s
nop
jal n93_swr_test
nop
jal wait_1s
nop
###check io access
LI (a0, IO_SIMU_ADDR)
LI (t0, 0x1234)

12
tools/mctrl1.txt
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@ -59,9 +59,9 @@
32'b100011?????????????????????????? 0 0 0 0 1 0 ? ALIGN 0 0 // LW
32'b100100?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 // LBU
32'b100101?????????????????????????? 0 0 0 0 1 0 0 ALIGN 0 0 // LHU
32'h100110?????????????????????????? 0 0 0 0 1 0 ? URIGHT 1 0 // LWR
32'b101000?????????????????????????? 0 0 0 0 1 1 ? ALIGN ? ? // SB
32'b101001?????????????????????????? 0 0 0 0 1 1 ? ALIGN ? ? // SH
32'b101010?????????????????????????? 0 0 0 0 1 1 ? ULEFT ? ? // SWL
32'b101011?????????????????????????? 0 0 0 0 1 1 ? ALIGN ? ? // SW
32'b101110?????????????????????????? 0 0 0 0 1 1 ? URIGHT ? ? // SWR
32'h100110?????????????????????????? 0 0 0 0 1 0 ? URIGHT 1 ? // LWR
32'b101000?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 // SB
32'b101001?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 // SH
32'b101010?????????????????????????? 0 0 0 0 1 1 ? ULEFT 0 1 // SWL
32'b101011?????????????????????????? 0 0 0 0 1 1 ? ALIGN 0 0 // SW
32'b101110?????????????????????????? 0 0 0 0 1 1 ? URIGHT 1 ? // SWR