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clarification for '+ alt'

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This commit is contained in:
cxy004 2021-07-05 23:44:27 +08:00
parent 603842fc8a
commit eb5c866925
2 changed files with 2 additions and 2 deletions
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2
src/Core/ALU.sv
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@ -16,7 +16,7 @@ module alu(
wire logic [31:0] sr = sa[1] ? sa[0] ? sr2[34: 3] : sr2[33:2]
: sa[0] ? sr2[32: 1] : sr2[31:0];
wire word_t b2 = alt ? ~b : b;
wire word_t b2 = alt ? ~b : b;
wire word_t sum;
wire logic lt, ltu;

2
src/testbench/alu/makefile
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@ -2,7 +2,7 @@ HOME = ../..
INC = ${HOME}/include
sources += testbench.sv
sources += ${HOME}/src/mips/alu.sv
sources += ${HOME}/Core/ALU.sv
run: test.vcd
open test.vcd