clarification for '+ alt'
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@ -12,16 +12,16 @@ module alu(
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wire logic ex = alt & b[31];
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wire logic [46:0] sr4 = sa[4] ? {{31{ex}}, b[31:16]} : {{15{ex}}, b[31:0]};
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wire logic [34:0] sr2 = sa[3] ? sa[2] ? sr4[46:12] : sr4[42:8]
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: sa[2] ? sr4[38: 4] : sr4[34:0];
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: sa[2] ? sr4[38: 4] : sr4[34:0];
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wire logic [31:0] sr = sa[1] ? sa[0] ? sr2[34: 3] : sr2[33:2]
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: sa[0] ? sr2[32: 1] : sr2[31:0];
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: sa[0] ? sr2[32: 1] : sr2[31:0];
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wire word_t b2 = alt ? ~b : b;
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wire word_t sum;
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wire logic lt, ltu;
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assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + {33'b0,alt};
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assign aluout = aluctrl.f_sl ? b << sa : 32'b0
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assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
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assign aluout = (aluctrl.f_sl ? b << sa : 32'b0)
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| (aluctrl.f_sr ? sr : 32'b0)
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| (aluctrl.f_add ? sum : 32'b0)
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| (aluctrl.f_and ? a & b : 32'b0)
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