clarification for '+ alt'
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@ -16,7 +16,7 @@ module alu(
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wire logic [31:0] sr = sa[1] ? sa[0] ? sr2[34: 3] : sr2[33:2]
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: sa[0] ? sr2[32: 1] : sr2[31:0];
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wire word_t b2 = alt ? ~b : b;
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wire word_t b2 = alt ? ~b : b;
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wire word_t sum;
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wire logic lt, ltu;
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@ -2,7 +2,7 @@ HOME = ../..
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INC = ${HOME}/include
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sources += testbench.sv
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sources += ${HOME}/src/mips/alu.sv
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sources += ${HOME}/Core/ALU.sv
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run: test.vcd
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open test.vcd
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