Configurable Cache & Bigger Cache
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@ -52,7 +52,7 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour
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####################
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.phony: lint verilate func_soft tlb_soft build coverage run clean
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default: func_run
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default: run
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lint:
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$(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top
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31
src/Gadgets/mux9.sv
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31
src/Gadgets/mux9.sv
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@ -0,0 +1,31 @@
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module mux9 #(
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parameter WIDTH = 8
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) (
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input logic [WIDTH-1:0] d0,
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input logic [WIDTH-1:0] d1,
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input logic [WIDTH-1:0] d2,
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input logic [WIDTH-1:0] d3,
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input logic [WIDTH-1:0] d4,
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input logic [WIDTH-1:0] d5,
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input logic [WIDTH-1:0] d6,
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input logic [WIDTH-1:0] d7,
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input logic [WIDTH-1:0] d8,
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input logic [ 3:0] s,
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output logic [WIDTH-1:0] q
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);
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always_comb begin
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case (s)
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4'b0000: q = d0;
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4'b0001: q = d1;
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4'b0010: q = d2;
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4'b0011: q = d3;
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4'b0100: q = d4;
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4'b0101: q = d5;
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4'b0110: q = d6;
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4'b0111: q = d7;
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default: q = d8;
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endcase
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end
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endmodule
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@ -15,7 +15,7 @@ module DCache (
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DCDataRAM_t DataRAM0/*verilator split_var*/, DataRAM1/*verilator split_var*/, DataRAM2/*verilator split_var*/, DataRAM3/*verilator split_var*/;
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(* RAM_STYLE="distributed" *)
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logic [3:0] LRU[128];
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logic [3:0] LRU[`DC_INDEX_DEPTH];
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logic [3:0] nowLRU;
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logic [3:0] nxtLRU;
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@ -89,7 +89,7 @@ module DCache (
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| (victim[1] ? tag[1].tag : {(32-`DC_TAGL){1'b0}})
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| (victim[2] ? tag[2].tag : {(32-`DC_TAGL){1'b0}})
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| (victim[3] ? tag[3].tag : {(32-`DC_TAGL){1'b0}});
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assign port.dirt_addr = {dirt_tag, port.index, 4'b0};
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assign port.dirt_addr = {dirt_tag, port.index, `DC_INDEXL'b0};
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assign port.dirt_row = (victim[0] ? data[0] : {`DC_DATA_LENGTH{1'b0}})
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| (victim[1] ? data[1] : {`DC_DATA_LENGTH{1'b0}})
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| (victim[2] ? data[2] : {`DC_DATA_LENGTH{1'b0}})
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@ -112,7 +112,7 @@ module DCache (
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assign nxtLRU = (setLRU_valid ? nxtsetLRU : 4'b0000)
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| (clrLRU_valid ? nxtclrLRU : 4'b0000);
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for (genvar i = 0; i < 128; i++)
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for (genvar i = 0; i < `DC_INDEX_DEPTH; i++)
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initial LRU[i] = 4'b0;
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always_ff @(posedge clk) begin
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@ -15,7 +15,7 @@ module ICache (
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ICDataRAM_t DataRAM0/*verilator split_var*/, DataRAM1/*verilator split_var*/, DataRAM2/*verilator split_var*/, DataRAM3/*verilator split_var*/;
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(* RAM_STYLE="distributed" *)
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logic [3:0] LRU[64];
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logic [3:0] LRU[`IC_INDEX_DEPTH];
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logic [3:0] nowLRU;
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logic [3:0] nxtLRU;
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@ -81,7 +81,7 @@ module ICache (
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assign nxtLRU = (setLRU_valid ? nxtsetLRU : 4'b0000)
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| (clrLRU_valid ? nxtclrLRU : 4'b0000);
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for (genvar i = 0; i < 64; i++)
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for (genvar i = 0; i < `IC_INDEX_DEPTH; i++)
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initial LRU[i] = 4'b0;
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always_ff @(posedge clk) begin
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26
src/MU/MU.sv
26
src/MU/MU.sv
@ -120,16 +120,9 @@ module MU (
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// ============
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logic if_source_select_direct; // only used when non-cached
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ICData_t if_source_data;
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// TODO: use macro/generator to dynamic mux
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mux5 #(2 * `XLEN) if_rdata_mux(
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if_source_data[ 63: 0],
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if_source_data[127: 64],
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if_source_data[191:128],
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if_source_data[255:192],
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if_source_data[255:192], // uncached
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{if_source_select_direct, stored_instfetch_addr[`IC_INDEXL-1:3]},
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{instfetch.rdata1, instfetch.rdata0}
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);
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assign {instfetch.rdata1, instfetch.rdata0} = if_source_select_direct
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? if_source_data[(`IC_ROW_LENGTH-1)*32+:64]
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: if_source_data[{stored_instfetch_addr[`IC_INDEXL-1:3], 6'b0}+:64];
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// =====================================
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// == InstFetch Control State Machine ==
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@ -368,16 +361,9 @@ module MU (
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logic mem_rdata_select_direct; // only used when non-cached
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DCData_t mem_rdata_source_data;
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// TODO: use macro/generator to dynamic mux
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mux5 #(`XLEN) mem_rdata_mux(
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mem_rdata_source_data[ 31: 0],
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mem_rdata_source_data[ 63: 32],
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mem_rdata_source_data[ 95: 64],
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mem_rdata_source_data[127: 96],
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mem_rdata_source_data[127: 96], // uncached
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{mem_rdata_select_direct, stored_memory_addr[`DC_INDEXL-1:2]},
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memory.rdata
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);
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assign memory.rdata = mem_rdata_select_direct
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? mem_rdata_source_data[`DC_ROW_LENGTH*32+:32]
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: mem_rdata_source_data[{stored_memory_addr[`DC_INDEXL-1:2], 5'b0}+:32];
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logic mem_wstrb_direct;
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DCData_t mem_wdata_source_data, mem_wdata_output;
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@ -4,11 +4,12 @@
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`include "defines.svh"
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// IC for I-Cache
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`define IC_TAGL 11
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`define IC_INDEXL 5
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`define IC_TAGL 12
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`define IC_INDEXL 6
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`define IC_TAG_LENGTH (`XLEN - `IC_IGAL + 1) // Tag + Valid
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`define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 32Bytes
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`define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 64Bytes
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`define IC_ROW_LENGTH (`IC_DATA_LENGTH / `XLEN - 1)
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`define IC_INDEX_DEPTH (2 ** (`IC_TAGL - `IC_INDEXL))
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typedef logic [`IC_DATA_LENGTH-1:0] ICData_t;
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typedef logic [32-`IC_TAGL-1:0] ICTagL_t;
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@ -41,11 +42,12 @@ typedef struct packed {
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// DC for D-Cache
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`define DC_TAGL 11
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`define DC_INDEXL 4
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`define DC_TAGL 12
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`define DC_INDEXL 5
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`define DC_TAG_LENGTH (`XLEN - `DC_TAGL + 1 + 1) // Tag + Valid + Dirty
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`define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 16Bytes
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`define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 8Bytes
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`define DC_ROW_LENGTH (`DC_DATA_LENGTH / `XLEN - 1)
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`define DC_INDEX_DEPTH (2 ** (`DC_TAGL - `DC_INDEXL))
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typedef logic [`DC_DATA_LENGTH-1:0] DCData_t;
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typedef logic [32-`DC_TAGL-1:0] DCTagL_t;
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@ -1,12 +1,12 @@
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`ifndef DEFINES_SVH
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`define DEFINES_SVH
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`define ILA_DEBUG
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// `define ILA_DEBUG
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`define ENABLE_CACHEOP
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`define ENABLE_TLB
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`define ENABLE_CpU
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`define ENABLE_TRAP
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// `define ENABLE_CACHEOP
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// `define ENABLE_TLB
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// `define ENABLE_CpU
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// `define ENABLE_TRAP
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`ifdef SIMULATION_VERILATOR
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`undef ENABLE_CpU
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