From d31446ae87bf14d5e5880f6443a4e88c782e9745 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Thu, 4 Aug 2022 13:00:33 +0800 Subject: [PATCH] Configurable Cache & Bigger Cache --- sim/Makefile | 2 +- src/Gadgets/mux9.sv | 31 +++++++++++++++++++++++++++++++ src/MU/DCache.sv | 6 +++--- src/MU/ICache.sv | 4 ++-- src/MU/MU.sv | 26 ++++++-------------------- src/include/Cache.svh | 14 ++++++++------ src/include/defines.svh | 10 +++++----- 7 files changed, 56 insertions(+), 37 deletions(-) create mode 100644 src/Gadgets/mux9.sv diff --git a/sim/Makefile b/sim/Makefile index a41ce73..6ca0302 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -52,7 +52,7 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour #################### .phony: lint verilate func_soft tlb_soft build coverage run clean -default: func_run +default: run lint: $(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top diff --git a/src/Gadgets/mux9.sv b/src/Gadgets/mux9.sv new file mode 100644 index 0000000..19a1959 --- /dev/null +++ b/src/Gadgets/mux9.sv @@ -0,0 +1,31 @@ +module mux9 #( + parameter WIDTH = 8 +) ( + input logic [WIDTH-1:0] d0, + input logic [WIDTH-1:0] d1, + input logic [WIDTH-1:0] d2, + input logic [WIDTH-1:0] d3, + input logic [WIDTH-1:0] d4, + input logic [WIDTH-1:0] d5, + input logic [WIDTH-1:0] d6, + input logic [WIDTH-1:0] d7, + input logic [WIDTH-1:0] d8, + + input logic [ 3:0] s, + output logic [WIDTH-1:0] q +); + + always_comb begin + case (s) + 4'b0000: q = d0; + 4'b0001: q = d1; + 4'b0010: q = d2; + 4'b0011: q = d3; + 4'b0100: q = d4; + 4'b0101: q = d5; + 4'b0110: q = d6; + 4'b0111: q = d7; + default: q = d8; + endcase + end +endmodule diff --git a/src/MU/DCache.sv b/src/MU/DCache.sv index 590d916..4c9ca43 100644 --- a/src/MU/DCache.sv +++ b/src/MU/DCache.sv @@ -15,7 +15,7 @@ module DCache ( DCDataRAM_t DataRAM0/*verilator split_var*/, DataRAM1/*verilator split_var*/, DataRAM2/*verilator split_var*/, DataRAM3/*verilator split_var*/; (* RAM_STYLE="distributed" *) - logic [3:0] LRU[128]; + logic [3:0] LRU[`DC_INDEX_DEPTH]; logic [3:0] nowLRU; logic [3:0] nxtLRU; @@ -89,7 +89,7 @@ module DCache ( | (victim[1] ? tag[1].tag : {(32-`DC_TAGL){1'b0}}) | (victim[2] ? tag[2].tag : {(32-`DC_TAGL){1'b0}}) | (victim[3] ? tag[3].tag : {(32-`DC_TAGL){1'b0}}); - assign port.dirt_addr = {dirt_tag, port.index, 4'b0}; + assign port.dirt_addr = {dirt_tag, port.index, `DC_INDEXL'b0}; assign port.dirt_row = (victim[0] ? data[0] : {`DC_DATA_LENGTH{1'b0}}) | (victim[1] ? data[1] : {`DC_DATA_LENGTH{1'b0}}) | (victim[2] ? data[2] : {`DC_DATA_LENGTH{1'b0}}) @@ -112,7 +112,7 @@ module DCache ( assign nxtLRU = (setLRU_valid ? nxtsetLRU : 4'b0000) | (clrLRU_valid ? nxtclrLRU : 4'b0000); - for (genvar i = 0; i < 128; i++) + for (genvar i = 0; i < `DC_INDEX_DEPTH; i++) initial LRU[i] = 4'b0; always_ff @(posedge clk) begin diff --git a/src/MU/ICache.sv b/src/MU/ICache.sv index 3aaf94d..39bf51a 100644 --- a/src/MU/ICache.sv +++ b/src/MU/ICache.sv @@ -15,7 +15,7 @@ module ICache ( ICDataRAM_t DataRAM0/*verilator split_var*/, DataRAM1/*verilator split_var*/, DataRAM2/*verilator split_var*/, DataRAM3/*verilator split_var*/; (* RAM_STYLE="distributed" *) - logic [3:0] LRU[64]; + logic [3:0] LRU[`IC_INDEX_DEPTH]; logic [3:0] nowLRU; logic [3:0] nxtLRU; @@ -81,7 +81,7 @@ module ICache ( assign nxtLRU = (setLRU_valid ? nxtsetLRU : 4'b0000) | (clrLRU_valid ? nxtclrLRU : 4'b0000); - for (genvar i = 0; i < 64; i++) + for (genvar i = 0; i < `IC_INDEX_DEPTH; i++) initial LRU[i] = 4'b0; always_ff @(posedge clk) begin diff --git a/src/MU/MU.sv b/src/MU/MU.sv index 6613e3e..7630f7d 100644 --- a/src/MU/MU.sv +++ b/src/MU/MU.sv @@ -120,16 +120,9 @@ module MU ( // ============ logic if_source_select_direct; // only used when non-cached ICData_t if_source_data; - // TODO: use macro/generator to dynamic mux - mux5 #(2 * `XLEN) if_rdata_mux( - if_source_data[ 63: 0], - if_source_data[127: 64], - if_source_data[191:128], - if_source_data[255:192], - if_source_data[255:192], // uncached - {if_source_select_direct, stored_instfetch_addr[`IC_INDEXL-1:3]}, - {instfetch.rdata1, instfetch.rdata0} - ); + assign {instfetch.rdata1, instfetch.rdata0} = if_source_select_direct + ? if_source_data[(`IC_ROW_LENGTH-1)*32+:64] + : if_source_data[{stored_instfetch_addr[`IC_INDEXL-1:3], 6'b0}+:64]; // ===================================== // == InstFetch Control State Machine == @@ -368,16 +361,9 @@ module MU ( logic mem_rdata_select_direct; // only used when non-cached DCData_t mem_rdata_source_data; - // TODO: use macro/generator to dynamic mux - mux5 #(`XLEN) mem_rdata_mux( - mem_rdata_source_data[ 31: 0], - mem_rdata_source_data[ 63: 32], - mem_rdata_source_data[ 95: 64], - mem_rdata_source_data[127: 96], - mem_rdata_source_data[127: 96], // uncached - {mem_rdata_select_direct, stored_memory_addr[`DC_INDEXL-1:2]}, - memory.rdata - ); + assign memory.rdata = mem_rdata_select_direct + ? mem_rdata_source_data[`DC_ROW_LENGTH*32+:32] + : mem_rdata_source_data[{stored_memory_addr[`DC_INDEXL-1:2], 5'b0}+:32]; logic mem_wstrb_direct; DCData_t mem_wdata_source_data, mem_wdata_output; diff --git a/src/include/Cache.svh b/src/include/Cache.svh index b0cc43c..5978bee 100644 --- a/src/include/Cache.svh +++ b/src/include/Cache.svh @@ -4,11 +4,12 @@ `include "defines.svh" // IC for I-Cache -`define IC_TAGL 11 -`define IC_INDEXL 5 +`define IC_TAGL 12 +`define IC_INDEXL 6 `define IC_TAG_LENGTH (`XLEN - `IC_IGAL + 1) // Tag + Valid -`define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 32Bytes +`define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 64Bytes `define IC_ROW_LENGTH (`IC_DATA_LENGTH / `XLEN - 1) +`define IC_INDEX_DEPTH (2 ** (`IC_TAGL - `IC_INDEXL)) typedef logic [`IC_DATA_LENGTH-1:0] ICData_t; typedef logic [32-`IC_TAGL-1:0] ICTagL_t; @@ -41,11 +42,12 @@ typedef struct packed { // DC for D-Cache -`define DC_TAGL 11 -`define DC_INDEXL 4 +`define DC_TAGL 12 +`define DC_INDEXL 5 `define DC_TAG_LENGTH (`XLEN - `DC_TAGL + 1 + 1) // Tag + Valid + Dirty -`define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 16Bytes +`define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 8Bytes `define DC_ROW_LENGTH (`DC_DATA_LENGTH / `XLEN - 1) +`define DC_INDEX_DEPTH (2 ** (`DC_TAGL - `DC_INDEXL)) typedef logic [`DC_DATA_LENGTH-1:0] DCData_t; typedef logic [32-`DC_TAGL-1:0] DCTagL_t; diff --git a/src/include/defines.svh b/src/include/defines.svh index d141cbd..43ff63f 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -1,12 +1,12 @@ `ifndef DEFINES_SVH `define DEFINES_SVH -`define ILA_DEBUG +// `define ILA_DEBUG -`define ENABLE_CACHEOP -`define ENABLE_TLB -`define ENABLE_CpU -`define ENABLE_TRAP +// `define ENABLE_CACHEOP +// `define ENABLE_TLB +// `define ENABLE_CpU +// `define ENABLE_TRAP `ifdef SIMULATION_VERILATOR `undef ENABLE_CpU