NSCSCC/MIPS
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fix bug in SWR

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Paul Pan 2021-08-29 20:16:57 +08:00
parent 6cc760be79
commit cf9d3e8ed0
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GPG Key ID: DA97C6DCB84DEC68
2 changed files with 34 additions and 17 deletions
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26
README.md
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@ -31,9 +31,9 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
| Status | Instruction | Type | Tier | Comment | | Status | Instruction | Type | Tier | Comment |
| :----------------: | :---------: | :------: | :--: | :-------------------------------------- | | :----------------: | :---------: | :------: | :--: | :-------------------------------------- |
| :clock3: | `Cache` | `SYS` | 2 | | | :clock3: | `Cache` | `SYS` | 2 | |
| :clock3: | `PREF` | `SYS` | 1 | Treat as `NOP` | | :hourglass: | `PREF` | `SYS` | 1 | Treat as `NOP` |
| :clock3: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) | | :hourglass: | `SYNC` | `SYS` | 1 | Treat as `NOP` (We're strongly ordered) |
| :clock3: | `WAIT` | `SYS` | 3 | | | :clock3: | `WAIT` | `SYS` | 2 | |
| :clock3: | `TEQ` | `SYS` | 2 | | | :clock3: | `TEQ` | `SYS` | 2 | |
| :clock3: | `TEQI` | `SYS` | 2 | | | :clock3: | `TEQI` | `SYS` | 2 | |
| :clock3: | `TGE` | `SYS` | 2 | | | :clock3: | `TGE` | `SYS` | 2 | |
@ -52,16 +52,16 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
| :clock3: | `MADDU` | `ARITH` | 2 | | | :clock3: | `MADDU` | `ARITH` | 2 | |
| :clock3: | `MSUB` | `ARITH` | 2 | | | :clock3: | `MSUB` | `ARITH` | 2 | |
| :clock3: | `MSUBU` | `ARITH` | 2 | | | :clock3: | `MSUBU` | `ARITH` | 2 | |
| :clock3: | `MOVN` | `ARITH` | 1 | | | :clock3: | `MOVN` | `ARITH` | 2 | |
| :clock3: | `MOVZ` | `ARITH` | 1 | | | :clock3: | `MOVZ` | `ARITH` | 2 | |
| :clock3: | `LL` | `MEM` | 3 | | | :hourglass: | `LL` | `MEM` | 1 | Treat as `LW` |
| :heavy_check_mark: | `LWL` | `MEM` | 1 | 需要补充测试 | | :heavy_check_mark: | `LWL` | `MEM` | 1 | |
| :heavy_check_mark: | `LWR` | `MEM` | 1 | 需要补充测试 | | :heavy_check_mark: | `LWR` | `MEM` | 1 | |
| :clock3: | `SC` | `MEM` | 3 | | | :hourglass: | `SC` | `MEM` | 1 | Treat as `SW` |
| :hourglass: | `SWL` | `MEM` | 1 | | | :heavy_check_mark: | `SWL` | `MEM` | 1 | |
| :hourglass: | `SWR` | `MEM` | 1 | | | :heavy_check_mark: | `SWR` | `MEM` | 1 | |
| :clock3: | `MOVF` | `FP` | 2 | | | :clock3: | `MOVF` | `FP` | 3 | |
| :clock3: | `MOVT` | `FP` | 2 | | | :clock3: | `MOVT` | `FP` | 3 | |
| :clock3: | `BEQL` | `BRANCH` | 3 | | | :clock3: | `BEQL` | `BRANCH` | 3 | |
| :clock3: | `BGEZALL` | `BRANCH` | 3 | | | :clock3: | `BGEZALL` | `BRANCH` | 3 | |
| :clock3: | `BGEZL` | `BRANCH` | 3 | | | :clock3: | `BGEZL` | `BRANCH` | 3 | |

25
src/Core/Gadgets.sv
View File

@ -127,6 +127,7 @@ module memoutput (
output word_t wdata, output word_t wdata,
output logic [3:0] wstrb output logic [3:0] wstrb
); );
// TODO: wdata fill zero or replica
always_comb always_comb
casez (size) casez (size)
2'b11: begin 2'b11: begin
@ -136,10 +137,26 @@ module memoutput (
2'b10: begin 2'b10: begin
wdata = data; wdata = data;
case (addr) case (addr)
2'b11: begin wstrb = alr[0] ? 4'b1111 : 4'b1000; end 2'b11: begin
2'b10: begin wstrb = alr[0] ? 4'b0111 : 4'b1100; end wstrb = alr[0] ? 4'b1111 : 4'b1000;
2'b01: begin wstrb = alr[0] ? 4'b0011 : 4'b1110; end wdata = alr[0] ? data
2'b00: begin wstrb = alr[0] ? 4'b0001 : 4'b1111; end : {data[7:0], data[31:8]};
end
2'b10: begin
wstrb = alr[0] ? 4'b0111 : 4'b1100;
wdata = alr[0] ? {data[7:0], data[31:8]}
: {data[15:0], data[31:16]};
end
2'b01: begin
wstrb = alr[0] ? 4'b0011 : 4'b1110;
wdata = alr[0] ? {data[15:0], data[31:16]}
: {data[23:0], data[31:24]};
end
2'b00: begin
wstrb = alr[0] ? 4'b0001 : 4'b1111;
wdata = alr[0] ? {data[23:0], data[31:24]}
: data;
end
endcase endcase
end end
2'b01: begin 2'b01: begin