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tlb entries 32 -> 4

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Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
This commit is contained in:
Paul Pan 2021-08-14 20:28:23 +08:00
parent 4a610a5093
commit cbf99e1b33
7 changed files with 24 additions and 44 deletions
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11
src/CP0/CP0.sv
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@ -5,6 +5,7 @@ module CP0 (
input logic clk, input logic clk,
input logic rst, input logic rst,
input logic [4:0] addr, input logic [4:0] addr,
input logic [2:0] sel,
output word_t rdata, output word_t rdata,
input logic en, input logic en,
input word_t wdata, input word_t wdata,
@ -62,8 +63,8 @@ module CP0 (
assign rf_cp0.PageMask.zero2 = 13'b0; assign rf_cp0.PageMask.zero2 = 13'b0;
assign rf_cp0.EntryLo1.zero = 6'b0; assign rf_cp0.EntryLo1.zero = 6'b0;
assign rf_cp0.EntryLo0.zero = 6'b0; assign rf_cp0.EntryLo0.zero = 6'b0;
assign rf_cp0.Index.zero = 26'b0; assign rf_cp0.Index.zero = 29'b0;
assign rf_cp0.Config1 = 32'b0_011111_000_100_011_001_011_011_0000000; assign rf_cp0.Config1 = 32'b0_000011_000_100_011_001_011_011_0000000;
always_ff @(posedge clk) always_ff @(posedge clk)
if (rst) begin if (rst) begin
@ -97,7 +98,7 @@ module CP0 (
rf_cp0.EntryLo0.V = 1'b0; rf_cp0.EntryLo0.V = 1'b0;
rf_cp0.EntryLo0.G = 1'b0; rf_cp0.EntryLo0.G = 1'b0;
rf_cp0.Index.P = 1'b0; rf_cp0.Index.P = 1'b0;
rf_cp0.Index.Index = 5'b0; rf_cp0.Index.Index = 2'b0;
count_lo = 0; count_lo = 0;
end else begin end else begin
@ -165,7 +166,7 @@ module CP0 (
end end
// 1: rf_cp0.Random = wdata; // 1: rf_cp0.Random = wdata;
0: begin 0: begin
rf_cp0.Index.Index = wdata[4:0]; rf_cp0.Index.Index = wdata[1:0];
end end
default: begin default: begin
end end
@ -237,7 +238,7 @@ module CP0 (
// 19: rdata = rf_cp0.WatchHi; // 19: rdata = rf_cp0.WatchHi;
// 18: rdata = rf_cp0.WatchLo; // 18: rdata = rf_cp0.WatchLo;
// 17: rdata = rf_cp0.LLAddr; // 17: rdata = rf_cp0.LLAddr;
16: rdata = rf_cp0.Config; 16: rdata = sel[0] ? rf_cp0.Config1 : rf_cp0.Config;
// 15: rdata = rf_cp0.PRId; // 15: rdata = rf_cp0.PRId;
14: rdata = rf_cp0.EPC; 14: rdata = rf_cp0.EPC;
13: rdata = rf_cp0.Cause; 13: rdata = rf_cp0.Cause;

1
src/Core/Controller.sv
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@ -67,6 +67,7 @@ module Controller (
assign ctrl.MCtrl0.C0D = inst[15:11]; assign ctrl.MCtrl0.C0D = inst[15:11];
// assign ctrl.MCtrl0.C0W = inst[30] & inst[23]; // assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
assign ctrl.MCtrl0.C0W = inst[30] & ~inst[29] & inst[23] & ~inst[3]; assign ctrl.MCtrl0.C0W = inst[30] & ~inst[29] & inst[23] & ~inst[3];
assign ctrl.MCtrl0.SEL = inst[2:0];
assign ctrl.MCtrl0.RS0 = RS0_t'({ctrl.DP1, inst[30], ~inst[29] & (inst[30] | ~inst[1])}); assign ctrl.MCtrl0.RS0 = RS0_t'({ctrl.DP1, inst[30], ~inst[29] & (inst[30] | ~inst[1])});
assign ctrl.MCtrl1.MR = inst[31]; assign ctrl.MCtrl1.MR = inst[31];

6
src/Core/Datapath.sv
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@ -21,6 +21,7 @@ module Datapath (
// CP0 // CP0
input logic C0_int, input logic C0_int,
output logic [4:0] C0_addr, output logic [4:0] C0_addr,
output logic [2:0] C0_sel,
input word_t C0_rdata, input word_t C0_rdata,
output logic C0_we, output logic C0_we,
output word_t C0_wdata, output word_t C0_wdata,
@ -669,7 +670,7 @@ module Datapath (
E.en, E.en,
E.I0.ECtrl E.I0.ECtrl
); );
ffenrc #(14) E_I0_MCtrl_ff ( ffenrc #(17) E_I0_MCtrl_ff (
clk, clk,
rst | rstM, rst | rstM,
D.I0.MCtrl, D.I0.MCtrl,
@ -965,7 +966,7 @@ module Datapath (
M.en, M.en,
M.I0.ALUOut M.I0.ALUOut
); );
ffenrc #(14) M_I0_MCtrl_ff ( ffenrc #(17) M_I0_MCtrl_ff (
clk, clk,
rst | rstM, rst | rstM,
E.I0.MCtrl, E.I0.MCtrl,
@ -1139,6 +1140,7 @@ module Datapath (
); );
assign C0_addr = M.I0.MCtrl.C0D; assign C0_addr = M.I0.MCtrl.C0D;
assign C0_sel = M.I0.MCtrl.SEL;
assign C0_we = M.I0.MCtrl.C0W & M_I0_go; assign C0_we = M.I0.MCtrl.C0W & M_I0_go;
assign C0_wdata = M_I0_ForwardT; assign C0_wdata = M_I0_ForwardT;

42
src/MMU/TLB.sv
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@ -51,13 +51,13 @@ module TLB (
Index_t Index0; Index_t Index0;
TLB_t [31:0] TLB_entries; TLB_t [3:0] TLB_entries;
TLB_t entry; TLB_t entry;
// CP0(TLBWI) EntryHi PageMask EntryLo0 EntryLo1 -> TLB[Index] // CP0(TLBWI) EntryHi PageMask EntryLo0 EntryLo1 -> TLB[Index]
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (rst) begin if (rst) begin
TLB_entries <= 2880'b0; TLB_entries <= 360'b0;
end else if (tlbwi) end else if (tlbwi)
TLB_entries[c0_Index.Index] <= {c0_EntryHi.VPN2, c0_EntryHi.ASID, TLB_entries[c0_Index.Index] <= {c0_EntryHi.VPN2, c0_EntryHi.ASID,
c0_PageMask.Mask, c0_PageMask.Mask,
@ -192,7 +192,7 @@ endmodule
module TLB_Lookup ( module TLB_Lookup (
input TLB_t [31:0] TLB_entries, input TLB_t [ 3:0] TLB_entries,
input logic [19:0] VPN, input logic [19:0] VPN,
input logic [ 7:0] ASID, input logic [ 7:0] ASID,
@ -204,8 +204,8 @@ module TLB_Lookup (
output Index_t index output Index_t index
); );
logic [31:0] hitWay; logic [3:0] hitWay;
for (genvar i = 0; i < 32; i++) for (genvar i = 0; i < 4; i++)
assign hitWay[i] = ((TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask}) assign hitWay[i] = ((TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask})
== (VPN[19:1] & ~{7'b0, TLB_entries[i].PageMask})) == (VPN[19:1] & ~{7'b0, TLB_entries[i].PageMask}))
& (TLB_entries[i].G | TLB_entries[i].ASID == ASID); & (TLB_entries[i].G | TLB_entries[i].ASID == ASID);
@ -213,42 +213,14 @@ module TLB_Lookup (
// assume: hit is unique // assume: hit is unique
assign hit = |{hitWay}; assign hit = |{hitWay};
assign index.P = ~hit; assign index.P = ~hit;
onehot_bin32 index_decoder(hitWay, index.Index); onehot_bin4 index_decoder(hitWay, index.Index);
// always_comb for (int i = 0; i < 32; i++) index.Index |= hitWay[i] ? i : 0; // always_comb for (int i = 0; i < 32; i++) index.Index |= hitWay[i] ? i : 0;
TLB_t found; TLB_t found;
assign found = (hitWay[ 0] ? TLB_entries[ 0] : 90'b0) assign found = (hitWay[ 0] ? TLB_entries[ 0] : 90'b0)
| (hitWay[ 1] ? TLB_entries[ 1] : 90'b0) | (hitWay[ 1] ? TLB_entries[ 1] : 90'b0)
| (hitWay[ 2] ? TLB_entries[ 2] : 90'b0) | (hitWay[ 2] ? TLB_entries[ 2] : 90'b0)
| (hitWay[ 3] ? TLB_entries[ 3] : 90'b0) | (hitWay[ 3] ? TLB_entries[ 3] : 90'b0);
| (hitWay[ 4] ? TLB_entries[ 4] : 90'b0)
| (hitWay[ 5] ? TLB_entries[ 5] : 90'b0)
| (hitWay[ 6] ? TLB_entries[ 6] : 90'b0)
| (hitWay[ 7] ? TLB_entries[ 7] : 90'b0)
| (hitWay[ 8] ? TLB_entries[ 8] : 90'b0)
| (hitWay[ 9] ? TLB_entries[ 9] : 90'b0)
| (hitWay[10] ? TLB_entries[10] : 90'b0)
| (hitWay[11] ? TLB_entries[11] : 90'b0)
| (hitWay[12] ? TLB_entries[12] : 90'b0)
| (hitWay[13] ? TLB_entries[13] : 90'b0)
| (hitWay[14] ? TLB_entries[14] : 90'b0)
| (hitWay[15] ? TLB_entries[15] : 90'b0)
| (hitWay[16] ? TLB_entries[16] : 90'b0)
| (hitWay[17] ? TLB_entries[17] : 90'b0)
| (hitWay[18] ? TLB_entries[18] : 90'b0)
| (hitWay[19] ? TLB_entries[19] : 90'b0)
| (hitWay[20] ? TLB_entries[20] : 90'b0)
| (hitWay[21] ? TLB_entries[21] : 90'b0)
| (hitWay[22] ? TLB_entries[22] : 90'b0)
| (hitWay[23] ? TLB_entries[23] : 90'b0)
| (hitWay[24] ? TLB_entries[24] : 90'b0)
| (hitWay[25] ? TLB_entries[25] : 90'b0)
| (hitWay[26] ? TLB_entries[26] : 90'b0)
| (hitWay[27] ? TLB_entries[27] : 90'b0)
| (hitWay[28] ? TLB_entries[28] : 90'b0)
| (hitWay[29] ? TLB_entries[29] : 90'b0)
| (hitWay[30] ? TLB_entries[30] : 90'b0)
| (hitWay[31] ? TLB_entries[31] : 90'b0);
logic parity; logic parity;
assign parity = |{ assign parity = |{

3
src/MyCPU.sv
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@ -82,6 +82,7 @@ module mycpu_top (
logic C0_int; logic C0_int;
logic [4:0] C0_addr; logic [4:0] C0_addr;
logic [2:0] C0_sel;
word_t C0_rdata; word_t C0_rdata;
logic C0_we; logic C0_we;
word_t C0_wdata; word_t C0_wdata;
@ -166,6 +167,7 @@ module mycpu_top (
.clk (aclk), .clk (aclk),
.rst (~aresetn), .rst (~aresetn),
.addr (C0_addr), .addr (C0_addr),
.sel (C0_sel),
.rdata (C0_rdata), .rdata (C0_rdata),
.en (C0_we), .en (C0_we),
.wdata (C0_wdata), .wdata (C0_wdata),
@ -206,6 +208,7 @@ module mycpu_top (
.C0_int (C0_int), .C0_int (C0_int),
.C0_addr (C0_addr), .C0_addr (C0_addr),
.C0_sel (C0_sel),
.C0_rdata (C0_rdata), .C0_rdata (C0_rdata),
.C0_we (C0_we), .C0_we (C0_we),
.C0_wdata (C0_wdata), .C0_wdata (C0_wdata),

4
src/include/TLB.svh
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@ -24,8 +24,8 @@ typedef struct packed {
typedef struct packed { typedef struct packed {
logic P; logic P;
logic [25:0] zero; logic [28:0] zero;
logic [ 4:0] Index; logic [ 1:0] Index;
} Index_t; } Index_t;
typedef struct packed { typedef struct packed {

1
src/include/defines.svh
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@ -80,6 +80,7 @@ typedef struct packed {
logic HW; // critical logic HW; // critical
logic LW; // critical logic LW; // critical
logic [4:0] C0D; logic [4:0] C0D;
logic [2:0] SEL;
logic C0W; // critical logic C0W; // critical
HLS_t HLS; HLS_t HLS;
} MCtrl0_t; } MCtrl0_t;