Configurable [l,s]w[l,r]
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@ -78,7 +78,9 @@ module Controller (
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assign ctrl.MCtrl1.MR = inst[31] & (~inst[26] | inst[26] & (~inst[27] | inst[27] & ~inst[28] & ~inst[30]));
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assign ctrl.MCtrl1.MWR = inst[29];
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assign ctrl.MCtrl1.MX = ~inst[28];
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`ifdef ENABLE_UNALIGNED
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assign ctrl.MCtrl1.ALR = ALR_t'({inst[28] & inst[27] & ~inst[26], ~inst[28] & inst[27] & ~inst[26]});
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`endif
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assign ctrl.MCtrl1.SZ = inst[27:26];
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`ifdef ENABLE_TLB
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assign ctrl.MCtrl1.TLBR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1];
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@ -195,8 +195,10 @@ module Datapath (
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word_t M_I1_ByteX;
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word_t M_I1_HalfX;
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word_t M_I1_MDataA;
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`ifdef ENABLE_UNALIGNED
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word_t M_I1_MDataUL;
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word_t M_I1_MDataUR;
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`endif
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word_t M_I1_MData;
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logic M_I0_DIV_valid;
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@ -535,8 +537,10 @@ module Datapath (
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
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// Not Arith -> Store
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
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`ifdef ENABLE_UNALIGNED
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// Not Arith -> LWL/LWR
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
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`endif
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// Any -> MOVN/MOVZ
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.DT
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// Arith -> MOVN/MOVZ
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@ -963,7 +967,11 @@ module Datapath (
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`endif
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assign mem.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
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assign E_I1_ADDR = E_I1_ForwardS + E.I1.imm;
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`ifdef ENABLE_UNALIGNED
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assign mem.addr = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0} : E_I1_ADDR;
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`else
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assign mem.addr = E_I1_ADDR;
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`endif
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assign mem.size = {E.I1.MCtrl.SZ[1], E.I1.MCtrl.SZ[0] & ~E.I1.MCtrl.SZ[1]};
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assign cache_op.req = cache_op.op.icache_op | cache_op.op.dcache_op;
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@ -1308,7 +1316,11 @@ module Datapath (
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.addr (M.I1.ALUOut[1:0]),
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.data (M_I1_ForwardT),
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.size (M.I1.MCtrl.SZ),
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`ifdef ENABLE_UNALIGNED
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.alr (M.I1.MCtrl.ALR),
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`else
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.alr (ALR_t'(2'b00)),
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`endif
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.wdata(mem.wdata),
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.wstrb(mem.wstrb)
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);
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@ -1344,6 +1356,7 @@ module Datapath (
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M.I1.MCtrl.SZ,
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M_I1_MDataA
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);
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`ifdef ENABLE_UNALIGNED
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mux4 #(32) M_I1_MDataUL_mux (
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{M_I1_DataR[ 7:0], M_I1_ForwardT[23:0]},
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{M_I1_DataR[15:0], M_I1_ForwardT[15:0]},
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@ -1367,6 +1380,9 @@ module Datapath (
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M.I1.MCtrl.ALR,
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M_I1_MData
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);
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`else
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assign M_I1_MData = M_I1_MDataA;
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`endif
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mux2 #(32) M_I1_DataRW_mux (
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M.I1.ALUOut,
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M_I1_MData,
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@ -104,16 +104,24 @@ module decoder2 (
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// 32'b01111100000??????????00000111011: begin cpu = 1'b1; ce = 2'b0; end // RDHWR (CpU)
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32'b100000??????????????????????????: ri = 1'b0; // LB
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32'b100001??????????????????????????: ri = 1'b0; // LH
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`ifdef ENABLE_UNALIGNED
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32'b100010??????????????????????????: ri = 1'b0; // LWL
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`endif
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32'b100011??????????????????????????: ri = 1'b0; // LW
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32'b100100??????????????????????????: ri = 1'b0; // LBU
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32'b100101??????????????????????????: ri = 1'b0; // LHU
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`ifdef ENABLE_UNALIGNED
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32'b100110??????????????????????????: ri = 1'b0; // LWR
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`endif
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32'b101000??????????????????????????: ri = 1'b0; // SB
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32'b101001??????????????????????????: ri = 1'b0; // SH
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`ifdef ENABLE_UNALIGNED
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32'b101010??????????????????????????: ri = 1'b0; // SWL
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`endif
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32'b101011??????????????????????????: ri = 1'b0; // SW
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`ifdef ENABLE_UNALIGNED
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32'b101110??????????????????????????: ri = 1'b0; // SWR
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`endif
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`ifdef ENABLE_CACHEOP
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32'b101111?????00000????????????????: ri = 1'b0; // I-Cache Index Invalid
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32'b101111?????01000????????????????: ri = 1'b0; // I-Cache Index Store Tag
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@ -8,6 +8,7 @@
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// `define ENABLE_CpU
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// `define ENABLE_TRAP
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// `define ENABLE_MADD
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// `define ENABLE_UNALIGNED
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`ifdef SIMULATION_VERILATOR
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`undef ENABLE_CpU
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@ -148,7 +149,9 @@ typedef struct packed {
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logic MR; // critical
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logic MWR; // critical
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logic MX;
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`ifdef ENABLE_UNALIGNED
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ALR_t ALR; // critical
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`endif
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logic [1:0] SZ;
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`ifdef ENABLE_TLB
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logic TLBWI; // critical
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