diff --git a/src/Core/Controller.sv b/src/Core/Controller.sv
index ba3e2e5..b619e6a 100644
--- a/src/Core/Controller.sv
+++ b/src/Core/Controller.sv
@@ -78,7 +78,9 @@ module Controller (
   assign ctrl.MCtrl1.MR       = inst[31] & (~inst[26] | inst[26] & (~inst[27] | inst[27] & ~inst[28] & ~inst[30]));
   assign ctrl.MCtrl1.MWR      = inst[29];
   assign ctrl.MCtrl1.MX       = ~inst[28];
+`ifdef ENABLE_UNALIGNED
   assign ctrl.MCtrl1.ALR      = ALR_t'({inst[28] & inst[27] & ~inst[26], ~inst[28] & inst[27] & ~inst[26]});
+`endif
   assign ctrl.MCtrl1.SZ       = inst[27:26];
 `ifdef ENABLE_TLB
   assign ctrl.MCtrl1.TLBR     = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & ~inst[1];
diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv
index 5ad5bf6..a0b90a4 100644
--- a/src/Core/Datapath.sv
+++ b/src/Core/Datapath.sv
@@ -195,8 +195,10 @@ module Datapath (
   word_t        M_I1_ByteX;
   word_t        M_I1_HalfX;
   word_t        M_I1_MDataA;
+`ifdef ENABLE_UNALIGNED
   word_t        M_I1_MDataUL;
   word_t        M_I1_MDataUR;
+`endif
   word_t        M_I1_MData;
 
   logic         M_I0_DIV_valid;
@@ -535,8 +537,10 @@ module Datapath (
                      | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
                 // Not Arith -> Store
                      | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
+`ifdef ENABLE_UNALIGNED
                 // Not Arith -> LWL/LWR
                      | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
+`endif
                 // Any -> MOVN/MOVZ
                      | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.DT
                 // Arith -> MOVN/MOVZ
@@ -963,7 +967,11 @@ module Datapath (
 `endif
   assign mem.req         = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
   assign E_I1_ADDR       = E_I1_ForwardS + E.I1.imm;
+`ifdef ENABLE_UNALIGNED
   assign mem.addr        = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0} : E_I1_ADDR;
+`else
+  assign mem.addr        = E_I1_ADDR;
+`endif
   assign mem.size        = {E.I1.MCtrl.SZ[1], E.I1.MCtrl.SZ[0] & ~E.I1.MCtrl.SZ[1]};
 
   assign cache_op.req  = cache_op.op.icache_op | cache_op.op.dcache_op;
@@ -1308,7 +1316,11 @@ module Datapath (
       .addr (M.I1.ALUOut[1:0]),
       .data (M_I1_ForwardT),
       .size (M.I1.MCtrl.SZ),
+`ifdef ENABLE_UNALIGNED
       .alr  (M.I1.MCtrl.ALR),
+`else
+      .alr  (ALR_t'(2'b00)),
+`endif
       .wdata(mem.wdata),
       .wstrb(mem.wstrb)
   );
@@ -1344,6 +1356,7 @@ module Datapath (
       M.I1.MCtrl.SZ,
       M_I1_MDataA
   );
+`ifdef ENABLE_UNALIGNED
   mux4 #(32) M_I1_MDataUL_mux (
       {M_I1_DataR[ 7:0], M_I1_ForwardT[23:0]},
       {M_I1_DataR[15:0], M_I1_ForwardT[15:0]},
@@ -1367,6 +1380,9 @@ module Datapath (
       M.I1.MCtrl.ALR,
       M_I1_MData
   );
+`else
+  assign M_I1_MData = M_I1_MDataA;
+`endif
   mux2 #(32) M_I1_DataRW_mux (
       M.I1.ALUOut,
       M_I1_MData,
diff --git a/src/Core/Gadgets/decoder2.sv b/src/Core/Gadgets/decoder2.sv
index 11afed5..bcfd031 100644
--- a/src/Core/Gadgets/decoder2.sv
+++ b/src/Core/Gadgets/decoder2.sv
@@ -104,16 +104,24 @@ module decoder2 (
       // 32'b01111100000??????????00000111011: begin cpu = 1'b1; ce = 2'b0; end // RDHWR (CpU)
       32'b100000??????????????????????????: ri = 1'b0;  // LB
       32'b100001??????????????????????????: ri = 1'b0;  // LH
+`ifdef ENABLE_UNALIGNED
       32'b100010??????????????????????????: ri = 1'b0;  // LWL
+`endif
       32'b100011??????????????????????????: ri = 1'b0;  // LW
       32'b100100??????????????????????????: ri = 1'b0;  // LBU
       32'b100101??????????????????????????: ri = 1'b0;  // LHU
+`ifdef ENABLE_UNALIGNED
       32'b100110??????????????????????????: ri = 1'b0;  // LWR
+`endif
       32'b101000??????????????????????????: ri = 1'b0;  // SB
       32'b101001??????????????????????????: ri = 1'b0;  // SH
+`ifdef ENABLE_UNALIGNED
       32'b101010??????????????????????????: ri = 1'b0;  // SWL
+`endif
       32'b101011??????????????????????????: ri = 1'b0;  // SW
+`ifdef ENABLE_UNALIGNED
       32'b101110??????????????????????????: ri = 1'b0;  // SWR
+`endif
 `ifdef ENABLE_CACHEOP
       32'b101111?????00000????????????????: ri = 1'b0;  // I-Cache Index Invalid
       32'b101111?????01000????????????????: ri = 1'b0;  // I-Cache Index Store Tag
diff --git a/src/include/defines.svh b/src/include/defines.svh
index 9e4fef0..f666ffc 100644
--- a/src/include/defines.svh
+++ b/src/include/defines.svh
@@ -8,6 +8,7 @@
 // `define ENABLE_CpU
 // `define ENABLE_TRAP
 // `define ENABLE_MADD
+// `define ENABLE_UNALIGNED
 
 `ifdef SIMULATION_VERILATOR
   `undef ENABLE_CpU
@@ -148,7 +149,9 @@ typedef struct packed {
   logic       MR;       // critical
   logic       MWR;      // critical
   logic       MX;
+`ifdef ENABLE_UNALIGNED
   ALR_t       ALR;      // critical
+`endif
   logic [1:0] SZ;
 `ifdef ENABLE_TLB
   logic       TLBWI;    // critical