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[Cache] init

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Paul Pan 2021-07-05 23:08:33 +08:00
parent 304ae7f8ce
commit c10cc74806
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11 changed files with 832 additions and 32 deletions
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src/Cache/Cache.svh
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`include "constants.svh"

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src/Cache/Design.md Normal file
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# Cache
I-Cache with D-Cache
## I-CACHE
四路组相联，行大小`16Bytes`，每路`1KBytes`，共`4KBytes`
|Tag|Index|Offset|
|:-:|:-:|:-:|
|x|$\log_2{64}=6$|$\log_2{16}=4$|
|`[31:10]`|组索引：`[9:4]`|行内索引：`[3:0]`|

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src/Cache/ICache.sv Normal file
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`include "defines.svh"
`include "ICache.svh"
module ICache (
input clk,
input rst,
// TODO add AXI interface
HandShake.prev handshake,
ICPipeline.ICache cacheInfo
);
// Four way assoc
ICTagRAM_t TagRAM0, TagRAM1, TagRAM2, TagRAM3;
ICDataRAM_t DataRAM0, DataRAM1, DataRAM2, DataRAM3;
// Block RAM
cache_tag_bram tag_ram0 (
.addra(TagRAM2.addr),
.clka (clk),
.dina (TagRAM2.wdata),
.douta(TagRAM2.rdata),
.wea (TagRAM2.wen)
);
cache_tag_bram tag_ram1 (
.addra(TagRAM1.addr),
.clka (clk),
.dina (TagRAM1.wdata),
.douta(TagRAM1.rdata),
.wea (TagRAM1.wen)
);
cache_tag_bram tag_ram2 (
.addra(TagRAM2.addr),
.clka (clk),
.dina (TagRAM2.wdata),
.douta(TagRAM2.rdata),
.wea (TagRAM2.wen)
);
cache_tag_bram tag_ram3 (
.addra(TagRAM3.addr),
.clka (clk),
.dina (TagRAM3.wdata),
.douta(TagRAM3.rdata),
.wea (TagRAM3.wen)
);
cache_data_bram data_ram0 (
.addra(DataRAM0.addr),
.clka (clk),
.dina (DataRAM0.wdata),
.douta(DataRAM0.rdata),
.wea (DataRAM0.wen)
);
cache_data_bram data_ram1 (
.addra(DataRAM1.addr),
.clka (clk),
.dina (DataRAM1.wdata),
.douta(DataRAM1.rdata),
.wea (DataRAM1.wen)
);
cache_data_bram data_ram2 (
.addra(DataRAM2.addr),
.clka (clk),
.dina (DataRAM2.wdata),
.douta(DataRAM2.rdata),
.wea (DataRAM2.wen)
);
cache_data_bram data_ram3 (
.addra(DataRAM3.addr),
.clka (clk),
.dina (DataRAM3.wdata),
.douta(DataRAM3.rdata),
.wea (DataRAM3.wen)
);
// Static
// Lookup Stage
logic cacheAddress = cacheInfo.PC[9:4]; // TODO: move cacheInfo.PC into a local reg and update it via ff
// Hit Check Stage
logic [`IC_DATA_LENGTH-1:0] cacheLine; // Cache Line
logic [31:0] cacheLineData[4]; // Map Cache Line into 4 Cache Data
assign cacheLineData[0] = cacheLine[31:0];
assign cacheLineData[1] = cacheLine[63:32];
assign cacheLineData[1] = cacheLine[95:64];
assign cacheLineData[1] = cacheLine[127:96];
logic hit; // Cache hit or not
logic hitPart[4]; // Cache Line hit or not
logic [21:0] tag;
assign tag = cacheInfo.PC[31:10]; // TODO: move cacheInfo.PC into a local reg and update it via ff
assign hitPart[0] = TagRAM0.rdata[0] && TagRAM0.rdata[`IC_TAG_LENGTH-1:1] == tag;
assign hitPart[1] = TagRAM1.rdata[0] && TagRAM1.rdata[`IC_TAG_LENGTH-1:1] == tag;
assign hitPart[2] = TagRAM2.rdata[0] && TagRAM2.rdata[`IC_TAG_LENGTH-1:1] == tag;
assign hitPart[3] = TagRAM3.rdata[0] && TagRAM3.rdata[`IC_TAG_LENGTH-1:1] == tag;
assign hit = hitPart[0] | hitPart[1] | hitPart[2] | hitPart[3];
assign cacheLine = // TODO: AXI Data ? :
hitPart[0] ? DataRAM0.rdata :
hitPart[1] ? DataRAM1.rdata :
hitPart[2] ? DataRAM2.rdata :
hitPart[3] ? DataRAM3.rdata :
0;
endmodule

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src/IP/cache_data_bram/cache_data_bram.xci Normal file
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<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
</xilinx:configElementInfos>
</xilinx:componentInstanceExtensions>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

6
src/AXI/AXI.svh → src/include/AXI.svh
View File

@ -1,3 +1,5 @@
`ifndef AXI_SVH
`define AXI_SVH
`include "constants.svh"
typedef struct packed {
@ -54,7 +56,7 @@ typedef struct packed {
typedef struct packed {
logic awready; // Write address ready
logic wready; // Write ready
logic wready; // Write ready
logic [3:0] bid; // Response ID
logic [1:0] bresp; // Write response
@ -68,3 +70,5 @@ interface AXIWrite;
modport master(input AXIWriteData, output AXIWriteAddr);
modport slave(input AXIWriteAddr, output AXIWriteData);
endinterface //AXIWrite
`endif

43
src/include/ICache.svh Normal file
View File

@ -0,0 +1,43 @@
`ifndef ICACHE_SVH
`define ICACHE_SVH
// IC for I-Cache
`define IC_TAG_LENGTH 22+1 // Tag + Valid
`define IC_DATA_LENGTH 128 // 16Bytes
// TODO: 考虑到指令4字节对齐，可否给TAG减少两位？Cache是否处理4字节对齐异常？
typedef struct packed {
logic wen;
logic [5:0] addr; // Index
logic [`IC_TAG_LENGTH-1:0] wdata;
logic [`IC_TAG_LENGTH-1:0] rdata;
} ICTagRAM_t; // 64 * 23
typedef struct packed {
logic wen;
logic [5:0] addr; // Index
logic [`IC_DATA_LENGTH-1:0] wdata;
logic [`IC_DATA_LENGTH-1:0] rdata;
} ICDataRAM_t; // 64 * 128
typedef enum {
ICLookup,
ICHitUpdate,
ICMissHandle,
ICSelect,
ICReplace,
ICRefill
} ICacheStatus_t;
interface ICPipeline;
logic [31:0] PC;
logic [31:0] inst;
modport ICache(input PC, output inst);
modport Pipe(input inst, output PC);
endinterface //ICPipeline
`endif

3
src/include/constants.svh
View File

@ -1,5 +1,6 @@
`ifndef CONSTANTS_SVH
`define CONSTANTS_SVH
`define WIDTH 32
`define LABEL 6
@ -14,4 +15,4 @@
`define OP_SPECIAL 6'b000000
`define OP_ADDI 6'b001000
`endif
`endif

27
src/include/defines.svh
View File

@ -3,18 +3,25 @@
typedef logic [31:0] word_t;
typedef logic [15:0] hfwd_t;
typedef logic [7:0] byte_t;
typedef logic [7:0] byte_t;
typedef struct packed {
logic f_sl;
logic f_sr;
logic f_add;
logic f_and;
logic f_or;
logic f_xor;
logic f_slt;
logic f_sltu;
logic alt;
logic f_sl;
logic f_sr;
logic f_add;
logic f_and;
logic f_or;
logic f_xor;
logic f_slt;
logic f_sltu;
logic alt;
} aluctrl_t;
interface HandShake;
logic valid;
logic ready;
modport prev(input valid, output ready);
modport next(input ready, output valid);
endinterface //HandShake
`endif

38
src/include/sram.svh
View File

@ -3,30 +3,30 @@
`include "defines.svh"
interface sram_i();
logic req;
logic wr;
word_t addr;
logic [3:0] wstrb;
word_t wdata;
logic addr_ok;
logic data_ok;
word_t rdata;
interface sram_i ();
logic req;
logic wr;
word_t addr;
logic [3:0] wstrb;
word_t wdata;
logic addr_ok;
logic data_ok;
word_t rdata;
modport master(output req, wr, addr, wstrb, wdata, input addr_ok, data_ok, rdata);
modport slave(input req, wr, addr, wstrb, wdata, output addr_ok, data_ok, rdata);
modport master(output req, wr, addr, wstrb, wdata, input addr_ok, data_ok, rdata);
modport slave(input req, wr, addr, wstrb, wdata, output addr_ok, data_ok, rdata);
endinterface
interface sramro_i();
logic req;
word_t addr;
logic addr_ok;
logic data_ok;
word_t rdata;
interface sramro_i ();
logic req;
word_t addr;
logic addr_ok;
logic data_ok;
word_t rdata;
modport master(output req, addr, input addr_ok, data_ok, rdata);
modport slave(input req, addr, output addr_ok, data_ok, rdata);
modport master(output req, addr, input addr_ok, data_ok, rdata);
modport slave(input req, addr, output addr_ok, data_ok, rdata);
endinterface