From c10cc74806493bbd3499b4e2ec57e99f07c20d9f Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Mon, 5 Jul 2021 23:08:33 +0800 Subject: [PATCH] [Cache] init --- assests/bram.png | Bin 0 -> 5916 bytes src/Cache/Cache.svh | 1 - src/Cache/Design.md | 13 + src/Cache/ICache.sv | 113 ++++++++ src/IP/cache_data_bram/cache_data_bram.xci | 310 +++++++++++++++++++++ src/IP/cache_tag_bram/cache_tag_bram.xci | 310 +++++++++++++++++++++ src/{AXI => include}/AXI.svh | 6 +- src/include/ICache.svh | 43 +++ src/include/constants.svh | 3 +- src/include/defines.svh | 27 +- src/include/sram.svh | 38 +-- 11 files changed, 832 insertions(+), 32 deletions(-) create mode 100644 assests/bram.png delete mode 100644 src/Cache/Cache.svh create mode 100644 src/Cache/Design.md create mode 100644 src/Cache/ICache.sv create mode 100644 src/IP/cache_data_bram/cache_data_bram.xci create mode 100644 src/IP/cache_tag_bram/cache_tag_bram.xci rename src/{AXI => include}/AXI.svh (96%) create mode 100644 src/include/ICache.svh diff --git a/assests/bram.png b/assests/bram.png new file mode 100644 index 0000000000000000000000000000000000000000..c79fa8dd7ba5aef7c269a0c5ea331d76cc14a7f5 GIT binary patch literal 5916 zcmcJTcT`i`v&SPvsUlqvLuew>1VltbgrI~bU=XBp>C&$R6(n>Jq$Lyss1Wf|M4EI1 z0#^YOKnT4Ulq&>~s&qpH-%0TP)?07AKi~V~tjwIV&)&0k_RM^~=b?oef|pC23j_l3 z8W~3dFfr#1A(eB+&^8|0iW|vLt7LG zBoNHF4t@5N3;}^es*SGb-3W17$(u@(KnN#zNyxL=$3!`ENL5D1P3p4LyzVuglm>&= zK&|Jm9DBzu3k9v8m|&B=r2F*bc1p=~P|?e#m-HKBZQnADFAX_5>d?z{rmS~9Y7mEb zkAR}`2zO{)pjV2dBcPX2XwWmR|3AYqGGJ^cl9tdT14>-``em=@ue)E(U=4rn@BSm2 zjo8u#|5)x6z?L2T=CHT$vtEw#j+`XFxyd^<3y25grj98t&^bJK|6@#CQ##*tE_cvK zdv=lGi-xGC*I!aX=3*SSI6P7+FL&bQ`l=|F0ff5TO&w%y zxx%yJ*`eu|2`mE%rgs+P%&lP$NpVQoU2Lg}?|OOtuD3Nzx#Iq5tU9&~oZ%4|TC;8& z#iGDUSRC-hk>pv}k%xmu{+d@xHwSSQ@=#wQzS&Ak@(CrvG871lYH%Eh7|onnOwOE& z(mRzU%~(cE0dQEEujYWH~mYwGkU0OnVj+>A1?hP(D7 zG$Wc)m0D`43SJ(Mck-U1k9=$M(WciG=yvN?HhsvN7gCgDhLhl~ZJ*!XlfaBv%@?QN zJ)f-FdI3$F%}!WS#YN(fs z`HJR1^oXbHY1(Ad?UcIXV`F342zsV;>~VXHv-G)E1tDktN2hMQc`&|T-ur>_qQZa$IYxFT*Prx_he-K8)FZwT87+giMC15&T;2u`Z2Emw%2h z*eN!lkC(*CdZ=-jUkPZDyPS>2scx9B1NGWo&c@)S>J1rB#so5@)J3f;`RG2X; zc#T{*c~dt)qnsa;tdsxB07_648wwmgK_+=2t_b*c)?T%d`Sn1gI*uwp$xiwfVhz0r zk(5iZaaHaZjEJSE&R%G=n2g~OelY>2GzwSTX4AlZ!r2U|o&wvJc35kg(8J5Mi$$^I zzrUZb>ZXOR1FT~ zX`y7WyDgZi0TN15p%VB=C8*OvjwICOq+e5&^_$y~%|5yXU)92JKc`d-53haI!`;z^ zorG5d#ui{m#WPJ{#XMjbJbz0Mc9LoMN1??N-~;hc$|2f0p7`ep?ne3k(P;5__&}@@ zg^hNOqx1O@+Xn7+Zw>{aq^o>2ekZ6y9E=zyV5E{mj2LS9inGY(mHQ!~H}LiG8FXBs z+|;|_l#>?|nx_H?9ckH0MO}#Aao&&aA0L@>vrKCRgJHH}oar8srr{HEEHC8>_>((# z&X*b--=@6ysQjq^0?c6lb#D4U`DETOlfvvP0RV`NO=|t7n_T) zVWt7Uj@c8dJ2TXA?h16YqD0u1n^v@y`BQ6;G_(rU7(vP%?hhB70Nd4%)BTX|YdE*~ z($ymjAu0-PoC>zPvauo4b!Wg|LNb~=lAtsPuh;i3|2S)ZxO6;H#W^euCx0g}B@zDI z_W2E5ZBk7=18}Wu+yFnO0l5YC~UU^$WgA*=Cf$YCSL3q2ZakeIs}k3`Drl@9dfWge zE|?VO1ZUE~lF0)sW;+gt!x9o|x17vw@q{%8{t^J-!+rNoQ?_}R(TIqJAsZp+*s|NQ zc?w7BqoAW*84Lp13s%PKoT~3QL)uZ(&}Oj{!05Dk!L)_cpzH9{8!J}WKdQ`Jl^znc(j?lGydp_=ax1NYcs1p> zGLL-2+jGaoxw_ZNo{VO|NAW-^8r#Q>v^G57I)c?@#_xL(NVz<-1R}Z8>hZM-PJg3| zG2b$}-$S+Dtr;Pn>2695p&vWbhK0yZg$~jaafKNySD*9cR{rHp8_pRG$za zRv-rI9EsC|E-frRKpAbn=@1ah@gzC+cI;ASDDxo4W90M2+2s5|ewQDG>55=cnVkL$ z3|1g;27U^k`6=8G9nzptkKWEmOHRjntE_GpMYOgK`Ymv*qHK;#54af9mI)tA+1a0C z+>I;m|4H`JJ$)>kbVHJ=aqOq33TrOz5RHe)fyzhL#h4UmCqf<4X6$7>lvLuzptU6! z1aDTLyP0m}kHJi!98i(S}<;M4xmLWz;;j*?0Q8N+;au;xb?cstev!M|tz=Rn2g zWzr!9L_5cI5X1^lyyF;HNnxd(V{6Op(Jl6mL5njtno+WuL3})K*5F?7F2hoWfsrXAr>xjeI zj?&NU1ndONE6gANN%j>bOo%RJQZ7GO5EUmHH2hjxh*Tv%JMwxS)&5yvaV_KTo10Sn z9E82bcOKS}5Xt00fee=PQ*8q)bM1}f&z@ik1^s%@H9S1=Y*1l3#rb=S%EqJ?Zo+dH zk`L2^fsGAGxU}Rz`;=id_{>~>mB%sjHVB@>jwOh@qx`6;eeAao`!jRZpUA6I8Bxn) z>>E*N5ui+~Pgi^VlVKkc@XId#1U(;3-A)L9QGfr&Bl21Zbg~&`QdIw5oO9%jESBY7 zvO|)yZ>Oat)WK)rx`v50EVq#BMLdgIjoP(jhji*TpH!|iSjWffAzJ+h^(}qA;Yu01 zbZ46tNVAjmejQeR-3WrXSRwS#aZ`Md{}}mrT}H`Ev{}i}m$h2oN24sIgZu`n*p^PW zG>w^YG<{X8&zUCL8(O#7bN!E5L5S5wcz4|Uq^`yaA>Y17iW!sp7WpEP+R~BMlYS?ji_hjOI2G$+|sx@yq?X}DGL+@+SE zDM4iU^noHvKxpaLECUKA^KTw@*MKV&twNK(a?2)XswsY(KQxliA~||cO+cXC?-c+l zGeeQw-+U?uROa6jrUlqvC?f$%Rb;3S(Ms-c1py$RvahdSfrv z3sdrxf&cQtCUR4U2hV+U%(qPl**Wf$VN&dQY|ds7dj6;{cs z8^uLCkdB@of2YNl=d7tU9Q7wJM7#oVxj#~!sMe7AfYMc;{Ye;DGV9)~u5SRypH zpXP1ydQYENxLQk(OH-qG2)o!Fl}?fHrf!R(t9qb2sU8ip5vt;lysDuVbe()X)kog? zs}!8>O7xREcQ^I<$wM78CBC#o5ZYF<^MOH*DtHIqKKT7-*hhuYZtF+dG zy4;vWLBV`GtCL7?lUvsood(se`inNbZR{1sq?(I}FI%0iHj$Ae?Aae$>sSby{YxQ# zbnT%Lhre@j*Kp%w?DUx38U%bcSWYsxKewY+G@#hve6e>r<9Js@g$#Z*fC0h;kl`wr zxl?jC74|Dwfa8%NH*JKlf|U#{eE%^~Z(OUOSs)FO-8^%5z}FCwa}|n3Y$!4slm};g zz-iylw^X`5Ppc7gZ~GY=@vfBv^?zBXR8G!4;26E|3q^#UjN6;MH={l3Y?E15m6JVg z57pFVwu23)EGN!~Jj){Qgt3$P;>XB$)8q*z<)lpV zod;n%v3$vuu%PN+=cWdij0@ZgvTUvoL+0tnuR||4?f&@A__9$O{>N;l;etsu^0x*6 z;5>Iz_L&ZMXKU4f}BQy)Rv-K#&{v*d!q$G*0s&Ib&7avwqgB(A8fA-c%XMQb>LTqkk9~a&^k*55L>k%JeT-fg#BwtcfLoSo63R z)lS#r-X!C<0Wf&@wO<)5HDpVHj-ku{9r*ig*gKOx-+a*kW!oWK^IN{I2X*@!;QV?4 zF5x7_WT8+)NoN$l6yZ77)(U5rz}iD|P!`_3UtSFdKk&j|tLv z9$5JI&xE35kB8;>JGP$)UwhGMxG;1kv4p1{W%Y=>5PT8(FY?1zj5JwHgatn!xZz&2 zf-b4Su9=I*e?$5F?{QWnxzh)ee0b;X{CMBM-WWG};h8@7G(XlnN@9USTToo!>aAwS zoB;gOY2MT+=?Wo|q0(N^9SSuiHe}OV z&60`&R*IW6+7d3m=GPX8_d_)%ynjXCW#fOR<@8lT4fj4>i5~;2@VwZ99yLbTTq;HW z86dUWKs&pK+il)kZe86FTE6W{EMC1wm&#MGd%85dZmW3mfVuncS6X&^E%|s2yH+>NWc7#VWOS_m+!^}yW)Q;LRab%s_V#bm z^u&|TT!o_dKM2v30MW|8dd-`6Xy~0M2%y^@(04w{V^%PVnKu1l0O$js*q9EJ`eT@x za`r#WzbKQN28ap*kU?&BEZ*__8hK8?LH|06!Tb!Z{XdxB>_4E-q<#kI+dlZ;nBT2| zWg=Nj + + xilinx.com + xci + unknown + 1.0 + + + cache_data_bram + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 2 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 13.4011 mW + artix7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + cache_data_bram.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 64 + 64 + 1 + 1 + 128 + 128 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 64 + 64 + WRITE_FIRST + WRITE_FIRST + 128 + 128 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + cache_data_bram + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 128 + 128 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 64 + 128 + 128 + No_ECC + false + false + false + Stand_Alone + artix7 + + + xc7a200t + fbg676 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/IP/cache_tag_bram/cache_tag_bram.xci b/src/IP/cache_tag_bram/cache_tag_bram.xci new file mode 100644 index 0000000..132bc5a --- /dev/null +++ b/src/IP/cache_tag_bram/cache_tag_bram.xci @@ -0,0 +1,310 @@ + + + xilinx.com + xci + unknown + 1.0 + + + cache_tag_bram + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 1 + 0 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 3.16405 mW + artix7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + cache_tag_bram.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 64 + 64 + 1 + 1 + 23 + 23 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 64 + 64 + WRITE_FIRST + WRITE_FIRST + 23 + 23 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + cache_tag_bram + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + false + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 23 + 23 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 64 + 23 + 23 + No_ECC + false + false + false + Stand_Alone + artix7 + + + xc7a200t + fbg676 + VERILOG + + MIXED + -1 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/AXI/AXI.svh b/src/include/AXI.svh similarity index 96% rename from src/AXI/AXI.svh rename to src/include/AXI.svh index 8f3a245..9392df0 100644 --- a/src/AXI/AXI.svh +++ b/src/include/AXI.svh @@ -1,3 +1,5 @@ +`ifndef AXI_SVH +`define AXI_SVH `include "constants.svh" typedef struct packed { @@ -54,7 +56,7 @@ typedef struct packed { typedef struct packed { logic awready; // Write address ready - logic wready; // Write ready + logic wready; // Write ready logic [3:0] bid; // Response ID logic [1:0] bresp; // Write response @@ -68,3 +70,5 @@ interface AXIWrite; modport master(input AXIWriteData, output AXIWriteAddr); modport slave(input AXIWriteAddr, output AXIWriteData); endinterface //AXIWrite + +`endif diff --git a/src/include/ICache.svh b/src/include/ICache.svh new file mode 100644 index 0000000..8009e91 --- /dev/null +++ b/src/include/ICache.svh @@ -0,0 +1,43 @@ +`ifndef ICACHE_SVH +`define ICACHE_SVH + +// IC for I-Cache + +`define IC_TAG_LENGTH 22+1 // Tag + Valid +`define IC_DATA_LENGTH 128 // 16Bytes + +// TODO: 考虑到指令4字节对齐，可否给TAG减少两位？Cache是否处理4字节对齐异常？ + +typedef struct packed { + logic wen; + logic [5:0] addr; // Index + logic [`IC_TAG_LENGTH-1:0] wdata; + logic [`IC_TAG_LENGTH-1:0] rdata; +} ICTagRAM_t; // 64 * 23 + +typedef struct packed { + logic wen; + logic [5:0] addr; // Index + logic [`IC_DATA_LENGTH-1:0] wdata; + logic [`IC_DATA_LENGTH-1:0] rdata; +} ICDataRAM_t; // 64 * 128 + +typedef enum { + ICLookup, + ICHitUpdate, + ICMissHandle, + ICSelect, + ICReplace, + ICRefill +} ICacheStatus_t; + +interface ICPipeline; + logic [31:0] PC; + logic [31:0] inst; + + modport ICache(input PC, output inst); + modport Pipe(input inst, output PC); + +endinterface //ICPipeline + +`endif diff --git a/src/include/constants.svh b/src/include/constants.svh index f3233ca..53055e5 100644 --- a/src/include/constants.svh +++ b/src/include/constants.svh @@ -1,5 +1,6 @@ `ifndef CONSTANTS_SVH `define CONSTANTS_SVH + `define WIDTH 32 `define LABEL 6 @@ -14,4 +15,4 @@ `define OP_SPECIAL 6'b000000 `define OP_ADDI 6'b001000 -`endif \ No newline at end of file +`endif diff --git a/src/include/defines.svh b/src/include/defines.svh index 20ae3e2..4b73c6b 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -3,18 +3,25 @@ typedef logic [31:0] word_t; typedef logic [15:0] hfwd_t; -typedef logic [7:0] byte_t; +typedef logic [7:0] byte_t; typedef struct packed { - logic f_sl; - logic f_sr; - logic f_add; - logic f_and; - logic f_or; - logic f_xor; - logic f_slt; - logic f_sltu; - logic alt; + logic f_sl; + logic f_sr; + logic f_add; + logic f_and; + logic f_or; + logic f_xor; + logic f_slt; + logic f_sltu; + logic alt; } aluctrl_t; +interface HandShake; + logic valid; + logic ready; + modport prev(input valid, output ready); + modport next(input ready, output valid); +endinterface //HandShake + `endif diff --git a/src/include/sram.svh b/src/include/sram.svh index 302e835..b5c1c29 100644 --- a/src/include/sram.svh +++ b/src/include/sram.svh @@ -3,30 +3,30 @@ `include "defines.svh" -interface sram_i(); - logic req; - logic wr; - word_t addr; - logic [3:0] wstrb; - word_t wdata; - logic addr_ok; - logic data_ok; - word_t rdata; +interface sram_i (); + logic req; + logic wr; + word_t addr; + logic [3:0] wstrb; + word_t wdata; + logic addr_ok; + logic data_ok; + word_t rdata; - modport master(output req, wr, addr, wstrb, wdata, input addr_ok, data_ok, rdata); - modport slave(input req, wr, addr, wstrb, wdata, output addr_ok, data_ok, rdata); + modport master(output req, wr, addr, wstrb, wdata, input addr_ok, data_ok, rdata); + modport slave(input req, wr, addr, wstrb, wdata, output addr_ok, data_ok, rdata); endinterface -interface sramro_i(); - logic req; - word_t addr; - logic addr_ok; - logic data_ok; - word_t rdata; +interface sramro_i (); + logic req; + word_t addr; + logic addr_ok; + logic data_ok; + word_t rdata; - modport master(output req, addr, input addr_ok, data_ok, rdata); - modport slave(input req, addr, output addr_ok, data_ok, rdata); + modport master(output req, addr, input addr_ok, data_ok, rdata); + modport slave(input req, addr, output addr_ok, data_ok, rdata); endinterface