fix1
Co-authored-by: cxy004 <cxy004@qq.com> Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
This commit is contained in:
parent
834f6e446b
commit
b33c1a2297
@ -89,6 +89,8 @@ wire [3 :0] debug_wb1_rf_wen;
|
|||||||
wire [4 :0] debug_wb1_rf_wnum;
|
wire [4 :0] debug_wb1_rf_wnum;
|
||||||
wire [31:0] debug_wb1_rf_wdata;
|
wire [31:0] debug_wb1_rf_wdata;
|
||||||
|
|
||||||
|
wire debug_wb_pc_A;
|
||||||
|
|
||||||
//clk and resetn
|
//clk and resetn
|
||||||
wire cpu_clk;
|
wire cpu_clk;
|
||||||
wire sys_clk;
|
wire sys_clk;
|
||||||
@ -378,7 +380,9 @@ mycpu_top u_cpu(
|
|||||||
.debug_wb1_pc (debug_wb1_pc ),
|
.debug_wb1_pc (debug_wb1_pc ),
|
||||||
.debug_wb1_rf_wen (debug_wb1_rf_wen ),
|
.debug_wb1_rf_wen (debug_wb1_rf_wen ),
|
||||||
.debug_wb1_rf_wnum (debug_wb1_rf_wnum ),
|
.debug_wb1_rf_wnum (debug_wb1_rf_wnum ),
|
||||||
.debug_wb1_rf_wdata(debug_wb1_rf_wdata)
|
.debug_wb1_rf_wdata(debug_wb1_rf_wdata),
|
||||||
|
|
||||||
|
.debug_wb_pc_A (debug_wb_pc_A)
|
||||||
);
|
);
|
||||||
//cpu axi wrap
|
//cpu axi wrap
|
||||||
axi_wrap u_cpu_axi_wrap(
|
axi_wrap u_cpu_axi_wrap(
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
`define SIMULATION_PC
|
||||||
`define TRACE_REF_FILE "../../../../../../../cpu132_gettrace/golden_trace.txt"
|
`define TRACE_REF_FILE "../../../../../../../cpu132_gettrace/golden_trace.txt"
|
||||||
`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
|
`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
|
||||||
`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
|
`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
|
||||||
@ -113,7 +114,6 @@ module tb2_top ();
|
|||||||
TRACE_INFO ref_trace[$];
|
TRACE_INFO ref_trace[$];
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
ref_trace.clear();
|
|
||||||
while (!$feof(
|
while (!$feof(
|
||||||
trace_ref
|
trace_ref
|
||||||
)) begin
|
)) begin
|
||||||
@ -135,7 +135,7 @@ module tb2_top ();
|
|||||||
logic [ 4:0] dbg_1_rf_wnum;
|
logic [ 4:0] dbg_1_rf_wnum;
|
||||||
logic [31:0] dbg_1_rf_wdata;
|
logic [31:0] dbg_1_rf_wdata;
|
||||||
|
|
||||||
always_ff @(posedge cpu_clk) begin
|
always @(posedge cpu_clk) begin
|
||||||
#2;
|
#2;
|
||||||
if (!resetn) begin
|
if (!resetn) begin
|
||||||
debug_wb_err <= 1'b0;
|
debug_wb_err <= 1'b0;
|
||||||
@ -165,14 +165,14 @@ module tb2_top ();
|
|||||||
if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0) begin
|
if (|dbg_0_rf_wen && dbg_0_rf_wnum != 5'd0) begin
|
||||||
if ( (dbg_0_pc !== ref_trace[0].ref_wb_pc )
|
if ( (dbg_0_pc !== ref_trace[0].ref_wb_pc )
|
||||||
|| (dbg_0_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|
|| (dbg_0_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|
||||||
|| (dbg_0_rf_wdata !== ref_trace[0].ref_wb_rf_wdata_v)
|
|| (dbg_0_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
|
||||||
)
|
)
|
||||||
begin
|
begin
|
||||||
$display("--------------------------------------------------------------");
|
$display("--------------------------------------------------------------");
|
||||||
$display("[%t] Error!!!", $time);
|
$display("[%t] Error!!!", $time);
|
||||||
$display(" reference: PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
|
$display(" reference: PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
|
||||||
ref_trace[0].ref_wb_pc, ref_trace[0].ref_wb_rf_wnum,
|
ref_trace[0].ref_wb_pc, ref_trace[0].ref_wb_rf_wnum,
|
||||||
ref_trace[0].ref_wb_rf_wdata_v);
|
ref_trace[0].ref_wb_rf_wdata);
|
||||||
$display(" mycpu : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_0_pc,
|
$display(" mycpu : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_0_pc,
|
||||||
dbg_0_rf_wnum, dbg_0_rf_wdata);
|
dbg_0_rf_wnum, dbg_0_rf_wdata);
|
||||||
$display("--------------------------------------------------------------");
|
$display("--------------------------------------------------------------");
|
||||||
@ -183,14 +183,14 @@ module tb2_top ();
|
|||||||
end else if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0) begin
|
end else if (|dbg_1_rf_wen && dbg_1_rf_wnum != 5'd0) begin
|
||||||
if ( (dbg_1_pc !== ref_trace[0].ref_wb_pc )
|
if ( (dbg_1_pc !== ref_trace[0].ref_wb_pc )
|
||||||
|| (dbg_1_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|
|| (dbg_1_rf_wnum !== ref_trace[0].ref_wb_rf_wnum )
|
||||||
|| (dbg_1_rf_wdata !== ref_trace[0].ref_wb_rf_wdata_v)
|
|| (dbg_1_rf_wdata !== ref_trace[0].ref_wb_rf_wdata)
|
||||||
)
|
)
|
||||||
begin
|
begin
|
||||||
$display("--------------------------------------------------------------");
|
$display("--------------------------------------------------------------");
|
||||||
$display("[%t] Error!!!", $time);
|
$display("[%t] Error!!!", $time);
|
||||||
$display(" reference: PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
|
$display(" reference: PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
|
||||||
ref_trace[0].ref_wb_pc, ref_trace[0].ref_wb_rf_wnum,
|
ref_trace[0].ref_wb_pc, ref_trace[0].ref_wb_rf_wnum,
|
||||||
ref_trace[0].ref_wb_rf_wdata_v);
|
ref_trace[0].ref_wb_rf_wdata);
|
||||||
$display(" mycpu : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_1_pc,
|
$display(" mycpu : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h", dbg_1_pc,
|
||||||
dbg_1_rf_wnum, dbg_1_rf_wdata);
|
dbg_1_rf_wnum, dbg_1_rf_wdata);
|
||||||
$display("--------------------------------------------------------------");
|
$display("--------------------------------------------------------------");
|
||||||
@ -246,7 +246,7 @@ module tb2_top ();
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
//模拟串口打印
|
//妯℃嫙涓插彛鎵撳嵃
|
||||||
logic uart_display;
|
logic uart_display;
|
||||||
logic [7:0] uart_data;
|
logic [7:0] uart_data;
|
||||||
assign uart_display = `CONFREG_UART_DISPLAY;
|
assign uart_display = `CONFREG_UART_DISPLAY;
|
||||||
@ -265,7 +265,7 @@ module tb2_top ();
|
|||||||
//test end
|
//test end
|
||||||
logic global_err = debug_wb_err || (err_count != 8'd0);
|
logic global_err = debug_wb_err || (err_count != 8'd0);
|
||||||
logic test_end = (dbg_0_pc == `END_PC) || (dbg_1_pc == `END_PC) || (uart_display && uart_data == 8'hff);
|
logic test_end = (dbg_0_pc == `END_PC) || (dbg_1_pc == `END_PC) || (uart_display && uart_data == 8'hff);
|
||||||
always_ff @(posedge cpu_clk) begin
|
always @(posedge cpu_clk) begin
|
||||||
if (!resetn) begin
|
if (!resetn) begin
|
||||||
debug_end <= 1'b0;
|
debug_end <= 1'b0;
|
||||||
end else if (test_end && !debug_end) begin
|
end else if (test_end && !debug_end) begin
|
||||||
|
@ -87,6 +87,9 @@ module AXI (
|
|||||||
inst.addr_ok = 1'b0;
|
inst.addr_ok = 1'b0;
|
||||||
rdata.addr_ok = 1'b0;
|
rdata.addr_ok = 1'b0;
|
||||||
end
|
end
|
||||||
|
end else begin
|
||||||
|
inst.addr_ok = 1'b0;
|
||||||
|
rdata.addr_ok = 1'b0;
|
||||||
end
|
end
|
||||||
|
|
||||||
end
|
end
|
||||||
|
@ -17,8 +17,8 @@ module Controller (
|
|||||||
);
|
);
|
||||||
|
|
||||||
mux3 #(32) imm_mux (
|
mux3 #(32) imm_mux (
|
||||||
{{16{inst[15]}}, inst[15:0]},
|
|
||||||
{16'b0, inst[15:0]},
|
{16'b0, inst[15:0]},
|
||||||
|
{{16{inst[15]}}, inst[15:0]},
|
||||||
{inst[15:0], 16'b0},
|
{inst[15:0], 16'b0},
|
||||||
{inst[28] & inst[27] & inst[26], inst[31] | ~inst[28]},
|
{inst[28] & inst[27] & inst[26], inst[31] | ~inst[28]},
|
||||||
imm
|
imm
|
||||||
@ -34,18 +34,16 @@ module Controller (
|
|||||||
assign ctrl.RS = inst[25:21];
|
assign ctrl.RS = inst[25:21];
|
||||||
assign ctrl.RT = inst[20:16];
|
assign ctrl.RT = inst[20:16];
|
||||||
|
|
||||||
assign ctrl.PFCtrl.PCS = {
|
assign ctrl.PFCtrl.PCS = PCS_t'({
|
||||||
~inst[28] & (~inst[27] & ~inst[26] & ~inst[31] & ~inst[30] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] | inst[27] & ~inst[29] & ~inst[31]),
|
~inst[28] & (~inst[27] & ~inst[26] & ~inst[31] & ~inst[30] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] | inst[27] & ~inst[29] & ~inst[31]),
|
||||||
~inst[26] & (~inst[27] & inst[28] & ~inst[31] & ~inst[29] & eq | inst[27] & ~inst[29] & (~inst[28] | eq & ltz)) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] & ~inst[30] & (~inst[28] & (~ltz & inst[16] | ltz & ~inst[16]) | inst[28] & ~eq) | inst[27] & (~inst[28] | ~eq | ~ltz))
|
~inst[26] & (~inst[27] & inst[28] & ~inst[31] & ~inst[29] & eq | inst[27] & ~inst[29] & (~inst[28] | eq & ltz)) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] & ~inst[30] & (~inst[28] & (~ltz & inst[16] | ltz & ~inst[16]) | inst[28] & ~eq) | inst[27] & (~inst[28] | ~eq | ~ltz))
|
||||||
};
|
});
|
||||||
assign ctrl.PFCtrl.BJRJ = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31];
|
assign ctrl.PFCtrl.BJRJ = ~inst[26] & (~inst[27] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[31] & ~inst[29]) | inst[27] & ~inst[29]) | inst[26] & ~inst[29] & ~inst[31];
|
||||||
assign ctrl.PFCtrl.BJR = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[27] & inst[28]);
|
assign ctrl.PFCtrl.BJR = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[29] & ~inst[31] & ~inst[27] & inst[3] & ~inst[4] & ~inst[5] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[29] & ~inst[31] & (~inst[27] | inst[27] & inst[28]);
|
||||||
assign ctrl.PFCtrl.BE = inst[28] & ~inst[29] & ~inst[31] & ~inst[27];
|
assign ctrl.PFCtrl.BE = inst[28] & ~inst[29] & ~inst[31] & ~inst[27];
|
||||||
|
|
||||||
assign ctrl.DCtrl.DP0 = ~inst[31];
|
assign ctrl.DCtrl.DP0 = ~inst[31];
|
||||||
assign ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25];
|
assign ctrl.DCtrl.DP1 = ~inst[30] & (~inst[26] & (~inst[29] & (~inst[28] & (~inst[31] & (~inst[27] & ~inst[4] | inst[27]) | inst[31]) | inst[28]) | inst[29]) | inst[26]) | inst[30] & inst[25];
|
||||||
assign ctrl.DCtrl.UI = inst[28] & inst[27] & inst[26];
|
|
||||||
assign ctrl.DCtrl.IX = ~inst[28] | inst[28] & inst[31];
|
|
||||||
|
|
||||||
assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & (~inst[2] | inst[1]);
|
assign ctrl.ECtrl.OP.f_sr = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & (~inst[2] | inst[1]);
|
||||||
assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & inst[2] & ~inst[1];
|
assign ctrl.ECtrl.OP.f_sl = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[3] & inst[2] & ~inst[1];
|
||||||
@ -56,25 +54,25 @@ module Controller (
|
|||||||
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
|
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
|
||||||
assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27]);
|
assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27]);
|
||||||
assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[29] & inst[1] & (inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]);
|
assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[29] & inst[1] & (inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]);
|
||||||
assign ctrl.ECtrl.SA = {
|
assign ctrl.ECtrl.SA = SA_t'({
|
||||||
((~inst[26] & ~inst[28] & (~inst[27] & ((~inst[2] & inst[3] & inst[4] | inst[2] & ~inst[3]) | inst[5]) | inst[30]) | inst[31]) | inst[29]),
|
((~inst[26] & ~inst[28] & (~inst[27] & ((~inst[2] & inst[3] & inst[4] | inst[2] & ~inst[3]) | inst[5]) | inst[30]) | inst[31]) | inst[29]),
|
||||||
~inst[30] & ((~inst[29] & (inst[3] | inst[2] | inst[4] | inst[5] | inst[27] | inst[28] | inst[26]) | inst[29] & (~inst[28] | ~inst[27] | ~inst[26])) | inst[31])
|
~inst[30] & ((~inst[29] & (inst[3] | inst[2] | inst[4] | inst[5] | inst[27] | inst[28] | inst[26]) | inst[29] & (~inst[28] | ~inst[27] | ~inst[26])) | inst[31])
|
||||||
};
|
});
|
||||||
assign ctrl.ECtrl.SB = {
|
assign ctrl.ECtrl.SB = SB_t'({
|
||||||
((inst[30] | inst[31]) | inst[29]),
|
((inst[30] | inst[31]) | inst[29]),
|
||||||
(~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27] | inst[31] | inst[28] | inst[30] | inst[29] | inst[26])
|
(~inst[5] & (~inst[1] & (~inst[0] & (~inst[3] & inst[4] | inst[3] & ~inst[4]) | inst[0] & (~inst[4] | ~inst[3])) | inst[1] & inst[4] & ~inst[3]) | inst[27] | inst[31] | inst[28] | inst[30] | inst[29] | inst[26])
|
||||||
};
|
});
|
||||||
|
|
||||||
|
|
||||||
assign ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[1] & inst[0] | inst[3]);
|
assign ctrl.MCtrl0.HW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (~inst[1] & inst[0] | inst[3]);
|
||||||
assign ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (inst[1] & inst[0] | inst[3]);
|
assign ctrl.MCtrl0.LW = ~inst[26] & ~inst[29] & ~inst[30] & ~inst[28] & ~inst[27] & inst[4] & (inst[1] & inst[0] | inst[3]);
|
||||||
assign ctrl.MCtrl0.HLS = {~inst[3], inst[1:0]};
|
assign ctrl.MCtrl0.HLS = HLS_t'({~inst[3], inst[1:0]});
|
||||||
assign ctrl.MCtrl0.C0D = inst[15:11];
|
assign ctrl.MCtrl0.C0D = inst[15:11];
|
||||||
assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
|
assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
|
||||||
assign ctrl.MCtrl0.RS0 = {
|
assign ctrl.MCtrl0.RS0 = RS0_t'({
|
||||||
(~inst[29] & ~inst[26] & inst[4] & ~inst[1] | inst[30]),
|
(~inst[29] & ~inst[26] & inst[4] & ~inst[1] | inst[30]),
|
||||||
(~inst[28] & (~inst[4] | inst[26]) | inst[29])
|
(~inst[28] & (~inst[4] | inst[26]) | inst[29])
|
||||||
};
|
});
|
||||||
|
|
||||||
assign ctrl.MCtrl1.MR = inst[31];
|
assign ctrl.MCtrl1.MR = inst[31];
|
||||||
assign ctrl.MCtrl1.MWR = inst[29];
|
assign ctrl.MCtrl1.MWR = inst[29];
|
||||||
|
@ -55,6 +55,9 @@ module Datapath (
|
|||||||
word_t PF_pcjr;
|
word_t PF_pcjr;
|
||||||
word_t PF_pc0;
|
word_t PF_pc0;
|
||||||
|
|
||||||
|
// F
|
||||||
|
logic F_valid;
|
||||||
|
|
||||||
// Instr Queue
|
// Instr Queue
|
||||||
logic IQ_IA_valid;
|
logic IQ_IA_valid;
|
||||||
word_t IQ_IA_inst;
|
word_t IQ_IA_inst;
|
||||||
@ -175,11 +178,6 @@ module Datapath (
|
|||||||
logic M_I0_FT_W_I1;
|
logic M_I0_FT_W_I1;
|
||||||
word_t M_I0_ForwardT;
|
word_t M_I0_ForwardT;
|
||||||
|
|
||||||
logic M_I1_FT_M_I0;
|
|
||||||
logic M_I1_FT_W_I0;
|
|
||||||
logic M_I1_FT_W_I1;
|
|
||||||
word_t M_I1_ForwardT;
|
|
||||||
|
|
||||||
word_t HI;
|
word_t HI;
|
||||||
word_t LO;
|
word_t LO;
|
||||||
|
|
||||||
@ -205,7 +203,7 @@ module Datapath (
|
|||||||
C0_EPC,
|
C0_EPC,
|
||||||
`PCEXC,
|
`PCEXC,
|
||||||
`PCRST,
|
`PCRST,
|
||||||
{rst, C0_exception.ExcValid, C0_exception.ERET, ~D_IA_valid},
|
{~F_valid, C0_exception.ExcValid, C0_exception.ERET, ~D_IA_valid},
|
||||||
PF.pc
|
PF.pc
|
||||||
);
|
);
|
||||||
|
|
||||||
@ -216,7 +214,12 @@ module Datapath (
|
|||||||
assign PF_go = PF.pc[1:0] == 2'b00
|
assign PF_go = PF.pc[1:0] == 2'b00
|
||||||
& ~D.IA_ExcValid & ~D.IB_ExcValid
|
& ~D.IA_ExcValid & ~D.IB_ExcValid
|
||||||
& ~E.I0.ExcValid & ~E.I1.ExcValid;
|
& ~E.I0.ExcValid & ~E.I1.ExcValid;
|
||||||
assign fetch_i.req = rst | C0_exception.ExcValid | C0_exception.ERET | ~D_IA_valid | F.en & PF_go;
|
assign fetch_i.req = rst | C0_exception.ExcValid | C0_exception.ERET | ~D_IA_valid | PF_go
|
||||||
|
& ~IQ_valids[3]
|
||||||
|
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_en0f)
|
||||||
|
| ~IQ_valids[1] & (~D_en0f & PF.pc[2] & F.pc[2] | D_en0f & (PF.pc[2] | F.pc[2] | D.en1))
|
||||||
|
| ~IQ_valids[0] & D_en0f & (~PF.pc[2] & F.pc[2] & D.en1 | PF.pc[2] & (F.pc[2] | D.en1))
|
||||||
|
| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_en0f & D.en1;
|
||||||
assign fetch_i.addr = PF.pc;
|
assign fetch_i.addr = PF.pc;
|
||||||
|
|
||||||
//---------------------------------------------------------------------------//
|
//---------------------------------------------------------------------------//
|
||||||
@ -224,19 +227,22 @@ module Datapath (
|
|||||||
//---------------------------------------------------------------------------//
|
//---------------------------------------------------------------------------//
|
||||||
|
|
||||||
// F.FF
|
// F.FF
|
||||||
|
ffenr #(1) F_valid_ff (
|
||||||
|
clk, rst,
|
||||||
|
1'b1,
|
||||||
|
1'b1,
|
||||||
|
F_valid
|
||||||
|
);
|
||||||
|
|
||||||
ffenr #(32) F_pc_ff (
|
ffenr #(32) F_pc_ff (
|
||||||
clk,
|
clk,
|
||||||
rst | rstD | rstM,
|
rst,
|
||||||
PF.pc,
|
PF.pc,
|
||||||
F.en,
|
F.en,
|
||||||
F.pc
|
F.pc
|
||||||
);
|
);
|
||||||
|
|
||||||
assign F.en = ~IQ_valids[3]
|
assign F.en = fetch_i.addr_ok;
|
||||||
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_en0f)
|
|
||||||
| ~IQ_valids[1] & (~D_en0f & PF.pc[2] & F.pc[2] | D_en0f & (PF.pc[2] | F.pc[2] | D.en1))
|
|
||||||
| ~IQ_valids[0] & D_en0f & (~PF.pc[2] & F.pc[2] & D.en1 | PF.pc[2] & (F.pc[2] | D.en1))
|
|
||||||
| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_en0f & D.en1;
|
|
||||||
|
|
||||||
//---------------------------------------------------------------------------//
|
//---------------------------------------------------------------------------//
|
||||||
// Instr Queue //
|
// Instr Queue //
|
||||||
@ -322,7 +328,7 @@ module Datapath (
|
|||||||
assign debug_wb1_rf_wnum = W.I1.RD;
|
assign debug_wb1_rf_wnum = W.I1.RD;
|
||||||
assign debug_wb1_rf_wdata = W.I1.RDataW;
|
assign debug_wb1_rf_wdata = W.I1.RDataW;
|
||||||
|
|
||||||
`ifndef SIMULATION
|
`ifndef SIMULATION_PC
|
||||||
assign debug_wb_pc = 32'hFFFFFFFF;
|
assign debug_wb_pc = 32'hFFFFFFFF;
|
||||||
assign debug_wb1_pc = 32'hFFFFFFFF;
|
assign debug_wb1_pc = 32'hFFFFFFFF;
|
||||||
`else
|
`else
|
||||||
@ -373,6 +379,8 @@ module Datapath (
|
|||||||
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ECtrl.SA == RS & E.I1.MCtrl.MR
|
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ECtrl.SA == RS & E.I1.MCtrl.MR
|
||||||
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
|
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
|
||||||
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ECtrl.SB == RT & E.I1.MCtrl.MR
|
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ECtrl.SB == RT & E.I1.MCtrl.MR
|
||||||
|
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR & D.IA.MCtrl1.MWR & E.I0.MCtrl.RS0 != ALUOut
|
||||||
|
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR & D.IA.MCtrl1.MWR & E.I1.MCtrl.MR
|
||||||
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.PFCtrl.BJR
|
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.PFCtrl.BJR
|
||||||
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.PFCtrl.BJR
|
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.PFCtrl.BJR
|
||||||
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.PFCtrl.BE
|
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.PFCtrl.BE
|
||||||
@ -386,8 +394,11 @@ module Datapath (
|
|||||||
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ECtrl.SA == RS & E.I1.MCtrl.MR
|
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ECtrl.SA == RS & E.I1.MCtrl.MR
|
||||||
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
|
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
|
||||||
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ECtrl.SB == RT & E.I1.MCtrl.MR
|
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ECtrl.SB == RT & E.I1.MCtrl.MR
|
||||||
|
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & ~D.IB.DCtrl.DP0 & D.IB.MCtrl1.MR & D.IB.MCtrl1.MWR & E.I0.MCtrl.RS0 != ALUOut
|
||||||
|
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & ~D.IB.DCtrl.DP0 & D.IB.MCtrl1.MR & D.IB.MCtrl1.MWR & E.I1.MCtrl.MR
|
||||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ECtrl.SA == RS
|
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ECtrl.SA == RS
|
||||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ECtrl.SB == RT
|
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ECtrl.SB == RT
|
||||||
|
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DCtrl.DP0 & D.IB.MCtrl1.MR & D.IB.MCtrl1.MWR
|
||||||
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS == HLRS & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR
|
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS == HLRS & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR
|
||||||
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DCtrl.DP1 & D.IB.MCtrl0.C0W & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR;
|
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DCtrl.DP1 & D.IB.MCtrl0.C0W & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR;
|
||||||
|
|
||||||
@ -511,7 +522,7 @@ module Datapath (
|
|||||||
{D.I0.ExcValid, D.I0.ERET, D.I0.ExcCode, D.I0.Delay, D.I0.OFA},
|
{D.I0.ExcValid, D.I0.ERET, D.I0.ExcCode, D.I0.Delay, D.I0.OFA},
|
||||||
E.en,
|
E.en,
|
||||||
~D_go,
|
~D_go,
|
||||||
{E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.Delay, E.I0.OFA}
|
{E_I0_PrevExcValid, E.I0.ERET, E_I0_PrevExcCode, E.I0.Delay, E.I0.OFA}
|
||||||
);
|
);
|
||||||
ffen #(5 + 5 + 32 + 32) E_I0_ST_ff (
|
ffen #(5 + 5 + 32 + 32) E_I0_ST_ff (
|
||||||
clk,
|
clk,
|
||||||
@ -523,7 +534,7 @@ module Datapath (
|
|||||||
clk,
|
clk,
|
||||||
{D.I0.imm, D.I0.sa},
|
{D.I0.imm, D.I0.sa},
|
||||||
E.en,
|
E.en,
|
||||||
{E.I0.imm, D.I0.sa}
|
{E.I0.imm, E.I0.sa}
|
||||||
);
|
);
|
||||||
ffenrc #(13) E_I0_ECtrl_ff (
|
ffenrc #(13) E_I0_ECtrl_ff (
|
||||||
clk,
|
clk,
|
||||||
@ -562,7 +573,7 @@ module Datapath (
|
|||||||
{D.I1.ExcValid, D.I1.ERET, D.I1.ExcCode, D.I1.Delay, D.I1.OFA},
|
{D.I1.ExcValid, D.I1.ERET, D.I1.ExcCode, D.I1.Delay, D.I1.OFA},
|
||||||
E.en,
|
E.en,
|
||||||
~D_go,
|
~D_go,
|
||||||
{E.I1.ExcValid, E.I1.ERET, E.I1.ExcCode, E.I1.Delay, E.I1.OFA}
|
{E_I1_PrevExcValid, E.I1.ERET, E_I1_PrevExcCode, E.I1.Delay, E.I1.OFA}
|
||||||
);
|
);
|
||||||
ffen #(5 + 5 + 32 + 32) E_I1_ST_ff (
|
ffen #(5 + 5 + 32 + 32) E_I1_ST_ff (
|
||||||
clk,
|
clk,
|
||||||
@ -574,7 +585,7 @@ module Datapath (
|
|||||||
clk,
|
clk,
|
||||||
{D.I1.imm, D.I1.sa},
|
{D.I1.imm, D.I1.sa},
|
||||||
E.en,
|
E.en,
|
||||||
{E.I1.imm, D.I1.sa}
|
{E.I1.imm, E.I1.sa}
|
||||||
);
|
);
|
||||||
ffenrc #(13) E_I1_ECtrl_ff (
|
ffenrc #(13) E_I1_ECtrl_ff (
|
||||||
clk,
|
clk,
|
||||||
@ -681,6 +692,7 @@ module Datapath (
|
|||||||
assign mem_i.req = E.I1.MCtrl.MR & ~E_I1_go & M.en;
|
assign mem_i.req = E.I1.MCtrl.MR & ~E_I1_go & M.en;
|
||||||
assign mem_i.wr = E.I1.MCtrl.MWR;
|
assign mem_i.wr = E.I1.MCtrl.MWR;
|
||||||
assign mem_i.addr = E.I1.ALUOut;
|
assign mem_i.addr = E.I1.ALUOut;
|
||||||
|
assign mem_i.wdata = E_I1_ForwardT;
|
||||||
|
|
||||||
assign E.en = E_go & M.en;
|
assign E.en = E_go & M.en;
|
||||||
assign E_go = ~mem_i.req | mem_i.addr_ok;
|
assign E_go = ~mem_i.req | mem_i.addr_ok;
|
||||||
@ -751,13 +763,13 @@ module Datapath (
|
|||||||
M.en,
|
M.en,
|
||||||
M.I0.pc
|
M.I0.pc
|
||||||
);
|
);
|
||||||
ffenrc #(1 + 1 + 5 + 32 + 1) M_I0_Exc_ff (
|
ffenrc #(1 + 1 + 5 + 1) M_I0_Exc_ff (
|
||||||
clk,
|
clk,
|
||||||
rst | rstM,
|
rst | rstM,
|
||||||
{E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.BadVAddr, E.I0.Delay},
|
{E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.Delay},
|
||||||
M.en,
|
M.en,
|
||||||
~E_go,
|
~E_go,
|
||||||
{M.I0.ExcValid, M.I0.ERET, M.I0.ExcCode, M.I0.BadVAddr, M.I0.Delay}
|
{M.I0.ExcValid, M.I0.ERET, M.I0.ExcCode, M.I0.Delay}
|
||||||
);
|
);
|
||||||
ffen #(5 + 5 + 32 + 32) M_I0_ST_ff (
|
ffen #(5 + 5 + 32 + 32) M_I0_ST_ff (
|
||||||
clk,
|
clk,
|
||||||
@ -851,6 +863,7 @@ module Datapath (
|
|||||||
);
|
);
|
||||||
|
|
||||||
// M.Exc
|
// M.Exc
|
||||||
|
assign M.I0.BadVAddr = M.I0.pc;
|
||||||
assign C0_exception = M.I1.ExcValid & M.A ? {
|
assign C0_exception = M.I1.ExcValid & M.A ? {
|
||||||
M.I1.ExcValid, M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET
|
M.I1.ExcValid, M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET
|
||||||
} : {
|
} : {
|
||||||
@ -966,17 +979,6 @@ module Datapath (
|
|||||||
M_I0_ForwardT
|
M_I0_ForwardT
|
||||||
);
|
);
|
||||||
|
|
||||||
assign M_I1_FT_M_I0 = ~M.A & M.I0.WCtrl.RW & M.I1.RT == M.I0.RD;
|
|
||||||
assign M_I1_FT_W_I0 = W.I0.WCtrl.RW & M.I1.RT == W.I0.RD;
|
|
||||||
assign M_I1_FT_W_I1 = W.I1.WCtrl.RW & M.I1.RT == W.I1.RD;
|
|
||||||
mux3 #(32) M_I1_ForwardT_mux (
|
|
||||||
M.I1.T,
|
|
||||||
(~M_I1_FT_W_I0 | M_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
|
|
||||||
M.I0.ALUOut,
|
|
||||||
{M_I1_FT_M_I0, M_I1_FT_W_I0 | M_I1_FT_W_I1},
|
|
||||||
M_I1_ForwardT
|
|
||||||
);
|
|
||||||
|
|
||||||
//----------------------------------------------------------------------------//
|
//----------------------------------------------------------------------------//
|
||||||
// Write-Back Stage //
|
// Write-Back Stage //
|
||||||
//----------------------------------------------------------------------------//
|
//----------------------------------------------------------------------------//
|
||||||
@ -1016,7 +1018,7 @@ module Datapath (
|
|||||||
~M_go,
|
~M_go,
|
||||||
{W.I1.RD, W.I1.WCtrl}
|
{W.I1.RD, W.I1.WCtrl}
|
||||||
);
|
);
|
||||||
`ifdef SIMULATION
|
`ifdef SIMULATION_PC
|
||||||
ffenrc #(64) W_I01_pc_ff (
|
ffenrc #(64) W_I01_pc_ff (
|
||||||
clk,
|
clk,
|
||||||
rst,
|
rst,
|
||||||
|
@ -8,7 +8,7 @@ module MMU (
|
|||||||
input clk, rst,
|
input clk, rst,
|
||||||
input inst_rst,
|
input inst_rst,
|
||||||
|
|
||||||
input logic [1:0] K0,
|
input logic [2:0] K0,
|
||||||
|
|
||||||
ICache_i.mmu ic,
|
ICache_i.mmu ic,
|
||||||
DCache_i.mmu dc,
|
DCache_i.mmu dc,
|
||||||
@ -429,7 +429,7 @@ module MMU (
|
|||||||
if (~wdata_axi.data_ok) dwNextState = DW_WB;
|
if (~wdata_axi.data_ok) dwNextState = DW_WB;
|
||||||
else begin
|
else begin
|
||||||
// fixme: AXI3 wait WA
|
// fixme: AXI3 wait WA
|
||||||
if (drState == DR_REFILL) $error("drState == DR_REFILL");
|
// if (drState == DR_REFILL) $error("drState == DR_REFILL");
|
||||||
dwNextState = DW_WAITR;
|
dwNextState = DW_WAITR;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -454,7 +454,7 @@ module MMU (
|
|||||||
if (~wdata_axi.data_ok) dwNextState = DW_WB;
|
if (~wdata_axi.data_ok) dwNextState = DW_WB;
|
||||||
else begin
|
else begin
|
||||||
// fixme: AXI3 wait WA
|
// fixme: AXI3 wait WA
|
||||||
if (drState != DR_REFILL) $error("drState != DR_REFILL");
|
// if (drState != DR_REFILL) $error("drState != DR_REFILL");
|
||||||
dwNextState = DW_IDLE;
|
dwNextState = DW_IDLE;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -590,7 +590,7 @@ module MMU (
|
|||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
module mapping (
|
module mapping (
|
||||||
input logic [1:0] K0,
|
input logic [2:0] K0,
|
||||||
input word_t addr_in,
|
input word_t addr_in,
|
||||||
output word_t addr_out,
|
output word_t addr_out,
|
||||||
output logic cached
|
output logic cached
|
||||||
@ -604,7 +604,7 @@ module mapping (
|
|||||||
cached = 0;
|
cached = 0;
|
||||||
end else begin // kseg0 -> CP0.K0 default: uncached
|
end else begin // kseg0 -> CP0.K0 default: uncached
|
||||||
addr_out = addr_in & 32'h1FFF_FFFF;
|
addr_out = addr_in & 32'h1FFF_FFFF;
|
||||||
cached = (K0 == 2'b11);
|
cached = (K0 == 3'b011);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
endmodule
|
endmodule
|
||||||
|
21
src/MyCPU.sv
21
src/MyCPU.sv
@ -86,7 +86,9 @@ module mycpu_top (
|
|||||||
word_t C0_wdata;
|
word_t C0_wdata;
|
||||||
EXCEPTION_t C0_exception;
|
EXCEPTION_t C0_exception;
|
||||||
word_t C0_EPC;
|
word_t C0_EPC;
|
||||||
logic [1:0] K0;
|
logic [2:0] K0;
|
||||||
|
|
||||||
|
logic inst_rst;
|
||||||
|
|
||||||
|
|
||||||
AXI axi (
|
AXI axi (
|
||||||
@ -102,6 +104,7 @@ module mycpu_top (
|
|||||||
MMU mmu (
|
MMU mmu (
|
||||||
.clk (aclk),
|
.clk (aclk),
|
||||||
.rst (~aresetn),
|
.rst (~aresetn),
|
||||||
|
.inst_rst (inst_rst),
|
||||||
.K0 (K0),
|
.K0 (K0),
|
||||||
.ic (icache.mmu),
|
.ic (icache.mmu),
|
||||||
.dc (dcache.mmu),
|
.dc (dcache.mmu),
|
||||||
@ -112,13 +115,13 @@ module mycpu_top (
|
|||||||
.wdata_axi(wdata_axi.master)
|
.wdata_axi(wdata_axi.master)
|
||||||
);
|
);
|
||||||
|
|
||||||
ICache icache (
|
ICache ICache (
|
||||||
.clk (aclk),
|
.clk (aclk),
|
||||||
.rst (~aresetn),
|
.rst (~aresetn),
|
||||||
.port(icache.cache)
|
.port(icache.cache)
|
||||||
);
|
);
|
||||||
|
|
||||||
DCache dcache (
|
DCache DCache (
|
||||||
.clk (aclk),
|
.clk (aclk),
|
||||||
.rst (~aresetn),
|
.rst (~aresetn),
|
||||||
.port(dcache.cache)
|
.port(dcache.cache)
|
||||||
@ -138,15 +141,25 @@ module mycpu_top (
|
|||||||
|
|
||||||
Datapath datapath (
|
Datapath datapath (
|
||||||
.clk (aclk),
|
.clk (aclk),
|
||||||
.rst (aresetn),
|
.rst (~aresetn),
|
||||||
.fetch_i (inst.master),
|
.fetch_i (inst.master),
|
||||||
.mem_i (data.master),
|
.mem_i (data.master),
|
||||||
|
.inst_rst (inst_rst),
|
||||||
.C0_addr (C0_addr),
|
.C0_addr (C0_addr),
|
||||||
.C0_rdata (C0_rdata),
|
.C0_rdata (C0_rdata),
|
||||||
.C0_we (C0_we),
|
.C0_we (C0_we),
|
||||||
.C0_wdata (C0_wdata),
|
.C0_wdata (C0_wdata),
|
||||||
.C0_exception (C0_exception),
|
.C0_exception (C0_exception),
|
||||||
.C0_EPC (C0_EPC),
|
.C0_EPC (C0_EPC),
|
||||||
|
.debug_wb_pc (debug_wb_pc),
|
||||||
|
.debug_wb_rf_wen (debug_wb_rf_wen),
|
||||||
|
.debug_wb_rf_wnum (debug_wb_rf_wnum),
|
||||||
|
.debug_wb_rf_wdata (debug_wb_rf_wdata),
|
||||||
|
.debug_wb1_pc (debug_wb1_pc),
|
||||||
|
.debug_wb1_rf_wen (debug_wb1_rf_wen),
|
||||||
|
.debug_wb1_rf_wnum (debug_wb1_rf_wnum),
|
||||||
|
.debug_wb1_rf_wdata(debug_wb1_rf_wdata),
|
||||||
|
.debug_wb_pc_A (debug_wb_pc_A),
|
||||||
.test_addr (),
|
.test_addr (),
|
||||||
.test_data ()
|
.test_data ()
|
||||||
);
|
);
|
||||||
|
@ -83,8 +83,6 @@ typedef struct packed {
|
|||||||
typedef struct packed {
|
typedef struct packed {
|
||||||
logic DP0;
|
logic DP0;
|
||||||
logic DP1;
|
logic DP1;
|
||||||
logic UI;
|
|
||||||
logic IX;
|
|
||||||
} DCtrl_t;
|
} DCtrl_t;
|
||||||
|
|
||||||
typedef struct packed {
|
typedef struct packed {
|
||||||
@ -229,7 +227,6 @@ typedef struct packed {
|
|||||||
logic ExcValid;
|
logic ExcValid;
|
||||||
logic ERET;
|
logic ERET;
|
||||||
logic [4:0] ExcCode;
|
logic [4:0] ExcCode;
|
||||||
word_t BadVAddr;
|
|
||||||
logic Delay;
|
logic Delay;
|
||||||
logic OFA;
|
logic OFA;
|
||||||
|
|
||||||
@ -340,7 +337,7 @@ typedef struct packed {
|
|||||||
logic A;
|
logic A;
|
||||||
|
|
||||||
struct packed {
|
struct packed {
|
||||||
`ifdef SIMULATION
|
`ifdef SIMULATION_PC
|
||||||
word_t pc;
|
word_t pc;
|
||||||
`endif
|
`endif
|
||||||
word_t RDataW;
|
word_t RDataW;
|
||||||
@ -350,7 +347,7 @@ typedef struct packed {
|
|||||||
} I0;
|
} I0;
|
||||||
|
|
||||||
struct packed {
|
struct packed {
|
||||||
`ifdef SIMULATION
|
`ifdef SIMULATION_PC
|
||||||
word_t pc;
|
word_t pc;
|
||||||
`endif
|
`endif
|
||||||
word_t RDataW;
|
word_t RDataW;
|
||||||
|
Loading…
Reference in New Issue
Block a user