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Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
Co-authored-by: cxy004 <cxy004@qq.com>
This commit is contained in:
Paul Pan 2021-07-28 17:30:29 +08:00
parent ebcd281f4b
commit 834f6e446b
12 changed files with 372 additions and 174 deletions
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2
src/CP0/CP0.sv
View File

@ -28,7 +28,7 @@ module CP0 (
end else if (clk) begin
if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
else begin
if (exception.valid && rf_cp0.Status.EXL == 1'b0) begin
if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
rf_cp0.Cause.ExcCode = exception.ExcCode;
if (exception.ExcCode == 4 || exception.ExcCode == 5)
rf_cp0.BadVAddr = exception.BadVAddr;

2
src/Core/Controller.sv
View File

@ -52,7 +52,7 @@ module Controller (
assign ctrl.ECtrl.OP.f_add = ((~inst[26] & ~inst[28] & ~inst[27] & ((~inst[5] & inst[3] | inst[5] & ~inst[3] & ~inst[2]) | inst[29]) | inst[26] & (~inst[29] | (~inst[28] & ~inst[27] | inst[28] & inst[27]))) | inst[31]);
assign ctrl.ECtrl.OP.f_slt = ~inst[31] & ~inst[26] & ~inst[28] & (~inst[29] & inst[5] & inst[3] & ~inst[2] & ~inst[0] | inst[27]);
assign ctrl.ECtrl.OP.f_sltu = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & ~inst[2] & inst[3] & inst[0] | inst[26] & inst[29] & ~inst[28] & inst[27]);
assign ctrl.ECtrl.OP.f_ans = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27]);
assign ctrl.ECtrl.OP.f_and = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & ~inst[1] | inst[28] & ~inst[27]);
assign ctrl.ECtrl.OP.f_xor = ~inst[31] & ~inst[26] & (~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & ~inst[0] & inst[1] | inst[28] & inst[27]);
assign ctrl.ECtrl.OP.f_or = ~inst[31] & (~inst[26] & ~inst[28] & ~inst[27] & ~inst[29] & inst[5] & inst[2] & inst[0] | inst[26] & inst[29] & inst[28] & ~inst[27]);
assign ctrl.ECtrl.OP.alt = ~inst[31] & (~inst[26] & (~inst[29] & inst[1] & (inst[0] | inst[5]) | inst[27]) | inst[26] & inst[27] & inst[29] & ~inst[28]);

211
src/Core/Datapath.sv
View File

@ -8,6 +8,7 @@ module Datapath (
// MMU
sramro_i.master fetch_i,
sram_i.master mem_i,
output inst_rst,
// CP0
output logic [4:0] C0_addr,
@ -19,9 +20,24 @@ module Datapath (
// test RF
input logic [4:0] test_addr,
output word_t test_data
output word_t test_data,
//debug interface
output wire [31:0] debug_wb_pc,
output wire [ 3:0] debug_wb_rf_wen,
output wire [ 4:0] debug_wb_rf_wnum,
output wire [31:0] debug_wb_rf_wdata,
output wire [31:0] debug_wb1_pc,
output wire [ 3:0] debug_wb1_rf_wen,
output wire [ 4:0] debug_wb1_rf_wnum,
output wire [31:0] debug_wb1_rf_wdata,
output wire debug_wb_pc_A
);
logic rstD, rstM;
PF_t PF;
F_t F;
D_t D;
@ -149,19 +165,19 @@ module Datapath (
word_t M_I0_HI;
word_t M_I0_LO;
word_t M_I0_FS_M_I1;
word_t M_I0_FS_W_I0;
word_t M_I0_FS_W_I1;
logic M_I0_FS_M_I1;
logic M_I0_FS_W_I0;
logic M_I0_FS_W_I1;
word_t M_I0_ForwardS;
word_t M_I0_FT_M_I1;
word_t M_I0_FT_W_I0;
word_t M_I0_FT_W_I1;
logic M_I0_FT_M_I1;
logic M_I0_FT_W_I0;
logic M_I0_FT_W_I1;
word_t M_I0_ForwardT;
word_t M_I1_FT_M_I0;
word_t M_I1_FT_W_I0;
word_t M_I1_FT_W_I1;
logic M_I1_FT_M_I0;
logic M_I1_FT_W_I0;
logic M_I1_FT_W_I1;
word_t M_I1_ForwardT;
word_t HI;
@ -180,7 +196,7 @@ module Datapath (
PF_pcb,
PF_pcjr,
PF_pcj,
D.IA.PCS,
D.IA.PFCtrl.PCS,
PF_pc0
);
prio_mux5 #(32) PF_pc_mux (
@ -193,8 +209,14 @@ module Datapath (
PF.pc
);
assign PF_go = (PF.pc[1:0] == 2'b00);
assign fetch_i.req = F.en & PF_go;
assign rstD = D.IA.PFCtrl.PCS != PCP8;
assign rstM = C0_exception.ExcValid | C0_exception.ERET;
assign inst_rst = rstD;
assign PF_go = PF.pc[1:0] == 2'b00
& ~D.IA_ExcValid & ~D.IB_ExcValid
& ~E.I0.ExcValid & ~E.I1.ExcValid;
assign fetch_i.req = rst | C0_exception.ExcValid | C0_exception.ERET | ~D_IA_valid | F.en & PF_go;
assign fetch_i.addr = PF.pc;
//---------------------------------------------------------------------------//
@ -204,13 +226,17 @@ module Datapath (
// F.FF
ffenr #(32) F_pc_ff (
clk,
rst,
rst | rstD | rstM,
PF.pc,
F.en,
F.pc
);
assign F.en = ~IQ_valids[3] | (~IQ_valids[2] & (F.pc[2] | PF.pc[2] | D_en0f) | IQ_valids[2] & (~IQ_valids[1] & (~D_en0f & PF.pc[2] & F.pc[2] | D_en0f & (D.en1 | F.pc[2] | PF.pc[2])) | IQ_valids[1] & D_en0f & (~PF.pc[2] & F.pc[2] & D.en1 & ~IQ_valids[0] | PF.pc[2] & (~F.pc[2] & D.en1 & ~IQ_valids[0] | F.pc[2] & (~IQ_valids[0] | D.en1)))));
assign F.en = ~IQ_valids[3]
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_en0f)
| ~IQ_valids[1] & (~D_en0f & PF.pc[2] & F.pc[2] | D_en0f & (PF.pc[2] | F.pc[2] | D.en1))
| ~IQ_valids[0] & D_en0f & (~PF.pc[2] & F.pc[2] & D.en1 | PF.pc[2] & (F.pc[2] | D.en1))
| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_en0f & D.en1;
//---------------------------------------------------------------------------//
// Instr Queue //
@ -218,7 +244,7 @@ module Datapath (
InstrQueue InstrQueue (
.clk(clk),
.rst(rst),
.rst(rst | rstD | rstM),
.vinA(fetch_i.data_ok),
.inA (F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0),
@ -252,14 +278,14 @@ module Datapath (
ffenr #(1 + 32 + 32) D_IA_ff (
clk,
rst,
rst | rstD | rstM,
D.en1 ? {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst} : {D_IB_valid, D.IB_pc, D.IB_inst},
D.en0,
{D_IA_valid, D.IA_pc, D.IA_instr}
{D_IA_valid, D.IA_pc, D.IA_inst}
);
ffenr #(1 + 32 + 32) D_IB_ff (
clk,
rst,
rst | rstD | rstM,
D.en1 ? {IQ_IB_valid, IQ_IB_pc, IQ_IB_inst} : {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst},
D.en0,
{D_IB_valid, D.IB_pc, D.IB_inst}
@ -286,6 +312,24 @@ module Datapath (
.test_data(test_data)
);
assign debug_wb_pc_A = W.A;
assign debug_wb_rf_wen = {4{W.I0.WCtrl.RW}};
assign debug_wb_rf_wnum = W.I0.RD;
assign debug_wb_rf_wdata = W.I0.RDataW;
assign debug_wb1_rf_wen = {4{W.I1.WCtrl.RW}};
assign debug_wb1_rf_wnum = W.I1.RD;
assign debug_wb1_rf_wdata = W.I1.RDataW;
`ifndef SIMULATION
assign debug_wb_pc = 32'hFFFFFFFF;
assign debug_wb1_pc = 32'hFFFFFFFF;
`else
assign debug_wb_pc = W.I0.pc;
assign debug_wb1_pc = W.I1.pc;
`endif
// D.Decode
Controller D_IA_ctrl (
.inst(D.IA_inst),
@ -325,32 +369,32 @@ module Datapath (
assign D.IB_Delay = D.IA.PFCtrl.BJRJ;
// D.Dispatch
assign D_IA_DataHazard = E.I0.RW & D.IA.RS == E.I0.RD & D.IA.SA == RS & E.I0.RS0 != ALUOut
| E.I1.RW & D.IA.RS == E.I1.RD & D.IA.SA == RS & E.I1.MR
| E.I0.RW & D.IA.RT == E.I0.RD & D.IA.SB == RT & E.I0.RS0 != ALUOut
| E.I1.RW & D.IA.RT == E.I1.RD & D.IA.SB == RT & E.I1.MR
| E.I0.RW & D.IA.RS == E.I0.RD & D.IA.BJR
| E.I1.RW & D.IA.RS == E.I1.RD & D.IA.BJR
| E.I0.RW & D.IA.RT == E.I0.RD & D.IA.BE
| E.I1.RW & D.IA.RT == E.I1.RD & D.IA.BE
| M.I0.RW & D.IA.RS == M.I0.RD & D.IA.BJR & M.I0.RS0 != ALUOut
| M.I1.RW & D.IA.RS == M.I1.RD & D.IA.BJR & M.I1.MR
| M.I0.RW & D.IA.RT == M.I0.RD & D.IA.BE & M.I0.RS0 != ALUOut
| M.I1.RW & D.IA.RT == M.I1.RD & D.IA.BE & M.I1.MR;
assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ECtrl.SA == RS & E.I0.MCtrl.RS0 != ALUOut
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ECtrl.SA == RS & E.I1.MCtrl.MR
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ECtrl.SB == RT & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.PFCtrl.BJR
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.PFCtrl.BJR
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.PFCtrl.BE
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.PFCtrl.BE
| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.PFCtrl.BJR & M.I0.MCtrl.RS0 != ALUOut
| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.PFCtrl.BJR & M.I1.MCtrl.MR
| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.PFCtrl.BE & M.I0.MCtrl.RS0 != ALUOut
| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.PFCtrl.BE & M.I1.MCtrl.MR;
assign D_IB_DataHazard = E.I0.RW & D.IB.RS == E.I0.RD & D.IB.SA == RS & E.I0.RS0 != ALUOut
| E.I1.RW & D.IB.RS == E.I1.RD & D.IB.SA == RS & E.I1.MR
| E.I0.RW & D.IB.RT == E.I0.RD & D.IB.SB == RT & E.I0.RS0 != ALUOut
| E.I1.RW & D.IB.RT == E.I1.RD & D.IB.SB == RT & E.I1.MR
| D.IA.RW & D.IB.RS == D.IA.RD & D.IB.SA == RS
| D.IA.RW & D.IB.RT == D.IA.RD & D.IB.SB == RT
| D.IA.RW & D.IB.RS == D.IA.RD & (D.IB.HW | D.IB.LW) & D.IB.HLS == HLRS & D.IA.MR
| D.IA.RW & D.IB.RT == D.IA.RD & D.IB.C0W & D.IA.MR;
assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ECtrl.SA == RS & E.I0.MCtrl.RS0 != ALUOut
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ECtrl.SA == RS & E.I1.MCtrl.MR
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ECtrl.SB == RT & E.I0.MCtrl.RS0 != ALUOut
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ECtrl.SB == RT & E.I1.MCtrl.MR
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ECtrl.SA == RS
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ECtrl.SB == RT
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DCtrl.DP1 & (D.IB.MCtrl0.HW | D.IB.MCtrl0.LW) & D.IB.MCtrl0.HLS == HLRS & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DCtrl.DP1 & D.IB.MCtrl0.C0W & ~D.IA.DCtrl.DP0 & D.IA.MCtrl1.MR;
assign D.A = (D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IB.DP0 : D.IA.DP1;
assign D.A = (D.IA.DCtrl.DP0 & D.IA.DCtrl.DP1 | D.IA_ExcValid) ? D.IB.DCtrl.DP0 : D.IA.DCtrl.DP1;
assign D_IA_readygo = ~D_IA_DataHazard;
assign D_IB_readygo = ~D_IB_DataHazard & ~D.IB.BJRJ & (D.A ? D.IB.DP0 : D.IB.DP1);
assign D_IB_readygo = ~D_IB_DataHazard & ~D.IB.PFCtrl.BJRJ & (D.A ? D.IB.DCtrl.DP0 : D.IB.DCtrl.DP1);
assign D_en0f = ~D_IA_valid | (D_IA_readygo | D.IA_ExcValid) & E.en;
assign D.en0 = ~D_IA_valid | D_go & E.en;
@ -373,7 +417,7 @@ module Datapath (
assign D.I0.imm = D.A ? D.IB_imm : D.IA_imm;
assign D.I0.sa = D.A ? D.IB_sa : D.IA_sa;
assign D.I0.ECtrl = D.A ? D.IB.ECtrl : D.IA.ECtrl;
assign D.I0.MCtrl = D.A ? D.IB.MCtrl : D.IA.MCtrl;
assign D.I0.MCtrl = D.A ? D.IB.MCtrl0 : D.IA.MCtrl0;
assign D.I0.RD = D.A ? D.IB.RD : D.IA.RD;
assign D.I0.WCtrl = D.A ? D.IB.WCtrl : D.IA.WCtrl;
@ -386,12 +430,12 @@ module Datapath (
assign D.I1.OFA = D.A ? D.IA.OFA : D.IB.OFA;
assign D.I1.RS = D.A ? D.IA.RS : D.IB.RS;
assign D.I1.RT = D.A ? D.IA.RT : D.IB.RT;
assign D.I1.S = D.A ? D.IA_ForwardS : D.IB_ForwardS;
assign D.I1.T = D.A ? D.IA_ForwardT : D.IB_ForwardT;
assign D.I1.S = D.A ? D_IA_ForwardS : D_IB_ForwardS;
assign D.I1.T = D.A ? D_IA_ForwardT : D_IB_ForwardT;
assign D.I1.imm = D.A ? D.IA_imm : D.IB_imm;
assign D.I1.sa = D.A ? D.IA_sa : D.IB_sa;
assign D.I1.ECtrl = D.A ? D.IA.ECtrl : D.IB.ECtrl;
assign D.I1.MCtrl = D.A ? D.IA.MCtrl : D.IB.MCtrl;
assign D.I1.MCtrl = D.A ? D.IA.MCtrl1 : D.IB.MCtrl1;
assign D.I1.RD = D.A ? D.IA.RD : D.IB.RD;
assign D.I1.WCtrl = D.A ? D.IA.WCtrl : D.IB.WCtrl;
@ -461,13 +505,13 @@ module Datapath (
E.en,
E.I0.pc
);
ffenrc #(1 + 1 + 5 + 32 + 1 + 1) E_I0_Exc_ff (
ffenrc #(1 + 1 + 5 + 1 + 1) E_I0_Exc_ff (
clk,
rst,
{D.I0.ExcValid, D.I0.ERET, D.I0.ExcCode, D.I0.BadVAddr, D.I0.Delay, D.I0.OFA},
rst | rstM,
{D.I0.ExcValid, D.I0.ERET, D.I0.ExcCode, D.I0.Delay, D.I0.OFA},
E.en,
~D_go,
{E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.BadVAddr, E.I0.Delay, E.I0.OFA}
{E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.Delay, E.I0.OFA}
);
ffen #(5 + 5 + 32 + 32) E_I0_ST_ff (
clk,
@ -481,17 +525,17 @@ module Datapath (
E.en,
{E.I0.imm, D.I0.sa}
);
ffenrc #(10) E_I0_ECtrl_ff (
ffenrc #(13) E_I0_ECtrl_ff (
clk,
rst,
rst | rstM,
D.I0.ECtrl,
E.en,
~D_go | ~D_I0_go,
E.I0.ECtrl
);
ffenrc #(10) E_I0_MCtrl_ff (
ffenrc #(13) E_I0_MCtrl_ff (
clk,
rst,
rst | rstM,
D.I0.MCtrl,
E.en,
~D_go | ~D_I0_go,
@ -499,7 +543,7 @@ module Datapath (
);
ffenrc #(5 + 1) E_I0_WCtrl_ff (
clk,
rst,
rst | rstM,
{D.I0.RD, D.I0.WCtrl},
E.en,
~D_go | ~D_I0_go,
@ -512,13 +556,13 @@ module Datapath (
E.en,
E.I1.pc
);
ffenrc #(1 + 1 + 5 + 32 + 1 + 1) E_I1_Exc_ff (
ffenrc #(1 + 1 + 5 + 1 + 1) E_I1_Exc_ff (
clk,
rst,
{D.I1.ExcValid, D.I1.ERET, D.I1.ExcCode, D.I1.BadVAddr, D.I1.Delay, D.I1.OFA},
rst | rstM,
{D.I1.ExcValid, D.I1.ERET, D.I1.ExcCode, D.I1.Delay, D.I1.OFA},
E.en,
~D_go,
{E.I1.ExcValid, E.I1.ERET, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay, E.I1.OFA}
{E.I1.ExcValid, E.I1.ERET, E.I1.ExcCode, E.I1.Delay, E.I1.OFA}
);
ffen #(5 + 5 + 32 + 32) E_I1_ST_ff (
clk,
@ -532,17 +576,17 @@ module Datapath (
E.en,
{E.I1.imm, D.I1.sa}
);
ffenrc #(10) E_I1_ECtrl_ff (
ffenrc #(13) E_I1_ECtrl_ff (
clk,
rst,
rst | rstM,
D.I1.ECtrl,
E.en,
~D_go | ~D_I1_go,
E.I1.ECtrl
);
ffenrc #(10) E_I1_MCtrl_ff (
ffenrc #(5) E_I1_MCtrl_ff (
clk,
rst,
rst | rstM,
D.I1.MCtrl,
E.en,
~D_go | ~D_I1_go,
@ -550,7 +594,7 @@ module Datapath (
);
ffenrc #(5 + 1) E_I1_WCtrl_ff (
clk,
rst,
rst | rstM,
{D.I1.RD, D.I1.WCtrl},
E.en,
~D_go | ~D_I1_go,
@ -565,7 +609,7 @@ module Datapath (
assign E_I1_NowExcValid = E_I1_Overflow & E.I1.OFA | E.I1.MCtrl.MR & E_I1_STRBERROR;
assign E.I1.ExcValid = E_I1_PrevExcValid | E_I1_NowExcValid;
assign E.I1.ExcCode = E_I1_PrevExcValid ? E_I1_PrevExcCode : E_I1_Overflow & E.I1.OFA ? `EXCCODE_OF : E.I1.MCtrl.MWR ? `EXCCODE_ADDRW : `EXCCODE_ADDRR;
assign E.I1.BadVaddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut;
assign E.I1.BadVAddr = E_I1_PrevExcValid ? E.I1.pc : E.I1.ALUOut;
assign E_I0_go = ~E_I0_NowExcValid & (~E.A | ~E_I1_NowExcValid);
assign E_I1_go = ~E_I1_NowExcValid & (E.A | ~E_I0_NowExcValid);
@ -707,13 +751,13 @@ module Datapath (
M.en,
M.I0.pc
);
ffenrc #(1 + 1 + 5 + 32 + 1 + 1) M_I0_Exc_ff (
ffenrc #(1 + 1 + 5 + 32 + 1) M_I0_Exc_ff (
clk,
rst,
{E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.BadVAddr, E.I0.Delay, E.I0.OFA},
rst | rstM,
{E.I0.ExcValid, E.I0.ERET, E.I0.ExcCode, E.I0.BadVAddr, E.I0.Delay},
M.en,
~E_go,
{M.I0.ExcValid, M.I0.ERET, M.I0.ExcCode, M.I0.BadVAddr, M.I0.Delay, M.I0.OFA}
{M.I0.ExcValid, M.I0.ERET, M.I0.ExcCode, M.I0.BadVAddr, M.I0.Delay}
);
ffen #(5 + 5 + 32 + 32) M_I0_ST_ff (
clk,
@ -747,9 +791,9 @@ module Datapath (
M.I0.DIVUL
}
);
ffenrc #(10) M_I0_MCtrl_ff (
ffenrc #(13) M_I0_MCtrl_ff (
clk,
rst,
rst | rstM,
E.I0.MCtrl,
M.en,
~E_go | ~E_I0_go,
@ -757,7 +801,7 @@ module Datapath (
);
ffenrc #(5 + 1) M_I0_WCtrl_ff (
clk,
rst,
rst | rstM,
{E.I0.RD, E.I0.WCtrl},
M.en,
~E_go | ~E_I0_go,
@ -769,13 +813,13 @@ module Datapath (
M.en,
M.I1.pc
);
ffenrc #(1 + 1 + 5 + 32 + 1 + 1) M_I1_Exc_ff (
ffenrc #(1 + 1 + 5 + 32 + 1) M_I1_Exc_ff (
clk,
rst,
{E.I1.ExcValid, E.I1.ERET, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay, E.I1.OFA},
rst | rstM,
{E.I1.ExcValid, E.I1.ERET, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay},
M.en,
~E_go,
{M.I1.ExcValid, M.I1.ERET, M.I1.ExcCode, M.I1.BadVAddr, M.I1.Delay, M.I1.OFA}
{M.I1.ExcValid, M.I1.ERET, M.I1.ExcCode, M.I1.BadVAddr, M.I1.Delay}
);
ffen #(5 + 32) M_I1_T_ff (
clk,
@ -789,9 +833,9 @@ module Datapath (
M.en,
M.I1.ALUOut
);
ffenrc #(10) M_I1_MCtrl_ff (
ffenrc #(5) M_I1_MCtrl_ff (
clk,
rst,
rst | rstM,
E.I1.MCtrl,
M.en,
~E_go | ~E_I1_go,
@ -799,7 +843,7 @@ module Datapath (
);
ffenrc #(5 + 1) M_I1_WCtrl_ff (
clk,
rst,
rst | rstM,
{E.I1.RD, E.I1.WCtrl},
M.en,
~E_go | ~E_I1_go,
@ -972,6 +1016,17 @@ module Datapath (
~M_go,
{W.I1.RD, W.I1.WCtrl}
);
`ifdef SIMULATION
ffenrc #(64) W_I01_pc_ff (
clk,
rst,
{M.I0.pc, M.I1.pc},
M.en,
~M_go,
{W.I0.pc, W.I1.pc}
);
`endif
assign W.en = 1'b1;

82
src/Core/Issue.sv
View File

@ -1,82 +0,0 @@
// `include "sram.svh"
// module Issue(
// input clk, rst,
// sramro_i.master fetch_i);
// wire logic validF, goF1, goF2;
// wire logic enD, validD, goD;
// //----------------------------------------------------------------------------//
// //----------------------------------------------------------------------------//
// // pre-fetch
// // assign pcp8F = {pcF[31:3], 3'b000} + 8;
// // assign pcbF = pcF + {{14{instrD[15]}}, instrD[15:0], 2'b0};
// // assign pcjF = {pcF[31:28], instrD[25:0], 2'b0};
// // assign pcjrF = datasD;
// logic [31:0] pcp4F, pcp8F, pcF, nextpcF;
// logic [31:0] pcb1F, pcj1F, pcjr1F;
// logic [31:0] pcb2F, pcj2F, pcjr2F;
// logic [31:0] pcbF, pcjF, pcjrF;
// logic [31:0] EPCF;
// logic enF;
// logic [31:0] instrD;
// logic jsrcD;
// logic [2:0] pcsrcD;
// mux2#(96) pcj_mux({pcb1F, pcj1F, pcjr1F}, {pcb2F, pcj2F, pcjr2F}, jsrcD, {pcbF, pcjF, pcjrF});
// // mux6#(32) nextpc_mux(pcp4F, pcp8F, EPCF, pcbF, pcjF, pcjrF, pcsrcD, nextpcF);
// assign fetch_i.req = enF;
// assign fetch_i.addr = nextpcF;
// // fetch stage logic
// ffenr#(1) valid_ffF(clk, rst, 1'b1, enF, validF);
// pcenr pc_reg(clk, rst, nextpcF, enF, pcF);
// assign enF = fetch_i.data_ok;
// assign goF1 = validF & enF;
// assign goF2 = validF & enF;
// HandShake HS_iq_in1(), HS_iq_in2();
// HandShake HS_iq_out1(), HS_iq_out2();
// logic [31:0] instr_toD1, instr_toD2, pc_toD1, pc_toD2;
// logic iq_clear = 1'b0;
// // TODO: if allowin == 0?
// assign HS_iq_in1.readygo = goF1;
// assign HS_iq_in2.readygo = goF2;
// InstrQueue InstrQueue (
// .clk(clk),
// .rst(rst),
// .HandShake_in1(HS_iq_in1),
// .in1(fetch_i.rdata0),
// .pin1(pcF),
// .HandShake_in2(HS_iq_in2),
// .in2(fetch_i.rdata1),
// .pin2(pcF + 4),
// .HandShake_out1(HS_iq_out1),
// .out1(instr_toD1),
// .pout1(pc_toD1),
// .HandShake_out2(HS_iq_out2),
// .out2(instr_toD2),
// .pout2(pc_toD2),
// .clear(iq_clear) //flush, will ignore the current input, need to keep the input instr!
// );
// //----------------------------------------------------------------------------//
// //----------------------------------------------------------------------------//
// ffenr#(1) valid_ffD(clk, rst, goF1, enD, validD);
// ffen#(32) instr_ffD(clk, fetch_i.rdata0, enD, instrD);
// // controller
// // controller c(instrD, pcsrcD, rsD, rtD, rdD, immD);
// // register file (operates in decode and writeback)
// // RF rf(clk, rst, rsD, rtD, datasD, datatD, rdW, datawW, regwriteW);
// assign enD = fetch_i.addr_ok;
// // assign goD = validD & enD;
// assign goD = validD;
// endmodule

82
src/Core/Issue.sv.bak Normal file
View File

@ -0,0 +1,82 @@
`include "sram.svh"
module Issue(
input clk, rst,
sramro_i.master fetch_i);
wire logic validF, goF1, goF2;
wire logic enD, validD, goD;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
pre-fetch
assign pcp8F = {pcF[31:3], 3'b000} + 8;
assign pcbF = pcF + {{14{instrD[15]}}, instrD[15:0], 2'b0};
assign pcjF = {pcF[31:28], instrD[25:0], 2'b0};
assign pcjrF = datasD;
logic [31:0] pcp4F, pcp8F, pcF, nextpcF;
logic [31:0] pcb1F, pcj1F, pcjr1F;
logic [31:0] pcb2F, pcj2F, pcjr2F;
logic [31:0] pcbF, pcjF, pcjrF;
logic [31:0] EPCF;
logic enF;
logic [31:0] instrD;
logic jsrcD;
logic [2:0] pcsrcD;
mux2#(96) pcj_mux({pcb1F, pcj1F, pcjr1F}, {pcb2F, pcj2F, pcjr2F}, jsrcD, {pcbF, pcjF, pcjrF});
mux6#(32) nextpc_mux(pcp4F, pcp8F, EPCF, pcbF, pcjF, pcjrF, pcsrcD, nextpcF);
assign fetch_i.req = enF;
assign fetch_i.addr = nextpcF;
fetch stage logic
ffenr#(1) valid_ffF(clk, rst, 1'b1, enF, validF);
pcenr pc_reg(clk, rst, nextpcF, enF, pcF);
assign enF = fetch_i.data_ok;
assign goF1 = validF & enF;
assign goF2 = validF & enF;
HandShake HS_iq_in1(), HS_iq_in2();
HandShake HS_iq_out1(), HS_iq_out2();
logic [31:0] instr_toD1, instr_toD2, pc_toD1, pc_toD2;
logic iq_clear = 1'b0;
TODO: if allowin == 0?
assign HS_iq_in1.readygo = goF1;
assign HS_iq_in2.readygo = goF2;
InstrQueue InstrQueue (
.clk(clk),
.rst(rst),
.HandShake_in1(HS_iq_in1),
.in1(fetch_i.rdata0),
.pin1(pcF),
.HandShake_in2(HS_iq_in2),
.in2(fetch_i.rdata1),
.pin2(pcF + 4),
.HandShake_out1(HS_iq_out1),
.out1(instr_toD1),
.pout1(pc_toD1),
.HandShake_out2(HS_iq_out2),
.out2(instr_toD2),
.pout2(pc_toD2),
.clear(iq_clear) //flush, will ignore the current input, need to keep the input instr!
);
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffD(clk, rst, goF1, enD, validD);
ffen#(32) instr_ffD(clk, fetch_i.rdata0, enD, instrD);
controller
controller c(instrD, pcsrcD, rsD, rtD, rdD, immD);
register file (operates in decode and writeback)
RF rf(clk, rst, rsD, rtD, datasD, datatD, rdW, datawW, regwriteW);
assign enD = fetch_i.addr_ok;
assign goD = validD & enD;
assign goD = validD;
endmodule

0
src/Core/RF_ss.sv → src/Core/RF.sv.bak
View File

21
src/MMU/MMU.sv
View File

@ -5,8 +5,8 @@
`include "AXI.svh"
module MMU (
input clk,
rst,
input clk, rst,
input inst_rst,
input logic [1:0] K0,
@ -34,6 +34,9 @@ module MMU (
logic iCached1;
word_t iPA1;
logic inst_rst1;
logic idata_ok;
word_t iD1, iD2, iD3;
// ================================
@ -60,14 +63,14 @@ module MMU (
always_comb begin
iEn = 0;
iNextState = iState;
inst.data_ok = 0;
idata_ok = 0;
inst_axi.req = 0;
case (iState)
I_IDLE: begin
if (~iValid1) iEn = 1;
else if (iCached1 & ic.hit) begin
iEn = 1;
inst.data_ok = 1;
idata_ok = 1;
end else begin
inst_axi.req = 1;
if (~inst_axi.addr_ok) iNextState = I_WA;
@ -86,7 +89,7 @@ module MMU (
end
I_WD2: begin
if (inst_axi.rvalid) begin
inst.data_ok = 1;
idata_ok = 1;
if (iCached1) iNextState = I_WD3;
else begin
iEn = 1;
@ -150,12 +153,20 @@ module MMU (
iD3
);
ffenr #(1) inst_rst_ff (
clk, rst,
inst_rst,
inst_rst ^ idata_ok,
inst_rst1
);
// ===============================
// ========== iFunction ==========
// ===============================
assign iVA = inst.addr;
assign inst.addr_ok = iEn;
assign inst.data_ok = idata_ok & ~inst_rst & ~inst_rst1;
assign {inst.rdata1, inst.rdata0} = (iState == I_WD2) ? {
inst_axi.rdata, iD1
} : iPA1[3] ? ic.row[127:64] : ic.row[63:0];

132
src/MyCPU.sv
View File

@ -1,3 +1,11 @@
`include "defines.svh"
`include "AXI.svh"
`include "CP0.svh"
`include "DCache.svh"
`include "ICache.svh"
`include "sram.svh"
module mycpu_top (
input wire [5:0] ext_int, //high active
@ -59,4 +67,128 @@ module mycpu_top (
output wire debug_wb_pc_A
);
AXIRead_i axi_read ();
AXIWrite_i axi_write ();
SRAM_RO_AXI_i inst_axi ();
SRAM_RO_AXI_i rdata_axi ();
SRAM_W_AXI_i wdata_axi ();
ICache_i icache ();
DCache_i dcache ();
sramro_i inst ();
sram_i data ();
logic [4:0] C0_addr;
word_t C0_rdata;
logic C0_we;
word_t C0_wdata;
EXCEPTION_t C0_exception;
word_t C0_EPC;
logic [1:0] K0;
AXI axi (
.clk (aclk),
.rst (~aresetn),
.AXIRead (axi_read.master),
.AXIWrite(axi_write.master),
.inst (inst_axi.slave),
.rdata (rdata_axi.slave),
.wdata (wdata_axi.slave)
);
MMU mmu (
.clk (aclk),
.rst (~aresetn),
.K0 (K0),
.ic (icache.mmu),
.dc (dcache.mmu),
.inst (inst.slave),
.data (data.slave),
.inst_axi (inst_axi.master),
.rdata_axi(rdata_axi.master),
.wdata_axi(wdata_axi.master)
);
ICache icache (
.clk (aclk),
.rst (~aresetn),
.port(icache.cache)
);
DCache dcache (
.clk (aclk),
.rst (~aresetn),
.port(dcache.cache)
);
CP0 cp0 (
.clk(aclk),
.rst(~aresetn),
.addr(C0_addr),
.rdata(C0_rdata),
.en(C0_we),
.wdata(C0_wdata),
.exception(C0_exception),
.EPC(C0_EPC),
.K0(K0)
);
Datapath datapath (
.clk (aclk),
.rst (aresetn),
.fetch_i (inst.master),
.mem_i (data.master),
.C0_addr (C0_addr),
.C0_rdata (C0_rdata),
.C0_we (C0_we),
.C0_wdata (C0_wdata),
.C0_exception(C0_exception),
.C0_EPC (C0_EPC),
.test_addr (),
.test_data ()
);
assign axi_read.AXIReadData.arready = arready;
assign axi_read.AXIReadData.rid = rid;
assign axi_read.AXIReadData.rdata = rdata;
assign axi_read.AXIReadData.rresp = rresp;
assign axi_read.AXIReadData.rlast = rlast;
assign axi_read.AXIReadData.rvalid = rvalid;
assign arid = axi_read.AXIReadAddr.arid;
assign araddr = axi_read.AXIReadAddr.araddr;
assign arlen = axi_read.AXIReadAddr.arlen;
assign arsize = axi_read.AXIReadAddr.arsize;
assign arburst = axi_read.AXIReadAddr.arburst;
assign arlock = axi_read.AXIReadAddr.arlock;
assign arcache = axi_read.AXIReadAddr.arcache;
assign arprot = axi_read.AXIReadAddr.arprot;
assign arvalid = axi_read.AXIReadAddr.arvalid;
assign rready = axi_read.AXIReadAddr.rready;
assign axi_write.AXIWriteData.awready = awready;
assign axi_write.AXIWriteData.wready = wready;
assign axi_write.AXIWriteData.bid = bid;
assign axi_write.AXIWriteData.bresp = bresp;
assign axi_write.AXIWriteData.bvalid = bvalid;
assign awid = axi_write.AXIWriteAddr.awid;
assign awaddr = axi_write.AXIWriteAddr.awaddr;
assign awlen = axi_write.AXIWriteAddr.awlen;
assign awsize = axi_write.AXIWriteAddr.awsize;
assign awburst = axi_write.AXIWriteAddr.awburst;
assign awlock = axi_write.AXIWriteAddr.awlock;
assign awcache = axi_write.AXIWriteAddr.awcache;
assign awprot = axi_write.AXIWriteAddr.awprot;
assign awvalid = axi_write.AXIWriteAddr.awvalid;
assign wid = axi_write.AXIWriteAddr.wid;
assign wdata = axi_write.AXIWriteAddr.wdata;
assign wstrb = axi_write.AXIWriteAddr.wstrb;
assign wlast = axi_write.AXIWriteAddr.wlast;
assign wvalid = axi_write.AXIWriteAddr.wvalid;
assign bready = axi_write.AXIWriteAddr.bready;
endmodule

2
src/include/CP0.svh
View File

@ -2,7 +2,7 @@
`define CP0_SVH
typedef struct packed {
logic valid;
logic ExcValid;
logic delay;
logic [4:0] ExcCode;
logic [31:0] BadVAddr;

0
src/include/constants.svh → src/include/constants.svh.bak
View File

6
src/include/defines.svh
View File

@ -340,6 +340,9 @@ typedef struct packed {
logic A;
struct packed {
`ifdef SIMULATION
word_t pc;
`endif
word_t RDataW;
logic [4:0] RD;
@ -347,6 +350,9 @@ typedef struct packed {
} I0;
struct packed {
`ifdef SIMULATION
word_t pc;
`endif
word_t RDataW;
logic [4:0] RD;

6
src/testbench/happy/happy.sv
View File

@ -171,12 +171,6 @@ module happy ();
.port(dc.cache)
);
Issue issue (
.clk(clk),
.rst(rst),
.fetch_i(inst)
);
InstrQueue InstrQueue (
.clk(clk),
.rst(rst),