mul support
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@ -15,7 +15,8 @@ module Controller (
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inst[15:11],
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5'b11111,
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ctrl.RT,
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{inst[31] | inst[30] & ~inst[26] | inst[29], inst[26]},
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// {inst[31] | inst[30] & ~inst[26] | inst[29], inst[26]},
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{(~inst[29] & (inst[31] | inst[30]) | inst[29] & ~inst[30]), inst[26]},
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ctrl.RD
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);
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@ -41,7 +42,8 @@ module Controller (
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assign ctrl.OFA = ~inst[31] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[30] & inst[5] & ~inst[3] & ~inst[2] & ~inst[0] | inst[29]);
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assign ctrl.ES = inst[31] | ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | inst[4] & inst[3] & ~inst[2] | ~inst[3] & inst[2]) | inst[29];;
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assign ctrl.ET = ~inst[28] & (~inst[26] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[0] & (~inst[4] & ~inst[3] | inst[4] & inst[3]) | inst[0] & inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) & ~inst[30] & ~inst[27] | inst[26] & inst[31] & inst[29]);
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// assign ctrl.ET = ~inst[28] & (~inst[26] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) & ~inst[30] & ~inst[27] | inst[26] & inst[31] & inst[29]);
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assign ctrl.ET = ~inst[26] & ~inst[27] & (~inst[30] & ~inst[28] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) | inst[30] & inst[29]) | inst[26] & inst[31] & inst[29];
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assign ctrl.DS = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[26]));
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assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
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@ -63,10 +65,12 @@ module Controller (
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assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | ~inst[1] & inst[0]);
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assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | inst[1] & inst[0]);
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assign ctrl.MCtrl0.HLS = HLS_t'({~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & inst[3], inst[1:0]});
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// assign ctrl.MCtrl0.HLS = HLS_t'({~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & inst[3], inst[1:0]});
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assign ctrl.MCtrl0.HLS = HLS_t'({~inst[27] & ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & inst[4] & inst[3] | inst[29] & inst[30]), ~inst[30] & inst[1], inst[0]});
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assign ctrl.MCtrl0.C0D = inst[15:11];
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assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
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assign ctrl.MCtrl0.RS0 = RS0_t'({inst[29] | inst[26] | ~inst[4], inst[30] | ~inst[29] & ~inst[26] & inst[4] & ~inst[1]});
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// assign ctrl.MCtrl0.RS0 = RS0_t'({inst[29] | inst[26] | ~inst[4], inst[30] | ~inst[29] & ~inst[26] & inst[4] & ~inst[1]});
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assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (inst[29] | inst[26] | ~inst[4]), inst[30], ~inst[29] & (inst[30] | ~inst[1])});
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assign ctrl.MCtrl1.MR = inst[31];
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assign ctrl.MCtrl1.MWR = inst[29];
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@ -125,7 +125,7 @@ module Datapath (
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logic E_I0_NowExcValidWithoutOF;
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logic E_I0_ExcValidWithoutOF;
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logic E_I0_PrevExcValid;
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logic [ 4:0] E_I0_PrevExcCode;
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logic [4:0] E_I0_PrevExcCode;
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logic E_I0_PrevERET;
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word_t E_I1_A;
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@ -135,7 +135,7 @@ module Datapath (
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logic E_I1_NowExcValidWithoutOF;
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logic E_I1_ExcValidWithoutOF;
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logic E_I1_PrevExcValid;
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logic [ 4:0] E_I1_PrevExcCode;
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logic [4:0] E_I1_PrevExcCode;
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logic E_I1_PrevERET;
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logic E_I1_STRBERROR;
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@ -196,10 +196,9 @@ module Datapath (
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word_t M_I0_MULTUL;
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logic M_I0_MULT_bvalid;
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word_t M_I0_MULTHB;
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word_t M_I0_MULTLB;
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word_t M_I0_MULTHB;
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word_t M_I0_MULTUHB;
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word_t M_I0_MULTULB;
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word_t M_I0_HI;
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word_t M_I0_LO;
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@ -413,22 +412,22 @@ module Datapath (
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assign D.IB_Delay = D.IA.BJRJ;
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// D.Dispatch
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assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & E.I0.MCtrl.RS0 != ALUOut
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assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl.RS0[2]
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & E.I0.MCtrl.RS0 != ALUOut
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl.RS0[2]
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR
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| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT
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| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & M.I0.MCtrl.RS0 != ALUOut
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| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl.RS0[2]
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| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR
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| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & M.I0.MCtrl.RS0 != ALUOut
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| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl.RS0[2]
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| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR;
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assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & E.I0.MCtrl.RS0 != ALUOut
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assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl.RS0[2]
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| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
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| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & E.I0.MCtrl.RS0 != ALUOut
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| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl.RS0[2]
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| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
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| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
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@ -591,7 +590,7 @@ module Datapath (
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E.en,
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E.I0.ECtrl
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);
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ffenrc #(13) E_I0_MCtrl_ff (
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ffenrc #(14) E_I0_MCtrl_ff (
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clk,
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rst | rstM,
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D.I0.MCtrl,
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@ -875,7 +874,7 @@ module Datapath (
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M.en,
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M.I0.ALUOut
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);
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ffenrc #(13) M_I0_MCtrl_ff (
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ffenrc #(14) M_I0_MCtrl_ff (
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clk,
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rst | rstM,
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E.I0.MCtrl,
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@ -952,13 +951,13 @@ module Datapath (
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};
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// M.I0.MUL
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buffer #(128) M_I0_MULT_buffer (
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buffer #(96) M_I0_MULT_buffer (
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clk, rst,
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M_I0_MULT_CNTR[0],
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{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUL, M_I0_MULTUH},
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{M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH},
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M.en,
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M_I0_MULT_bvalid,
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{M_I0_MULTLB, M_I0_MULTHB, M_I0_MULTULB, M_I0_MULTUHB}
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{M_I0_MULTLB, M_I0_MULTHB, M_I0_MULTUHB}
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);
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// M.I0.DIV
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@ -980,17 +979,18 @@ module Datapath (
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);
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// M.I0.HILOC0
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mux4 #(32) M_I0_RDataW_mux (
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mux5 #(32) M_I0_RDataW_mux (
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LO,
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HI,
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M.I0.ALUOut,
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M_I0_MULTLB,
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C0_rdata,
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M.I0.ALUOut,
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M.I0.MCtrl.RS0,
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M.I0.RDataW
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);
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mux5 #(64) M_I0_HILO_mux (
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{M_I0_MULTHB, M_I0_MULTLB},
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{M_I0_MULTUHB, M_I0_MULTULB},
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{M_I0_MULTUHB, M_I0_MULTLB},
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{M_I0_DIVHB, M_I0_DIVLB},
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{M_I0_DIVUHB, M_I0_DIVULB},
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{M_I0_ForwardS, M_I0_ForwardS},
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@ -69,6 +69,7 @@ module instr_valid (
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32'b01000000000??????????00000000???: valid = 1'b1; // MFC0
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32'b01000000100??????????00000000???: valid = 1'b1; // MTC0
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32'b01000010000000000000000000011000: valid = 1'b1; // ERET
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32'b011100???????????????00000000010: valid = 1'b1; // MUL
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32'b100000??????????????????????????: valid = 1'b1; // LB
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32'b100001??????????????????????????: valid = 1'b1; // LH
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32'b100011??????????????????????????: valid = 1'b1; // LW
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@ -58,11 +58,12 @@ typedef enum logic [1:0] {
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IMM = 2'b11 // 2'b1?
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} SB_t;
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typedef enum logic [1:0] {
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LO = 2'b00,
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HI = 2'b01,
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ALUOut = 2'b10,
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C0 = 2'b11
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typedef enum logic [2:0] {
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LO = 3'b000,
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HI = 3'b001,
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MUL = 3'b010,
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C0 = 3'b011,
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ALUOut = 3'b100 // 3'b1??
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} RS0_t;
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typedef enum logic [2:0] {
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