From b2f32735d0d50a4e8403f31b63923dab4eb41c37 Mon Sep 17 00:00:00 2001 From: cxy004 Date: Wed, 4 Aug 2021 11:35:21 +0800 Subject: [PATCH] mul support --- src/Core/Controller.sv | 12 ++++++++---- src/Core/Datapath.sv | 36 ++++++++++++++++++------------------ src/Core/Gadgets.sv | 1 + src/include/defines.svh | 11 ++++++----- 4 files changed, 33 insertions(+), 27 deletions(-) diff --git a/src/Core/Controller.sv b/src/Core/Controller.sv index fb17a21..631f0b0 100644 --- a/src/Core/Controller.sv +++ b/src/Core/Controller.sv @@ -15,7 +15,8 @@ module Controller ( inst[15:11], 5'b11111, ctrl.RT, - {inst[31] | inst[30] & ~inst[26] | inst[29], inst[26]}, + // {inst[31] | inst[30] & ~inst[26] | inst[29], inst[26]}, + {(~inst[29] & (inst[31] | inst[30]) | inst[29] & ~inst[30]), inst[26]}, ctrl.RD ); @@ -41,7 +42,8 @@ module Controller ( assign ctrl.OFA = ~inst[31] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[30] & inst[5] & ~inst[3] & ~inst[2] & ~inst[0] | inst[29]); assign ctrl.ES = inst[31] | ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | inst[4] & inst[3] & ~inst[2] | ~inst[3] & inst[2]) | inst[29];; - assign ctrl.ET = ~inst[28] & (~inst[26] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[0] & (~inst[4] & ~inst[3] | inst[4] & inst[3]) | inst[0] & inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) & ~inst[30] & ~inst[27] | inst[26] & inst[31] & inst[29]); + // assign ctrl.ET = ~inst[28] & (~inst[26] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) & ~inst[30] & ~inst[27] | inst[26] & inst[31] & inst[29]); + assign ctrl.ET = ~inst[26] & ~inst[27] & (~inst[30] & ~inst[28] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) | inst[30] & inst[29]) | inst[26] & inst[31] & inst[29]; assign ctrl.DS = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[26])); assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27]; @@ -63,10 +65,12 @@ module Controller ( assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | ~inst[1] & inst[0]); assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | inst[1] & inst[0]); - assign ctrl.MCtrl0.HLS = HLS_t'({~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & inst[3], inst[1:0]}); + // assign ctrl.MCtrl0.HLS = HLS_t'({~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & inst[3], inst[1:0]}); + assign ctrl.MCtrl0.HLS = HLS_t'({~inst[27] & ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & inst[4] & inst[3] | inst[29] & inst[30]), ~inst[30] & inst[1], inst[0]}); assign ctrl.MCtrl0.C0D = inst[15:11]; assign ctrl.MCtrl0.C0W = inst[30] & inst[23]; - assign ctrl.MCtrl0.RS0 = RS0_t'({inst[29] | inst[26] | ~inst[4], inst[30] | ~inst[29] & ~inst[26] & inst[4] & ~inst[1]}); + // assign ctrl.MCtrl0.RS0 = RS0_t'({inst[29] | inst[26] | ~inst[4], inst[30] | ~inst[29] & ~inst[26] & inst[4] & ~inst[1]}); + assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (inst[29] | inst[26] | ~inst[4]), inst[30], ~inst[29] & (inst[30] | ~inst[1])}); assign ctrl.MCtrl1.MR = inst[31]; assign ctrl.MCtrl1.MWR = inst[29]; diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 1ce832a..178ff1b 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -125,7 +125,7 @@ module Datapath ( logic E_I0_NowExcValidWithoutOF; logic E_I0_ExcValidWithoutOF; logic E_I0_PrevExcValid; - logic [ 4:0] E_I0_PrevExcCode; + logic [4:0] E_I0_PrevExcCode; logic E_I0_PrevERET; word_t E_I1_A; @@ -135,7 +135,7 @@ module Datapath ( logic E_I1_NowExcValidWithoutOF; logic E_I1_ExcValidWithoutOF; logic E_I1_PrevExcValid; - logic [ 4:0] E_I1_PrevExcCode; + logic [4:0] E_I1_PrevExcCode; logic E_I1_PrevERET; logic E_I1_STRBERROR; @@ -196,10 +196,9 @@ module Datapath ( word_t M_I0_MULTUL; logic M_I0_MULT_bvalid; - word_t M_I0_MULTHB; word_t M_I0_MULTLB; + word_t M_I0_MULTHB; word_t M_I0_MULTUHB; - word_t M_I0_MULTULB; word_t M_I0_HI; word_t M_I0_LO; @@ -413,22 +412,22 @@ module Datapath ( assign D.IB_Delay = D.IA.BJRJ; // D.Dispatch - assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & E.I0.MCtrl.RS0 != ALUOut + assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl.RS0[2] | E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR - | E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & E.I0.MCtrl.RS0 != ALUOut + | E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl.RS0[2] | E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR | E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS | E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS | E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT | E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT - | M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & M.I0.MCtrl.RS0 != ALUOut + | M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl.RS0[2] | M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR - | M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & M.I0.MCtrl.RS0 != ALUOut + | M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl.RS0[2] | M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR; - assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & E.I0.MCtrl.RS0 != ALUOut + assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl.RS0[2] | E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR - | E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & E.I0.MCtrl.RS0 != ALUOut + | E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl.RS0[2] | E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR | D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET @@ -591,7 +590,7 @@ module Datapath ( E.en, E.I0.ECtrl ); - ffenrc #(13) E_I0_MCtrl_ff ( + ffenrc #(14) E_I0_MCtrl_ff ( clk, rst | rstM, D.I0.MCtrl, @@ -875,7 +874,7 @@ module Datapath ( M.en, M.I0.ALUOut ); - ffenrc #(13) M_I0_MCtrl_ff ( + ffenrc #(14) M_I0_MCtrl_ff ( clk, rst | rstM, E.I0.MCtrl, @@ -952,13 +951,13 @@ module Datapath ( }; // M.I0.MUL - buffer #(128) M_I0_MULT_buffer ( + buffer #(96) M_I0_MULT_buffer ( clk, rst, M_I0_MULT_CNTR[0], - {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUL, M_I0_MULTUH}, + {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH}, M.en, M_I0_MULT_bvalid, - {M_I0_MULTLB, M_I0_MULTHB, M_I0_MULTULB, M_I0_MULTUHB} + {M_I0_MULTLB, M_I0_MULTHB, M_I0_MULTUHB} ); // M.I0.DIV @@ -980,17 +979,18 @@ module Datapath ( ); // M.I0.HILOC0 - mux4 #(32) M_I0_RDataW_mux ( + mux5 #(32) M_I0_RDataW_mux ( LO, HI, - M.I0.ALUOut, + M_I0_MULTLB, C0_rdata, + M.I0.ALUOut, M.I0.MCtrl.RS0, M.I0.RDataW ); mux5 #(64) M_I0_HILO_mux ( {M_I0_MULTHB, M_I0_MULTLB}, - {M_I0_MULTUHB, M_I0_MULTULB}, + {M_I0_MULTUHB, M_I0_MULTLB}, {M_I0_DIVHB, M_I0_DIVLB}, {M_I0_DIVUHB, M_I0_DIVULB}, {M_I0_ForwardS, M_I0_ForwardS}, diff --git a/src/Core/Gadgets.sv b/src/Core/Gadgets.sv index 64c6bf2..c1112da 100644 --- a/src/Core/Gadgets.sv +++ b/src/Core/Gadgets.sv @@ -69,6 +69,7 @@ module instr_valid ( 32'b01000000000??????????00000000???: valid = 1'b1; // MFC0 32'b01000000100??????????00000000???: valid = 1'b1; // MTC0 32'b01000010000000000000000000011000: valid = 1'b1; // ERET + 32'b011100???????????????00000000010: valid = 1'b1; // MUL 32'b100000??????????????????????????: valid = 1'b1; // LB 32'b100001??????????????????????????: valid = 1'b1; // LH 32'b100011??????????????????????????: valid = 1'b1; // LW diff --git a/src/include/defines.svh b/src/include/defines.svh index 5e9079c..228a24d 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -58,11 +58,12 @@ typedef enum logic [1:0] { IMM = 2'b11 // 2'b1? } SB_t; -typedef enum logic [1:0] { - LO = 2'b00, - HI = 2'b01, - ALUOut = 2'b10, - C0 = 2'b11 +typedef enum logic [2:0] { + LO = 3'b000, + HI = 3'b001, + MUL = 3'b010, + C0 = 3'b011, + ALUOut = 3'b100 // 3'b1?? } RS0_t; typedef enum logic [2:0] {