mfw
Co-authored-by: cxy004 <cxy004@qq.com> Co-authored-by: Paul <1323564116@qq.com>
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@ -77,12 +77,56 @@ module Datapath (
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word_t M_I0_HI;
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word_t M_I0_LO;
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word_t M_I0_FS_M_I1;
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word_t M_I0_FS_W_I0;
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word_t M_I0_FS_W_I1;
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word_t M_I0_ForwardS;
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word_t M_I0_FT_M_I1;
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word_t M_I0_FT_W_I0;
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word_t M_I0_FT_W_I1;
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word_t M_I0_ForwardT;
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word_t M_I1_FT_M_I0;
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word_t M_I1_FT_W_I0;
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word_t M_I1_FT_W_I1;
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word_t M_I1_ForwardT;
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word_t HI;
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word_t LO;
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// Write Back
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logic R_we1;
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logic R_we2;
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logic [4:0] R_waddr1;
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logic [4:0] R_waddr2;
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word_t R_wdata1;
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word_t R_wdata2;
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//---------------------------------------------------------------------------//
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// Decode Stage //
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//---------------------------------------------------------------------------//
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RF RegisterFile(
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.clk(clk),
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.raddr1(R_raddr1),
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.raddr2(R_raddr2),
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.raddr3(R_raddr3),
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.raddr4(R_raddr4),
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.we1(R_we1),
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.we2(R_we2),
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.waddr1(R_waddr1),
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.waddr2(R_waddr2),
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.wdata1(R_wdata1),
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.wdata2(R_wdata2),
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.rdata1(R_rdata1),
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.rdata2(R_rdata2),
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.rdata3(R_rdata3),
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.rdata4(R_rdata4),
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.test_addr(R_test_addr),
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.test_data(R_test_data)
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);
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//---------------------------------------------------------------------------//
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// Execute Stage //
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//---------------------------------------------------------------------------//
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@ -182,8 +226,8 @@ module Datapath (
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assign E_I0_FS_W_I1 = W.I1.WCtrl.RW & E.I0.RS == W.I1.RD;
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mux3 #(32) E_I0_ForwardS_mux (
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E.I0.S,
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E_I0_FS_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW,
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E_I0_FS_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW,
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(~E_I0_FS_W_I0 | E_I0_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
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(~E_I0_FS_M_I0 | E_I0_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW,
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{E_I0_FS_M_I0 | E_I0_FS_M_I1, E_I0_FS_W_I0 | E_I0_FS_W_I1},
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E_I0_ForwardS
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);
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@ -194,8 +238,8 @@ module Datapath (
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assign E_I0_FT_W_I1 = W.I1.WCtrl.RW & E.I0.RT == W.I1.RD;
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mux3 #(32) E_I0_ForwardT_mux (
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E.I0.T,
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E_I0_FT_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW,
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E_I0_FT_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW,
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(~E_I0_FT_W_I0 | E_I0_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
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(~E_I0_FT_M_I0 | E_I0_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW,
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{E_I0_FT_M_I0 | E_I0_FT_M_I1, E_I0_FT_W_I0 | E_I0_FT_W_I1},
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E_I0_ForwardT
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);
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@ -206,8 +250,8 @@ module Datapath (
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assign E_I1_FS_W_I1 = W.I1.WCtrl.RW & E.I1.RS == W.I1.RD;
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mux3 #(32) E_I1_ForwardS_mux (
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E.I1.S,
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E_I1_FS_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW,
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E_I1_FS_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW,
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(~E_I1_FS_W_I0 | E_I1_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
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(~E_I1_FS_M_I0 | E_I1_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW,
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{E_I1_FS_M_I0 | E_I1_FS_M_I1, E_I1_FS_W_I0 | E_I1_FS_W_I1},
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E_I1_ForwardS
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);
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@ -218,8 +262,8 @@ module Datapath (
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assign E_I1_FT_W_I1 = W.I1.WCtrl.RW & E.I1.RT == W.I1.RD;
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mux3 #(32) E_I1_ForwardT_mux (
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E.I1.T,
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E_I1_FT_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW,
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E_I1_FT_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW,
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(~E_I1_FT_W_I0 | E_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
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(~E_I1_FT_M_I0 | E_I1_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW,
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{E_I1_FT_M_I0 | E_I1_FT_M_I1, E_I1_FT_W_I0 | E_I1_FT_W_I1},
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E_I1_ForwardT
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);
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@ -433,16 +477,84 @@ module Datapath (
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assign M.en = M_go & W.en;
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assign M_go = ~M.I1.MCtrl.MR | mem_i.data_ok;
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// M.Forwarding
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assign M_I0_FS_M_I1 = M.A & M.I1.WCtrl.RW & M.I0.RS == M.I1.RD & ~M.I1.MCtrl.MR;
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assign M_I0_FS_W_I0 = W.I0.WCtrl.RW & M.I0.RS == W.I0.RD;
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assign M_I0_FS_W_I1 = W.I1.WCtrl.RW & M.I0.RS == W.I1.RD;
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mux3 #(32) M_I0_ForwardS_mux (
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M.I0.S,
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(~M_I0_FS_W_I0 | M_I0_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
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M.I1.ALUOut,
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{M_I0_FS_M_I1, M_I0_FS_W_I0 | M_I0_FS_W_I1},
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M_I0_ForwardS);
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assign M_I0_FT_M_I1 = M.A & M.I1.WCtrl.RW & M.I0.RT == M.I1.RD & ~M.I1.MCtrl.MR;
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assign M_I0_FT_W_I0 = W.I0.WCtrl.RW & M.I0.RT == W.I0.RD;
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assign M_I0_FT_W_I1 = W.I1.WCtrl.RW & M.I0.RT == W.I1.RD;
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mux3 #(32) M_I0_ForwardT_mux (
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M.I0.T,
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(~M_I0_FT_W_I0 | M_I0_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
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M.I1.ALUOut,
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{M_I0_FT_M_I1, M_I0_FT_W_I0 | M_I0_FT_W_I1},
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M_I0_ForwardT);
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assign M_I1_FT_M_I0 = ~M.A & M.I0.WCtrl.RW & M.I1.RT == M.I0.RD;
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assign M_I1_FT_W_I0 = W.I0.WCtrl.RW & M.I1.RT == W.I0.RD;
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assign M_I1_FT_W_I1 = W.I1.WCtrl.RW & M.I1.RT == W.I1.RD;
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mux3 #(32) M_I1_ForwardT_mux (
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M.I1.T,
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(~M_I1_FT_W_I0 | M_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
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M.I0.RDataW,
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{M_I1_FT_M_I0, M_I1_FT_W_I0 | M_I1_FT_W_I1},
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M_I1_ForwardT);
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//----------------------------------------------------------------------------//
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// Write-Back Stage //
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//----------------------------------------------------------------------------//
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mux2 #(32) wd_mux (
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aluoutW,
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memdataW,
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mwW,
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wdW
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// W.FF
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ffen #(1) W_A_ff (
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clk,
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M.A,
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W.en,
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W.A
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);
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ffen #(32) W_I0_RDataW_ff (
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clk,
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M.I0.RDataW,
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W.en,
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W.I0.RDataW
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);
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ffenrc #(5 + 1) W_I0_WCtrl_ff (
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clk,
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rst,
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{M.I0.RD, M.I0.WCtrl},
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M.en,
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~M_go,
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{W.I0.RD, W.I0.WCtrl}
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);
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ffen #(32) W_I1_RDataW_ff (
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clk,
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M.I1.RDataW,
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W.en,
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W.I1.RDataW
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);
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ffenrc #(5 + 1) W_I1_WCtrl_ff (
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clk,
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rst,
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{M.I1.RD, M.I1.WCtrl},
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M.en,
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~M_go,
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{W.I1.RD, W.I1.WCtrl}
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);
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assign W.en = 1'b1;
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assign R_we1 = W.I0.WCtrl.RW;
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assign R_we2 = W.I1.WCtrl.RW;
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assign R_waddr1 = W.I0.RD;
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assign R_waddr2 = W.I1.RD;
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assign R_wdata1 = W.I0.RDataW;
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assign R_wdata2 = W.I1.RDataW;
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endmodule
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@ -6,7 +6,8 @@ module RF (
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input logic [4:0] raddr2,
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input logic [4:0] raddr3,
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input logic [4:0] raddr4,
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input logic en,
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input logic we1,
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input logic we2,
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input logic [4:0] waddr1,
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input logic [4:0] waddr2,
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input word_t wdata1,
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@ -21,9 +22,9 @@ module RF (
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word_t rf[31:0];
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always_ff @(posedge clk) begin
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if(en & waddr1 != 0)
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if(we1 & waddr1 != 0)
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rf[waddr1] <= wdata1;
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if(en & waddr2 != 0)
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if(we2 & waddr2 != 0)
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rf[waddr2] <= wdata2;
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end
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@ -276,7 +276,6 @@ typedef struct packed {
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struct packed {
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word_t RDataW;
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logic [4:0] RD;
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WCtrl_t WCtrl;
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} I0;
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@ -284,7 +283,6 @@ typedef struct packed {
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struct packed {
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word_t RDataW;
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logic [4:0] RD;
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WCtrl_t WCtrl;
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} I1;
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