From b133bcf138ae696e17f01bbfbce2b1a54204d729 Mon Sep 17 00:00:00 2001 From: hoo Date: Mon, 26 Jul 2021 11:18:07 +0800 Subject: [PATCH] mfw Co-authored-by: cxy004 Co-authored-by: Paul <1323564116@qq.com> --- src/Core/Datapath.sv | 138 ++++++++++++++++++++++++++++++++++++---- src/Core/RF.sv | 7 +- src/include/defines.svh | 2 - 3 files changed, 129 insertions(+), 18 deletions(-) diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 5d0fbcd..4a5ad69 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -77,12 +77,56 @@ module Datapath ( word_t M_I0_HI; word_t M_I0_LO; + word_t M_I0_FS_M_I1; + word_t M_I0_FS_W_I0; + word_t M_I0_FS_W_I1; word_t M_I0_ForwardS; + + word_t M_I0_FT_M_I1; + word_t M_I0_FT_W_I0; + word_t M_I0_FT_W_I1; word_t M_I0_ForwardT; + word_t M_I1_FT_M_I0; + word_t M_I1_FT_W_I0; + word_t M_I1_FT_W_I1; + word_t M_I1_ForwardT; + word_t HI; word_t LO; + // Write Back + logic R_we1; + logic R_we2; + logic [4:0] R_waddr1; + logic [4:0] R_waddr2; + word_t R_wdata1; + word_t R_wdata2; + + //---------------------------------------------------------------------------// + // Decode Stage // + //---------------------------------------------------------------------------// + + RF RegisterFile( + .clk(clk), + .raddr1(R_raddr1), + .raddr2(R_raddr2), + .raddr3(R_raddr3), + .raddr4(R_raddr4), + .we1(R_we1), + .we2(R_we2), + .waddr1(R_waddr1), + .waddr2(R_waddr2), + .wdata1(R_wdata1), + .wdata2(R_wdata2), + .rdata1(R_rdata1), + .rdata2(R_rdata2), + .rdata3(R_rdata3), + .rdata4(R_rdata4), + .test_addr(R_test_addr), + .test_data(R_test_data) + ); + //---------------------------------------------------------------------------// // Execute Stage // //---------------------------------------------------------------------------// @@ -182,8 +226,8 @@ module Datapath ( assign E_I0_FS_W_I1 = W.I1.WCtrl.RW & E.I0.RS == W.I1.RD; mux3 #(32) E_I0_ForwardS_mux ( E.I0.S, - E_I0_FS_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW, - E_I0_FS_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW, + (~E_I0_FS_W_I0 | E_I0_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, + (~E_I0_FS_M_I0 | E_I0_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW, {E_I0_FS_M_I0 | E_I0_FS_M_I1, E_I0_FS_W_I0 | E_I0_FS_W_I1}, E_I0_ForwardS ); @@ -194,8 +238,8 @@ module Datapath ( assign E_I0_FT_W_I1 = W.I1.WCtrl.RW & E.I0.RT == W.I1.RD; mux3 #(32) E_I0_ForwardT_mux ( E.I0.T, - E_I0_FT_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW, - E_I0_FT_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW, + (~E_I0_FT_W_I0 | E_I0_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, + (~E_I0_FT_M_I0 | E_I0_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW, {E_I0_FT_M_I0 | E_I0_FT_M_I1, E_I0_FT_W_I0 | E_I0_FT_W_I1}, E_I0_ForwardT ); @@ -206,8 +250,8 @@ module Datapath ( assign E_I1_FS_W_I1 = W.I1.WCtrl.RW & E.I1.RS == W.I1.RD; mux3 #(32) E_I1_ForwardS_mux ( E.I1.S, - E_I1_FS_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW, - E_I1_FS_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW, + (~E_I1_FS_W_I0 | E_I1_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, + (~E_I1_FS_M_I0 | E_I1_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW, {E_I1_FS_M_I0 | E_I1_FS_M_I1, E_I1_FS_W_I0 | E_I1_FS_W_I1}, E_I1_ForwardS ); @@ -218,8 +262,8 @@ module Datapath ( assign E_I1_FT_W_I1 = W.I1.WCtrl.RW & E.I1.RT == W.I1.RD; mux3 #(32) E_I1_ForwardT_mux ( E.I1.T, - E_I1_FT_W_I1 & W.A ? W.I1.RDataW : W.I0.RDataW, - E_I1_FT_M_I1 & M.A ? M.I1.ALUOut : M.I0.RDataW, + (~E_I1_FT_W_I0 | E_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, + (~E_I1_FT_M_I0 | E_I1_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.RDataW, {E_I1_FT_M_I0 | E_I1_FT_M_I1, E_I1_FT_W_I0 | E_I1_FT_W_I1}, E_I1_ForwardT ); @@ -433,16 +477,84 @@ module Datapath ( assign M.en = M_go & W.en; assign M_go = ~M.I1.MCtrl.MR | mem_i.data_ok; + // M.Forwarding + assign M_I0_FS_M_I1 = M.A & M.I1.WCtrl.RW & M.I0.RS == M.I1.RD & ~M.I1.MCtrl.MR; + assign M_I0_FS_W_I0 = W.I0.WCtrl.RW & M.I0.RS == W.I0.RD; + assign M_I0_FS_W_I1 = W.I1.WCtrl.RW & M.I0.RS == W.I1.RD; + mux3 #(32) M_I0_ForwardS_mux ( + M.I0.S, + (~M_I0_FS_W_I0 | M_I0_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, + M.I1.ALUOut, + {M_I0_FS_M_I1, M_I0_FS_W_I0 | M_I0_FS_W_I1}, + M_I0_ForwardS); + + assign M_I0_FT_M_I1 = M.A & M.I1.WCtrl.RW & M.I0.RT == M.I1.RD & ~M.I1.MCtrl.MR; + assign M_I0_FT_W_I0 = W.I0.WCtrl.RW & M.I0.RT == W.I0.RD; + assign M_I0_FT_W_I1 = W.I1.WCtrl.RW & M.I0.RT == W.I1.RD; + mux3 #(32) M_I0_ForwardT_mux ( + M.I0.T, + (~M_I0_FT_W_I0 | M_I0_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, + M.I1.ALUOut, + {M_I0_FT_M_I1, M_I0_FT_W_I0 | M_I0_FT_W_I1}, + M_I0_ForwardT); + + assign M_I1_FT_M_I0 = ~M.A & M.I0.WCtrl.RW & M.I1.RT == M.I0.RD; + assign M_I1_FT_W_I0 = W.I0.WCtrl.RW & M.I1.RT == W.I0.RD; + assign M_I1_FT_W_I1 = W.I1.WCtrl.RW & M.I1.RT == W.I1.RD; + mux3 #(32) M_I1_ForwardT_mux ( + M.I1.T, + (~M_I1_FT_W_I0 | M_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW, + M.I0.RDataW, + {M_I1_FT_M_I0, M_I1_FT_W_I0 | M_I1_FT_W_I1}, + M_I1_ForwardT); + //----------------------------------------------------------------------------// // Write-Back Stage // //----------------------------------------------------------------------------// - mux2 #(32) wd_mux ( - aluoutW, - memdataW, - mwW, - wdW + // W.FF + ffen #(1) W_A_ff ( + clk, + M.A, + W.en, + W.A + ); + ffen #(32) W_I0_RDataW_ff ( + clk, + M.I0.RDataW, + W.en, + W.I0.RDataW + ); + ffenrc #(5 + 1) W_I0_WCtrl_ff ( + clk, + rst, + {M.I0.RD, M.I0.WCtrl}, + M.en, + ~M_go, + {W.I0.RD, W.I0.WCtrl} + ); + ffen #(32) W_I1_RDataW_ff ( + clk, + M.I1.RDataW, + W.en, + W.I1.RDataW + ); + ffenrc #(5 + 1) W_I1_WCtrl_ff ( + clk, + rst, + {M.I1.RD, M.I1.WCtrl}, + M.en, + ~M_go, + {W.I1.RD, W.I1.WCtrl} ); assign W.en = 1'b1; + + assign R_we1 = W.I0.WCtrl.RW; + assign R_we2 = W.I1.WCtrl.RW; + assign R_waddr1 = W.I0.RD; + assign R_waddr2 = W.I1.RD; + assign R_wdata1 = W.I0.RDataW; + assign R_wdata2 = W.I1.RDataW; + endmodule diff --git a/src/Core/RF.sv b/src/Core/RF.sv index bc03375..961abc8 100644 --- a/src/Core/RF.sv +++ b/src/Core/RF.sv @@ -6,7 +6,8 @@ module RF ( input logic [4:0] raddr2, input logic [4:0] raddr3, input logic [4:0] raddr4, - input logic en, + input logic we1, + input logic we2, input logic [4:0] waddr1, input logic [4:0] waddr2, input word_t wdata1, @@ -21,9 +22,9 @@ module RF ( word_t rf[31:0]; always_ff @(posedge clk) begin - if(en & waddr1 != 0) + if(we1 & waddr1 != 0) rf[waddr1] <= wdata1; - if(en & waddr2 != 0) + if(we2 & waddr2 != 0) rf[waddr2] <= wdata2; end diff --git a/src/include/defines.svh b/src/include/defines.svh index 77054f6..49ae21c 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -276,7 +276,6 @@ typedef struct packed { struct packed { word_t RDataW; - logic [4:0] RD; WCtrl_t WCtrl; } I0; @@ -284,7 +283,6 @@ typedef struct packed { struct packed { word_t RDataW; - logic [4:0] RD; WCtrl_t WCtrl; } I1;