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fix DCache

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This commit is contained in:
Paul Pan 2022-08-04 18:41:16 +08:00
parent dfa2e628a2
commit 8db46ab67b
1 changed files with 10 additions and 13 deletions
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23
src/MU/DCache.sv
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@ -80,16 +80,13 @@ module DCache (
: victim_lrud != `DC_WAYS'b0 ? victim_lrud
: victim_lru;
assign port.dirt = |{victim & {tag[3].dirty, tag[2].dirty, tag[1].dirty, tag[0].dirty}};
assign dirt_tag = (victim[0] ? tag[0].tag : {(32-`DC_TAGL){1'b0}})
| (victim[1] ? tag[1].tag : {(32-`DC_TAGL){1'b0}})
| (victim[2] ? tag[2].tag : {(32-`DC_TAGL){1'b0}})
| (victim[3] ? tag[3].tag : {(32-`DC_TAGL){1'b0}});
logic [$clog2(`DC_WAYS)-1:0] victim_bin;
onehot_bin #(`DC_WAYS) victim_conv (.onehot(victim), .bin(victim_bin));
assign port.dirt = |{victim & victim_dirt_collect};
assign dirt_tag = tag[victim_bin].tag;
assign port.dirt_addr = {dirt_tag, port.index, `DC_INDEXL'b0};
assign port.dirt_row = (victim[0] ? data[0] : {`DC_DATA_LENGTH{1'b0}})
| (victim[1] ? data[1] : {`DC_DATA_LENGTH{1'b0}})
| (victim[2] ? data[2] : {`DC_DATA_LENGTH{1'b0}})
| (victim[3] ? data[3] : {`DC_DATA_LENGTH{1'b0}});
assign port.dirt_row = data[victim_bin];
assign setLRU_valid = port.ctrl.read_and_hit | port.ctrl.read_but_replace | port.ctrl.write_and_hit | port.ctrl.write_but_replace;
assign setLRU = (port.ctrl.read_and_hit ? hitway : `DC_WAYS'b0)
@ -124,7 +121,7 @@ module DCache (
// ==============================
// 地址
for (genvar i = 0; i < `IC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin
assign TagRAM[i].addr = port.index_for_lookup;
assign DataRAM[i].addr = port.index_for_lookup;
end
@ -138,20 +135,20 @@ module DCache (
| ({`DC_WAYS{port.ctrl.cache_hit_invalidate}} & hitway)
| ({`DC_WAYS{port.ctrl.cache_hit_writeback}} & hitway);
for (genvar i = 0; i < `IC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin
assign TagRAM[i].wen = wen[i];
assign DataRAM[i].wen = wen[i];
end
// 写数据
for (genvar i = 0; i < `IC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin
assign TagRAM[i].wdata = {port.tag, port.ctrl.write_and_hit | port.ctrl.write_but_replace, port.ctrl.read_but_replace | port.ctrl.write_and_hit | port.ctrl.write_but_replace};
assign DataRAM[i].wdata = port.update_row;
end
// BRAM 实例
for (genvar i = 0; i < `IC_WAYS; i++) begin : dbram
for (genvar i = 0; i < `DC_WAYS; i++) begin : dbram
bram #(.DATA_WIDTH(32-`DC_TAGL+2), .DATA_DEPTH(2 ** (`DC_TAGL-`DC_INDEXL)))
tag_ram (.rst(rst), .addra(TagRAM[i].addr), .clka(clk), .dina(TagRAM[i].wdata), .douta(TagRAM[i].rdata), .wea(TagRAM[i].wen));