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2alu fix

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This commit is contained in:
cxy004 2022-08-03 18:45:44 +08:00
parent d9f08727d0
commit 828190a98e
2 changed files with 3 additions and 4 deletions
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5
src/Core/Controller.sv
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@ -84,10 +84,7 @@ module Controller (
assign ctrl.MCtrl1.TLBWR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & (inst[2] | ~inst[1]);
assign ctrl.MCtrl1.TLBP = ~inst[31] & inst[30] & ~inst[4] & inst[3];
assign ctrl.MCtrl1.CACHE_OP.icache_op = inst[31] & inst[29] & inst[28] & inst[26] & ~inst[16];
assign ctrl.MCtrl1.CACHE_OP.dcache_op = inst[31] & inst[29] & inst[28] & inst[26] & inst[16];
assign ctrl.MCtrl1.CACHE_OP.index_or_hit = inst[20];
assign ctrl.MCtrl1.CACHE_OP.writeback = ~inst[20] & ~inst[19] & inst[16] | inst[18];
assign ctrl.MCtrl1.CACHE_OP = CacheOp_t'({inst[29] & inst[28] & inst[26] & inst[16], inst[29] & inst[28] & inst[26] & ~inst[20], inst[29] & inst[28] & inst[26] & ~inst[18] & (inst[20] | inst[19] | ~inst[16])});
assign ctrl.Trap.TEN = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & (~inst[30] & ~inst[26] & inst[5] & inst[4] | inst[26] & inst[19]);
assign ctrl.Trap.TP = TrapOp_t'({~inst[26] & inst[2] | inst[26] & inst[18], ~inst[26] & inst[1] | inst[26] & inst[17]});

2
src/Core/Datapath.sv
View File

@ -581,8 +581,10 @@ module Datapath (
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
// Not Arith -> Store
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & D_IA_HazardALU2
// Not Arith -> LWL/LWR
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & D_IA_HazardALU2
// CP0 Execution Hazards
// Hazards Related to the TLB
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX