From 828190a98ed2586d065398af3963398000ed5976 Mon Sep 17 00:00:00 2001 From: cxy004 Date: Wed, 3 Aug 2022 18:45:44 +0800 Subject: [PATCH] 2alu fix --- src/Core/Controller.sv | 5 +---- src/Core/Datapath.sv | 2 ++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/src/Core/Controller.sv b/src/Core/Controller.sv index 177714b..289db6e 100644 --- a/src/Core/Controller.sv +++ b/src/Core/Controller.sv @@ -84,10 +84,7 @@ module Controller ( assign ctrl.MCtrl1.TLBWR = ~inst[31] & inst[30] & ~inst[29] & inst[25] & ~inst[3] & (inst[2] | ~inst[1]); assign ctrl.MCtrl1.TLBP = ~inst[31] & inst[30] & ~inst[4] & inst[3]; - assign ctrl.MCtrl1.CACHE_OP.icache_op = inst[31] & inst[29] & inst[28] & inst[26] & ~inst[16]; - assign ctrl.MCtrl1.CACHE_OP.dcache_op = inst[31] & inst[29] & inst[28] & inst[26] & inst[16]; - assign ctrl.MCtrl1.CACHE_OP.index_or_hit = inst[20]; - assign ctrl.MCtrl1.CACHE_OP.writeback = ~inst[20] & ~inst[19] & inst[16] | inst[18]; + assign ctrl.MCtrl1.CACHE_OP = CacheOp_t'({inst[29] & inst[28] & inst[26] & inst[16], inst[29] & inst[28] & inst[26] & ~inst[20], inst[29] & inst[28] & inst[26] & ~inst[18] & (inst[20] | inst[19] | ~inst[16])}); assign ctrl.Trap.TEN = ~inst[31] & ~inst[29] & ~inst[28] & ~inst[27] & (~inst[30] & ~inst[26] & inst[5] & inst[4] | inst[26] & inst[19]); assign ctrl.Trap.TP = TrapOp_t'({~inst[26] & inst[2] | inst[26] & inst[18], ~inst[26] & inst[1] | inst[26] & inst[17]}); diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 95f9da0..bef0222 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -581,8 +581,10 @@ module Datapath ( | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0 // Not Arith -> Store | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1 + | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & D_IA_HazardALU2 // Not Arith -> LWL/LWR | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1 + | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & D_IA_HazardALU2 // CP0 Execution Hazards // Hazards Related to the TLB | D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_INDEX