Fix LRU
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21ff0f0c19
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7a506ba611
@ -17,13 +17,16 @@ module decoder2 (
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always_comb begin
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always_comb begin
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ri = 1'b1;
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ri = 1'b1;
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`ifdef ENABLE_CpU
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`ifdef ENABLE_CpU
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ce = instr[27:26];
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ce = {instr[27] & ~instr[26], instr[26]};
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cpu = ce != 2'b11
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cpu = ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx
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& ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx
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| instr[31:26] == 6'b110001 // LWC1
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| instr[31:28] == 4'b1100 // LWCx
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| instr[31:26] == 6'b110010 // LWC2
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| instr[31:28] == 4'b1101 // LDCx
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| instr[31:26] == 6'b110101 // LDC1
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| instr[31:28] == 4'b1110 // SWCx
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| instr[31:26] == 6'b110110 // LDC2
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| instr[31:28] == 4'b1111 // SDCx
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| instr[31:26] == 6'b111001 // SWC1
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| instr[31:26] == 6'b111010 // SWC2
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| instr[31:26] == 6'b111101 // SDC1
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| instr[31:26] == 6'b111110 // SDC2
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); // TODO: Cache instruction
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); // TODO: Cache instruction
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`else
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`else
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ce = 2'b0;
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ce = 2'b0;
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@ -141,9 +144,7 @@ module decoder2 (
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32'b101111?????10001????????????????: ri = 1'b0; // D-Cache Hit Invalid
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32'b101111?????10001????????????????: ri = 1'b0; // D-Cache Hit Invalid
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32'b101111?????10101????????????????: ri = 1'b0; // D-Cache Hit Writeback Invalid
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32'b101111?????10101????????????????: ri = 1'b0; // D-Cache Hit Writeback Invalid
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`endif
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`endif
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// 32'b110000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // LL (CpU)
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32'b110011??????????????????????????: ri = 1'b0; // PREF (NOP)
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32'b110011??????????????????????????: ri = 1'b0; // PREF (NOP)
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// 32'b111000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // SC (CpU)
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endcase
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endcase
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end
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end
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endmodule
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endmodule
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@ -112,13 +112,15 @@ module DCache (
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for (genvar i = 0; i < `DC_INDEX_DEPTH; i++)
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for (genvar i = 0; i < `DC_INDEX_DEPTH; i++)
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initial LRU[i] = `DC_WAYS'b0;
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initial LRU[i] = `DC_WAYS'b0;
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/*verilator lint_off BLKSEQ*/
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (~rst) begin
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if (~rst) begin
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if (setLRU_valid | clrLRU_valid)
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if (setLRU_valid | clrLRU_valid)
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LRU[port.index] <= nxtLRU;
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LRU[port.index] = nxtLRU;
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nowLRU <= LRU[port.index_for_lookup];
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nowLRU = LRU[port.index_for_lookup];
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end
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end
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end
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end
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/*verilator lint_on BLKSEQ*/
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// ==============================
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// ==============================
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// ========= Block RAM ==========
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// ========= Block RAM ==========
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@ -309,14 +311,16 @@ module DCache (
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for (genvar i = 0; i < `DC_INDEX_DEPTH; i++)
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for (genvar i = 0; i < `DC_INDEX_DEPTH; i++)
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initial LRU[i] = 1'b0;
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initial LRU[i] = 1'b0;
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/*verilator lint_off BLKSEQ*/
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (~rst) begin
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if (~rst) begin
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if (port.ctrl.read_and_hit | port.ctrl.read_but_replace
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if (port.ctrl.read_and_hit | port.ctrl.read_but_replace
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| port.ctrl.write_and_hit | port.ctrl.write_but_replace)
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| port.ctrl.write_and_hit | port.ctrl.write_but_replace)
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LRU[port.index] <= nxtLRU;
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LRU[port.index] = nxtLRU;
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nowLRU <= LRU[port.index_for_lookup];
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nowLRU = LRU[port.index_for_lookup];
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end
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end
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end
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end
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/*verilator lint_on BLKSEQ*/
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// ==============================
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// ==============================
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// ========= Block RAM ==========
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// ========= Block RAM ==========
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@ -77,13 +77,15 @@ module ICache (
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for (genvar i = 0; i < `IC_INDEX_DEPTH; i++)
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for (genvar i = 0; i < `IC_INDEX_DEPTH; i++)
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initial LRU[i] = `IC_WAYS'b0;
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initial LRU[i] = `IC_WAYS'b0;
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/*verilator lint_off BLKSEQ*/
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (~rst) begin
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if (~rst) begin
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if (setLRU_valid | clrLRU_valid)
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if (setLRU_valid | clrLRU_valid)
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LRU[port.index] <= nxtLRU;
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LRU[port.index] = nxtLRU;
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nowLRU <= LRU[port.index_for_lookup];
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nowLRU = LRU[port.index_for_lookup];
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end
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end
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end
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end
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/*verilator lint_on BLKSEQ*/
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// ==============================
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// ==============================
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// ========= Block RAM ==========
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// ========= Block RAM ==========
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@ -233,13 +235,15 @@ module ICache (
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for (genvar i = 0; i < `IC_INDEX_DEPTH; i++)
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for (genvar i = 0; i < `IC_INDEX_DEPTH; i++)
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initial LRU[i] = 1'b0;
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initial LRU[i] = 1'b0;
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/*verilator lint_off BLKSEQ*/
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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if (~rst) begin
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if (~rst) begin
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if (port.ctrl.read_and_hit | port.ctrl.read_but_replace)
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if (port.ctrl.read_and_hit | port.ctrl.read_but_replace)
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LRU[port.index] <= nxtLRU;
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LRU[port.index] = nxtLRU;
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nowLRU <= LRU[port.index_for_lookup];
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nowLRU = LRU[port.index_for_lookup];
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end
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end
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end
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end
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/*verilator lint_on BLKSEQ*/
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// ==============================
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// ==============================
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// ========= Block RAM ==========
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// ========= Block RAM ==========
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20
src/MU/MU.sv
20
src/MU/MU.sv
@ -112,9 +112,6 @@ module MU (
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ffenr #(1) ifreq_store (.*, .d(instfetch.req), .en(in_if_ready), .q(if_req), .rst(rst | if_wait_cache));
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ffenr #(1) ifreq_store (.*, .d(instfetch.req), .en(in_if_ready), .q(if_req), .rst(rst | if_wait_cache));
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ffen #(`XLEN) ifaddr_store (.*, .d(instfetch.addr), .en(in_if_ready), .q(stored_instfetch_addr));
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ffen #(`XLEN) ifaddr_store (.*, .d(instfetch.addr), .en(in_if_ready), .q(stored_instfetch_addr));
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logic stored_if_handshake;
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ffenr #(1) ifc_handshake_store (.*, .d(in_if_valid), .en(in_if_ready), .q(stored_if_handshake));
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// ============
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// ============
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// row data mux
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// row data mux
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// ============
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// ============
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@ -166,15 +163,14 @@ module MU (
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case (ifc_cur_state)
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case (ifc_cur_state)
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IFC_LOOKUP: begin
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IFC_LOOKUP: begin
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cop_i_addr_ok = ~stored_if_handshake;
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cop_i_addr_ok = ~if_req;
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if (cop_i_req & ~stored_if_handshake) begin
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if (cop_i_req & ~if_req) begin
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// Handle Cache Instruction
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// Handle Cache Instruction
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ifc_nxt_state = IFC_CACHE_INVALID;
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ifc_nxt_state = IFC_CACHE_INVALID;
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icache.index_for_lookup = cacheop.addr[`IC_TAGL-1:`IC_INDEXL];
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icache.index_for_lookup = cacheop.addr[`IC_TAGL-1:`IC_INDEXL];
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end else if (~instfetch_valid) begin
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end else if (~instfetch_valid) begin
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// if cache read -> one more cycle to write bram
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in_if_ready = 1;
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in_if_ready = 1;
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end else if (if_req & instfetch_cached & icache.hit) begin
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end else if (if_req & instfetch_cached & icache.hit) begin
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@ -185,7 +181,6 @@ module MU (
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out_if_valid = 1'b1;
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out_if_valid = 1'b1;
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icache.ctrl.read_and_hit = 1'b1; // notify cache to update LRU
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icache.ctrl.read_and_hit = 1'b1; // notify cache to update LRU
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// icache.index
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if_source_select_direct = 0;
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if_source_select_direct = 0;
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if_source_data = icache.hit_row;
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if_source_data = icache.hit_row;
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@ -352,9 +347,6 @@ module MU (
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ffen #(4) memwstrb_store (.*, .d(memory.wstrb), .en(mem_store_winfo), .q(stored_memory_wstrb));
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ffen #(4) memwstrb_store (.*, .d(memory.wstrb), .en(mem_store_winfo), .q(stored_memory_wstrb));
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ffen #(`XLEN) memwdata_store (.*, .d(memory.wdata), .en(mem_store_winfo), .q(stored_memory_wdata));
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ffen #(`XLEN) memwdata_store (.*, .d(memory.wdata), .en(mem_store_winfo), .q(stored_memory_wdata));
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logic stored_mem_handshake;
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ffenr #(1) mem_handshake_store (.*, .d(in_mem_valid), .en(in_mem_ready), .q(stored_mem_handshake));
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// ============
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// ============
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// row data mux
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// row data mux
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// ============
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// ============
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@ -434,9 +426,9 @@ module MU (
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case (mem_cur_state)
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case (mem_cur_state)
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MEM_LOOKUP: begin
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MEM_LOOKUP: begin
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cop_d_addr_ok = ~stored_mem_handshake;
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cop_d_addr_ok = ~mem_req;
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if (cop_d_req & ~stored_mem_handshake) begin
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if (cop_d_req & ~mem_req) begin
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// Handle Cache Instruction
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// Handle Cache Instruction
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mem_nxt_state = MEM_CACHE_INVALID;
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mem_nxt_state = MEM_CACHE_INVALID;
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dcache.index_for_lookup = cacheop.addr[`DC_TAGL-1:`DC_INDEXL];
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dcache.index_for_lookup = cacheop.addr[`DC_TAGL-1:`DC_INDEXL];
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@ -712,7 +704,7 @@ module MU (
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// non-aligned: Never
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// non-aligned: Never
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// instfetch
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// instfetch
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assign iVA = choose_cop_i ? cacheop.addr : (instfetch.req & ~if_wait_cache & ifc_nxt_state == IFC_LOOKUP ? instfetch.addr : stored_instfetch_addr);
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assign iVA = choose_cop_i ? cacheop.addr : (instfetch.req & instfetch.addr_ok & ~if_wait_cache ? instfetch.addr : stored_instfetch_addr);
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assign instfetch_phy_addr = iPA1;
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assign instfetch_phy_addr = iPA1;
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assign instfetch_valid = iHit1 & iMValid1 & (cp0.cp0_in_kernel | iUser1);
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assign instfetch_valid = iHit1 & iMValid1 & (cp0.cp0_in_kernel | iUser1);
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assign instfetch_cached = iCached1;
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assign instfetch_cached = iCached1;
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@ -722,7 +714,7 @@ module MU (
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assign cp0.tlb_iAddressError = if_req & ~(cp0.cp0_in_kernel | iUser1);
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assign cp0.tlb_iAddressError = if_req & ~(cp0.cp0_in_kernel | iUser1);
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// memory
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// memory
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assign dVA = choose_cop_d ? cacheop.addr : (memory.req & ~mem_wait_cache & mem_nxt_state == MEM_LOOKUP ? memory.addr : stored_memory_addr);
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assign dVA = choose_cop_d ? cacheop.addr : (memory.req & memory.addr_ok & ~mem_wait_cache ? memory.addr : stored_memory_addr);
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assign memory_phy_addr = dPA1;
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assign memory_phy_addr = dPA1;
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assign memory_valid = dHit1 & dMValid1 & (cp0.cp0_in_kernel | dUser1) & (~memory.wr | dDirty1);
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assign memory_valid = dHit1 & dMValid1 & (cp0.cp0_in_kernel | dUser1) & (~memory.wr | dDirty1);
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assign memory_cached = dCached1;
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assign memory_cached = dCached1;
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@ -7,7 +7,7 @@
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// 3/4 <= INDEXL <= 6
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// 3/4 <= INDEXL <= 6
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// IC for I-Cache
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// IC for I-Cache
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`define IC_TAGL 13
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`define IC_TAGL 12
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`define IC_INDEXL 6
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`define IC_INDEXL 6
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`define IC_TAG_LENGTH (`XLEN - `IC_IGAL + 1) // Tag + Valid
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`define IC_TAG_LENGTH (`XLEN - `IC_IGAL + 1) // Tag + Valid
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`define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 64Bytes
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`define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 64Bytes
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@ -48,7 +48,7 @@ typedef struct packed {
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// DC for D-Cache
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// DC for D-Cache
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`define DC_TAGL 13
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`define DC_TAGL 12
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`define DC_INDEXL 5
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`define DC_INDEXL 5
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`define DC_TAG_LENGTH (`XLEN - `DC_TAGL + 1 + 1) // Tag + Valid + Dirty
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`define DC_TAG_LENGTH (`XLEN - `DC_TAGL + 1 + 1) // Tag + Valid + Dirty
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`define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 8Bytes
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`define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 8Bytes
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@ -1,14 +1,14 @@
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`ifndef DEFINES_SVH
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`ifndef DEFINES_SVH
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`define DEFINES_SVH
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`define DEFINES_SVH
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// `define ILA_DEBUG
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`define ILA_DEBUG
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// `define ENABLE_CACHEOP
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`define ENABLE_CACHEOP
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// `define ENABLE_TLB
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`define ENABLE_TLB
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// `define ENABLE_CpU
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`define ENABLE_CpU
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// `define ENABLE_TRAP
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`define ENABLE_TRAP
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// `define ENABLE_MADD
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`define ENABLE_MADD
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// `define ENABLE_UNALIGNED
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`define ENABLE_UNALIGNED
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`ifdef SIMULATION_VERILATOR
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`ifdef SIMULATION_VERILATOR
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`undef ENABLE_CpU
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`undef ENABLE_CpU
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