diff --git a/src/Core/Gadgets/decoder2.sv b/src/Core/Gadgets/decoder2.sv index 7f0f524..99f0376 100644 --- a/src/Core/Gadgets/decoder2.sv +++ b/src/Core/Gadgets/decoder2.sv @@ -17,13 +17,16 @@ module decoder2 ( always_comb begin ri = 1'b1; `ifdef ENABLE_CpU - ce = instr[27:26]; - cpu = ce != 2'b11 - & ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx - | instr[31:28] == 4'b1100 // LWCx - | instr[31:28] == 4'b1101 // LDCx - | instr[31:28] == 4'b1110 // SWCx - | instr[31:28] == 4'b1111 // SDCx + ce = {instr[27] & ~instr[26], instr[26]}; + cpu = ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx + | instr[31:26] == 6'b110001 // LWC1 + | instr[31:26] == 6'b110010 // LWC2 + | instr[31:26] == 6'b110101 // LDC1 + | instr[31:26] == 6'b110110 // LDC2 + | instr[31:26] == 6'b111001 // SWC1 + | instr[31:26] == 6'b111010 // SWC2 + | instr[31:26] == 6'b111101 // SDC1 + | instr[31:26] == 6'b111110 // SDC2 ); // TODO: Cache instruction `else ce = 2'b0; @@ -141,9 +144,7 @@ module decoder2 ( 32'b101111?????10001????????????????: ri = 1'b0; // D-Cache Hit Invalid 32'b101111?????10101????????????????: ri = 1'b0; // D-Cache Hit Writeback Invalid `endif - // 32'b110000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // LL (CpU) 32'b110011??????????????????????????: ri = 1'b0; // PREF (NOP) - // 32'b111000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // SC (CpU) endcase end endmodule diff --git a/src/MU/DCache.sv b/src/MU/DCache.sv index cb5a602..84ddf2b 100644 --- a/src/MU/DCache.sv +++ b/src/MU/DCache.sv @@ -112,13 +112,15 @@ module DCache ( for (genvar i = 0; i < `DC_INDEX_DEPTH; i++) initial LRU[i] = `DC_WAYS'b0; + /*verilator lint_off BLKSEQ*/ always_ff @(posedge clk) begin if (~rst) begin if (setLRU_valid | clrLRU_valid) - LRU[port.index] <= nxtLRU; - nowLRU <= LRU[port.index_for_lookup]; + LRU[port.index] = nxtLRU; + nowLRU = LRU[port.index_for_lookup]; end end + /*verilator lint_on BLKSEQ*/ // ============================== // ========= Block RAM ========== @@ -309,14 +311,16 @@ module DCache ( for (genvar i = 0; i < `DC_INDEX_DEPTH; i++) initial LRU[i] = 1'b0; + /*verilator lint_off BLKSEQ*/ always_ff @(posedge clk) begin if (~rst) begin if (port.ctrl.read_and_hit | port.ctrl.read_but_replace | port.ctrl.write_and_hit | port.ctrl.write_but_replace) - LRU[port.index] <= nxtLRU; - nowLRU <= LRU[port.index_for_lookup]; + LRU[port.index] = nxtLRU; + nowLRU = LRU[port.index_for_lookup]; end end + /*verilator lint_on BLKSEQ*/ // ============================== // ========= Block RAM ========== diff --git a/src/MU/ICache.sv b/src/MU/ICache.sv index bdb0082..908653d 100644 --- a/src/MU/ICache.sv +++ b/src/MU/ICache.sv @@ -77,13 +77,15 @@ module ICache ( for (genvar i = 0; i < `IC_INDEX_DEPTH; i++) initial LRU[i] = `IC_WAYS'b0; + /*verilator lint_off BLKSEQ*/ always_ff @(posedge clk) begin if (~rst) begin if (setLRU_valid | clrLRU_valid) - LRU[port.index] <= nxtLRU; - nowLRU <= LRU[port.index_for_lookup]; + LRU[port.index] = nxtLRU; + nowLRU = LRU[port.index_for_lookup]; end end + /*verilator lint_on BLKSEQ*/ // ============================== // ========= Block RAM ========== @@ -233,13 +235,15 @@ module ICache ( for (genvar i = 0; i < `IC_INDEX_DEPTH; i++) initial LRU[i] = 1'b0; + /*verilator lint_off BLKSEQ*/ always_ff @(posedge clk) begin if (~rst) begin if (port.ctrl.read_and_hit | port.ctrl.read_but_replace) - LRU[port.index] <= nxtLRU; - nowLRU <= LRU[port.index_for_lookup]; + LRU[port.index] = nxtLRU; + nowLRU = LRU[port.index_for_lookup]; end end + /*verilator lint_on BLKSEQ*/ // ============================== // ========= Block RAM ========== diff --git a/src/MU/MU.sv b/src/MU/MU.sv index c4e1d87..40e3913 100644 --- a/src/MU/MU.sv +++ b/src/MU/MU.sv @@ -112,9 +112,6 @@ module MU ( ffenr #(1) ifreq_store (.*, .d(instfetch.req), .en(in_if_ready), .q(if_req), .rst(rst | if_wait_cache)); ffen #(`XLEN) ifaddr_store (.*, .d(instfetch.addr), .en(in_if_ready), .q(stored_instfetch_addr)); - logic stored_if_handshake; - ffenr #(1) ifc_handshake_store (.*, .d(in_if_valid), .en(in_if_ready), .q(stored_if_handshake)); - // ============ // row data mux // ============ @@ -166,15 +163,14 @@ module MU ( case (ifc_cur_state) IFC_LOOKUP: begin - cop_i_addr_ok = ~stored_if_handshake; + cop_i_addr_ok = ~if_req; - if (cop_i_req & ~stored_if_handshake) begin + if (cop_i_req & ~if_req) begin // Handle Cache Instruction ifc_nxt_state = IFC_CACHE_INVALID; icache.index_for_lookup = cacheop.addr[`IC_TAGL-1:`IC_INDEXL]; end else if (~instfetch_valid) begin - // if cache read -> one more cycle to write bram in_if_ready = 1; end else if (if_req & instfetch_cached & icache.hit) begin @@ -185,7 +181,6 @@ module MU ( out_if_valid = 1'b1; icache.ctrl.read_and_hit = 1'b1; // notify cache to update LRU - // icache.index if_source_select_direct = 0; if_source_data = icache.hit_row; @@ -352,9 +347,6 @@ module MU ( ffen #(4) memwstrb_store (.*, .d(memory.wstrb), .en(mem_store_winfo), .q(stored_memory_wstrb)); ffen #(`XLEN) memwdata_store (.*, .d(memory.wdata), .en(mem_store_winfo), .q(stored_memory_wdata)); - logic stored_mem_handshake; - ffenr #(1) mem_handshake_store (.*, .d(in_mem_valid), .en(in_mem_ready), .q(stored_mem_handshake)); - // ============ // row data mux // ============ @@ -434,9 +426,9 @@ module MU ( case (mem_cur_state) MEM_LOOKUP: begin - cop_d_addr_ok = ~stored_mem_handshake; + cop_d_addr_ok = ~mem_req; - if (cop_d_req & ~stored_mem_handshake) begin + if (cop_d_req & ~mem_req) begin // Handle Cache Instruction mem_nxt_state = MEM_CACHE_INVALID; dcache.index_for_lookup = cacheop.addr[`DC_TAGL-1:`DC_INDEXL]; @@ -712,7 +704,7 @@ module MU ( // non-aligned: Never // instfetch - assign iVA = choose_cop_i ? cacheop.addr : (instfetch.req & ~if_wait_cache & ifc_nxt_state == IFC_LOOKUP ? instfetch.addr : stored_instfetch_addr); + assign iVA = choose_cop_i ? cacheop.addr : (instfetch.req & instfetch.addr_ok & ~if_wait_cache ? instfetch.addr : stored_instfetch_addr); assign instfetch_phy_addr = iPA1; assign instfetch_valid = iHit1 & iMValid1 & (cp0.cp0_in_kernel | iUser1); assign instfetch_cached = iCached1; @@ -722,7 +714,7 @@ module MU ( assign cp0.tlb_iAddressError = if_req & ~(cp0.cp0_in_kernel | iUser1); // memory - assign dVA = choose_cop_d ? cacheop.addr : (memory.req & ~mem_wait_cache & mem_nxt_state == MEM_LOOKUP ? memory.addr : stored_memory_addr); + assign dVA = choose_cop_d ? cacheop.addr : (memory.req & memory.addr_ok & ~mem_wait_cache ? memory.addr : stored_memory_addr); assign memory_phy_addr = dPA1; assign memory_valid = dHit1 & dMValid1 & (cp0.cp0_in_kernel | dUser1) & (~memory.wr | dDirty1); assign memory_cached = dCached1; diff --git a/src/include/Cache.svh b/src/include/Cache.svh index 5ca1f4f..2a2a6bd 100644 --- a/src/include/Cache.svh +++ b/src/include/Cache.svh @@ -7,7 +7,7 @@ // 3/4 <= INDEXL <= 6 // IC for I-Cache -`define IC_TAGL 13 +`define IC_TAGL 12 `define IC_INDEXL 6 `define IC_TAG_LENGTH (`XLEN - `IC_IGAL + 1) // Tag + Valid `define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 64Bytes @@ -48,7 +48,7 @@ typedef struct packed { // DC for D-Cache -`define DC_TAGL 13 +`define DC_TAGL 12 `define DC_INDEXL 5 `define DC_TAG_LENGTH (`XLEN - `DC_TAGL + 1 + 1) // Tag + Valid + Dirty `define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 8Bytes diff --git a/src/include/defines.svh b/src/include/defines.svh index 500223f..8685a79 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -1,14 +1,14 @@ `ifndef DEFINES_SVH `define DEFINES_SVH -// `define ILA_DEBUG +`define ILA_DEBUG -// `define ENABLE_CACHEOP -// `define ENABLE_TLB -// `define ENABLE_CpU -// `define ENABLE_TRAP -// `define ENABLE_MADD -// `define ENABLE_UNALIGNED +`define ENABLE_CACHEOP +`define ENABLE_TLB +`define ENABLE_CpU +`define ENABLE_TRAP +`define ENABLE_MADD +`define ENABLE_UNALIGNED `ifdef SIMULATION_VERILATOR `undef ENABLE_CpU