queue opt

src/Core/Datapath.sv

@@ -220,13 +220,13 @@ module Datapath (
 
   assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
   assign fetch_i.req = ~F_valid | M_exception.ExcValid
-    | PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.BJRJ | D_readygo)
+    | PF_go & (~D_IB_valid & ~IQ_valids[0] | (~D.IA.BJRJ | D_readygo)
       & (rstD
-         | ~IQ_valids[3]
+         | ~IQ_valids[0]
-         | ~IQ_valids[2] & (F_free | PF.pc[2] | F.pc[2] | D_readygo)
+         | ~IQ_valids[1] & (F_free | PF.pc[2] | F.pc[2] | D_readygo)
-         | ~IQ_valids[1] & (F_free | PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
+         | ~IQ_valids[2] & (F_free | PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
-         | ~IQ_valids[0] & (F_free & (PF.pc[2] | F.pc[2] | D_readygo) | PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
+         | ~IQ_valids[3] & (F_free & (PF.pc[2] | F.pc[2] | D_readygo) | PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
-         |  IQ_valids[0] & (F_free & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1) | PF.pc[2] & F.pc[2] & D_readygo & D_readygo1)));
+         |  IQ_valids[3] & (F_free & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1) | PF.pc[2] & F.pc[2] & D_readygo & D_readygo1)));
   assign fetch_i.addr = {PF.pc[31:3], 3'b000};
 
   //---------------------------------------------------------------------------//
@@ -262,27 +262,23 @@ module Datapath (
   //                                Instr Queue                                //
   //---------------------------------------------------------------------------//
 
-  InstrQueue InstrQueue (
+  Queue #(64) InstrQueue (
       .clk(clk),
       .rst(rst | rstD | rstM),
 
       .vinA(fetch_i.data_ok | F.pc[1:0] != 2'b00),
-      .inA (F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0),
+      .inA ({F.pc[2] ? fetch_i.rdata1 : fetch_i.rdata0, F.pc}),
-      .pinA(F.pc),
 
       .vinB(fetch_i.data_ok & ~F.pc[2]),
-      .inB (fetch_i.rdata1),
+      .inB ({fetch_i.rdata1, F.pc[31:3], 3'b100}),
-      .pinB({F.pc[31:3], 3'b100}),
 
       .enA  (D.en0),
       .voutA(IQ_IA_valid),
-      .outA (IQ_IA_inst),
+      .outA ({IQ_IA_inst, IQ_IA_pc}),
-      .poutA(IQ_IA_pc),
 
       .enB  (D.en1),
       .voutB(IQ_IB_valid),
-      .outB (IQ_IB_inst),
+      .outB ({IQ_IB_inst, IQ_IB_pc}),
-      .poutB(IQ_IB_pc),
 
       .valids(IQ_valids)
   );
@@ -295,14 +291,14 @@ module Datapath (
   ffenr #(1 + 32 + 32) D_IA_ff (
       clk,
       rst | rstM,
-      D.en1 ? {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst} : {D_IB_valid, D.IB_pc, D.IB_inst},
+      D.en1 ? {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst} : {D_IB_valid, D.IB_pc, D.IB_inst},
       ~D_IA_valid | D_go & E.en,
       {D_IA_valid, D.IA_pc, D.IA_inst}
   );
   ffenr #(1 + 32 + 32) D_IB_ff (
       clk,
       rst | rstM,
-      D.en1 ? {IQ_IB_valid, IQ_IB_pc, IQ_IB_inst} : {IQ_IA_valid, IQ_IA_pc, IQ_IA_inst},
+      D.en1 ? {IQ_IB_valid & ~rstD, IQ_IB_pc, IQ_IB_inst} : {IQ_IA_valid & ~rstD, IQ_IA_pc, IQ_IA_inst},
       D.en0,
       {D_IB_valid, D.IB_pc, D.IB_inst}
   );

src/Core/Queue.sv

@@ -0,0 +1,81 @@
+`include "defines.svh"
+
+module Queue #(parameter WIDTH = 64) (
+    input clk,
+    input rst,
+
+    input  logic             vinA,
+    input  logic [WIDTH-1:0] inA,
+
+    input  logic             vinB,
+    input  logic [WIDTH-1:0] inB,
+
+    input  logic             enA,
+    output logic             voutA,
+    output logic [WIDTH-1:0] outA,
+
+    input  logic             enB,
+    output logic             voutB,
+    output logic [WIDTH-1:0] outB,
+
+    output logic [3:0]       valids
+);
+
+  typedef struct packed {
+    logic             valid;
+    logic [WIDTH-1:0] data;
+  } item_t;
+
+  logic  en1,   en2,   en3,   en4;
+  item_t item1, item2, item3, item4;
+  item_t next1, next2, next3, next4;
+
+  assign {voutA, outA} = item1.valid ? item1 : {vinA, inA};
+  assign {voutB, outB} = item2.valid ? item2 : item1.valid ? {vinA, inA} : {vinB, inB};
+
+  assign en1 = ~enA & ~item1.valid | enA & (~enB | item1.valid);
+  assign en2 = ~enA & ~item2.valid | enA & (~enB & item1.valid | item2.valid);
+  assign en3 = ~enA & (item1.valid & ~item2.valid | item2.valid & ~item3.valid) | enA & item2.valid & (~enB | item3.valid);
+  assign en4 = ~enA & (item2.valid & ~item3.valid | item3.valid & ~item4.valid) | enA & item3.valid & (~enB | item4.valid);
+
+  assign valids = {item4.valid, item3.valid, item2.valid, item1.valid};
+
+  mux4 #(1 + WIDTH) next1_mux (
+      {vinB, inB},
+      {vinA, inA},
+      item3,
+      item2,
+      {item2.valid & (~enB | item3.valid), (~enB & (~enA | item1.valid) | enB & ~item3.valid & item2.valid)}
+      next1
+  );
+  mux4 #(1 + WIDTH) next2_mux (
+      {vinB, inB},
+      {vinA, inA},
+      item4,
+      item3,
+      {item3.valid & (~enB | item4.valid), item1.valid & (~enB & (~enA | item2.valid) | enB & item3.valid & ~item4.valid)}
+      next2
+  );
+  mux3 #(1 + WIDTH) next3_mux (
+      {vinB, inB},
+      {vinA, inA},
+      item4,
+      {~enB & item4.valid, item2.valid & (~enB & (~enA | item3.valid) | item4.valid)},
+      next3
+  );
+  mux2 #(1 + WIDTH) next4_mux (
+      {vinB, inB},
+      {vinA, inA},
+      ~enB & item3.valid & (~enA | item4.valid),
+      next4
+  );
+
+  ffenr #(1) valid1_ff (clk, rst, next1.valid, en1, item1.valid);
+  ffenr #(1) valid2_ff (clk, rst, next2.valid, en2, item2.valid);
+  ffenr #(1) valid3_ff (clk, rst, next3.valid, en3, item3.valid);
+  ffenr #(1) valid4_ff (clk, rst, next4.valid, en4, item4.valid);
+  ffen #(WIDTH) data1_ff (clk, next1.data, en1, item1.data);
+  ffen #(WIDTH) data2_ff (clk, next2.data, en2, item2.data);
+  ffen #(WIDTH) data3_ff (clk, next3.data, en3, item3.data);
+  ffen #(WIDTH) data4_ff (clk, next4.data, en4, item4.data);
+endmodule