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fix bug
This commit is contained in:
cxy004 2021-08-01 18:39:19 +08:00 committed by Paul Pan
parent b352e51af0
commit 988cf28b3e
1 changed files with 16 additions and 9 deletions
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25
src/Core/Datapath.sv
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@ -56,6 +56,7 @@ module Datapath (
// F
logic F_valid;
logic F_free;
// Instr Queue
logic IQ_IA_valid;
@ -111,7 +112,6 @@ module Datapath (
logic D_IA_DataHazard;
logic D_IB_DataHazard;
// Execute
logic E_valid;
logic E_go;
@ -223,10 +223,10 @@ module Datapath (
| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.BJRJ | D_readygo)
& (rstD
| ~IQ_valids[3]
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo)
| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_readygo & D_readygo1));
| ~IQ_valids[2] & (F_free | PF.pc[2] | F.pc[2] | D_readygo)
| ~IQ_valids[1] & (F_free | PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
| ~IQ_valids[0] & (F_free & (PF.pc[2] | F.pc[2] | D_readygo) | PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
| IQ_valids[0] & (F_free & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1) | PF.pc[2] & F.pc[2] & D_readygo & D_readygo1)));
assign fetch_i.addr = {PF.pc[31:3], 3'b000};
//---------------------------------------------------------------------------//
@ -235,10 +235,17 @@ module Datapath (
// F.FF
ffenr #(1) F_valid_ff (
clk, rst,
1'b1,
1'b1,
F_valid
clk, rst,
1'b1,
1'b1,
F_valid
);
ffenr #(1) F_free_ff (
clk, rst,
~F.en,
F.en | fetch_i.data_ok,
F_free
);
ffenr #(32) F_pc_ff (