Fix HI/LO
This commit is contained in:
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7c5fef05b0
commit
57b9d66643
@ -1,7 +1,7 @@
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//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
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//Date : Mon Aug 8 13:32:33 2022
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//Date : Tue Aug 16 17:39:17 2022
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//Host : Laptop-Paul running 64-bit Manjaro Linux
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//Command : generate_target mycpu_block_wrapper.bd
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//Design : mycpu_block_wrapper
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@ -42,6 +42,12 @@ module mycpu_block_wrapper
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spi_rtl_0_io1_io,
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spi_rtl_0_sck_io,
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spi_rtl_0_ss_io,
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uart_rtl_0_cts,
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uart_rtl_0_dcd,
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uart_rtl_0_dsr,
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uart_rtl_0_dtr,
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uart_rtl_0_ri,
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uart_rtl_0_rts,
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uart_rtl_0_rxd,
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uart_rtl_0_txd);
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input clk;
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@ -76,6 +82,12 @@ module mycpu_block_wrapper
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inout spi_rtl_0_io1_io;
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inout spi_rtl_0_sck_io;
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inout [0:0]spi_rtl_0_ss_io;
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input uart_rtl_0_cts;
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input uart_rtl_0_dcd;
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input uart_rtl_0_dsr;
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output uart_rtl_0_dtr;
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input uart_rtl_0_ri;
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output uart_rtl_0_rts;
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input uart_rtl_0_rxd;
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output uart_rtl_0_txd;
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@ -126,6 +138,12 @@ module mycpu_block_wrapper
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wire [0:0]spi_rtl_0_ss_io_0;
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wire [0:0]spi_rtl_0_ss_o_0;
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wire spi_rtl_0_ss_t;
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wire uart_rtl_0_cts;
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wire uart_rtl_0_dcd;
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wire uart_rtl_0_dsr;
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wire uart_rtl_0_dtr;
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wire uart_rtl_0_ri;
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wire uart_rtl_0_rts;
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wire uart_rtl_0_rxd;
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wire uart_rtl_0_txd;
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@ -177,11 +195,15 @@ module mycpu_block_wrapper
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.spi_rtl_0_ss_i(spi_rtl_0_ss_i_0),
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.spi_rtl_0_ss_o(spi_rtl_0_ss_o_0),
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.spi_rtl_0_ss_t(spi_rtl_0_ss_t),
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.uart_rtl_0_ctsn(1'b0),
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.uart_rtl_0_dcdn(1'b0),
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.uart_rtl_0_ri(1'b1),
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.uart_rtl_0_ctsn(~uart_rtl_0_cts),
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.uart_rtl_0_dcdn(~uart_rtl_0_dcd),
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.uart_rtl_0_dsrn(~uart_rtl_0_dsr),
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.uart_rtl_0_dtrn(~uart_rtl_0_dtr),
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.uart_rtl_0_ri(uart_rtl_0_ri),
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.uart_rtl_0_rtsn(~uart_rtl_0_rts),
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.uart_rtl_0_rxd(uart_rtl_0_rxd),
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.uart_rtl_0_txd(uart_rtl_0_txd));
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IOBUF spi_rtl_0_io0_iobuf
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(.I(spi_rtl_0_io0_o),
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.IO(spi_rtl_0_io0_io),
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File diff suppressed because it is too large
Load Diff
@ -195,9 +195,7 @@ module mycpu_block_wrapper
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.uart_rtl_0_ctsn(~uart_rtl_0_cts),
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.uart_rtl_0_dcdn(~uart_rtl_0_dcd),
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.uart_rtl_0_dsrn(~uart_rtl_0_dsr),
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.uart_rtl_0_dtrn(~uart_rtl_0_dtr),
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.uart_rtl_0_ri(uart_rtl_0_ri),
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.uart_rtl_0_rtsn(~uart_rtl_0_rts),
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.uart_rtl_0_rxd(uart_rtl_0_rxd),
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.uart_rtl_0_txd(uart_rtl_0_txd));
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endmodule
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333
resources/soft/func/inst/n103_memory1.S
Normal file
333
resources/soft/func/inst/n103_memory1.S
Normal file
@ -0,0 +1,333 @@
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#include <asm.h>
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#include <regdef.h>
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#include <inst_test.h>
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LEAF(n103_memory1_test)
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.set noreorder
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addiu s0, s0 ,1
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li s2, 0x0
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###test inst
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move a0, k0
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move a1, k1
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#########################################
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li v0, 0x800d0000
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li v1, 0x800f0000
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mfc0 t5, $9, 0
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move k0, t5
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move k1, t5
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addiu t6, t5, 42
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addiu t7, t6, 42
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addiu t8, t7, 42
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addiu s5, t8, 42
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addiu s6, s5, 42
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addiu s7, s6, 42
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addiu s8, s7, 42
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1:
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beq v0, v1, 2f
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nop
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sw t5, 0(v0)
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sw t6, 4(v0)
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sw t7, 8(v0)
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sw t8, 12(v0)
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sw s5, 16(v0)
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sw s6, 20(v0)
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sw s7, 24(v0)
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sw s8, 28(v0)
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addiu v0, v0, 32
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addiu t5, t5, 11
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addiu t6, t6, 11
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addiu t7, t7, 11
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addiu t8, t8, 11
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addiu s5, s5, 11
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addiu s6, s6, 11
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addiu s7, s7, 11
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addiu s8, s8, 11
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j 1b
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nop
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2:
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li v0, 0x800d0000
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1:
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beq v0, v1, 2f
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nop
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lw t5, 0(v0)
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lw t6, 4(v0)
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lw t7, 8(v0)
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lw t8, 12(v0)
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lw s5, 16(v0)
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lw s6, 20(v0)
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lw s7, 24(v0)
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lw s8, 28(v0)
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move t4, k0
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bne t5, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t6, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t7, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t8, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s5, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s6, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s7, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s8, t4, inst_error
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nop
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addiu v0, v0, 32
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addiu k0, k0, 11
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j 1b
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nop
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2:
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#########################################
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li v0, 0x800e0000
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move t5, k0
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move t9, k0
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addiu t6, t5, 42
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addiu t7, t6, 42
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addiu t8, t7, 42
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addiu s5, t8, 42
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addiu s6, s5, 42
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addiu s7, s6, 42
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addiu s8, s7, 42
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1:
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beq v0, v1, 2f
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nop
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sw t5, 0(v0)
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sw t6, 4(v0)
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sw t7, 8(v0)
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sw t8, 12(v0)
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sw s5, 16(v0)
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sw s6, 20(v0)
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sw s7, 24(v0)
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sw s8, 28(v0)
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addiu v0, v0, 32
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addiu t5, t5, 11
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addiu t6, t6, 11
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addiu t7, t7, 11
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addiu t8, t8, 11
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addiu s5, s5, 11
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addiu s6, s6, 11
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addiu s7, s7, 11
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addiu s8, s8, 11
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j 1b
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nop
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2:
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li v0, 0x800d0000
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li v1, 0x800e0000
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1:
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beq v0, v1, 2f
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nop
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lw t5, 0(v0)
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lw t6, 4(v0)
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lw t7, 8(v0)
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lw t8, 12(v0)
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lw s5, 16(v0)
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lw s6, 20(v0)
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lw s7, 24(v0)
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lw s8, 28(v0)
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move t4, k1
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bne t5, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t6, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t7, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t8, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s5, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s6, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s7, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s8, t4, inst_error
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nop
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addiu v0, v0, 32
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addiu k1, k1, 11
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j 1b
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nop
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2:
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li v0, 0x800e0000
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li v1, 0x800f0000
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1:
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beq v0, v1, 2f
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nop
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lw t5, 0(v0)
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lw t6, 4(v0)
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lw t7, 8(v0)
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lw t8, 12(v0)
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lw s5, 16(v0)
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lw s6, 20(v0)
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lw s7, 24(v0)
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lw s8, 28(v0)
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move t4, t9
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bne t5, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t6, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t7, t4, inst_error
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nop
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addiu t4, t4, 42
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bne t8, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s5, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s6, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s7, t4, inst_error
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nop
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addiu t4, t4, 42
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bne s8, t4, inst_error
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nop
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addiu v0, v0, 32
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addiu t9, t9, 11
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j 1b
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nop
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2:
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#########################################
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li v0, 0x800d0000
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li v1, 0x800f0000
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mfc0 t5, $9, 0
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move k0, t5
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move k1, t5
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addiu t6, t5, 42
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addiu t7, t6, 42
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addiu t8, t7, 42
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addiu s5, t8, 42
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addiu s6, s5, 42
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addiu s7, s6, 42
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addiu s8, s7, 42
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1:
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beq v0, v1, 2f
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nop
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sw t5, 0(v0)
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sw t6, 4(v0)
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sw t7, 8(v0)
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sw t8, 12(v0)
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sw s5, 16(v0)
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sw s6, 20(v0)
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sw s7, 24(v0)
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sw s8, 28(v0)
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addiu v0, v0, 32
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addiu t5, t5, 11
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addiu t6, t6, 11
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addiu t7, t7, 11
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addiu t8, t8, 11
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addiu s5, s5, 11
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addiu s6, s6, 11
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addiu s7, s7, 11
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addiu s8, s8, 11
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j 1b
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nop
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2:
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li v0, 0x800d0000
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1:
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beq v0, v1, 2f
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nop
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lw t5, 0(v0)
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sw t5, 4(v0)
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lw t5, 8(v0)
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sw t5, 12(v0)
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lw t5, 16(v0)
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sw t5, 20(v0)
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lw t5, 24(v0)
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sw t5, 28(v0)
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addiu v0, v0, 32
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j 1b
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nop
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2:
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li v0, 0x800d0000
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1:
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beq v0, v1, 2f
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nop
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lw t5, 0(v0)
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lw t6, 4(v0)
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lw t7, 8(v0)
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lw t8, 12(v0)
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lw s5, 16(v0)
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lw s6, 20(v0)
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lw s7, 24(v0)
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lw s8, 28(v0)
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addiu v0, v0, 32
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move t4, k0
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bne t4, t5, inst_error
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nop
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bne t4, t6, inst_error
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nop
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addiu t4, t4, 84
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bne t4, t7, inst_error
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nop
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bne t4, t8, inst_error
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nop
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addiu t4, t4, 84
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bne t4, s5, inst_error
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nop
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bne t4, s6, inst_error
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nop
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addiu t4, t4, 84
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bne t4, s7, inst_error
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nop
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bne t4, s8, inst_error
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nop
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addiu k0, k0, 11
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j 1b
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nop
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2:
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#########################################
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move k0, a0
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move k1, a1
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###detect exception
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bne s2, zero, inst_error
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nop
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###score ++
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addiu s3, s3, 1
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###output (s0<<24)|s3
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inst_error:
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sll t1, s0, 24
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or t0, t1, s3
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sw t0, 0(s1)
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jr ra
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nop
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END(n103_memory1_test)
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61
resources/soft/func/inst/n104_linux.S
Normal file
61
resources/soft/func/inst/n104_linux.S
Normal file
@ -0,0 +1,61 @@
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#include <asm.h>
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#include <regdef.h>
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#include <inst_test.h>
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LEAF(n104_linux)
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.set noreorder
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addiu s0, s0 ,1
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li s2, 0x0
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###test inst
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#########################
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## lw + mthi/lo hazard ##
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#########################
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li a0, 0x42424242
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li a1, 0x800d0000
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sw a0, 0(a1)
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j 1f
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nop
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1:
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lw v0, 0(a1)
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mthi v0
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nop;nop;nop;nop;
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mfhi v1
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bne a0, v1, inst_error
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nop
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mfhi v0
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sw v0, 4(a1)
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nop;nop;nop;nop;nop;nop;nop;
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nop;nop;nop;nop;nop;nop;nop;
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lw v1, 4(a1)
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bne a0, v1, inst_error
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nop
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## mips_next_event
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#########################################
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move k0, a0
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move k1, a1
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###detect exception
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bne s2, zero, inst_error
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nop
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###score ++
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addiu s3, s3, 1
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###output (s0<<24)|s3
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inst_error:
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sll t1, s0, 24
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or t0, t1, s3
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sw t0, 0(s1)
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jr ra
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nop
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END(n104_linux)
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@ -8,6 +8,52 @@ LEAF(n99_cache_icache_test)
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li s2, 0x0
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###test inst
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# series test
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li v0, 0x9fc00000
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li v1, 0x9fc0ff00
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1:
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beq v0, v1, 2f
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nop
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addiu v0, v0, 0x100
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cache 16, 0(v0)
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cache 16, 64(v0)
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cache 16, 128(v0)
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cache 16, 192(v0)
|
||||
cache 16, 256(v0)
|
||||
cache 16, 320(v0)
|
||||
cache 16, 384(v0)
|
||||
cache 16, 448(v0)
|
||||
cache 16, 512(v0)
|
||||
cache 16, 576(v0)
|
||||
cache 16, 640(v0)
|
||||
cache 16, 704(v0)
|
||||
cache 16, 768(v0)
|
||||
cache 16, 832(v0)
|
||||
cache 16, 896(v0)
|
||||
cache 16, 960(v0)
|
||||
cache 16, 1024(v0)
|
||||
cache 16, 1088(v0)
|
||||
cache 16, 1152(v0)
|
||||
cache 16, 1216(v0)
|
||||
cache 16, 1280(v0)
|
||||
cache 16, 1344(v0)
|
||||
cache 16, 1408(v0)
|
||||
cache 16, 1472(v0)
|
||||
cache 16, 1536(v0)
|
||||
cache 16, 1600(v0)
|
||||
cache 16, 1664(v0)
|
||||
cache 16, 1728(v0)
|
||||
cache 16, 1792(v0)
|
||||
cache 16, 1856(v0)
|
||||
cache 16, 1920(v0)
|
||||
cache 16, 1984(v0)
|
||||
j 1b
|
||||
nop
|
||||
2:
|
||||
|
||||
|
||||
|
||||
.n99_1_prepare:
|
||||
addi a1, zero, 0
|
||||
.n99_1:
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
#include <utils.h>
|
||||
|
||||
#define TEST_NUM 152
|
||||
#define TEST_NUM 156
|
||||
|
||||
|
||||
##s0, number
|
||||
@ -309,6 +309,8 @@ locate:
|
||||
lui s0, 0 ## initial run number
|
||||
|
||||
inst_test:
|
||||
TEST_UNIT_CACHE(n104_linux)
|
||||
|
||||
TEST_UNIT_CACHE(n1_lui_test) # 1 2
|
||||
TEST_UNIT_CACHE(n2_addu_test)
|
||||
TEST_UNIT_CACHE(n3_addiu_test)
|
||||
@ -417,8 +419,6 @@ inst_test:
|
||||
TEST_UNIT_CACHE(n96_maddu_test)
|
||||
TEST_UNIT_CACHE(n97_msub_msubu_test)
|
||||
|
||||
TEST_UNIT(n98_cache_dcache_test) # 146
|
||||
TEST_UNIT_ONLY_CACHE(n99_cache_icache_test)
|
||||
|
||||
TEST_UNIT_CACHE(n100_movz_movn_test) # 148 149
|
||||
|
||||
@ -426,6 +426,11 @@ inst_test:
|
||||
|
||||
TEST_UNIT_CACHE(n102_memory_test) # 151 152
|
||||
|
||||
TEST_UNIT_ONLY_CACHE(n103_memory1_test) # 153
|
||||
|
||||
TEST_UNIT(n98_cache_dcache_test) # 146
|
||||
TEST_UNIT_ONLY_CACHE(n99_cache_icache_test)
|
||||
|
||||
###check io access
|
||||
LI (a0, IO_SIMU_ADDR)
|
||||
LI (t0, 0x1234)
|
||||
|
||||
@ -883,7 +883,7 @@ module Datapath (
|
||||
assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid;
|
||||
assign E.I0.ERET = E_I0_PrevERET & ~C0_int;
|
||||
assign E.I0.REFILL = E_I0_PrevREFILL & ~C0_int;
|
||||
assign E.I0.ExcCode = C0_int ? 5'h0
|
||||
assign E.I0.ExcCode = C0_int ? `EXCCODE_INT
|
||||
: E_I0_PrevExcValid ? E_I0_PrevExcCode : `EXCCODE_OV;
|
||||
|
||||
assign E_I1_NowExcValidWithoutOF = C0_int & E_valid | E.I1.MCtrl.MR & E_I1_STRBERROR;
|
||||
@ -892,7 +892,7 @@ module Datapath (
|
||||
assign E.I1.ExcValid = E_I1_PrevExcValid | E_I1_NowExcValid;
|
||||
assign E.I1.ERET = E_I1_PrevERET & ~C0_int;
|
||||
assign E.I1.REFILL = E_I1_PrevREFILL & ~C0_int;
|
||||
assign E.I1.ExcCode = C0_int ? 5'h0
|
||||
assign E.I1.ExcCode = C0_int ? `EXCCODE_INT
|
||||
: E_I1_PrevExcValid ? E_I1_PrevExcCode
|
||||
: E_I1_Overflow & E.I1.OFA ? `EXCCODE_OV
|
||||
: E.I1.MCtrl.MWR ? `EXCCODE_ADES : `EXCCODE_ADEL;
|
||||
@ -1354,19 +1354,19 @@ module Datapath (
|
||||
ffen #(32) HI_ff (
|
||||
clk,
|
||||
M_I0_HI,
|
||||
M.I0.MCtrl.HW & M_go,
|
||||
M.I0.MCtrl.HW & M_I0_go & M.en,
|
||||
HI
|
||||
);
|
||||
ffen #(32) LO_ff (
|
||||
clk,
|
||||
M_I0_LO,
|
||||
M.I0.MCtrl.LW & M_go,
|
||||
M.I0.MCtrl.LW & M_I0_go & M.en,
|
||||
LO
|
||||
);
|
||||
|
||||
assign C0_addr = M.I0.MCtrl.C0D;
|
||||
assign C0_sel = M.I0.MCtrl.SEL;
|
||||
assign C0_we = M.I0.MCtrl.C0W & M_I0_go;
|
||||
assign C0_we = M.I0.MCtrl.C0W & M_I0_go & M.en;
|
||||
assign C0_wdata = M_I0_ForwardT;
|
||||
|
||||
// M.I1.MEM
|
||||
|
||||
Loading…
Reference in New Issue
Block a user