508 lines
10 KiB
ArmAsm
508 lines
10 KiB
ArmAsm
#include <asm.h>
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#include <regdef.h>
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#include <cpu_cde.h>
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#include <utils.h>
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#define TEST_NUM 156
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##s0, number
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##s1, number adress
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##s2, exception use
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##s3, score
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##s4, exception pc
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.set noreorder
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.globl _start
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.globl start
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.globl __main
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_start:
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start:
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li t0, 0xffffffff
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addiu t0, zero, 0xffff
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b locate
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nop
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##avoid "j locate" not taken
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lui t0, 0x8000
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addiu t1, t1, 1
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or t2, t0, zero
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addu t3, t5, t6
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lw t4, 0(t0)
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nop
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##avoid cpu run error
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.org 0x0ec
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lui t0, 0x8000
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addiu t1, t1, 1
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or t2, t0, zero
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addu t3, t5, t6
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lw t4, 0(t0)
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.org 0x100
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test_finish:
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addiu t0, t0, 1
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li t1, 0xff
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LI (t2, UART_ADDR)
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sw t1, 0x0(t2)
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b test_finish
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nop
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##avoid cpu run error
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lui t0, 0x8000
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addiu t1, t1, 1
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or t2, t0, zero
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addu t3, t5, t6
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lw t4, 0(t0)
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/*
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* exception handle
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*/
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.org 0x380
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1:
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mfhi k0
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mflo k1
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li k0, 0x800d0000
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lw k1, 0x0(k0)
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li k0, 0x01 # syscall
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beq k1, k0, syscall_ex
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nop
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li k0, 0x02 # break
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beq k1, k0, break_ex
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nop
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li k0, 0x03 # overflow
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beq k1, k0, overflow_ex
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nop
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li k0, 0x04 # adel(load)
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beq k1, k0, adel_load_ex
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nop
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li k0, 0x05 # ades
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beq k1, k0, ades_ex
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nop
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li k0, 0x06 # adel(inst fetch)
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beq k1, k0, adel_if_ex
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nop
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li k0, 0x07 # reserved inst
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beq k1, k0, reserved_inst_ex
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nop
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li k0, 0x08 # int
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beq k1, k0, int_ex
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nop
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li k0, 0x09 # trap
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beq k1, k0, trap_ex
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nop
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b test_finish # Not recognized
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nop
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syscall_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2
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li k1, 0x20 # 010_0000
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02
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li k1, 0x02
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bne k0, k1, ex_finish
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nop
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lui s2, 0x1
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b ex_finish
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nop
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break_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2
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li k1, 0x24 # 010_0100
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # exl
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li k1, 0x02 # exl = 1
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bne k0, k1, ex_finish
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nop
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lui s2, 0x2
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b ex_finish
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nop
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overflow_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2 exc code
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li k1, 0x30 # 011_0000
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # exl
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li k1, 0x02 # exl = 1
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bne k0, k1, ex_finish
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nop
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lui s2, 0x3
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b ex_finish
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nop
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adel_load_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2 exc code
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li k1, 0x10 # 001_0000
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # exl
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li k1, 0x02 # exl = 1
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bne k0, k1, ex_finish
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nop
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lui s2, 0x4
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b ex_finish
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nop
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ades_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2 exc code
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li k1, 0x14 # 001_0100
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # exl
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li k1, 0x02 # exl = 1
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bne k0, k1, ex_finish
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nop
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lui s2, 0x5
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b ex_finish
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nop
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adel_if_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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mtc0 s5, c0_epc
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2 exc code
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li k1, 0x10 # 001_0000
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # exl
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li k1, 0x02 # exl = 1
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bne k0, k1, ex_finish
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nop
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lui s2, 0x6
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b ex_finish
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nop
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reserved_inst_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2 exc code
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li k1, 0x28 # 010_1000
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # exl
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li k1, 0x02 # exl = 1
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bne k0, k1, ex_finish
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nop
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lui s2, 0x7
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b ex_finish
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nop
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int_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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addiu k0, k0, 8
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mtc0 k0, c0_epc //epc+8
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disable_trace_cmp_s
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mfc0 k0, c0_cause //don't compare cause.bd
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enable_trace_cmp_s
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andi k0, k0, 0x7c # 6..2 exc code
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li k1, 0x00 # 000_0000
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # exl
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li k1, 0x02 # exl = 1
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bne k0, k1, ex_finish
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nop
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li k0, 0xffffffff
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li k1, 0x00000000
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mtc0 k0, c0_compare //clear compare
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mtc0 k1, c0_cause
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lui s2, 0x8
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b ex_ret
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nop
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trap_ex:
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addu s2, zero, zero
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mfc0 k0, c0_epc
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bne k0, s4, ex_finish
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nop
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mfc0 k0, c0_cause
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andi k0, k0, 0x7c # 6..2
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li k1, 0x34 # Trap EXCCODE << 2
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bne k0, k1, ex_finish
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nop
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mfc0 k0, c0_status
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andi k0, k0, 0x02 # EXL
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li k1, 0x02
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bne k0, k1, ex_finish
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nop
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lui s2, 0x9
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b ex_finish
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nop
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ex_finish:
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mfc0 k0,c0_cause
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lui k1,0x8000
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and k0,k0,k1
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mfc0 k1,c0_epc
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addiu k1,k1,0x4
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beq k0,zero, 1f
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nop
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addiu k1,k1,0x4
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1:
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mtc0 k1,c0_epc
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nop
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bne s2, zero, ex_ret
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nop
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lui s2, 0xffff
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ex_ret:
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.set mips32
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eret
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.set mips1
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nop
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locate:
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.set noreorder
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LI (a0, LED_RG1_ADDR)
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LI (a1, LED_RG0_ADDR)
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LI (s1, NUM_ADDR)
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LI (t1, 0x0002)
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LI (t2, 0x0001)
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lui s3, 0
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sw t1, 0(a0)
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sw t2, 0(a1)
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sw s3, 0(s1)
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lui s0, 0 ## initial run number
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inst_test:
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TEST_UNIT_CACHE(n104_linux)
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TEST_UNIT_CACHE(n1_lui_test) # 1 2
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TEST_UNIT_CACHE(n2_addu_test)
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TEST_UNIT_CACHE(n3_addiu_test)
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TEST_UNIT(n4_beq_test) # 7
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TEST_UNIT(n5_bne_test)
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TEST_UNIT_CACHE(n6_lw_test) # 9 10
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TEST_UNIT_CACHE(n7_or_test)
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TEST_UNIT_CACHE(n8_slt_test)
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TEST_UNIT_CACHE(n9_slti_test)
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TEST_UNIT_CACHE(n10_sltiu_test)
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TEST_UNIT_CACHE(n11_sll_test)
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TEST_UNIT_CACHE(n12_sw_test)
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TEST_UNIT(n13_j_test) # 23
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TEST_UNIT(n14_jal_test)
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TEST_UNIT(n15_jr_test)
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TEST_UNIT(n16_beq_ds_test)
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TEST_UNIT(n17_bne_ds_test)
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TEST_UNIT(n18_j_ds_test)
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TEST_UNIT(n19_jal_ds_test)
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TEST_UNIT(n20_jr_ds_test)
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TEST_UNIT_CACHE(n21_add_test) # 31 32
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TEST_UNIT_CACHE(n22_addi_test)
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TEST_UNIT_CACHE(n23_sub_test)
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TEST_UNIT_CACHE(n24_subu_test)
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TEST_UNIT_CACHE(n25_sltu_test)
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TEST_UNIT_CACHE(n26_and_test)
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TEST_UNIT_CACHE(n27_andi_test)
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TEST_UNIT_CACHE(n28_nor_test)
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TEST_UNIT_CACHE(n29_ori_test)
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TEST_UNIT_CACHE(n30_xor_test)
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TEST_UNIT_CACHE(n31_xori_test)
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TEST_UNIT_CACHE(n32_sllv_test)
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TEST_UNIT_CACHE(n33_sra_test)
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TEST_UNIT_CACHE(n34_srav_test)
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TEST_UNIT_CACHE(n35_srl_test)
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TEST_UNIT_CACHE(n36_srlv_test)
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TEST_UNIT(n37_bgez_test) # 63
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TEST_UNIT(n38_bgtz_test)
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TEST_UNIT(n39_blez_test)
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TEST_UNIT(n40_bltz_test)
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TEST_UNIT(n41_bltzal_test)
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TEST_UNIT(n42_bgezal_test)
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TEST_UNIT(n43_jalr_test)
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TEST_UNIT_CACHE(n44_div_test) # 70 71
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TEST_UNIT_CACHE(n45_divu_test)
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TEST_UNIT_CACHE(n46_mult_test)
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TEST_UNIT_CACHE(n47_multu_test)
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TEST_UNIT_CACHE(n48_mfhi_test)
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TEST_UNIT_CACHE(n49_mflo_test)
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TEST_UNIT_CACHE(n50_mthi_test)
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TEST_UNIT_CACHE(n51_mtlo_test)
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TEST_UNIT(n52_bgez_ds_test) # 86
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TEST_UNIT(n53_bgtz_ds_test)
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TEST_UNIT(n54_blez_ds_test)
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TEST_UNIT(n55_bltz_ds_test)
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TEST_UNIT(n56_bltzal_ds_test)
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TEST_UNIT(n57_bgezal_ds_test)
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TEST_UNIT(n58_jalr_ds_test)
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TEST_UNIT_CACHE(n59_lb_test) # 93 94
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TEST_UNIT_CACHE(n60_lbu_test)
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TEST_UNIT_CACHE(n61_lh_test)
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TEST_UNIT_CACHE(n62_lhu_test)
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TEST_UNIT_CACHE(n63_sb_test)
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TEST_UNIT_CACHE(n64_sh_test)
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TEST_UNIT(n65_syscall_ex_test) # 105
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TEST_UNIT(n66_break_ex_test)
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TEST_UNIT(n67_add_ov_ex_test)
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TEST_UNIT(n68_addi_ov_ex_test)
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TEST_UNIT(n69_sub_ov_ex_test)
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TEST_UNIT(n70_lw_adel_ex_test)
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TEST_UNIT(n71_lh_adel_ex_test)
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TEST_UNIT(n72_lhu_adel_ex_test)
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TEST_UNIT(n73_sw_ades_ex_test)
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TEST_UNIT(n74_sh_ades_ex_test)
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TEST_UNIT(n75_ft_adel_ex_test)
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TEST_UNIT(n76_ri_ex_test)
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TEST_UNIT(n77_soft_int_ex_test)
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TEST_UNIT(n78_beq_ds_ex_test)
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TEST_UNIT(n79_bne_ds_ex_test)
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TEST_UNIT(n80_bgez_ds_ex_test)
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TEST_UNIT(n81_bgtz_ds_ex_test)
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TEST_UNIT(n82_blez_ds_ex_test)
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TEST_UNIT(n83_bltz_ds_ex_test)
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TEST_UNIT(n84_bltzal_ds_ex_test)
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TEST_UNIT(n85_bgezal_ds_ex_test)
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TEST_UNIT(n86_j_ds_ex_test)
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TEST_UNIT(n87_jal_ds_ex_test)
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TEST_UNIT(n88_jr_ds_ex_test)
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TEST_UNIT(n89_jalr_ds_ex_test)
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TEST_UNIT_CACHE(n90_lwl_test) # 130 131
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TEST_UNIT_CACHE(n91_lwr_test)
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TEST_UNIT_CACHE(n92_swl_test)
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TEST_UNIT_CACHE(n93_swr_test)
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TEST_UNIT_CACHE(n94_perf_sync_nop_test)
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TEST_UNIT_CACHE(n95_madd_test)
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TEST_UNIT_CACHE(n96_maddu_test)
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TEST_UNIT_CACHE(n97_msub_msubu_test)
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TEST_UNIT_CACHE(n100_movz_movn_test) # 148 149
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TEST_UNIT(n101_trap_test) # 150
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TEST_UNIT_CACHE(n102_memory_test) # 151 152
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TEST_UNIT_ONLY_CACHE(n103_memory1_test) # 153
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TEST_UNIT(n98_cache_dcache_test) # 146
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TEST_UNIT_ONLY_CACHE(n99_cache_icache_test)
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###check io access
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LI (a0, IO_SIMU_ADDR)
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LI (t0, 0x1234)
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sw t0, 0(a0)
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lw t1, 0(a0) //t1=0x12340000
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sll t0, t0, 16
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bne t0, t1, io_err
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nop
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LI (t0, 0x56780000)
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sw t0, 0(a0)
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srl t0, t0, 16
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lw t1, 0(a0) //t1=0x5678
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bne t0, t1, io_err
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nop
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b test_end
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nop
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io_err:
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addiu s0, s0, 1
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sw s0, 0(s1)
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test_end:
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LI (s0, TEST_NUM)
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beq s0, s3, 1f
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nop
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LI (a0, LED_ADDR)
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LI (a1, LED_RG1_ADDR)
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LI (a2, LED_RG0_ADDR)
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LI (t1, 0x0002)
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sw zero, 0(a0)
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sw t1, 0(a1)
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sw t1, 0(a2)
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b 2f
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nop
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1:
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LI (t1, 0x0001)
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LI (a0, LED_RG1_ADDR)
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LI (a1, LED_RG0_ADDR)
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sw t1, 0(a0)
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sw t1, 0(a1)
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2:
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jal test_finish
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nop
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wait_1s:
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LI (t0,SW_INTER_ADDR)
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LI (t1, 0xaaaa)
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#initial t3
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lw t2, 0x0(t0) #switch_interleave: {switch[7],1'b0, switch[6],1'b0...switch[0],1'b0}
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xor t2, t2, t1
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sll t3, t2, 9 #t3 = switch interleave << 9
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addiu t3, t3, 1
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sub1:
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addiu t3, t3, -1
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#select min{t3, switch_interleave}
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lw t2, 0x0(t0) #switch_interleave: {switch[7],1'b0, switch[6],1'b0...switch[0],1'b0}
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xor t2, t2, t1
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sll t2, t2, 9 #switch interleave << 9
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sltu t4, t3, t2
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bnez t4, 1f
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|
nop
|
|
addu t3, t2, 0
|
|
1:
|
|
bne t3,zero, sub1
|
|
nop
|
|
jr ra
|
|
nop
|