fix: MU wstrb could directly passthrough
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b25fbb5ee1
commit
56cc2e5dcb
15
sim/Makefile
15
sim/Makefile
@ -14,7 +14,7 @@ VERILATOR_BUILD_FLAGS += -cc --exe
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# Generate makefile dependencies (not shown as complicates the Makefile)
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VERILATOR_BUILD_FLAGS += -MMD
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# Optimize
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VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast --no-threads
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VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast
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# Warn abount lint issues; may not want this on less solid designs
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VERILATOR_BUILD_FLAGS += -Wall
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# Make waveforms
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@ -54,24 +54,21 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour
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default: run
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test:
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@echo $(SOURCE)
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lint:
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$(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top
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func_test:
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func_build:
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$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT)
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func_coverage: func_test
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func_coverage: func_build
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@rm -rf logs/annotated
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$(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS)
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run: func_test
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run: func_build
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@rm -rf logs
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@mkdir -p logs
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obj_dir/Vtestbench_top
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GTK_THEME=Breath gtkwave logs/trace.vcd
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gtkwave logs/trace.vcd
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clean:
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-rm -rf obj_dir logs *.log *.dmp
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-rm -rf obj_dir logs
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@ -1,11 +1,11 @@
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#include <verilated.h>
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#include <chrono>
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#include <iostream>
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#include "Vtestbench_top.h"
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#include <verilated.h>
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vluint64_t main_time = 0;
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double sc_time_stamp() {
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return main_time;
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}
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double sc_time_stamp() { return main_time; }
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int main(int argc, char **argv, char **env) {
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Verilated::commandArgs(argc, argv);
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@ -14,22 +14,31 @@ int main(int argc, char **argv, char **env) {
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Verilated::mkdir("logs");
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const int reset_time = 10;
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const int time_limit = 2000000;
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const int time_limit = 2100000;
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Vtestbench_top *top = new Vtestbench_top;
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std::cout << "<<< Simulation Started >>>" << std::endl;
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auto time_start = std::chrono::high_resolution_clock::now();
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top->clk = 0;
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while (!Verilated::gotFinish() && main_time < time_limit) {
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++main_time;
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top->clk = !top->clk;
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top->resetn = (main_time < reset_time) ? 0 : 1;
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if (main_time < reset_time) VerilatedCov::zero();
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if (main_time < reset_time)
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VerilatedCov::zero();
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top->eval();
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}
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auto time_end = std::chrono::high_resolution_clock::now();
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if (main_time == time_limit)
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std::cout << "Time Limit Reached" << std::endl;
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std::cout << "<<< Time Limit Reached >>>" << std::endl;
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std::cout << "<<< Simulation Ended >>>" << std::endl;
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std::cout << "Realworld Time: "
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<< std::chrono::duration_cast<std::chrono::seconds>(time_end - time_start).count()
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<< "s" << std::endl;
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std::cout << "Simulation Time: " << main_time / 2 << " cycles" << std::endl;
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top->final();
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12
src/MU/MU.sv
12
src/MU/MU.sv
@ -354,16 +354,17 @@ module MU (
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memory.rdata
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);
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logic mem_wstrb_direct;
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DCData_t mem_wdata_source_data, mem_wdata_output;
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word_t mem_wdata_data;
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logic [`DC_INDEXL-3:0] base;
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assign base = stored_memory_addr[`DC_INDEXL-1:2];
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always_comb begin
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mem_wdata_output = mem_wdata_source_data;
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if (stored_memory_wstrb[3]) mem_wdata_output[{base, 5'd24}+:8] = mem_wdata_data[24+:8];
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if (stored_memory_wstrb[2]) mem_wdata_output[{base, 5'd16}+:8] = mem_wdata_data[16+:8];
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if (stored_memory_wstrb[1]) mem_wdata_output[{base, 5'd08}+:8] = mem_wdata_data[ 8+:8];
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if (stored_memory_wstrb[0]) mem_wdata_output[{base, 5'd00}+:8] = mem_wdata_data[ 0+:8];
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if ((mem_wstrb_direct ? memory.wstrb[3] : stored_memory_wstrb[3])) mem_wdata_output[{base, 5'd24}+:8] = mem_wdata_data[24+:8];
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if ((mem_wstrb_direct ? memory.wstrb[2] : stored_memory_wstrb[2])) mem_wdata_output[{base, 5'd16}+:8] = mem_wdata_data[16+:8];
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if ((mem_wstrb_direct ? memory.wstrb[1] : stored_memory_wstrb[1])) mem_wdata_output[{base, 5'd08}+:8] = mem_wdata_data[ 8+:8];
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if ((mem_wstrb_direct ? memory.wstrb[0] : stored_memory_wstrb[0])) mem_wdata_output[{base, 5'd00}+:8] = mem_wdata_data[ 0+:8];
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end
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@ -394,6 +395,7 @@ module MU (
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mem_rdata_source_data = dcache.hit_row;
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mem_wdata_source_data = dcache.hit_row;
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mem_wdata_data = stored_memory_wdata;
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mem_wstrb_direct = 0;
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// AXI Data Read
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amr_call = 0;
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@ -448,6 +450,7 @@ module MU (
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dcache.index_for_lookup = stored_memory_addr[`DC_TAGL-1:`DC_INDEXL];
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dcache.index = dcache.index_for_lookup; // stored_memory_addr[`DC_TAGL-1:`DC_INDEXL];
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mem_wstrb_direct = 1'b1; // wstrb is provided in stage M
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mem_wdata_source_data = dcache.hit_row;
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mem_wdata_data = memory.wdata; // wdata is provided in stage M
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dcache.update_row = mem_wdata_output;
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@ -526,6 +529,7 @@ module MU (
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dcache.tag = memory_phy_addr[`XLEN-1:`DC_TAGL];
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if (stored_memory_wr) begin
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mem_wstrb_direct = 0;
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mem_wdata_source_data = amr_buffer;
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mem_wdata_data = stored_memory_wdata;
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dcache.update_row = mem_wdata_output;
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