From 56cc2e5dcbf5def6e6c7fe977e9ca83ff94a1006 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Fri, 29 Jul 2022 23:25:14 +0800 Subject: [PATCH] fix: MU wstrb could directly passthrough --- sim/Makefile | 15 ++++++--------- sim/sim_main.cpp | 23 ++++++++++++++++------- src/MU/MU.sv | 12 ++++++++---- 3 files changed, 30 insertions(+), 20 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 3824c8b..11b0159 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -14,7 +14,7 @@ VERILATOR_BUILD_FLAGS += -cc --exe # Generate makefile dependencies (not shown as complicates the Makefile) VERILATOR_BUILD_FLAGS += -MMD # Optimize -VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast --no-threads +VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast # Warn abount lint issues; may not want this on less solid designs VERILATOR_BUILD_FLAGS += -Wall # Make waveforms @@ -54,24 +54,21 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour default: run -test: - @echo $(SOURCE) - lint: $(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top -func_test: +func_build: $(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT) -func_coverage: func_test +func_coverage: func_build @rm -rf logs/annotated $(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS) -run: func_test +run: func_build @rm -rf logs @mkdir -p logs obj_dir/Vtestbench_top - GTK_THEME=Breath gtkwave logs/trace.vcd + gtkwave logs/trace.vcd clean: - -rm -rf obj_dir logs *.log *.dmp + -rm -rf obj_dir logs diff --git a/sim/sim_main.cpp b/sim/sim_main.cpp index 403250d..fb31caa 100644 --- a/sim/sim_main.cpp +++ b/sim/sim_main.cpp @@ -1,11 +1,11 @@ -#include +#include +#include #include "Vtestbench_top.h" +#include vluint64_t main_time = 0; -double sc_time_stamp() { - return main_time; -} +double sc_time_stamp() { return main_time; } int main(int argc, char **argv, char **env) { Verilated::commandArgs(argc, argv); @@ -14,22 +14,31 @@ int main(int argc, char **argv, char **env) { Verilated::mkdir("logs"); const int reset_time = 10; - const int time_limit = 2000000; + const int time_limit = 2100000; Vtestbench_top *top = new Vtestbench_top; + std::cout << "<<< Simulation Started >>>" << std::endl; + auto time_start = std::chrono::high_resolution_clock::now(); top->clk = 0; while (!Verilated::gotFinish() && main_time < time_limit) { ++main_time; top->clk = !top->clk; top->resetn = (main_time < reset_time) ? 0 : 1; - if (main_time < reset_time) VerilatedCov::zero(); + if (main_time < reset_time) + VerilatedCov::zero(); top->eval(); } + auto time_end = std::chrono::high_resolution_clock::now(); if (main_time == time_limit) - std::cout << "Time Limit Reached" << std::endl; + std::cout << "<<< Time Limit Reached >>>" << std::endl; + std::cout << "<<< Simulation Ended >>>" << std::endl; + std::cout << "Realworld Time: " + << std::chrono::duration_cast(time_end - time_start).count() + << "s" << std::endl; + std::cout << "Simulation Time: " << main_time / 2 << " cycles" << std::endl; top->final(); diff --git a/src/MU/MU.sv b/src/MU/MU.sv index ce83f7b..b52a543 100644 --- a/src/MU/MU.sv +++ b/src/MU/MU.sv @@ -354,16 +354,17 @@ module MU ( memory.rdata ); + logic mem_wstrb_direct; DCData_t mem_wdata_source_data, mem_wdata_output; word_t mem_wdata_data; logic [`DC_INDEXL-3:0] base; assign base = stored_memory_addr[`DC_INDEXL-1:2]; always_comb begin mem_wdata_output = mem_wdata_source_data; - if (stored_memory_wstrb[3]) mem_wdata_output[{base, 5'd24}+:8] = mem_wdata_data[24+:8]; - if (stored_memory_wstrb[2]) mem_wdata_output[{base, 5'd16}+:8] = mem_wdata_data[16+:8]; - if (stored_memory_wstrb[1]) mem_wdata_output[{base, 5'd08}+:8] = mem_wdata_data[ 8+:8]; - if (stored_memory_wstrb[0]) mem_wdata_output[{base, 5'd00}+:8] = mem_wdata_data[ 0+:8]; + if ((mem_wstrb_direct ? memory.wstrb[3] : stored_memory_wstrb[3])) mem_wdata_output[{base, 5'd24}+:8] = mem_wdata_data[24+:8]; + if ((mem_wstrb_direct ? memory.wstrb[2] : stored_memory_wstrb[2])) mem_wdata_output[{base, 5'd16}+:8] = mem_wdata_data[16+:8]; + if ((mem_wstrb_direct ? memory.wstrb[1] : stored_memory_wstrb[1])) mem_wdata_output[{base, 5'd08}+:8] = mem_wdata_data[ 8+:8]; + if ((mem_wstrb_direct ? memory.wstrb[0] : stored_memory_wstrb[0])) mem_wdata_output[{base, 5'd00}+:8] = mem_wdata_data[ 0+:8]; end @@ -394,6 +395,7 @@ module MU ( mem_rdata_source_data = dcache.hit_row; mem_wdata_source_data = dcache.hit_row; mem_wdata_data = stored_memory_wdata; + mem_wstrb_direct = 0; // AXI Data Read amr_call = 0; @@ -448,6 +450,7 @@ module MU ( dcache.index_for_lookup = stored_memory_addr[`DC_TAGL-1:`DC_INDEXL]; dcache.index = dcache.index_for_lookup; // stored_memory_addr[`DC_TAGL-1:`DC_INDEXL]; + mem_wstrb_direct = 1'b1; // wstrb is provided in stage M mem_wdata_source_data = dcache.hit_row; mem_wdata_data = memory.wdata; // wdata is provided in stage M dcache.update_row = mem_wdata_output; @@ -526,6 +529,7 @@ module MU ( dcache.tag = memory_phy_addr[`XLEN-1:`DC_TAGL]; if (stored_memory_wr) begin + mem_wstrb_direct = 0; mem_wdata_source_data = amr_buffer; mem_wdata_data = stored_memory_wdata; dcache.update_row = mem_wdata_output;