spec
This commit is contained in:
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9048a4749d
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203
src/MU/DCache.sv
203
src/MU/DCache.sv
@ -1,6 +1,10 @@
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`include "defines.svh"
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`include "Cache.svh"
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`ifndef DC_SPEC_2WAY
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`ifndef DC_SPEC_1WAY
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module DCache (
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input clk,
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input rst,
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@ -158,3 +162,202 @@ module DCache (
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endmodule
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`else // 1way
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module DCache (
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input clk,
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input rst,
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DCache_i.cache port
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);
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// ==============================
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// ============ Vars ============
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// ==============================
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DCTagRAM_t TagRAM/*verilator split_var*/;
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DCDataRAM_t DataRAM/*verilator split_var*/;
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DCTag_t tag;
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DCData_t data;
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logic hit;
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DCTagL_t dirt_tag;
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logic wen;
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// ==============================
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// =========== Lookup ===========
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// ==============================
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assign tag = TagRAM.rdata;
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assign data = DataRAM.rdata;
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assign hit = tag.valid & tag.tag == port.tag;
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assign port.hit = hit;
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assign port.hit_row = data;
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// ==============================
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// ========== Replace ===========
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// ==============================
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assign port.dirt = tag.dirty;
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assign dirt_tag = tag.tag;
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assign port.dirt_addr = {dirt_tag, port.index, `DC_INDEXL'b0};
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assign port.dirt_row = data;
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// ==============================
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// ========= Block RAM ==========
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// ==============================
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// 地址
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assign TagRAM.addr = port.index_for_lookup;
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assign DataRAM.addr = port.index_for_lookup;
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// 写使能
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assign wen = port.ctrl.read_but_replace
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| port.ctrl.write_and_hit
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| port.ctrl.write_but_replace
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| port.ctrl.cache_index_invalidate
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| port.ctrl.cache_index_writeback
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| port.ctrl.cache_hit_invalidate & hit
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| port.ctrl.cache_hit_writeback & hit;
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assign TagRAM.wen = wen;
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assign DataRAM.wen = wen;
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// 写数据
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assign TagRAM.wdata = {port.tag, port.ctrl.write_and_hit | port.ctrl.write_but_replace, port.ctrl.read_but_replace | port.ctrl.write_and_hit | port.ctrl.write_but_replace};
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assign DataRAM.wdata = port.update_row;
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// BRAM 实例
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bram #(.DATA_WIDTH(32-`DC_TAGL+2), .DATA_DEPTH(2 ** (`DC_TAGL-`DC_INDEXL)))
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tag_ram (.rst(rst), .addra(TagRAM.addr), .clka(clk), .dina(TagRAM.wdata), .douta(TagRAM.rdata), .wea(TagRAM.wen));
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bram #(.DATA_WIDTH(`DC_DATA_LENGTH), .DATA_DEPTH(2 ** (`DC_TAGL-`DC_INDEXL)))
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data_ram (.rst(rst), .addra(DataRAM.addr), .clka(clk), .dina(DataRAM.wdata), .douta(DataRAM.rdata), .wea(DataRAM.wen));
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endmodule
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`endif
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`else // 2way
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module DCache (
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input clk,
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input rst,
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DCache_i.cache port
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);
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// ==============================
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// ============ Vars ============
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// ==============================
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DCTagRAM_t TagRAM[2]/*verilator split_var*/;
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DCDataRAM_t DataRAM[2]/*verilator split_var*/;
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logic LRU[`DC_INDEX_DEPTH];
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logic nowLRU;
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logic nxtLRU;
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DCTag_t tag[2];
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DCData_t data[2];
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logic [1:0] hitway;
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logic victim;
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DCTagL_t dirt_tag;
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logic [1:0] wen;
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// ==============================
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// =========== Lookup ===========
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// ==============================
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for (genvar i = 0; i < `DC_WAYS; i++) begin
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assign tag[i] = TagRAM[i].rdata;
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assign data[i] = DataRAM[i].rdata;
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assign hitway[i] = tag[i].valid & tag[i].tag == port.tag;
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end
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assign port.hit = |{hitway};
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assign port.hit_row = (hitway[0] ? data[0] : {`DC_DATA_LENGTH{1'b0}})
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| (hitway[1] ? data[1] : {`DC_DATA_LENGTH{1'b0}});
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// ==============================
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// ========== Replace ===========
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// ==============================
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assign victim = port.ctrl.cache_hit_writeback ? hitway[1]
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: port.ctrl.cache_index_writeback & tag[0].dirty ? 1'b0
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: port.ctrl.cache_index_writeback & tag[1].dirty ? 1'b1
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: tag[0].valid == 0 ? 1'b0
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: tag[1].valid == 0 ? 1'b1
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: ~nowLRU;
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assign port.dirt = tag[victim].dirty;
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assign dirt_tag = tag[victim].tag;
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assign port.dirt_addr = {dirt_tag, port.index, `DC_INDEXL'b0};
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assign port.dirt_row = data[victim];
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assign nxtLRU = (port.ctrl.read_and_hit ? hitway[1] : 1'b0)
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| (port.ctrl.read_but_replace ? victim : 1'b0)
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| (port.ctrl.write_and_hit ? hitway[1] : 1'b0)
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| (port.ctrl.write_but_replace ? victim : 1'b0);
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for (genvar i = 0; i < `DC_INDEX_DEPTH; i++)
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initial LRU[i] = 1'b0;
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always_ff @(posedge clk) begin
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if (~rst) begin
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if (port.ctrl.read_and_hit | port.ctrl.read_but_replace
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| port.ctrl.write_and_hit | port.ctrl.write_but_replace)
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LRU[port.index] <= nxtLRU;
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nowLRU <= LRU[port.index_for_lookup];
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end
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end
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// ==============================
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// ========= Block RAM ==========
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// ==============================
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// 地址
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for (genvar i = 0; i < `DC_WAYS; i++) begin
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assign TagRAM[i].addr = port.index_for_lookup;
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assign DataRAM[i].addr = port.index_for_lookup;
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end
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// 写使能
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assign wen = (port.ctrl.read_but_replace ? {victim, ~victim} : 2'b00)
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| (port.ctrl.write_and_hit ? hitway : 2'b00)
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| (port.ctrl.write_but_replace ? {victim, ~victim} : 2'b00)
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| (port.ctrl.cache_index_invalidate ? 2'b11 : 2'b00)
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| (port.ctrl.cache_index_writeback ? port.dirt ? {victim, ~victim} : 2'b11 : 2'b00)
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| (port.ctrl.cache_hit_invalidate ? hitway : 2'b00)
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| (port.ctrl.cache_hit_writeback ? hitway : 2'b00);
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for (genvar i = 0; i < `DC_WAYS; i++) begin
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assign TagRAM[i].wen = wen[i];
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assign DataRAM[i].wen = wen[i];
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end
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// 写数据
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for (genvar i = 0; i < `DC_WAYS; i++) begin
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assign TagRAM[i].wdata = {port.tag, port.ctrl.write_and_hit | port.ctrl.write_but_replace, port.ctrl.read_but_replace | port.ctrl.write_and_hit | port.ctrl.write_but_replace};
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assign DataRAM[i].wdata = port.update_row;
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end
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// BRAM 实例
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for (genvar i = 0; i < `DC_WAYS; i++) begin : dbram
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bram #(.DATA_WIDTH(32-`DC_TAGL+2), .DATA_DEPTH(2 ** (`DC_TAGL-`DC_INDEXL)))
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tag_ram (.rst(rst), .addra(TagRAM[i].addr), .clka(clk), .dina(TagRAM[i].wdata), .douta(TagRAM[i].rdata), .wea(TagRAM[i].wen));
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bram #(.DATA_WIDTH(`DC_DATA_LENGTH), .DATA_DEPTH(2 ** (`DC_TAGL-`DC_INDEXL)))
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data_ram (.rst(rst), .addra(DataRAM[i].addr), .clka(clk), .dina(DataRAM[i].wdata), .douta(DataRAM[i].rdata), .wea(DataRAM[i].wen));
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end
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endmodule
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`endif
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162
src/MU/ICache.sv
162
src/MU/ICache.sv
@ -1,6 +1,10 @@
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`include "defines.svh"
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`include "Cache.svh"
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`ifndef IC_SPEC_2WAY
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`ifndef IC_SPEC_1WAY
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module ICache (
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input clk,
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input rst,
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@ -117,3 +121,161 @@ module ICache (
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end
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endmodule
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`else // 1way
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module ICache (
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input clk,
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input rst,
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ICache_i.cache port
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);
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// ==============================
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// ============ Vars ============
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// ==============================
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ICTagRAM_t TagRAM/*verilator split_var*/;
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ICDataRAM_t DataRAM/*verilator split_var*/;
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ICTag_t tag;
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ICData_t data;
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logic hit;
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logic wen;
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// ==============================
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// =========== Lookup ===========
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// ==============================
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assign tag = TagRAM.rdata;
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assign data = DataRAM.rdata;
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assign hit = tag.valid & tag.tag == port.tag;
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assign port.hit = hit;
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assign port.hit_row = data;
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// ==============================
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// ========= Block RAM ==========
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// ==============================
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// 地址
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assign TagRAM.addr = port.index_for_lookup;
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assign DataRAM.addr = port.index_for_lookup;
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// 写使能
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assign wen = port.ctrl.read_but_replace | port.ctrl.cache_index_invalidate | port.ctrl.cache_hit_invalidate & hit;
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assign TagRAM.wen = wen;
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assign DataRAM.wen = wen;
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// 写数据
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assign TagRAM.wdata = {port.tag, port.ctrl.read_but_replace};
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assign DataRAM.wdata = port.update_row;
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// BRAM 实例
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bram #(.DATA_WIDTH(32-`IC_TAGL+1), .DATA_DEPTH(2 ** (`IC_TAGL-`IC_INDEXL)))
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tag_ram (.rst(rst), .addra(TagRAM.addr), .clka(clk), .dina(TagRAM.wdata), .douta(TagRAM.rdata), .wea(TagRAM.wen));
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bram #(.DATA_WIDTH(`IC_DATA_LENGTH), .DATA_DEPTH(2 ** (`IC_TAGL-`IC_INDEXL)))
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data_ram (.rst(rst), .addra(DataRAM.addr), .clka(clk), .dina(DataRAM.wdata), .douta(DataRAM.rdata), .wea(DataRAM.wen));
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endmodule
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`endif
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`else // 2way
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module ICache (
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input clk,
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input rst,
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ICache_i.cache port
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);
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// ==============================
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// ============ Vars ============
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// ==============================
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ICTagRAM_t TagRAM[2]/*verilator split_var*/;
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ICDataRAM_t DataRAM[2]/*verilator split_var*/;
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logic LRU[`IC_INDEX_DEPTH];
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logic nowLRU;
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logic nxtLRU;
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ICTag_t tag[2];
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ICData_t data[2];
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logic [1:0] hitway;
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logic victim;
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logic [1:0] wen;
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// ==============================
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// =========== Lookup ===========
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// ==============================
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for (genvar i = 0; i < `IC_WAYS; i++) begin
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assign tag[i] = TagRAM[i].rdata;
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assign data[i] = DataRAM[i].rdata;
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assign hitway[i] = tag[i].valid & tag[i].tag == port.tag;
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end
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assign port.hit = |{hitway};
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assign port.hit_row = (hitway[0] ? data[0] : {`IC_DATA_LENGTH{1'b0}})
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| (hitway[1] ? data[1] : {`IC_DATA_LENGTH{1'b0}});
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assign victim = tag[0].valid == 0 ? 1'b0
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: tag[1].valid == 0 ? 1'b1
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: ~nowLRU;
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assign nxtLRU = (port.ctrl.read_and_hit ? hitway[1] : 1'b0)
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| (port.ctrl.read_but_replace ? victim : 1'b0);
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for (genvar i = 0; i < `IC_INDEX_DEPTH; i++)
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initial LRU[i] = 1'b0;
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always_ff @(posedge clk) begin
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if (~rst) begin
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if (port.ctrl.read_and_hit | port.ctrl.read_but_replace)
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LRU[port.index] <= nxtLRU;
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nowLRU <= LRU[port.index_for_lookup];
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end
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end
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// ==============================
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// ========= Block RAM ==========
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// ==============================
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// 地址
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for (genvar i = 0; i < `IC_WAYS; i++) begin
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assign TagRAM[i].addr = port.index_for_lookup;
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assign DataRAM[i].addr = port.index_for_lookup;
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end
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// 写使能
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assign wen = (port.ctrl.read_but_replace ? {victim, ~victim} : 2'b00)
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| (port.ctrl.cache_index_invalidate ? 2'b11 : 2'b00)
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| (port.ctrl.cache_hit_invalidate ? hitway : 2'b00);
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for (genvar i = 0; i < `IC_WAYS; i++) begin
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assign TagRAM[i].wen = wen[i];
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assign DataRAM[i].wen = wen[i];
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end
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// 写数据
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for (genvar i = 0; i < `IC_WAYS; i++) begin
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assign TagRAM[i].wdata = {port.tag, port.ctrl.read_but_replace};
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assign DataRAM[i].wdata = port.update_row;
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end
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// BRAM 实例
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for (genvar i = 0; i < `IC_WAYS; i++) begin : ibram
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bram #(.DATA_WIDTH(32-`IC_TAGL+1), .DATA_DEPTH(2 ** (`IC_TAGL-`IC_INDEXL)))
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tag_ram (.rst(rst), .addra(TagRAM[i].addr), .clka(clk), .dina(TagRAM[i].wdata), .douta(TagRAM[i].rdata), .wea(TagRAM[i].wen));
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bram #(.DATA_WIDTH(`IC_DATA_LENGTH), .DATA_DEPTH(2 ** (`IC_TAGL-`IC_INDEXL)))
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data_ram (.rst(rst), .addra(DataRAM[i].addr), .clka(clk), .dina(DataRAM[i].wdata), .douta(DataRAM[i].rdata), .wea(DataRAM[i].wen));
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end
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endmodule
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`endif
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@ -14,6 +14,8 @@
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`define IC_ROW_LENGTH (`IC_DATA_LENGTH / `XLEN - 1)
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`define IC_INDEX_DEPTH (2 ** (`IC_TAGL - `IC_INDEXL))
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`define IC_WAYS 2
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// `define IC_SPEC_1WAY
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`define IC_SPEC_2WAY
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typedef logic [`IC_DATA_LENGTH-1:0] ICData_t;
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typedef logic [32-`IC_TAGL-1:0] ICTagL_t;
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@ -53,6 +55,8 @@ typedef struct packed {
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`define DC_ROW_LENGTH (`DC_DATA_LENGTH / `XLEN - 1)
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`define DC_INDEX_DEPTH (2 ** (`DC_TAGL - `DC_INDEXL))
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`define DC_WAYS 2
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// `define DC_SPEC_1WAY
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`define DC_SPEC_2WAY
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typedef logic [`DC_DATA_LENGTH-1:0] DCData_t;
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typedef logic [32-`DC_TAGL-1:0] DCTagL_t;
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@ -18,7 +18,7 @@
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`undef ENABLE_TLB
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`endif
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`define MUL_PIPE_STAGES 3
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`define MUL_PIPE_STAGES 6
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`define XLEN 32
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`define PCRST 32'hBFC00000
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