K0 cached
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@ -27,7 +27,9 @@ module CP0 (
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reg count_lo;
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always_ff @(posedge rst or posedge clk)
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if (rst) begin
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rf_cp0 = {504'b0, 8'b10000010, 105'b0, 1'b1, 406'b0};
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rf_cp0 = {
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504'b0, 8'b100000_11, 105'b0, 1'b1, 406'b0
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}; // 11 means K0 cached when Status.ERL=0, others uncached
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count_lo = 0;
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end else if (clk) begin
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if (ERET) rf_cp0.Status.EXL = 1'b0;
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@ -40,8 +42,7 @@ module CP0 (
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if (exception.delay) begin
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rf_cp0.Cause.BD = 1'b1;
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rf_cp0.EPC = rf_cp0.EPC - 4;
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end
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else rf_cp0.Cause.BD = 1'b0;
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end else rf_cp0.Cause.BD = 1'b0;
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end
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end
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// count
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111
src/testbench/CP0/testbench.sv
Normal file
111
src/testbench/CP0/testbench.sv
Normal file
@ -0,0 +1,111 @@
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`include "defines.svh"
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`timescale 1ns / 1ps
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module testbench_CP0();
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logic clk, rst;
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HandShake fakehsi1 ();
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HandShake fakehsi2 ();
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HandShake fakehso1 ();
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HandShake fakehso2 ();
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word_t in1;
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word_t pin1;
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word_t in2;
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word_t pin2;
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word_t out1;
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word_t pout1;
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word_t out2;
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word_t pout2;
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logic clear;
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InstrQueue iq (
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clk,
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rst,
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fakehsi1.prev,
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in1,
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pin1,
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fakehsi2.prev,
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in2,
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pin2,
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fakehso1.next,
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out1,
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pout1,
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fakehso2.next,
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out2,
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pout2,
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clear
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);
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always begin
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clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
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fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
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in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
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clk = 0; rst = 0; #50;
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clk = 1;
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in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
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clk = 0; #50;
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clk = 1;
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in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; clear = 1; #50;
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clk = 0; #50;
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clk = 1; clear = 0;fakehso1.allowin = 1; fakehso2.allowin = 1;
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in1 = 5; in2 = 6 ; pin1 = 5; pin2 = 6; #50;
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fakehsi1.readygo = 0; fakehsi2.readygo = 0;
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clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
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clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
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fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
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in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
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clk = 0; rst = 0; #50;
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clk = 1;
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in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
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clk = 0; #50;
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clk = 1;
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in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
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clk = 0; #50;
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clk = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
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in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; clear = 1; #50;
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fakehsi1.readygo = 0; fakehsi2.readygo = 0;
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clk = 0; #50; clear = 0; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
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clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
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fakehsi1.readygo = 1; fakehsi2.readygo = 1;
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in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
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clk = 0; rst = 0; #50;
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clk = 1;
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in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
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clk = 0; #50;
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clk = 1;
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in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
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clk = 0; #50;
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clk = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
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in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #50;
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fakehsi1.readygo = 0; fakehsi2.readygo = 0;
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clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
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clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
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fakehsi1.readygo = 1; fakehsi2.readygo = 1;
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in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
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clk = 0; rst = 0; #50;
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clk = 1;
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in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
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clk = 0; #50;
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clk = 1;
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in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
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clk = 0; #50;
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clk = 1;
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in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #50;
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fakehsi1.readygo = 0; fakehsi2.readygo = 0;
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clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
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clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 0;
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fakehsi1.readygo = 1; fakehsi2.readygo = 1;
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in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
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clk = 0; rst = 0; #50;
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clk = 1;
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in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
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clk = 0; #50;
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clk = 1;
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in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
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clk = 0; #50;
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clk = 1;
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in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; fakehso2.allowin = 1; #50;
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fakehsi1.readygo = 0; fakehsi2.readygo = 0;
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clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
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$finish;
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end
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endmodule
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