From 3992e107a12c40d46eebee12df3f414bc3b03157 Mon Sep 17 00:00:00 2001
From: hoo <jiahao1941@outlook.com>
Date: Wed, 14 Jul 2021 10:54:35 +0800
Subject: [PATCH] K0 cached

---
 src/CP0/CP0.sv                 |   9 +--
 src/testbench/CP0/testbench.sv | 111 +++++++++++++++++++++++++++++++++
 2 files changed, 116 insertions(+), 4 deletions(-)
 create mode 100644 src/testbench/CP0/testbench.sv

diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv
index 4c91d88..542476e 100644
--- a/src/CP0/CP0.sv
+++ b/src/CP0/CP0.sv
@@ -27,7 +27,9 @@ module CP0 (
   reg count_lo;
   always_ff @(posedge rst or posedge clk)
     if (rst) begin
-      rf_cp0   = {504'b0, 8'b10000010, 105'b0, 1'b1, 406'b0};
+      rf_cp0 = {
+        504'b0, 8'b100000_11, 105'b0, 1'b1, 406'b0
+      };  // 11 means K0 cached when  Status.ERL=0, others uncached
       count_lo = 0;
     end else if (clk) begin
       if (ERET) rf_cp0.Status.EXL = 1'b0;
@@ -40,8 +42,7 @@ module CP0 (
           if (exception.delay) begin
             rf_cp0.Cause.BD = 1'b1;
             rf_cp0.EPC = rf_cp0.EPC - 4;
-          end
-          else rf_cp0.Cause.BD = 1'b0;
+          end else rf_cp0.Cause.BD = 1'b0;
         end
       end
       // count
@@ -71,7 +72,7 @@ module CP0 (
           13: rf_cp0.Cause[9:8] = wdata[9:8];
           12: begin
             rf_cp0.Status[15:8] = wdata[15:8];
-            rf_cp0.Status[1:0] = wdata[1:0];
+            rf_cp0.Status[1:0]  = wdata[1:0];
           end
           11: rf_cp0.Compare = wdata;
           10: rf_cp0.EntryHi = wdata;
diff --git a/src/testbench/CP0/testbench.sv b/src/testbench/CP0/testbench.sv
new file mode 100644
index 0000000..126c16f
--- /dev/null
+++ b/src/testbench/CP0/testbench.sv
@@ -0,0 +1,111 @@
+`include "defines.svh"
+
+`timescale 1ns / 1ps
+module testbench_CP0();
+  logic clk, rst;
+  HandShake fakehsi1 ();
+  HandShake fakehsi2 ();
+  HandShake fakehso1 ();
+  HandShake fakehso2 ();
+  word_t in1;
+  word_t pin1;
+  word_t in2;
+  word_t pin2;
+  word_t out1;
+  word_t pout1;
+  word_t out2;
+  word_t pout2;
+  logic clear;
+  InstrQueue iq (
+      clk,
+      rst,
+      fakehsi1.prev,
+      in1,
+      pin1,
+      fakehsi2.prev,
+      in2,
+      pin2,
+      fakehso1.next,
+      out1,
+      pout1,
+      fakehso2.next,
+      out2,
+      pout2,
+      clear
+  );
+    always begin
+        clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
+        fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
+        in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
+        clk = 0; rst = 0; #50;
+        clk = 1;
+        in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
+        clk = 0; #50;
+        clk = 1;
+        in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; clear = 1; #50;
+        clk = 0; #50;
+        clk = 1; clear = 0;fakehso1.allowin = 1; fakehso2.allowin = 1;
+        in1 = 5; in2 = 6 ; pin1 = 5; pin2 = 6; #50;
+        fakehsi1.readygo = 0; fakehsi2.readygo = 0;
+        clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
+
+        clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
+        fakehsi1.readygo = 1; fakehsi2.readygo = 1; clear = 0;
+        in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
+        clk = 0; rst = 0; #50;
+        clk = 1;
+        in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
+        clk = 0; #50;
+        clk = 1;
+        in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
+        clk = 0; #50;
+        clk = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
+        in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; clear = 1; #50;
+        fakehsi1.readygo = 0; fakehsi2.readygo = 0;
+        clk = 0; #50; clear = 0; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
+
+        clk = 1; rst = 1; fakehso1.allowin = 0; fakehso2.allowin = 0;
+        fakehsi1.readygo = 1; fakehsi2.readygo = 1;
+        in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
+        clk = 0; rst = 0; #50;
+        clk = 1;
+        in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
+        clk = 0; #50;
+        clk = 1;
+        in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
+        clk = 0; #50;
+        clk = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
+        in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #50;
+        fakehsi1.readygo = 0; fakehsi2.readygo = 0;
+        clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
+        clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 1;
+        fakehsi1.readygo = 1; fakehsi2.readygo = 1;
+        in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
+        clk = 0; rst = 0; #50;
+        clk = 1;
+        in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
+        clk = 0; #50;
+        clk = 1;
+        in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
+        clk = 0; #50;
+        clk = 1;
+        in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; #50;
+        fakehsi1.readygo = 0; fakehsi2.readygo = 0;
+        clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
+        clk = 1; rst = 1; fakehso1.allowin = 1; fakehso2.allowin = 0;
+        fakehsi1.readygo = 1; fakehsi2.readygo = 1;
+        in1 = 0; in2 = 0; pin1 = 0; pin2 = 0; #50;
+        clk = 0; rst = 0; #50;
+        clk = 1;
+        in1 = 1; in2 = 2; pin1 = 1; pin2 = 2; #50;
+        clk = 0; #50;
+        clk = 1;
+        in1 = 3; in2 = 4; pin1 = 3; pin2 = 4; #50;
+        clk = 0; #50;
+        clk = 1;
+        in1 = 5; in2 = 6; pin1 = 5; pin2 = 6; fakehso2.allowin = 1; #50;
+        fakehsi1.readygo = 0; fakehsi2.readygo = 0;
+        clk = 0; #50; clk = 1; #50; clk = 0; #50; clk = 1; #50; clk = 0; #50;
+        $finish;
+    end
+endmodule