sync partial debugging sources
This commit is contained in:
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57b9d66643
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2
mips_env
Executable file
2
mips_env
Executable file
@ -0,0 +1,2 @@
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export ARCH=mips
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export CROSS_COMPILE=mipsel-linux-gnu-
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@ -1,8 +1,8 @@
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TOPDIR=$(shell pwd)
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#export LD_PRELOAD =
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CFLAGS := -D_KERNEL -fno-builtin -mips32r2 -DMEMSTART=0x80000000 -DMEMSIZE=0x04000 -DCPU_COUNT_PER_US=1000 -I $(TOPDIR)/include
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CFLAGS += -fno-reorder-blocks -fno-reorder-functions -msoft-float
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CFLAGS := -D_KERNEL -fno-builtin -mips32 -DMEMSTART=0x80000100 -DMEMSIZE=0x04000 -DCPU_COUNT_PER_US=1000 -I $(TOPDIR)/include
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CFLAGS += -fno-reorder-blocks -fno-reorder-functions -msoft-float -funroll-loops
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OBJDIR = ./obj
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22
resources/soft/func/find_rand.c
Normal file
22
resources/soft/func/find_rand.c
Normal file
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#include <stdio.h>
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unsigned short lfsr = 0xACE1u;
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unsigned rand16() {
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unsigned bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1;
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return lfsr = (lfsr >> 1) | (bit << 15);
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}
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unsigned rand() { return (rand16() << 16) | rand16(); }
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int main() {
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unsigned target;
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while (~scanf("%x", &target)) {
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lfsr = 0xACE1u;
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int cnt = 0;
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while (rand() != target)
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cnt++;
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printf("cnt = %d(0x%x)\n", cnt, cnt);
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}
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}
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22
resources/soft/func/get_rand.c
Normal file
22
resources/soft/func/get_rand.c
Normal file
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#include <stdio.h>
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unsigned short lfsr = 0xACE1u;
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unsigned rand16() {
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unsigned bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1;
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return lfsr = (lfsr >> 1) | (bit << 15);
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}
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unsigned rand() { return (rand16() << 16) | rand16(); }
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int main() {
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unsigned target;
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while (~scanf("%d", &target)) {
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lfsr = 0xACE1u;
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int cnt = 0;
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for (int i = 0; i < target; i++)
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rand();
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printf("rand = 0x%x\n", rand());
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}
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}
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116
resources/soft/func/include/cacheops.h
Normal file
116
resources/soft/func/include/cacheops.h
Normal file
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/*
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* Cache operations for the cache instruction.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
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* (C) Copyright 1999 Silicon Graphics, Inc.
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*/
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#ifndef __ASM_CACHEOPS_H
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#define __ASM_CACHEOPS_H
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/*
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* Most cache ops are split into a 2 bit field identifying the cache, and a 3
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* bit field identifying the cache operation.
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*/
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#define CacheOp_Cache 0x03
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#define CacheOp_Op 0x1c
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#define Cache_I 0x00
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#define Cache_D 0x01
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#define Cache_T 0x02
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#define Cache_V 0x02 /* Loongson-3 */
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#define Cache_S 0x03
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#define Index_Writeback_Inv 0x00
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#define Index_Load_Tag 0x04
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#define Index_Store_Tag 0x08
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#define Hit_Invalidate 0x10
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#define Hit_Writeback_Inv 0x14 /* not with Cache_I though */
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#define Hit_Writeback 0x18
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/*
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* Cache Operations available on all MIPS processors with R4000-style caches
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*/
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#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv)
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#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv)
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#define Index_Load_Tag_I (Cache_I | Index_Load_Tag)
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#define Index_Load_Tag_D (Cache_D | Index_Load_Tag)
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#define Index_Store_Tag_I (Cache_I | Index_Store_Tag)
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#define Index_Store_Tag_D (Cache_D | Index_Store_Tag)
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#define Hit_Invalidate_I (Cache_I | Hit_Invalidate)
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#define Hit_Invalidate_D (Cache_D | Hit_Invalidate)
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#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv)
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/*
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* R4000-specific cacheops
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*/
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#define Create_Dirty_Excl_D (Cache_D | 0x0c)
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#define Fill_I (Cache_I | 0x14)
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#define Hit_Writeback_I (Cache_I | Hit_Writeback)
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#define Hit_Writeback_D (Cache_D | Hit_Writeback)
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/*
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* R4000SC and R4400SC-specific cacheops
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*/
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#define Cache_SI 0x02
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#define Cache_SD 0x03
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#define Index_Invalidate_SI (Cache_SI | Index_Writeback_Inv)
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#define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv)
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#define Index_Load_Tag_SI (Cache_SI | Index_Load_Tag)
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#define Index_Load_Tag_SD (Cache_SD | Index_Load_Tag)
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#define Index_Store_Tag_SI (Cache_SI | Index_Store_Tag)
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#define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag)
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#define Create_Dirty_Excl_SD (Cache_SD | 0x0c)
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#define Hit_Invalidate_SI (Cache_SI | Hit_Invalidate)
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#define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate)
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#define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv)
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#define Hit_Writeback_SD (Cache_SD | Hit_Writeback)
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#define Hit_Set_Virtual_SI (Cache_SI | 0x1c)
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#define Hit_Set_Virtual_SD (Cache_SD | 0x1c)
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/*
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* R5000-specific cacheops
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*/
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#define R5K_Page_Invalidate_S (Cache_S | 0x14)
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/*
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* RM7000-specific cacheops
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*/
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#define Page_Invalidate_T (Cache_T | 0x14)
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#define Index_Store_Tag_T (Cache_T | Index_Store_Tag)
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#define Index_Load_Tag_T (Cache_T | Index_Load_Tag)
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/*
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* R10000-specific cacheops
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*
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* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
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* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
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*/
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#define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv)
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#define Index_Load_Tag_S (Cache_S | Index_Load_Tag)
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#define Index_Store_Tag_S (Cache_S | Index_Store_Tag)
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#define Hit_Invalidate_S (Cache_S | Hit_Invalidate)
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#define Cache_Barrier 0x14
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#define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv)
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#define Index_Load_Data_I (Cache_I | 0x18)
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#define Index_Load_Data_D (Cache_D | 0x18)
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#define Index_Load_Data_S (Cache_S | 0x18)
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#define Index_Store_Data_I (Cache_I | 0x1c)
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#define Index_Store_Data_D (Cache_D | 0x1c)
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#define Index_Store_Data_S (Cache_S | 0x1c)
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/*
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* Loongson2-specific cacheops
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*/
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#define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00)
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/*
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* Loongson3-specific cacheops
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*/
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#define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv)
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#endif /* __ASM_CACHEOPS_H */
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170
resources/soft/func/include/r4k_cache.h
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170
resources/soft/func/include/r4k_cache.h
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Inline assembly cache operations.
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*
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef _ASM_R4KCACHE_H
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#define _ASM_R4KCACHE_H
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#include "cacheops.h"
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#include "unroll.h"
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#define CKSEG0 0x80000000
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#define PAGE_SIZE (1UL << 12)
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#define MIPS_ISA_ARCH_LEVEL "mips32"
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#define kernel_cache(op, base) "cache " op ", " base "\n"
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#define user_cache(op, base) kernel_cache(op, base)
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struct cache_desc {
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unsigned int waysize;
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unsigned short sets;
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unsigned char ways;
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unsigned char linesz;
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unsigned char waybit;
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};
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struct cpuinfo_mips {
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struct cache_desc icache;
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struct cache_desc dcache;
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};
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extern struct cpuinfo_mips current_cpu_data;
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#define INDEX_BASE CKSEG0
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#define _cache_op(insn, op, addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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" " insn("%0", "%1") " \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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#define cache_op(op, addr) \
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_cache_op(kernel_cache, op, addr)
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static inline void
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flush_icache_line_indexed(unsigned long addr) { cache_op(Index_Invalidate_I, addr); }
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{ cache_op(Index_Writeback_Inv_D, addr); }
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static inline void flush_icache_line(unsigned long addr)
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{ cache_op(Hit_Invalidate_I, addr); }
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static inline void flush_dcache_line(unsigned long addr)
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{ cache_op(Hit_Writeback_Inv_D, addr); }
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static inline void invalidate_dcache_line(unsigned long addr)
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{ cache_op(Hit_Invalidate_D, addr); }
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#define cache_unroll(times, insn, op, addr, lsize) do { \
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int i = 0; \
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unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \
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} while (0)
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/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
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#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
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static inline void extra##blast_##pfx##cache##lsize(void) \
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{ \
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unsigned long start = INDEX_BASE; \
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unsigned long end = start + current_cpu_data.desc.waysize; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache_unroll(32, kernel_cache, indexop, \
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addr | ws, lsize); \
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} \
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\
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static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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do { \
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cache_unroll(32, kernel_cache, hitop, start, lsize); \
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start += lsize * 32; \
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} while (start < end); \
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} \
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\
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static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
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{ \
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unsigned long indexmask = current_cpu_data.desc.waysize - 1; \
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unsigned long start = INDEX_BASE + (page & indexmask); \
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unsigned long end = start + PAGE_SIZE; \
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unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \
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unsigned long ws_end = current_cpu_data.desc.ways << \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache_unroll(32, kernel_cache, indexop, \
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addr | ws, lsize); \
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}
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
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__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
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__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
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#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
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static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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{ \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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do { \
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cache_unroll(32, user_cache, hitop, start, lsize); \
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start += lsize * 32; \
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} while (start < end); \
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}
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
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__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
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/* build blast_xxx_range, protected_blast_xxx_range */
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#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
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static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
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unsigned long end) \
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{ \
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unsigned long lsize = current_cpu_data.desc.linesz; \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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\
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while (1) { \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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}
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
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__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
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#endif /* _ASM_R4KCACHE_H */
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68
resources/soft/func/include/unroll.h
Normal file
68
resources/soft/func/include/unroll.h
Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __ASM_UNROLL_H__
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#define __ASM_UNROLL_H__
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#define __compiletime_error(msg) __attribute__((__error__(msg)))
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#define fallthrough __attribute__((__fallthrough__))
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/*
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* Explicitly unroll a loop, for use in cases where doing so is performance
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* critical.
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*
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* Ideally we'd rely upon the compiler to provide this but there's no commonly
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* available means to do so. For example GCC's "#pragma GCC unroll"
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* functionality would be ideal but is only available from GCC 8 onwards. Using
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* -funroll-loops is an option but GCC tends to make poor choices when
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* compiling our string functions. -funroll-all-loops leads to massive code
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* bloat, even if only applied to the string functions.
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*/
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#define unroll(times, fn, ...) do { \
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void bad_unroll(void) \
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__compiletime_error("Unsupported unroll"); \
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\
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switch (times) { \
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case 32: fn(__VA_ARGS__); fallthrough; \
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case 31: fn(__VA_ARGS__); fallthrough; \
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case 30: fn(__VA_ARGS__); fallthrough; \
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case 29: fn(__VA_ARGS__); fallthrough; \
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case 28: fn(__VA_ARGS__); fallthrough; \
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case 27: fn(__VA_ARGS__); fallthrough; \
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case 26: fn(__VA_ARGS__); fallthrough; \
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case 25: fn(__VA_ARGS__); fallthrough; \
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case 24: fn(__VA_ARGS__); fallthrough; \
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case 23: fn(__VA_ARGS__); fallthrough; \
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case 22: fn(__VA_ARGS__); fallthrough; \
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case 21: fn(__VA_ARGS__); fallthrough; \
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case 20: fn(__VA_ARGS__); fallthrough; \
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case 19: fn(__VA_ARGS__); fallthrough; \
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case 18: fn(__VA_ARGS__); fallthrough; \
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case 17: fn(__VA_ARGS__); fallthrough; \
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case 16: fn(__VA_ARGS__); fallthrough; \
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case 15: fn(__VA_ARGS__); fallthrough; \
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case 14: fn(__VA_ARGS__); fallthrough; \
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case 13: fn(__VA_ARGS__); fallthrough; \
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case 12: fn(__VA_ARGS__); fallthrough; \
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case 11: fn(__VA_ARGS__); fallthrough; \
|
||||
case 10: fn(__VA_ARGS__); fallthrough; \
|
||||
case 9: fn(__VA_ARGS__); fallthrough; \
|
||||
case 8: fn(__VA_ARGS__); fallthrough; \
|
||||
case 7: fn(__VA_ARGS__); fallthrough; \
|
||||
case 6: fn(__VA_ARGS__); fallthrough; \
|
||||
case 5: fn(__VA_ARGS__); fallthrough; \
|
||||
case 4: fn(__VA_ARGS__); fallthrough; \
|
||||
case 3: fn(__VA_ARGS__); fallthrough; \
|
||||
case 2: fn(__VA_ARGS__); fallthrough; \
|
||||
case 1: fn(__VA_ARGS__); fallthrough; \
|
||||
case 0: break; \
|
||||
\
|
||||
default: \
|
||||
/* \
|
||||
* Either the iteration count is unreasonable \
|
||||
* or we need to add more cases above. \
|
||||
*/ \
|
||||
bad_unroll(); \
|
||||
break; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#endif /* __ASM_UNROLL_H__ */
|
||||
@ -30,3 +30,102 @@
|
||||
JUMP_TO_CACHED; \
|
||||
TEST_UNIT(test); \
|
||||
JUMP_TO_UNCACHED;
|
||||
|
||||
// a0 buf
|
||||
#define TEST_SAVE_REGS \
|
||||
sw v0, 0(a0); \
|
||||
sw v1, 4(a0); \
|
||||
nop; \
|
||||
sw a1, 8(a0); \
|
||||
sw a2, 12(a0); \
|
||||
sw a3, 16(a0); \
|
||||
sw t0, 20(a0); \
|
||||
sw t1, 24(a0); \
|
||||
sw t2, 28(a0); \
|
||||
sw t3, 32(a0); \
|
||||
sw t4, 36(a0); \
|
||||
sw t5, 40(a0); \
|
||||
sw t6, 44(a0); \
|
||||
sw t7, 48(a0); \
|
||||
sw t8, 52(a0); \
|
||||
sw t9, 56(a0); \
|
||||
sw s0, 60(a0); \
|
||||
sw s1, 64(a0); \
|
||||
sw s2, 68(a0); \
|
||||
sw s3, 72(a0); \
|
||||
sw s4, 76(a0); \
|
||||
sw s5, 80(a0); \
|
||||
sw s6, 84(a0); \
|
||||
sw s7, 88(a0); \
|
||||
sw k0, 92(a0); \
|
||||
sw k1, 96(a0); \
|
||||
sw gp, 100(a0); \
|
||||
sw sp, 104(a0); \
|
||||
sw fp, 108(a0); \
|
||||
sw ra, 112(a0); \
|
||||
nop;
|
||||
|
||||
#define TEST_RESTORE_REGS \
|
||||
lw v0, 0(a0); \
|
||||
lw v1, 4(a0); \
|
||||
nop; \
|
||||
lw a1, 8(a0); \
|
||||
lw a2, 12(a0); \
|
||||
lw a3, 16(a0); \
|
||||
lw t0, 20(a0); \
|
||||
lw t1, 24(a0); \
|
||||
lw t2, 28(a0); \
|
||||
lw t3, 32(a0); \
|
||||
lw t4, 36(a0); \
|
||||
lw t5, 40(a0); \
|
||||
lw t6, 44(a0); \
|
||||
lw t7, 48(a0); \
|
||||
lw t8, 52(a0); \
|
||||
lw t9, 56(a0); \
|
||||
lw s0, 60(a0); \
|
||||
lw s1, 64(a0); \
|
||||
lw s2, 68(a0); \
|
||||
lw s3, 72(a0); \
|
||||
lw s4, 76(a0); \
|
||||
lw s5, 80(a0); \
|
||||
lw s6, 84(a0); \
|
||||
lw s7, 88(a0); \
|
||||
lw k0, 92(a0); \
|
||||
lw k1, 96(a0); \
|
||||
lw gp, 100(a0); \
|
||||
lw sp, 104(a0); \
|
||||
lw fp, 108(a0); \
|
||||
lw ra, 112(a0); \
|
||||
nop;
|
||||
|
||||
#define TEST_C_ENV(test) \
|
||||
JUMP_TO_CACHED; \
|
||||
addiu s0, s0 ,1; \
|
||||
li s2, 0x0; \
|
||||
\
|
||||
la a0, 0x80000000; \
|
||||
TEST_SAVE_REGS; \
|
||||
\
|
||||
jal test; \
|
||||
nop; \
|
||||
\
|
||||
la a0, 0x80000000; \
|
||||
sw v0, 116(a0); \
|
||||
sw s2, 120(a0); \
|
||||
TEST_RESTORE_REGS; \
|
||||
\
|
||||
lw v0, 116(a0); \
|
||||
lw s2, 120(a0); \
|
||||
bne v0, zero, inst_error; \
|
||||
nop; \
|
||||
bne s2, zero, inst_error; \
|
||||
nop; \
|
||||
addiu s3, s3, 1; \
|
||||
inst_error: \
|
||||
sll t1, s0, 24; \
|
||||
or t0, t1, s3; \
|
||||
sw t0, 0(s1); \
|
||||
\
|
||||
jal wait_1s; \
|
||||
nop; \
|
||||
JUMP_TO_UNCACHED;
|
||||
|
||||
@ -1,7 +1,9 @@
|
||||
srcs = $(wildcard *.S)
|
||||
objs = $(patsubst %.S, %.o, $(srcs))
|
||||
asm_srcs = $(wildcard *.S)
|
||||
asm_objs = $(patsubst %.S, %.o, $(asm_srcs))
|
||||
c_srcs = $(wildcard *.c)
|
||||
c_objs = $(patsubst %.c, %.o, $(c_srcs))
|
||||
|
||||
$(TOPDIR)/libinst.a: $(objs)
|
||||
$(TOPDIR)/libinst.a: $(asm_objs) $(c_objs)
|
||||
$(CROSS_COMPILE)$(AR) -cr $@ $?
|
||||
|
||||
clean:
|
||||
|
||||
@ -1437,95 +1437,3 @@
|
||||
nop; \
|
||||
bne v1, s6, inst_error; \
|
||||
nop
|
||||
|
||||
/*CACHE instruction*/
|
||||
|
||||
// address and result stored in v0
|
||||
#define GET_ICACHE_INDEX \
|
||||
srl v0, v0, 5; \
|
||||
andi v0, v0, 0x3f; \
|
||||
nop
|
||||
|
||||
#define GET_DCACHE_INDEX \
|
||||
srl v0, v0, 4; \
|
||||
andi v0, v0, 0x7f; \
|
||||
nop
|
||||
|
||||
/*98*/
|
||||
/*
|
||||
* addr1 : uncached
|
||||
* addr2 : cached and mapped to addr1
|
||||
*/
|
||||
#define TEST_CACHE_DCACHE_HIT(addr1, addr2, offset, data1, data2) \
|
||||
LI(t0, addr1); \
|
||||
LI(t1, addr2); \
|
||||
LI(t2, data1); \
|
||||
LI(t3, data2); \
|
||||
/* prepare -> hit writeback invalidate */ \
|
||||
sw t3, offset(t0); \
|
||||
sw t2, offset(t1); \
|
||||
cache 21, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne t2, a0, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne t2, a0, inst_error; \
|
||||
nop; \
|
||||
/* test hit invalidate */ \
|
||||
sw t2, offset(t0); \
|
||||
sw t3, offset(t1); \
|
||||
cache 17, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne a0, t2, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne a0, t2, inst_error; \
|
||||
nop; \
|
||||
/* test hit writeback invalidate */ \
|
||||
sw t3, offset(t1); \
|
||||
cache 21, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne a0, t3, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne a0, t3, inst_error; \
|
||||
nop; \
|
||||
/* test multiple*/ \
|
||||
addi a1, t1, 4; \
|
||||
cache 17, offset(t1); \
|
||||
cache 17, offset(a1); \
|
||||
sw t2, offset(t1); \
|
||||
sw t3, offset(a1); \
|
||||
cache 21, offset(t1); \
|
||||
cache 21, offset(a1); \
|
||||
addi a1, t0, 4; \
|
||||
lw v0, offset(t0); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t2, inst_error; \
|
||||
nop; \
|
||||
bne v1, t3, inst_error; \
|
||||
nop; \
|
||||
sw t3, offset(t0); \
|
||||
sw t2, offset(a1); \
|
||||
addi a1, t1, 4; \
|
||||
lw v0, offset(t1); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop; \
|
||||
sw t2, offset(t1); \
|
||||
sw t3, offset(a1); \
|
||||
cache 17, offset(t1); \
|
||||
cache 17, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop; \
|
||||
addi a1, t0, 4; \
|
||||
lw v0, offset(t0); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop
|
||||
|
||||
164
resources/soft/func/inst/n105_playground.c
Normal file
164
resources/soft/func/inst/n105_playground.c
Normal file
@ -0,0 +1,164 @@
|
||||
#include "r4k_cache.h"
|
||||
|
||||
extern void srand(unsigned short seed);
|
||||
extern unsigned rand();
|
||||
|
||||
extern void puts(char *str);
|
||||
extern void putstr(char *str);
|
||||
extern void puthex(unsigned x);
|
||||
extern void putchar(char ch);
|
||||
|
||||
#define PREFIX "n105: "
|
||||
|
||||
#define TEST(func) \
|
||||
do { \
|
||||
puts(PREFIX "start " #func); \
|
||||
if (func()) \
|
||||
return 1; \
|
||||
} while (0)
|
||||
|
||||
int n105_playground_test_fib() __attribute__((optimize("O0")));
|
||||
int n105_playground_test_mem();
|
||||
int n105_playground_test_cache();
|
||||
|
||||
int n105_playground_test() {
|
||||
TEST(n105_playground_test_cache);
|
||||
TEST(n105_playground_test_fib);
|
||||
TEST(n105_playground_test_mem);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int n105_playground_test_fib() {
|
||||
volatile unsigned buf[1000];
|
||||
buf[0] = buf[1] = 1;
|
||||
for (int i = 2; i < 1000; i++)
|
||||
buf[i] = buf[i - 1] + buf[i - 2];
|
||||
putstr(PREFIX "buf[999]="), puthex(buf[999]), putchar('\n');
|
||||
return buf[999] != 0x5cc0604b;
|
||||
}
|
||||
|
||||
int n105_playground_test_mem() {
|
||||
const unsigned len = 0x3ff;
|
||||
volatile unsigned buf[len];
|
||||
|
||||
srand(0xACE1u);
|
||||
for (unsigned i = 0; i < len; i++)
|
||||
buf[i] = rand();
|
||||
|
||||
srand(0xACE1u);
|
||||
for (unsigned i = 0; i < len; i++) {
|
||||
unsigned rnd = rand();
|
||||
if (buf[i] != rnd) {
|
||||
putstr(PREFIX "mem(#5): ERROR occured! expected: ");
|
||||
puthex(rnd);
|
||||
putstr(", but got: ");
|
||||
puthex(buf[i]);
|
||||
putstr(". ptr=");
|
||||
puthex((unsigned)&buf[i]);
|
||||
putstr(", i=");
|
||||
puthex(i);
|
||||
putchar('\n');
|
||||
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int n105_playground_test_cache() {
|
||||
// blast_dcache_range: Hit_Writeback_Inv_D
|
||||
|
||||
unsigned *uncached_bgn = (unsigned *)0xa4000000;
|
||||
unsigned *uncached_end = (unsigned *)0xa4004000;
|
||||
unsigned *cached_bgn = (unsigned *)0x84000000;
|
||||
unsigned *cached_end = (unsigned *)0x84004000;
|
||||
|
||||
// clear
|
||||
puts(PREFIX "cache: clear");
|
||||
for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++)
|
||||
*ptr = 0;
|
||||
|
||||
// cache
|
||||
puts(PREFIX "cache: blast clear");
|
||||
blast_dcache_range((unsigned)cached_bgn, (unsigned)(cached_end));
|
||||
|
||||
// check uncache clear
|
||||
puts(PREFIX "cache: check uncache clear");
|
||||
for (volatile unsigned *ptr = uncached_bgn; ptr < uncached_end; ptr++)
|
||||
if (*ptr != 0) {
|
||||
putstr(PREFIX "cache(#1): ERROR occured! expected: 0, but got: ");
|
||||
puthex(*ptr);
|
||||
putstr(". ptr=");
|
||||
puthex((unsigned)ptr);
|
||||
putchar('\n');
|
||||
return 1;
|
||||
}
|
||||
|
||||
// check cache clear
|
||||
puts(PREFIX "cache: check cache clear");
|
||||
for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++)
|
||||
if (*ptr != 0) {
|
||||
putstr(PREFIX "cache(#2): ERROR occured! expected: 0, but got: ");
|
||||
puthex(*ptr);
|
||||
putstr(". ptr=");
|
||||
puthex((unsigned)ptr);
|
||||
putchar('\n');
|
||||
return 1;
|
||||
}
|
||||
|
||||
// fill
|
||||
puts(PREFIX "cache: fill cache");
|
||||
// srand(0xACE1u);
|
||||
// for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++)
|
||||
// *ptr = rand();
|
||||
unsigned counter = 0;
|
||||
for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++)
|
||||
*ptr = ++counter;
|
||||
|
||||
// blast fill
|
||||
puts(PREFIX "cache: blast fill");
|
||||
blast_dcache_range((unsigned)cached_bgn, (unsigned)(cached_end));
|
||||
|
||||
// check uncache
|
||||
puts(PREFIX "cache: check uncache");
|
||||
// srand(0xACE1u);
|
||||
counter = 0;
|
||||
for (volatile unsigned *ptr = uncached_bgn; ptr < uncached_end; ptr++) {
|
||||
// unsigned rnd = rand();
|
||||
unsigned rnd = ++counter;
|
||||
if (*ptr != rnd) {
|
||||
putstr(PREFIX "cache(#3): ERROR occured! expected: ");
|
||||
puthex(rnd);
|
||||
putstr(", but got: ");
|
||||
puthex(*ptr);
|
||||
putstr(". ptr=");
|
||||
puthex((unsigned)ptr);
|
||||
putchar('\n');
|
||||
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
// check cache
|
||||
puts(PREFIX "cache: check cache");
|
||||
// srand(0xACE1u);
|
||||
counter = 0;
|
||||
for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++) {
|
||||
// unsigned rnd = rand();
|
||||
unsigned rnd = ++counter;
|
||||
if (*ptr != rnd) {
|
||||
putstr(PREFIX "cache(#4): ERROR occured! expected: ");
|
||||
puthex(rnd);
|
||||
putstr(", but got: ");
|
||||
puthex(*ptr);
|
||||
putstr(". ptr=");
|
||||
puthex((unsigned)ptr);
|
||||
putchar('\n');
|
||||
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -2,6 +2,91 @@
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
#define GET_DCACHE_INDEX \
|
||||
srl v0, v0, 4; \
|
||||
andi v0, v0, 0x7f; \
|
||||
nop
|
||||
|
||||
/*98*/
|
||||
/*
|
||||
* addr1 : uncached
|
||||
* addr2 : cached and mapped to addr1
|
||||
*/
|
||||
#define TEST_CACHE_DCACHE_HIT(addr1, addr2, offset, data1, data2) \
|
||||
LI(t0, addr1); \
|
||||
LI(t1, addr2); \
|
||||
LI(t2, data1); \
|
||||
LI(t3, data2); \
|
||||
/* prepare -> hit writeback invalidate */ \
|
||||
sw t3, offset(t0); \
|
||||
sw t2, offset(t1); \
|
||||
cache 21, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne t2, a0, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne t2, a0, inst_error; \
|
||||
nop; \
|
||||
/* test hit invalidate */ \
|
||||
sw t2, offset(t0); \
|
||||
sw t3, offset(t1); \
|
||||
cache 17, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne a0, t2, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne a0, t2, inst_error; \
|
||||
nop; \
|
||||
/* test hit writeback invalidate */ \
|
||||
sw t3, offset(t1); \
|
||||
cache 21, offset(t1); \
|
||||
lw a0, offset(t0); \
|
||||
bne a0, t3, inst_error; \
|
||||
nop; \
|
||||
lw a0, offset(t1); \
|
||||
bne a0, t3, inst_error; \
|
||||
nop; \
|
||||
/* test multiple*/ \
|
||||
addi a1, t1, 4; \
|
||||
cache 17, offset(t1); \
|
||||
cache 17, offset(a1); \
|
||||
sw t2, offset(t1); \
|
||||
sw t3, offset(a1); \
|
||||
cache 21, offset(t1); \
|
||||
cache 21, offset(a1); \
|
||||
addi a1, t0, 4; \
|
||||
lw v0, offset(t0); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t2, inst_error; \
|
||||
nop; \
|
||||
bne v1, t3, inst_error; \
|
||||
nop; \
|
||||
sw t3, offset(t0); \
|
||||
sw t2, offset(a1); \
|
||||
addi a1, t1, 4; \
|
||||
lw v0, offset(t1); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop; \
|
||||
sw t2, offset(t1); \
|
||||
sw t3, offset(a1); \
|
||||
cache 17, offset(t1); \
|
||||
cache 17, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop; \
|
||||
addi a1, t0, 4; \
|
||||
lw v0, offset(t0); \
|
||||
lw v1, offset(a1); \
|
||||
bne v0, t3, inst_error; \
|
||||
nop; \
|
||||
bne v1, t2, inst_error; \
|
||||
nop
|
||||
|
||||
|
||||
LEAF(n98_cache_dcache_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
|
||||
@ -2,6 +2,12 @@
|
||||
#include <regdef.h>
|
||||
#include <inst_test.h>
|
||||
|
||||
// address and result stored in v0
|
||||
#define GET_ICACHE_INDEX \
|
||||
srl v0, v0, 5; \
|
||||
andi v0, v0, 0x3f; \
|
||||
nop
|
||||
|
||||
LEAF(n99_cache_icache_test)
|
||||
.set noreorder
|
||||
addiu s0, s0 ,1
|
||||
|
||||
180
resources/soft/func/inst/utils.c
Normal file
180
resources/soft/func/inst/utils.c
Normal file
@ -0,0 +1,180 @@
|
||||
#include "r4k_cache.h"
|
||||
|
||||
// 0x80000000 - 0x8000007c saved reg
|
||||
// 0x8000007c lfsr
|
||||
// 0x80000100 - 0x80004100.data
|
||||
// 0x88000000 sp
|
||||
// 0x84000000 - random
|
||||
|
||||
#define MAKE_ERR \
|
||||
do { \
|
||||
*(unsigned *)(0) = 0; \
|
||||
} while (0)
|
||||
|
||||
void putchar(char ch) {
|
||||
volatile char *virt_addr = (char *)0xbfaffff0;
|
||||
*virt_addr = ch;
|
||||
}
|
||||
|
||||
void putstr(char *str) {
|
||||
while (*str)
|
||||
putchar(*str++);
|
||||
}
|
||||
|
||||
void puthex(unsigned x) {
|
||||
char buf[11];
|
||||
char *num = &buf[2];
|
||||
unsigned mask = 0xf;
|
||||
for (int i = 0; i < 8; i++) {
|
||||
num[7 - i] = "0123456789ABCDEF"[x & mask];
|
||||
x >>= 4;
|
||||
}
|
||||
buf[0] = '0', buf[1] = 'x', buf[10] = 0;
|
||||
putstr(buf);
|
||||
}
|
||||
|
||||
void puts(char *str) {
|
||||
putstr(str);
|
||||
putchar('\n');
|
||||
}
|
||||
|
||||
unsigned long __ffs(unsigned long word) {
|
||||
int num = 0;
|
||||
|
||||
if ((word & 0xffff) == 0) {
|
||||
num += 16;
|
||||
word >>= 16;
|
||||
}
|
||||
if ((word & 0xff) == 0) {
|
||||
num += 8;
|
||||
word >>= 8;
|
||||
}
|
||||
if ((word & 0xf) == 0) {
|
||||
num += 4;
|
||||
word >>= 4;
|
||||
}
|
||||
if ((word & 0x3) == 0) {
|
||||
num += 2;
|
||||
word >>= 2;
|
||||
}
|
||||
if ((word & 0x1) == 0)
|
||||
num += 1;
|
||||
return num;
|
||||
}
|
||||
|
||||
#define ___read_32bit_c0_register(source, sel, vol) \
|
||||
({ \
|
||||
unsigned int __res; \
|
||||
if (sel == 0) \
|
||||
__asm__ vol("mfc0\t%0, " #source "\n\t" : "=r"(__res)); \
|
||||
else \
|
||||
__asm__ vol(".set\tpush\n\t" \
|
||||
".set\tmips32\n\t" \
|
||||
"mfc0\t%0, " #source ", " #sel "\n\t" \
|
||||
".set\tpop\n\t" \
|
||||
: "=r"(__res)); \
|
||||
__res; \
|
||||
})
|
||||
|
||||
#define __read_32bit_c0_register(source, sel) ___read_32bit_c0_register(source, sel, __volatile__)
|
||||
#define read_c0_config() __read_32bit_c0_register($16, 0)
|
||||
#define read_c0_config1() __read_32bit_c0_register($16, 1)
|
||||
|
||||
struct cpuinfo_mips current_cpu_data;
|
||||
|
||||
void probe_pcache(void) {
|
||||
unsigned long icache_size;
|
||||
unsigned long dcache_size;
|
||||
|
||||
struct cpuinfo_mips *c = ¤t_cpu_data;
|
||||
unsigned int config = read_c0_config();
|
||||
unsigned long config1;
|
||||
unsigned int lsize;
|
||||
|
||||
puts("init: probing cache");
|
||||
|
||||
config1 = read_c0_config1();
|
||||
|
||||
lsize = (config1 >> 19) & 7;
|
||||
|
||||
/* IL == 7 is reserved */
|
||||
if (lsize == 7) {
|
||||
puts("init: Invalid icache line size");
|
||||
MAKE_ERR;
|
||||
return;
|
||||
}
|
||||
|
||||
c->icache.linesz = lsize ? 2 << lsize : 0;
|
||||
|
||||
c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
|
||||
c->icache.ways = 1 + ((config1 >> 16) & 7);
|
||||
|
||||
icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
|
||||
c->icache.waybit = __ffs(icache_size / c->icache.ways);
|
||||
|
||||
lsize = (config1 >> 10) & 7;
|
||||
|
||||
/* DL == 7 is reserved */
|
||||
if (lsize == 7) {
|
||||
puts("Invalid dcache line size");
|
||||
MAKE_ERR;
|
||||
return;
|
||||
}
|
||||
|
||||
c->dcache.linesz = lsize ? 2 << lsize : 0;
|
||||
|
||||
c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
|
||||
c->dcache.ways = 1 + ((config1 >> 7) & 7);
|
||||
|
||||
dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
|
||||
c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
|
||||
|
||||
/* compute a couple of other cache variables */
|
||||
c->icache.waysize = icache_size / c->icache.ways;
|
||||
c->dcache.waysize = dcache_size / c->dcache.ways;
|
||||
|
||||
c->icache.sets = c->icache.linesz ? icache_size / (c->icache.linesz * c->icache.ways) : 0;
|
||||
c->dcache.sets = c->dcache.linesz ? dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
|
||||
|
||||
putstr("init: icache: "), puthex(icache_size >> 10), putstr("kB, linesz="), puthex(c->icache.linesz),
|
||||
putstr(", ways="), puthex(c->icache.ways), putstr(", waysize="), puthex(c->icache.waysize), putstr(", waybit="),
|
||||
puthex(c->icache.waybit), putstr(", sets="), puthex(c->icache.sets), putchar('\n');
|
||||
putstr("init: dcache: "), puthex(dcache_size >> 10), putstr("kB, linesz="), puthex(c->dcache.linesz),
|
||||
putstr(", ways="), puthex(c->dcache.ways), putstr(", waysize="), puthex(c->dcache.waysize), putstr(", waybit="),
|
||||
puthex(c->dcache.waybit), putstr(", sets="), puthex(c->dcache.sets), putchar('\n');
|
||||
// pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10,
|
||||
// c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", way_string[c->icache.ways], c->icache.linesz);
|
||||
|
||||
// pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", dcache_size >> 10,
|
||||
// way_string[c->dcache.ways],
|
||||
// (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
|
||||
// (c->dcache.flags & MIPS_CACHE_ALIASES) ? "cache aliases" : "no aliases", c->dcache.linesz);
|
||||
}
|
||||
|
||||
void srand(unsigned short seed) {
|
||||
volatile unsigned short *lfsr = (unsigned short *)0x8000007c;
|
||||
*lfsr = seed;
|
||||
}
|
||||
|
||||
inline unsigned rand16() {
|
||||
volatile unsigned short *lfsr = (unsigned short *)0x8000007c;
|
||||
unsigned prv = *lfsr;
|
||||
|
||||
unsigned bit = ((prv >> 0) ^ (prv >> 2) ^ (prv >> 3) ^ (prv >> 5)) & 1;
|
||||
*lfsr = (prv >> 1) | (bit << 15);
|
||||
|
||||
return *lfsr;
|
||||
}
|
||||
|
||||
unsigned rand() { return (rand16() << 16) | rand16(); }
|
||||
|
||||
void init_crt() {
|
||||
// moved to start.S
|
||||
// register volatile unsigned sp asm("sp");
|
||||
// sp = 0x88000000;
|
||||
|
||||
srand(0xACE1u);
|
||||
probe_pcache();
|
||||
|
||||
puts("init: crt inited");
|
||||
}
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
#include <utils.h>
|
||||
|
||||
#define TEST_NUM 156
|
||||
#define TEST_NUM 155
|
||||
|
||||
|
||||
##s0, number
|
||||
@ -309,7 +309,12 @@ locate:
|
||||
lui s0, 0 ## initial run number
|
||||
|
||||
inst_test:
|
||||
TEST_UNIT_CACHE(n104_linux)
|
||||
lui sp, 0x8800
|
||||
jal init_crt
|
||||
nop
|
||||
|
||||
|
||||
TEST_C_ENV(n105_playground_test) # 155
|
||||
|
||||
TEST_UNIT_CACHE(n1_lui_test) # 1 2
|
||||
TEST_UNIT_CACHE(n2_addu_test)
|
||||
@ -419,6 +424,8 @@ inst_test:
|
||||
TEST_UNIT_CACHE(n96_maddu_test)
|
||||
TEST_UNIT_CACHE(n97_msub_msubu_test)
|
||||
|
||||
TEST_UNIT(n98_cache_dcache_test) # 146
|
||||
TEST_UNIT_ONLY_CACHE(n99_cache_icache_test)
|
||||
|
||||
TEST_UNIT_CACHE(n100_movz_movn_test) # 148 149
|
||||
|
||||
@ -428,8 +435,8 @@ inst_test:
|
||||
|
||||
TEST_UNIT_ONLY_CACHE(n103_memory1_test) # 153
|
||||
|
||||
TEST_UNIT(n98_cache_dcache_test) # 146
|
||||
TEST_UNIT_ONLY_CACHE(n99_cache_icache_test)
|
||||
TEST_UNIT_CACHE(n104_linux) # 154
|
||||
|
||||
|
||||
###check io access
|
||||
LI (a0, IO_SIMU_ADDR)
|
||||
|
||||
@ -13,12 +13,6 @@ module testbench_top ();
|
||||
logic clk;
|
||||
|
||||
//gpio
|
||||
logic [15:0] led;
|
||||
logic [ 1:0] led_rg0;
|
||||
logic [ 1:0] led_rg1;
|
||||
logic [ 7:0] num_csn;
|
||||
logic [ 6:0] num_a_g;
|
||||
logic [ 7:0] switch;
|
||||
logic [ 3:0] btn_key_col;
|
||||
logic [ 3:0] btn_key_row;
|
||||
logic [ 1:0] btn_step;
|
||||
@ -28,7 +22,7 @@ module testbench_top ();
|
||||
logic [31:0] confreg_num_reg;
|
||||
logic [31:0] confreg_num_reg_r;
|
||||
|
||||
assign switch = 8'hff;
|
||||
assign switch_sim = 8'hff;
|
||||
assign btn_key_row = 4'd0;
|
||||
assign btn_step = 2'd3;
|
||||
assign uart_display = `CONFREG_UART_DISPLAY;
|
||||
@ -36,8 +30,6 @@ module testbench_top ();
|
||||
assign confreg_num_reg = `CONFREG_NUM_REG;
|
||||
|
||||
// soc clk & debug info
|
||||
logic cpu_clk;
|
||||
logic sys_clk;
|
||||
logic [31:0] debug_wb_pc;
|
||||
logic [ 3:0] debug_wb_rf_wen;
|
||||
logic [ 4:0] debug_wb_rf_wnum;
|
||||
@ -47,16 +39,14 @@ module testbench_top ();
|
||||
logic [ 4:0] debug_wb1_rf_wnum;
|
||||
logic [31:0] debug_wb1_rf_wdata;
|
||||
logic debug_wb_pc_A;
|
||||
logic dbg_0_rf_wen;
|
||||
logic [ 3:0] dbg_0_rf_wen;
|
||||
logic [31:0] dbg_0_pc;
|
||||
logic [ 4:0] dbg_0_rf_wnum;
|
||||
logic [31:0] dbg_0_rf_wdata;
|
||||
logic dbg_1_rf_wen;
|
||||
logic [ 3:0] dbg_1_rf_wen;
|
||||
logic [31:0] dbg_1_pc;
|
||||
logic [ 4:0] dbg_1_rf_wnum;
|
||||
logic [31:0] dbg_1_rf_wdata;
|
||||
assign cpu_clk = soc_lite.cpu_clk;
|
||||
assign sys_clk = soc_lite.sys_clk;
|
||||
assign debug_wb_pc = soc_lite.debug_wb_pc;
|
||||
assign debug_wb_rf_wen = soc_lite.debug_wb_rf_wen;
|
||||
assign debug_wb_rf_wnum = soc_lite.debug_wb_rf_wnum;
|
||||
@ -67,7 +57,7 @@ module testbench_top ();
|
||||
assign debug_wb1_rf_wdata = soc_lite.u_cpu.debug_wb1_rf_wdata;
|
||||
assign debug_wb_pc_A = soc_lite.u_cpu.debug_wb_pc_A;
|
||||
|
||||
always @(posedge cpu_clk) begin
|
||||
always @(posedge clk) begin
|
||||
if (debug_wb_pc_A) begin
|
||||
dbg_0_rf_wen <= debug_wb1_rf_wen;
|
||||
dbg_0_pc <= debug_wb1_pc;
|
||||
@ -90,18 +80,18 @@ module testbench_top ();
|
||||
dbg_0_rf_wdata <= debug_wb_rf_wdata;
|
||||
end
|
||||
|
||||
// if (|dbg_0_rf_wen) begin
|
||||
// $display("path0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
|
||||
// dbg_0_pc, dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen);
|
||||
// end
|
||||
// if (|dbg_1_rf_wen) begin
|
||||
// $display("path1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
|
||||
// dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
|
||||
// end
|
||||
//if (|dbg_0_rf_wen & resetn) begin
|
||||
// $display("path0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
|
||||
// dbg_0_pc, dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen);
|
||||
//end
|
||||
//if (|dbg_1_rf_wen & resetn) begin
|
||||
// $display("path1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
|
||||
// dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
|
||||
//end
|
||||
end
|
||||
|
||||
// UART
|
||||
always @(posedge sys_clk) begin
|
||||
always @(posedge clk) begin
|
||||
if (uart_display) begin
|
||||
if (uart_data == 8'hff) begin
|
||||
; //$finish;
|
||||
@ -113,7 +103,7 @@ module testbench_top ();
|
||||
|
||||
// Numeric Display
|
||||
logic [7:0] err_count;
|
||||
always_ff @(posedge sys_clk) begin
|
||||
always_ff @(posedge clk) begin
|
||||
confreg_num_reg_r <= confreg_num_reg;
|
||||
if (!resetn) begin
|
||||
err_count <= 8'd0;
|
||||
@ -123,11 +113,13 @@ module testbench_top ();
|
||||
$display("[%t] Error(%d)! Occurred in number 8'd%02d Functional Test Point!", $time, err_count, confreg_num_reg[31:24]);
|
||||
$display("--------------------------------------------------------------");
|
||||
err_count <= err_count + 1'b1;
|
||||
$finish;
|
||||
end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin
|
||||
$display("--------------------------------------------------------------");
|
||||
$display("[%t] Error(%d)! Unknown, Functional Test Point numbers are unequal!", $time, err_count);
|
||||
$display("--------------------------------------------------------------");
|
||||
err_count <= err_count + 1'b1;
|
||||
$finish;
|
||||
end else begin
|
||||
$display("----[%t] Number 8'd%02d Functional Test Point PASS!", $time, confreg_num_reg[31:24]);
|
||||
end
|
||||
@ -137,7 +129,7 @@ module testbench_top ();
|
||||
//test end
|
||||
logic test_end;
|
||||
assign test_end = (dbg_0_pc == `END_PC) || (dbg_1_pc == `END_PC) || (uart_display && uart_data == 8'hff);
|
||||
always @(posedge cpu_clk)
|
||||
always @(posedge clk)
|
||||
if (test_end) begin
|
||||
if (err_count != 0) begin
|
||||
$display("");
|
||||
@ -163,7 +155,7 @@ module testbench_top ();
|
||||
.led (led),
|
||||
.led_rg0 (led_rg0),
|
||||
.led_rg1 (led_rg1),
|
||||
.switch (switch),
|
||||
.switch (switch_sim),
|
||||
.btn_key_col(btn_key_col),
|
||||
.btn_key_row(btn_key_row),
|
||||
.btn_step (btn_step)
|
||||
@ -171,7 +163,7 @@ module testbench_top ();
|
||||
|
||||
initial begin
|
||||
resetn = 1'b0;
|
||||
#2000;
|
||||
#200;
|
||||
resetn = 1'b1;
|
||||
end
|
||||
|
||||
|
||||
2
sim/.gitignore
vendored
2
sim/.gitignore
vendored
@ -2,3 +2,5 @@
|
||||
/logs
|
||||
*.gtkw
|
||||
*.mif
|
||||
nohup.out
|
||||
logs.txt
|
||||
|
||||
14
sim/Makefile
14
sim/Makefile
@ -24,7 +24,9 @@ VERILATOR_BUILD_FLAGS += --assert
|
||||
# Generate coverage analysis
|
||||
VERILATOR_BUILD_FLAGS += --coverage
|
||||
# Run make to compile model, with as many CPUs as are free
|
||||
VERILATOR_BUILD_FLAGS += --compiler clang -CFLAGS "-Wno-parentheses-equality" -j
|
||||
VERILATOR_BUILD_FLAGS += -CFLAGS "-Wno-parentheses-equality" -j
|
||||
# Report UNOPTFLAT
|
||||
VERILATOR_BUILD_FLAGS += --report-unoptflat
|
||||
|
||||
# Simulation Defines
|
||||
VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC
|
||||
@ -52,7 +54,7 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour
|
||||
####################
|
||||
.phony: lint verilate func_soft tlb_soft build coverage run clean
|
||||
|
||||
default: run
|
||||
default: build
|
||||
|
||||
lint:
|
||||
$(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top
|
||||
@ -61,13 +63,13 @@ verilate:
|
||||
$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT)
|
||||
|
||||
func_soft:
|
||||
cd ../resources/soft/func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim
|
||||
cd ../resources/soft/func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
|
||||
|
||||
tlb_soft:
|
||||
cd ../resources/soft/tlb_func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim
|
||||
cd ../resources/soft/tlb_func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
|
||||
|
||||
build: verilate
|
||||
make -C obj_dir -f Vtestbench_top.mk -j
|
||||
make -C obj_dir -f Vtestbench_top.mk -j 10
|
||||
|
||||
coverage:
|
||||
@rm -rf logs/annotated
|
||||
@ -76,7 +78,7 @@ coverage:
|
||||
run: build
|
||||
@rm -rf logs
|
||||
obj_dir/Vtestbench_top
|
||||
gtkwave logs/trace.fst
|
||||
# gtkwave logs/trace.fst
|
||||
|
||||
clean:
|
||||
-rm -rf obj_dir logs
|
||||
|
||||
@ -1,13 +1,16 @@
|
||||
`verilator_config
|
||||
lint_off -rule TIMESCALEMOD
|
||||
lint_off -rule DECLFILENAME
|
||||
lint_off -rule INITIALDLY
|
||||
lint_off -rule UNUSEDSIGNAL
|
||||
|
||||
lint_off -file "model/*.v"
|
||||
lint_off -file "../resources/func_test/*.v"
|
||||
|
||||
lint_off -rule UNOPTFLAT -file "model/axi_crossbar_addr.v"
|
||||
lint_off -rule UNOPTFLAT -file "model/priority_encoder.v"
|
||||
lint_off -rule UNOPTFLAT -file "model/axi_crossbar_addr.v"
|
||||
lint_off -rule UNOPTFLAT -file "model/priority_encoder.v"
|
||||
lint_off -rule INITIALDLY -file "model/axi_crossbar_addr.v"
|
||||
lint_off -rule BLKSEQ -file "../src/CP0/CP0.sv"
|
||||
lint_off -rule UNOPTFLAT -file "../src/Core/Datapath.sv"
|
||||
lint_off -rule UNOPTFLAT -file "../src/Gadgets/mux3.sv"
|
||||
|
||||
//lint_off -rule UNOPTFLAT -file "../src/Core/Datapath.sv"
|
||||
//lint_off -rule UNOPTFLAT -file "../src/Gadgets/mux3.sv"
|
||||
//lint_off -rule UNOPTFLAT -file "../src/Core/Controller.sv"
|
||||
|
||||
@ -77,7 +77,7 @@ module axi_crossbar #
|
||||
parameter M_BASE_ADDR = {{32'h1fc00000, 32'h20000000, 32'h40000000, 32'h80000000, 32'h0}, {32'h1faf0000, 32'hffffffff, 32'hffffffff, 32'hffffffff, 32'hffffffff}},
|
||||
// Master interface address widths
|
||||
// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
|
||||
parameter M_ADDR_WIDTH = {{32'd22, 32'd29, 32'd30, 32'd31, 32'd28}, {32'd16, 32'd0, 32'd0, 32'd0, 32'd0}}, //{M_COUNT{{M_REGIONS{32'd24}}}},
|
||||
parameter M_ADDR_WIDTH = {{32'd22, 32'd29, 32'd30, 32'd28, 32'd28}, {32'd16, 32'd0, 32'd0, 32'd0, 32'd0}}, //{M_COUNT{{M_REGIONS{32'd24}}}},
|
||||
// Read connections between interfaces
|
||||
// M_COUNT concatenated fields of S_COUNT bits
|
||||
parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}},
|
||||
|
||||
@ -31,7 +31,7 @@ module axi_ram #
|
||||
// Width of data bus in bits
|
||||
parameter DATA_WIDTH = 32,
|
||||
// Width of address bus in bits
|
||||
parameter ADDR_WIDTH = 20,
|
||||
parameter ADDR_WIDTH = 28,
|
||||
// Width of wstrb (width of data bus in words)
|
||||
parameter STRB_WIDTH = (DATA_WIDTH/8),
|
||||
// Width of ID signal
|
||||
@ -135,9 +135,36 @@ reg s_axi_rvalid_pipe_reg = 1'b0;
|
||||
// (* RAM_STYLE="BLOCK" *)
|
||||
reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
|
||||
initial begin
|
||||
$display("[%0t] Loading ram.mif", $time);
|
||||
$readmemb("axi_ram.mif", mem);
|
||||
$display("[%0t] ram.mif[0] = 0x%0h", $time, mem[0]);
|
||||
// ADDR_WIDTH = 28
|
||||
// (28 - 4)
|
||||
// |
|
||||
// v
|
||||
// 1ff0_0000: 0001 1111 1111 0000 0000 0000 0000 0000 -> 0x3fc0000
|
||||
// bfc0_0000: 1011 1111 1100 0000 0000 0000 0000 0000 -> 0x3f00000
|
||||
// 1fc0_0000: 0001 1111 1100 0000 0000 0000 0000 0000 -> 0x3f00000
|
||||
// 9fc0_0000: 1001 1111 1100 0000 0000 0000 0000 0000 -> 0x3f00000
|
||||
// 8800_0000: 1000 1000 0000 0000 0000 0000 0000 0000 -> 0x2000000
|
||||
// 8000_0000: 1000 0000 0000 0000 0000 0000 0000 0000 -> 0x0000000
|
||||
// |------------------------------|
|
||||
|
||||
$display("[%0t] Loading inst_ram.mif", $time);
|
||||
$readmemb("inst_ram.mif", mem, 'h3f00000);
|
||||
|
||||
$display("[%0t] Loading data_ram.mif", $time);
|
||||
$readmemb("data_ram.mif", mem, 'h40);
|
||||
|
||||
$display("[%0t] ram[0x3f00000] = 0x%0h", $time, mem['h3f00000]);
|
||||
$display("[%0t] ram[0x3f00001] = 0x%0h", $time, mem['h3f00001]);
|
||||
$display("[%0t] ram[0x3f00002] = 0x%0h", $time, mem['h3f00002]);
|
||||
$display("[%0t] ram[0x40] = 0x%0h", $time, mem['h40]);
|
||||
end
|
||||
|
||||
reg [31:0] trace_before = 0;
|
||||
always @(posedge s_aclk) begin
|
||||
if (mem['h1000000] != trace_before) begin
|
||||
trace_before <= mem['h1000000];
|
||||
$display("[%0t] ram['h1000000] = 0x%0h, before = 0x%0h", $time, mem['h1000000], trace_before);
|
||||
end
|
||||
end
|
||||
|
||||
wire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
|
||||
|
||||
@ -1015,6 +1015,12 @@ module Datapath (
|
||||
: cache_op.op.dcache_op ? {E_I1_ADDR[32-`DC_INDEXL-1:0], `DC_INDEXL'b0}
|
||||
: {E_I1_ADDR[32-`IC_INDEXL-1:0], `IC_INDEXL'b0};
|
||||
|
||||
always_ff @(posedge clk) begin
|
||||
if (cache_op.req) begin
|
||||
$display("<< dp index_or_hit=%0h writeback=%0h addr=0x%0h >>", cache_op.op.index_or_hit, cache_op.op.writeback, cache_op.addr);
|
||||
end
|
||||
end
|
||||
|
||||
assign E.en = E_go & M.en;
|
||||
assign E_go = (~mem.req | mem.addr_ok) & (~cache_op.req | cache_op.addr_ok);
|
||||
|
||||
|
||||
@ -1,289 +1,208 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||
<spirit:library>xci</spirit:library>
|
||||
<spirit:name>unknown</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:componentInstances>
|
||||
<spirit:componentInstance>
|
||||
<spirit:instanceName>div_signed</spirit:instanceName>
|
||||
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="div_gen" spirit:version="5.1"/>
|
||||
<spirit:configurableElementValues>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.ASSOCIATED_PORT"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_HZ">1000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.FREQ_TOLERANCE_HZ">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ACLK_INTF.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.ARESETN_INTF.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TREADY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDATA_NUM_BYTES">8</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.M_AXIS_DOUT.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TREADY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVIDEND.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.CLK_DOMAIN"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TKEEP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TREADY">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.HAS_TSTRB">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.INSERT_VIP">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.LAYERED_METADATA">undef</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.PHASE">0.0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDATA_NUM_BYTES">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TDEST_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TID_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.S_AXIS_DIVISOR.TUSER_WIDTH">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.ALGORITHM_TYPE">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ACLKEN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ARESETN">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_DIV_BY_ZERO">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVIDEND_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TLAST">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_S_AXIS_DIVISOR_TUSER">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LATENCY">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TDATA_WIDTH">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_AXIS_DOUT_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVIDEND_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TDATA_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXIS_DIVISOR_TUSER_WIDTH">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_THROTTLE_SCHEME">3</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_TLAST_RESOLUTION">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVCLK_SEL">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVIDEND_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.DIVISOR_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.FRACTIONAL_WIDTH">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.SIGNED_B">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ACLKEN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ARESETN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">div_signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FlowControl">NonBlocking</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OptimizeGoal">Performance</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTLASTBehv">Null</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OutTready">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.algorithm_type">Radix2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.clocks_per_division">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divide_by_zero_detect">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_and_quotient_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.dividend_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tlast">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_has_tuser">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_tuser_width">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.divisor_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.fractional_width">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency">16</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.latency_configuration">Manual</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.operand_sign">Signed</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.remainder_type">Remainder</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">19</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
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||||
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||||
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||||
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||||
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|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}"/>
|
||||
</xilinx:boundaryDescriptionInfo>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
{
|
||||
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||
"ip_inst": {
|
||||
"xci_name": "mul_unsigned",
|
||||
"component_reference": "xilinx.com:ip:mult_gen:12.0",
|
||||
"ip_revision": "18",
|
||||
"gen_directory": ".",
|
||||
"parameters": {
|
||||
"component_parameters": {
|
||||
"InternalUser": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"Component_Name": [ { "value": "mul_unsigned", "resolve_type": "user", "usage": "all" } ],
|
||||
"MultType": [ { "value": "Parallel_Multiplier", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAType": [ { "value": "Unsigned", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortAWidth": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"PortBType": [ { "value": "Unsigned", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"PortBWidth": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"ConstValue": [ { "value": "129", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"CcmImp": [ { "value": "Distributed_Memory", "resolve_type": "user", "usage": "all" } ],
|
||||
"Multiplier_Construction": [ { "value": "Use_Mults", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"OptGoal": [ { "value": "Speed", "resolve_type": "user", "usage": "all" } ],
|
||||
"Use_Custom_Output_Width": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"OutputWidthHigh": [ { "value": "63", "value_src": "user", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"OutputWidthLow": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"UseRounding": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ],
|
||||
"RoundPoint": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ],
|
||||
"PipeStages": [ { "value": "6", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||
"ClockEnable": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SyncClear": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||
"SclrCePriority": [ { "value": "SCLR_Overrides_CE", "resolve_type": "user", "enabled": false, "usage": "all" } ],
|
||||
"ZeroDetect": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||
},
|
||||
"model_parameters": {
|
||||
"C_VERBOSITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MODEL_TYPE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OPTIMIZE_GOAL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_CE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_HAS_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_LATENCY": [ { "value": "6", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_A_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_HIGH": [ { "value": "63", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_OUT_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_MULT_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CE_OVERRIDES_SCLR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_CCM_IMP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_B_VALUE": [ { "value": "10000001", "resolve_type": "generated", "usage": "all" } ],
|
||||
"C_HAS_ZERO_DETECT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_OUTPUT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||
"C_ROUND_PT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
|
||||
},
|
||||
"project_parameters": {
|
||||
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||
"DEVICE": [ { "value": "xc7a200t" } ],
|
||||
"PACKAGE": [ { "value": "fbg676" } ],
|
||||
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||
"SILICON_REVISION": [ { "value": "" } ],
|
||||
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||
"SPEEDGRADE": [ { "value": "-2" } ],
|
||||
"STATIC_POWER": [ { "value": "" } ],
|
||||
"TEMPERATURE_GRADE": [ { "value": "" } ],
|
||||
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
|
||||
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
|
||||
},
|
||||
"runtime_parameters": {
|
||||
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||
"IPREVISION": [ { "value": "18" } ],
|
||||
"MANAGED": [ { "value": "TRUE" } ],
|
||||
"OUTPUTDIR": [ { "value": "." } ],
|
||||
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||
"SHAREDDIR": [ { "value": "." } ],
|
||||
"SWVERSION": [ { "value": "2022.2" } ],
|
||||
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||
}
|
||||
},
|
||||
"boundary": {
|
||||
"ports": {
|
||||
"CLK": [ { "direction": "in", "driver_value": "0x1" } ],
|
||||
"A": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"B": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
|
||||
"P": [ { "direction": "out", "size_left": "63", "size_right": "0", "driver_value": "0" } ]
|
||||
},
|
||||
"interfaces": {
|
||||
"a_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "A" } ]
|
||||
}
|
||||
},
|
||||
"clk_intf": {
|
||||
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"ASSOCIATED_BUSIF": [ { "value": "p_intf:b_intf:a_intf", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_RESET": [ { "value": "sclr", "value_src": "constant", "usage": "all" } ],
|
||||
"ASSOCIATED_CLKEN": [ { "value": "ce", "value_src": "constant", "usage": "all" } ],
|
||||
"FREQ_HZ": [ { "value": "10000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_static_object": false } ],
|
||||
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_static_object": false } ],
|
||||
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_static_object": false } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"CLK": [ { "physical_name": "CLK" } ]
|
||||
}
|
||||
},
|
||||
"sclr_intf": {
|
||||
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ]
|
||||
}
|
||||
},
|
||||
"ce_intf": {
|
||||
"vlnv": "xilinx.com:signal:clockenable:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:clockenable_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ]
|
||||
}
|
||||
},
|
||||
"b_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "slave",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "B" } ]
|
||||
}
|
||||
},
|
||||
"p_intf": {
|
||||
"vlnv": "xilinx.com:signal:data:1.0",
|
||||
"abstraction_type": "xilinx.com:signal:data_rtl:1.0",
|
||||
"mode": "master",
|
||||
"parameters": {
|
||||
"LAYERED_METADATA": [ { "value": "undef", "resolve_type": "generated", "is_static_object": false } ]
|
||||
},
|
||||
"port_maps": {
|
||||
"DATA": [ { "physical_name": "P" } ]
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -34,10 +34,10 @@ module DCache (
|
||||
DCTag_t tag[`DC_WAYS];
|
||||
DCData_t data[`DC_WAYS];
|
||||
|
||||
logic [`DC_WAYS-1:0] hitway;
|
||||
logic [`DC_WAYS-1:0] victim;
|
||||
DCTagL_t dirt_tag;
|
||||
logic [`DC_WAYS-1:0] wen;
|
||||
logic [`DC_WAYS-1:0] hitway/*verilator split_var*/;
|
||||
logic [`DC_WAYS-1:0] victim/*verilator split_var*/;
|
||||
DCTagL_t dirt_tag/*verilator split_var*/;
|
||||
logic [`DC_WAYS-1:0] wen/*verilator split_var*/;
|
||||
|
||||
|
||||
// ==============================
|
||||
@ -153,6 +153,27 @@ module DCache (
|
||||
end
|
||||
|
||||
|
||||
logic [31:0] magic_counter = 0;
|
||||
always_ff @(posedge clk) magic_counter <= magic_counter + 1;
|
||||
|
||||
// 0x04000000
|
||||
// 0000 0100 0000 0000 0000 0000 0000 0000
|
||||
// tag = 0x04000
|
||||
// index = 0
|
||||
// offset = 0
|
||||
for (genvar i = 0; i < `DC_WAYS; i++)
|
||||
always_ff @(posedge clk) begin
|
||||
if (TagRAM[i].wen) begin
|
||||
if (TagRAM[i].addr == 0 && TagRAM[i].wdata.tag[19:4] == 'h0400) begin
|
||||
$display("<< counter=0x%0h way=0x%0h tag=0x%0h index=0x%0h addr=0x%0h dirty=0x%0h valid=0x%0h data=0x%0h read_and_hit=%0h read_but_replace=%0h write_and_hit=%0h write_but_replace=%0h cache_index_invalidate=%0h cache_index_writeback=%0h cache_hit_invalidate=%0h cache_hit_writeback=%0h >>",
|
||||
magic_counter, i, TagRAM[i].wdata.tag, TagRAM[i].addr, {TagRAM[i].wdata.tag, TagRAM[i].addr, `DC_INDEXL'b0},
|
||||
TagRAM[i].wdata.dirty, TagRAM[i].wdata.valid, DataRAM[i].wdata,
|
||||
port.ctrl.read_and_hit, port.ctrl.read_but_replace, port.ctrl.write_and_hit, port.ctrl.write_but_replace, port.ctrl.cache_index_invalidate, port.ctrl.cache_index_writeback, port.ctrl.cache_hit_invalidate, port.ctrl.cache_hit_writeback
|
||||
);
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// BRAM 实例
|
||||
for (genvar i = 0; i < `DC_WAYS; i++) begin : dbram
|
||||
bram #(.DATA_WIDTH(32-`DC_TAGL+2), .DATA_DEPTH(2 ** (`DC_TAGL-`DC_INDEXL)))
|
||||
|
||||
10
src/MU/MU.sv
10
src/MU/MU.sv
@ -358,7 +358,8 @@ module MU (
|
||||
: mem_rdata_source_data[{stored_memory_addr[`DC_INDEXL-1:2], 5'b0}+:32];
|
||||
|
||||
logic mem_wstrb_direct;
|
||||
DCData_t mem_wdata_source_data, mem_wdata_output;
|
||||
DCData_t mem_wdata_source_data/*verilator split_var*/;
|
||||
DCData_t mem_wdata_output;
|
||||
word_t mem_wdata_data;
|
||||
logic [`DC_INDEXL-3:0] base;
|
||||
assign base = stored_memory_addr[`DC_INDEXL-1:2];
|
||||
@ -375,6 +376,9 @@ module MU (
|
||||
// == Memory Control State Machine ==
|
||||
// ==================================
|
||||
|
||||
logic [31:0] wb_magic_counter = 0;
|
||||
always_ff @(posedge clk) wb_magic_counter <= wb_magic_counter + 1;
|
||||
|
||||
typedef enum bit [1:0] {
|
||||
MEM_LOOKUP,
|
||||
MEM_READ,
|
||||
@ -434,7 +438,6 @@ module MU (
|
||||
dcache.index_for_lookup = cacheop.addr[`DC_TAGL-1:`DC_INDEXL];
|
||||
end else if (~memory_valid) begin
|
||||
in_mem_ready = 1;
|
||||
|
||||
end else if (mem_req & memory_cached & dcache.hit) begin
|
||||
// Cached + Hit
|
||||
if (~memory.wr) begin
|
||||
@ -612,6 +615,9 @@ module MU (
|
||||
dcache.ctrl.cache_hit_writeback = stored_cacheop_op.index_or_hit;
|
||||
|
||||
if (dcache.dirt) begin
|
||||
$display("<< wb: cnt=0x%0h op.hit=%0h dc.hit=%0h dc.index=%0h dc.tag=%0h dc.dirt=%0h dc.dirt_addr=0x%0h dc.data=%0h >>",
|
||||
wb_magic_counter, stored_cacheop_op.index_or_hit, dcache.hit, dcache.index, dcache.tag, dcache.dirt, dcache.dirt_addr, dcache.dirt_row);
|
||||
|
||||
mem_nxt_state = MEM_WRITE;
|
||||
|
||||
amw_call = 1'b1;
|
||||
|
||||
@ -12,6 +12,7 @@
|
||||
|
||||
`ifdef SIMULATION_VERILATOR
|
||||
`undef ENABLE_CpU
|
||||
`undef ILA_DEBUG
|
||||
`endif
|
||||
|
||||
`ifndef ENABLE_CACHEOP
|
||||
|
||||
Loading…
Reference in New Issue
Block a user