From 2e0dbc2f205f26ae1d42faf9ba82643a6ba3a656 Mon Sep 17 00:00:00 2001 From: Paul Pan Date: Sun, 11 Jun 2023 19:48:37 +0800 Subject: [PATCH] sync partial debugging sources --- mips_env | 2 + resources/soft/func/Makefile | 4 +- resources/soft/func/find_rand.c | 22 + resources/soft/func/get_rand.c | 22 + resources/soft/func/include/cacheops.h | 116 +++++ resources/soft/func/include/r4k_cache.h | 170 +++++++ resources/soft/func/include/unroll.h | 68 +++ resources/soft/func/include/utils.h | 99 ++++ resources/soft/func/inst/Makefile | 8 +- resources/soft/func/inst/inst_test.h | 92 ---- resources/soft/func/inst/n105_playground.c | 164 +++++++ resources/soft/func/inst/n98_cache_dcache.S | 85 ++++ resources/soft/func/inst/n99_cache_icache.S | 6 + resources/soft/func/inst/utils.c | 180 +++++++ resources/soft/func/start.S | 15 +- resources/test_vivado.sv | 48 +- sim/.gitignore | 2 + sim/Makefile | 14 +- sim/config.vlt | 13 +- sim/model/axi_crossbar.v | 2 +- sim/model/axi_ram.v | 35 +- src/Core/Datapath.sv | 6 + src/IP/div_signed/div_signed.xci | 497 ++++++++------------ src/IP/div_unsigned/div_unsigned.xci | 494 ++++++++----------- src/IP/mul_signed/mul_signed.xci | 342 +++++++------- src/IP/mul_unsigned/mul_unsigned.xci | 344 +++++++------- src/MU/DCache.sv | 29 +- src/MU/MU.sv | 10 +- src/include/defines.svh | 1 + 29 files changed, 1798 insertions(+), 1092 deletions(-) create mode 100755 mips_env create mode 100644 resources/soft/func/find_rand.c create mode 100644 resources/soft/func/get_rand.c create mode 100644 resources/soft/func/include/cacheops.h create mode 100644 resources/soft/func/include/r4k_cache.h create mode 100644 resources/soft/func/include/unroll.h create mode 100644 resources/soft/func/inst/n105_playground.c create mode 100644 resources/soft/func/inst/utils.c diff --git a/mips_env b/mips_env new file mode 100755 index 0000000..a68ed59 --- /dev/null +++ b/mips_env @@ -0,0 +1,2 @@ +export ARCH=mips +export CROSS_COMPILE=mipsel-linux-gnu- diff --git a/resources/soft/func/Makefile b/resources/soft/func/Makefile index b5e640d..60f3a1f 100644 --- a/resources/soft/func/Makefile +++ b/resources/soft/func/Makefile @@ -1,8 +1,8 @@ TOPDIR=$(shell pwd) #export LD_PRELOAD = -CFLAGS := -D_KERNEL -fno-builtin -mips32r2 -DMEMSTART=0x80000000 -DMEMSIZE=0x04000 -DCPU_COUNT_PER_US=1000 -I $(TOPDIR)/include -CFLAGS += -fno-reorder-blocks -fno-reorder-functions -msoft-float +CFLAGS := -D_KERNEL -fno-builtin -mips32 -DMEMSTART=0x80000100 -DMEMSIZE=0x04000 -DCPU_COUNT_PER_US=1000 -I $(TOPDIR)/include +CFLAGS += -fno-reorder-blocks -fno-reorder-functions -msoft-float -funroll-loops OBJDIR = ./obj diff --git a/resources/soft/func/find_rand.c b/resources/soft/func/find_rand.c new file mode 100644 index 0000000..be28442 --- /dev/null +++ b/resources/soft/func/find_rand.c @@ -0,0 +1,22 @@ +#include + +unsigned short lfsr = 0xACE1u; + +unsigned rand16() { + unsigned bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1; + return lfsr = (lfsr >> 1) | (bit << 15); +} + +unsigned rand() { return (rand16() << 16) | rand16(); } + +int main() { + unsigned target; + + while (~scanf("%x", &target)) { + lfsr = 0xACE1u; + int cnt = 0; + while (rand() != target) + cnt++; + printf("cnt = %d(0x%x)\n", cnt, cnt); + } +} diff --git a/resources/soft/func/get_rand.c b/resources/soft/func/get_rand.c new file mode 100644 index 0000000..6312e4d --- /dev/null +++ b/resources/soft/func/get_rand.c @@ -0,0 +1,22 @@ +#include + +unsigned short lfsr = 0xACE1u; + +unsigned rand16() { + unsigned bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5)) & 1; + return lfsr = (lfsr >> 1) | (bit << 15); +} + +unsigned rand() { return (rand16() << 16) | rand16(); } + +int main() { + unsigned target; + + while (~scanf("%d", &target)) { + lfsr = 0xACE1u; + int cnt = 0; + for (int i = 0; i < target; i++) + rand(); + printf("rand = 0x%x\n", rand()); + } +} diff --git a/resources/soft/func/include/cacheops.h b/resources/soft/func/include/cacheops.h new file mode 100644 index 0000000..e283fbb --- /dev/null +++ b/resources/soft/func/include/cacheops.h @@ -0,0 +1,116 @@ +/* + * Cache operations for the cache instruction. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle + * (C) Copyright 1999 Silicon Graphics, Inc. + */ +#ifndef __ASM_CACHEOPS_H +#define __ASM_CACHEOPS_H + +/* + * Most cache ops are split into a 2 bit field identifying the cache, and a 3 + * bit field identifying the cache operation. + */ +#define CacheOp_Cache 0x03 +#define CacheOp_Op 0x1c + +#define Cache_I 0x00 +#define Cache_D 0x01 +#define Cache_T 0x02 +#define Cache_V 0x02 /* Loongson-3 */ +#define Cache_S 0x03 + +#define Index_Writeback_Inv 0x00 +#define Index_Load_Tag 0x04 +#define Index_Store_Tag 0x08 +#define Hit_Invalidate 0x10 +#define Hit_Writeback_Inv 0x14 /* not with Cache_I though */ +#define Hit_Writeback 0x18 + +/* + * Cache Operations available on all MIPS processors with R4000-style caches + */ +#define Index_Invalidate_I (Cache_I | Index_Writeback_Inv) +#define Index_Writeback_Inv_D (Cache_D | Index_Writeback_Inv) +#define Index_Load_Tag_I (Cache_I | Index_Load_Tag) +#define Index_Load_Tag_D (Cache_D | Index_Load_Tag) +#define Index_Store_Tag_I (Cache_I | Index_Store_Tag) +#define Index_Store_Tag_D (Cache_D | Index_Store_Tag) +#define Hit_Invalidate_I (Cache_I | Hit_Invalidate) +#define Hit_Invalidate_D (Cache_D | Hit_Invalidate) +#define Hit_Writeback_Inv_D (Cache_D | Hit_Writeback_Inv) + +/* + * R4000-specific cacheops + */ +#define Create_Dirty_Excl_D (Cache_D | 0x0c) +#define Fill_I (Cache_I | 0x14) +#define Hit_Writeback_I (Cache_I | Hit_Writeback) +#define Hit_Writeback_D (Cache_D | Hit_Writeback) + +/* + * R4000SC and R4400SC-specific cacheops + */ +#define Cache_SI 0x02 +#define Cache_SD 0x03 + +#define Index_Invalidate_SI (Cache_SI | Index_Writeback_Inv) +#define Index_Writeback_Inv_SD (Cache_SD | Index_Writeback_Inv) +#define Index_Load_Tag_SI (Cache_SI | Index_Load_Tag) +#define Index_Load_Tag_SD (Cache_SD | Index_Load_Tag) +#define Index_Store_Tag_SI (Cache_SI | Index_Store_Tag) +#define Index_Store_Tag_SD (Cache_SD | Index_Store_Tag) +#define Create_Dirty_Excl_SD (Cache_SD | 0x0c) +#define Hit_Invalidate_SI (Cache_SI | Hit_Invalidate) +#define Hit_Invalidate_SD (Cache_SD | Hit_Invalidate) +#define Hit_Writeback_Inv_SD (Cache_SD | Hit_Writeback_Inv) +#define Hit_Writeback_SD (Cache_SD | Hit_Writeback) +#define Hit_Set_Virtual_SI (Cache_SI | 0x1c) +#define Hit_Set_Virtual_SD (Cache_SD | 0x1c) + +/* + * R5000-specific cacheops + */ +#define R5K_Page_Invalidate_S (Cache_S | 0x14) + +/* + * RM7000-specific cacheops + */ +#define Page_Invalidate_T (Cache_T | 0x14) +#define Index_Store_Tag_T (Cache_T | Index_Store_Tag) +#define Index_Load_Tag_T (Cache_T | Index_Load_Tag) + +/* + * R10000-specific cacheops + * + * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. + * Most of the _S cacheops are identical to the R4000SC _SD cacheops. + */ +#define Index_Writeback_Inv_S (Cache_S | Index_Writeback_Inv) +#define Index_Load_Tag_S (Cache_S | Index_Load_Tag) +#define Index_Store_Tag_S (Cache_S | Index_Store_Tag) +#define Hit_Invalidate_S (Cache_S | Hit_Invalidate) +#define Cache_Barrier 0x14 +#define Hit_Writeback_Inv_S (Cache_S | Hit_Writeback_Inv) +#define Index_Load_Data_I (Cache_I | 0x18) +#define Index_Load_Data_D (Cache_D | 0x18) +#define Index_Load_Data_S (Cache_S | 0x18) +#define Index_Store_Data_I (Cache_I | 0x1c) +#define Index_Store_Data_D (Cache_D | 0x1c) +#define Index_Store_Data_S (Cache_S | 0x1c) + +/* + * Loongson2-specific cacheops + */ +#define Hit_Invalidate_I_Loongson2 (Cache_I | 0x00) + +/* + * Loongson3-specific cacheops + */ +#define Index_Writeback_Inv_V (Cache_V | Index_Writeback_Inv) + +#endif /* __ASM_CACHEOPS_H */ diff --git a/resources/soft/func/include/r4k_cache.h b/resources/soft/func/include/r4k_cache.h new file mode 100644 index 0000000..7834772 --- /dev/null +++ b/resources/soft/func/include/r4k_cache.h @@ -0,0 +1,170 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Inline assembly cache operations. + * + * Copyright (C) 1996 David S. Miller (davem@davemloft.net) + * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org) + */ + +#ifndef _ASM_R4KCACHE_H +#define _ASM_R4KCACHE_H + +#include "cacheops.h" +#include "unroll.h" + +#define CKSEG0 0x80000000 +#define PAGE_SIZE (1UL << 12) +#define MIPS_ISA_ARCH_LEVEL "mips32" +#define kernel_cache(op, base) "cache " op ", " base "\n" +#define user_cache(op, base) kernel_cache(op, base) + +struct cache_desc { + unsigned int waysize; + unsigned short sets; + unsigned char ways; + unsigned char linesz; + unsigned char waybit; +}; + +struct cpuinfo_mips { + struct cache_desc icache; + struct cache_desc dcache; +}; + +extern struct cpuinfo_mips current_cpu_data; + +#define INDEX_BASE CKSEG0 + +#define _cache_op(insn, op, addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set "MIPS_ISA_ARCH_LEVEL" \n" \ + " " insn("%0", "%1") " \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +#define cache_op(op, addr) \ + _cache_op(kernel_cache, op, addr) + +static inline void +flush_icache_line_indexed(unsigned long addr) { cache_op(Index_Invalidate_I, addr); } + +static inline void flush_dcache_line_indexed(unsigned long addr) +{ cache_op(Index_Writeback_Inv_D, addr); } + +static inline void flush_icache_line(unsigned long addr) +{ cache_op(Hit_Invalidate_I, addr); } + +static inline void flush_dcache_line(unsigned long addr) +{ cache_op(Hit_Writeback_Inv_D, addr); } + +static inline void invalidate_dcache_line(unsigned long addr) +{ cache_op(Hit_Invalidate_D, addr); } + +#define cache_unroll(times, insn, op, addr, lsize) do { \ + int i = 0; \ + unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \ +} while (0) + +/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */ +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \ +static inline void extra##blast_##pfx##cache##lsize(void) \ +{ \ + unsigned long start = INDEX_BASE; \ + unsigned long end = start + current_cpu_data.desc.waysize; \ + unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ + unsigned long ws_end = current_cpu_data.desc.ways << \ + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache_unroll(32, kernel_cache, indexop, \ + addr | ws, lsize); \ +} \ + \ +static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = page + PAGE_SIZE; \ + \ + do { \ + cache_unroll(32, kernel_cache, hitop, start, lsize); \ + start += lsize * 32; \ + } while (start < end); \ +} \ + \ +static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \ +{ \ + unsigned long indexmask = current_cpu_data.desc.waysize - 1; \ + unsigned long start = INDEX_BASE + (page & indexmask); \ + unsigned long end = start + PAGE_SIZE; \ + unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit; \ + unsigned long ws_end = current_cpu_data.desc.ways << \ + current_cpu_data.desc.waybit; \ + unsigned long ws, addr; \ + \ + for (ws = 0; ws < ws_end; ws += ws_inc) \ + for (addr = start; addr < end; addr += lsize * 32) \ + cache_unroll(32, kernel_cache, indexop, \ + addr | ws, lsize); \ +} + +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, ) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, ) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, ) +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, ) +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, ) +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, ) +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, ) + +#define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \ +static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \ +{ \ + unsigned long start = page; \ + unsigned long end = page + PAGE_SIZE; \ + \ + do { \ + cache_unroll(32, user_cache, hitop, start, lsize); \ + start += lsize * 32; \ + } while (start < end); \ +} + +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16) +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32) +__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64) +__BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64) + +/* build blast_xxx_range, protected_blast_xxx_range */ +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \ +static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \ + unsigned long end) \ +{ \ + unsigned long lsize = current_cpu_data.desc.linesz; \ + unsigned long addr = start & ~(lsize - 1); \ + unsigned long aend = (end - 1) & ~(lsize - 1); \ + \ + while (1) { \ + prot##cache_op(hitop, addr); \ + if (addr == aend) \ + break; \ + addr += lsize; \ + } \ +} + +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , ) +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , ) +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , ) + +#endif /* _ASM_R4KCACHE_H */ diff --git a/resources/soft/func/include/unroll.h b/resources/soft/func/include/unroll.h new file mode 100644 index 0000000..b97c5a9 --- /dev/null +++ b/resources/soft/func/include/unroll.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __ASM_UNROLL_H__ +#define __ASM_UNROLL_H__ + +#define __compiletime_error(msg) __attribute__((__error__(msg))) +#define fallthrough __attribute__((__fallthrough__)) + +/* + * Explicitly unroll a loop, for use in cases where doing so is performance + * critical. + * + * Ideally we'd rely upon the compiler to provide this but there's no commonly + * available means to do so. For example GCC's "#pragma GCC unroll" + * functionality would be ideal but is only available from GCC 8 onwards. Using + * -funroll-loops is an option but GCC tends to make poor choices when + * compiling our string functions. -funroll-all-loops leads to massive code + * bloat, even if only applied to the string functions. + */ +#define unroll(times, fn, ...) do { \ + void bad_unroll(void) \ + __compiletime_error("Unsupported unroll"); \ + \ + switch (times) { \ + case 32: fn(__VA_ARGS__); fallthrough; \ + case 31: fn(__VA_ARGS__); fallthrough; \ + case 30: fn(__VA_ARGS__); fallthrough; \ + case 29: fn(__VA_ARGS__); fallthrough; \ + case 28: fn(__VA_ARGS__); fallthrough; \ + case 27: fn(__VA_ARGS__); fallthrough; \ + case 26: fn(__VA_ARGS__); fallthrough; \ + case 25: fn(__VA_ARGS__); fallthrough; \ + case 24: fn(__VA_ARGS__); fallthrough; \ + case 23: fn(__VA_ARGS__); fallthrough; \ + case 22: fn(__VA_ARGS__); fallthrough; \ + case 21: fn(__VA_ARGS__); fallthrough; \ + case 20: fn(__VA_ARGS__); fallthrough; \ + case 19: fn(__VA_ARGS__); fallthrough; \ + case 18: fn(__VA_ARGS__); fallthrough; \ + case 17: fn(__VA_ARGS__); fallthrough; \ + case 16: fn(__VA_ARGS__); fallthrough; \ + case 15: fn(__VA_ARGS__); fallthrough; \ + case 14: fn(__VA_ARGS__); fallthrough; \ + case 13: fn(__VA_ARGS__); fallthrough; \ + case 12: fn(__VA_ARGS__); fallthrough; \ + case 11: fn(__VA_ARGS__); fallthrough; \ + case 10: fn(__VA_ARGS__); fallthrough; \ + case 9: fn(__VA_ARGS__); fallthrough; \ + case 8: fn(__VA_ARGS__); fallthrough; \ + case 7: fn(__VA_ARGS__); fallthrough; \ + case 6: fn(__VA_ARGS__); fallthrough; \ + case 5: fn(__VA_ARGS__); fallthrough; \ + case 4: fn(__VA_ARGS__); fallthrough; \ + case 3: fn(__VA_ARGS__); fallthrough; \ + case 2: fn(__VA_ARGS__); fallthrough; \ + case 1: fn(__VA_ARGS__); fallthrough; \ + case 0: break; \ + \ + default: \ + /* \ + * Either the iteration count is unreasonable \ + * or we need to add more cases above. \ + */ \ + bad_unroll(); \ + break; \ + } \ +} while (0) + +#endif /* __ASM_UNROLL_H__ */ diff --git a/resources/soft/func/include/utils.h b/resources/soft/func/include/utils.h index 0f6bdb4..abc0299 100644 --- a/resources/soft/func/include/utils.h +++ b/resources/soft/func/include/utils.h @@ -30,3 +30,102 @@ JUMP_TO_CACHED; \ TEST_UNIT(test); \ JUMP_TO_UNCACHED; + +// a0 buf +#define TEST_SAVE_REGS \ + sw v0, 0(a0); \ + sw v1, 4(a0); \ + nop; \ + sw a1, 8(a0); \ + sw a2, 12(a0); \ + sw a3, 16(a0); \ + sw t0, 20(a0); \ + sw t1, 24(a0); \ + sw t2, 28(a0); \ + sw t3, 32(a0); \ + sw t4, 36(a0); \ + sw t5, 40(a0); \ + sw t6, 44(a0); \ + sw t7, 48(a0); \ + sw t8, 52(a0); \ + sw t9, 56(a0); \ + sw s0, 60(a0); \ + sw s1, 64(a0); \ + sw s2, 68(a0); \ + sw s3, 72(a0); \ + sw s4, 76(a0); \ + sw s5, 80(a0); \ + sw s6, 84(a0); \ + sw s7, 88(a0); \ + sw k0, 92(a0); \ + sw k1, 96(a0); \ + sw gp, 100(a0); \ + sw sp, 104(a0); \ + sw fp, 108(a0); \ + sw ra, 112(a0); \ + nop; + +#define TEST_RESTORE_REGS \ + lw v0, 0(a0); \ + lw v1, 4(a0); \ + nop; \ + lw a1, 8(a0); \ + lw a2, 12(a0); \ + lw a3, 16(a0); \ + lw t0, 20(a0); \ + lw t1, 24(a0); \ + lw t2, 28(a0); \ + lw t3, 32(a0); \ + lw t4, 36(a0); \ + lw t5, 40(a0); \ + lw t6, 44(a0); \ + lw t7, 48(a0); \ + lw t8, 52(a0); \ + lw t9, 56(a0); \ + lw s0, 60(a0); \ + lw s1, 64(a0); \ + lw s2, 68(a0); \ + lw s3, 72(a0); \ + lw s4, 76(a0); \ + lw s5, 80(a0); \ + lw s6, 84(a0); \ + lw s7, 88(a0); \ + lw k0, 92(a0); \ + lw k1, 96(a0); \ + lw gp, 100(a0); \ + lw sp, 104(a0); \ + lw fp, 108(a0); \ + lw ra, 112(a0); \ + nop; + +#define TEST_C_ENV(test) \ + JUMP_TO_CACHED; \ + addiu s0, s0 ,1; \ + li s2, 0x0; \ + \ + la a0, 0x80000000; \ + TEST_SAVE_REGS; \ + \ + jal test; \ + nop; \ + \ + la a0, 0x80000000; \ + sw v0, 116(a0); \ + sw s2, 120(a0); \ + TEST_RESTORE_REGS; \ + \ + lw v0, 116(a0); \ + lw s2, 120(a0); \ + bne v0, zero, inst_error; \ + nop; \ + bne s2, zero, inst_error; \ + nop; \ + addiu s3, s3, 1; \ +inst_error: \ + sll t1, s0, 24; \ + or t0, t1, s3; \ + sw t0, 0(s1); \ + \ + jal wait_1s; \ + nop; \ + JUMP_TO_UNCACHED; diff --git a/resources/soft/func/inst/Makefile b/resources/soft/func/inst/Makefile index 336119c..f197eaf 100644 --- a/resources/soft/func/inst/Makefile +++ b/resources/soft/func/inst/Makefile @@ -1,7 +1,9 @@ -srcs = $(wildcard *.S) -objs = $(patsubst %.S, %.o, $(srcs)) +asm_srcs = $(wildcard *.S) +asm_objs = $(patsubst %.S, %.o, $(asm_srcs)) +c_srcs = $(wildcard *.c) +c_objs = $(patsubst %.c, %.o, $(c_srcs)) -$(TOPDIR)/libinst.a: $(objs) +$(TOPDIR)/libinst.a: $(asm_objs) $(c_objs) $(CROSS_COMPILE)$(AR) -cr $@ $? clean: diff --git a/resources/soft/func/inst/inst_test.h b/resources/soft/func/inst/inst_test.h index 9330971..c1502cc 100644 --- a/resources/soft/func/inst/inst_test.h +++ b/resources/soft/func/inst/inst_test.h @@ -1437,95 +1437,3 @@ nop; \ bne v1, s6, inst_error; \ nop - -/*CACHE instruction*/ - -// address and result stored in v0 -#define GET_ICACHE_INDEX \ - srl v0, v0, 5; \ - andi v0, v0, 0x3f; \ - nop - -#define GET_DCACHE_INDEX \ - srl v0, v0, 4; \ - andi v0, v0, 0x7f; \ - nop - -/*98*/ -/* - * addr1 : uncached - * addr2 : cached and mapped to addr1 - */ -#define TEST_CACHE_DCACHE_HIT(addr1, addr2, offset, data1, data2) \ - LI(t0, addr1); \ - LI(t1, addr2); \ - LI(t2, data1); \ - LI(t3, data2); \ - /* prepare -> hit writeback invalidate */ \ - sw t3, offset(t0); \ - sw t2, offset(t1); \ - cache 21, offset(t1); \ - lw a0, offset(t0); \ - bne t2, a0, inst_error; \ - nop; \ - lw a0, offset(t1); \ - bne t2, a0, inst_error; \ - nop; \ - /* test hit invalidate */ \ - sw t2, offset(t0); \ - sw t3, offset(t1); \ - cache 17, offset(t1); \ - lw a0, offset(t0); \ - bne a0, t2, inst_error; \ - nop; \ - lw a0, offset(t1); \ - bne a0, t2, inst_error; \ - nop; \ - /* test hit writeback invalidate */ \ - sw t3, offset(t1); \ - cache 21, offset(t1); \ - lw a0, offset(t0); \ - bne a0, t3, inst_error; \ - nop; \ - lw a0, offset(t1); \ - bne a0, t3, inst_error; \ - nop; \ - /* test multiple*/ \ - addi a1, t1, 4; \ - cache 17, offset(t1); \ - cache 17, offset(a1); \ - sw t2, offset(t1); \ - sw t3, offset(a1); \ - cache 21, offset(t1); \ - cache 21, offset(a1); \ - addi a1, t0, 4; \ - lw v0, offset(t0); \ - lw v1, offset(a1); \ - bne v0, t2, inst_error; \ - nop; \ - bne v1, t3, inst_error; \ - nop; \ - sw t3, offset(t0); \ - sw t2, offset(a1); \ - addi a1, t1, 4; \ - lw v0, offset(t1); \ - lw v1, offset(a1); \ - bne v0, t3, inst_error; \ - nop; \ - bne v1, t2, inst_error; \ - nop; \ - sw t2, offset(t1); \ - sw t3, offset(a1); \ - cache 17, offset(t1); \ - cache 17, offset(a1); \ - bne v0, t3, inst_error; \ - nop; \ - bne v1, t2, inst_error; \ - nop; \ - addi a1, t0, 4; \ - lw v0, offset(t0); \ - lw v1, offset(a1); \ - bne v0, t3, inst_error; \ - nop; \ - bne v1, t2, inst_error; \ - nop diff --git a/resources/soft/func/inst/n105_playground.c b/resources/soft/func/inst/n105_playground.c new file mode 100644 index 0000000..2ac8122 --- /dev/null +++ b/resources/soft/func/inst/n105_playground.c @@ -0,0 +1,164 @@ +#include "r4k_cache.h" + +extern void srand(unsigned short seed); +extern unsigned rand(); + +extern void puts(char *str); +extern void putstr(char *str); +extern void puthex(unsigned x); +extern void putchar(char ch); + +#define PREFIX "n105: " + +#define TEST(func) \ + do { \ + puts(PREFIX "start " #func); \ + if (func()) \ + return 1; \ + } while (0) + +int n105_playground_test_fib() __attribute__((optimize("O0"))); +int n105_playground_test_mem(); +int n105_playground_test_cache(); + +int n105_playground_test() { + TEST(n105_playground_test_cache); + TEST(n105_playground_test_fib); + TEST(n105_playground_test_mem); + return 0; +} + +int n105_playground_test_fib() { + volatile unsigned buf[1000]; + buf[0] = buf[1] = 1; + for (int i = 2; i < 1000; i++) + buf[i] = buf[i - 1] + buf[i - 2]; + putstr(PREFIX "buf[999]="), puthex(buf[999]), putchar('\n'); + return buf[999] != 0x5cc0604b; +} + +int n105_playground_test_mem() { + const unsigned len = 0x3ff; + volatile unsigned buf[len]; + + srand(0xACE1u); + for (unsigned i = 0; i < len; i++) + buf[i] = rand(); + + srand(0xACE1u); + for (unsigned i = 0; i < len; i++) { + unsigned rnd = rand(); + if (buf[i] != rnd) { + putstr(PREFIX "mem(#5): ERROR occured! expected: "); + puthex(rnd); + putstr(", but got: "); + puthex(buf[i]); + putstr(". ptr="); + puthex((unsigned)&buf[i]); + putstr(", i="); + puthex(i); + putchar('\n'); + + return 1; + } + } + + return 0; +} + +int n105_playground_test_cache() { + // blast_dcache_range: Hit_Writeback_Inv_D + + unsigned *uncached_bgn = (unsigned *)0xa4000000; + unsigned *uncached_end = (unsigned *)0xa4004000; + unsigned *cached_bgn = (unsigned *)0x84000000; + unsigned *cached_end = (unsigned *)0x84004000; + + // clear + puts(PREFIX "cache: clear"); + for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++) + *ptr = 0; + + // cache + puts(PREFIX "cache: blast clear"); + blast_dcache_range((unsigned)cached_bgn, (unsigned)(cached_end)); + + // check uncache clear + puts(PREFIX "cache: check uncache clear"); + for (volatile unsigned *ptr = uncached_bgn; ptr < uncached_end; ptr++) + if (*ptr != 0) { + putstr(PREFIX "cache(#1): ERROR occured! expected: 0, but got: "); + puthex(*ptr); + putstr(". ptr="); + puthex((unsigned)ptr); + putchar('\n'); + return 1; + } + + // check cache clear + puts(PREFIX "cache: check cache clear"); + for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++) + if (*ptr != 0) { + putstr(PREFIX "cache(#2): ERROR occured! expected: 0, but got: "); + puthex(*ptr); + putstr(". ptr="); + puthex((unsigned)ptr); + putchar('\n'); + return 1; + } + + // fill + puts(PREFIX "cache: fill cache"); + // srand(0xACE1u); + // for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++) + // *ptr = rand(); + unsigned counter = 0; + for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++) + *ptr = ++counter; + + // blast fill + puts(PREFIX "cache: blast fill"); + blast_dcache_range((unsigned)cached_bgn, (unsigned)(cached_end)); + + // check uncache + puts(PREFIX "cache: check uncache"); + // srand(0xACE1u); + counter = 0; + for (volatile unsigned *ptr = uncached_bgn; ptr < uncached_end; ptr++) { + // unsigned rnd = rand(); + unsigned rnd = ++counter; + if (*ptr != rnd) { + putstr(PREFIX "cache(#3): ERROR occured! expected: "); + puthex(rnd); + putstr(", but got: "); + puthex(*ptr); + putstr(". ptr="); + puthex((unsigned)ptr); + putchar('\n'); + + return 1; + } + } + + // check cache + puts(PREFIX "cache: check cache"); + // srand(0xACE1u); + counter = 0; + for (volatile unsigned *ptr = cached_bgn; ptr < cached_end; ptr++) { + // unsigned rnd = rand(); + unsigned rnd = ++counter; + if (*ptr != rnd) { + putstr(PREFIX "cache(#4): ERROR occured! expected: "); + puthex(rnd); + putstr(", but got: "); + puthex(*ptr); + putstr(". ptr="); + puthex((unsigned)ptr); + putchar('\n'); + + return 1; + } + } + + return 0; +} diff --git a/resources/soft/func/inst/n98_cache_dcache.S b/resources/soft/func/inst/n98_cache_dcache.S index 2cfb3c4..b5ff142 100644 --- a/resources/soft/func/inst/n98_cache_dcache.S +++ b/resources/soft/func/inst/n98_cache_dcache.S @@ -2,6 +2,91 @@ #include #include +#define GET_DCACHE_INDEX \ + srl v0, v0, 4; \ + andi v0, v0, 0x7f; \ + nop + +/*98*/ +/* + * addr1 : uncached + * addr2 : cached and mapped to addr1 + */ +#define TEST_CACHE_DCACHE_HIT(addr1, addr2, offset, data1, data2) \ + LI(t0, addr1); \ + LI(t1, addr2); \ + LI(t2, data1); \ + LI(t3, data2); \ + /* prepare -> hit writeback invalidate */ \ + sw t3, offset(t0); \ + sw t2, offset(t1); \ + cache 21, offset(t1); \ + lw a0, offset(t0); \ + bne t2, a0, inst_error; \ + nop; \ + lw a0, offset(t1); \ + bne t2, a0, inst_error; \ + nop; \ + /* test hit invalidate */ \ + sw t2, offset(t0); \ + sw t3, offset(t1); \ + cache 17, offset(t1); \ + lw a0, offset(t0); \ + bne a0, t2, inst_error; \ + nop; \ + lw a0, offset(t1); \ + bne a0, t2, inst_error; \ + nop; \ + /* test hit writeback invalidate */ \ + sw t3, offset(t1); \ + cache 21, offset(t1); \ + lw a0, offset(t0); \ + bne a0, t3, inst_error; \ + nop; \ + lw a0, offset(t1); \ + bne a0, t3, inst_error; \ + nop; \ + /* test multiple*/ \ + addi a1, t1, 4; \ + cache 17, offset(t1); \ + cache 17, offset(a1); \ + sw t2, offset(t1); \ + sw t3, offset(a1); \ + cache 21, offset(t1); \ + cache 21, offset(a1); \ + addi a1, t0, 4; \ + lw v0, offset(t0); \ + lw v1, offset(a1); \ + bne v0, t2, inst_error; \ + nop; \ + bne v1, t3, inst_error; \ + nop; \ + sw t3, offset(t0); \ + sw t2, offset(a1); \ + addi a1, t1, 4; \ + lw v0, offset(t1); \ + lw v1, offset(a1); \ + bne v0, t3, inst_error; \ + nop; \ + bne v1, t2, inst_error; \ + nop; \ + sw t2, offset(t1); \ + sw t3, offset(a1); \ + cache 17, offset(t1); \ + cache 17, offset(a1); \ + bne v0, t3, inst_error; \ + nop; \ + bne v1, t2, inst_error; \ + nop; \ + addi a1, t0, 4; \ + lw v0, offset(t0); \ + lw v1, offset(a1); \ + bne v0, t3, inst_error; \ + nop; \ + bne v1, t2, inst_error; \ + nop + + LEAF(n98_cache_dcache_test) .set noreorder addiu s0, s0 ,1 diff --git a/resources/soft/func/inst/n99_cache_icache.S b/resources/soft/func/inst/n99_cache_icache.S index 3654bf6..d0da1ed 100644 --- a/resources/soft/func/inst/n99_cache_icache.S +++ b/resources/soft/func/inst/n99_cache_icache.S @@ -2,6 +2,12 @@ #include #include +// address and result stored in v0 +#define GET_ICACHE_INDEX \ + srl v0, v0, 5; \ + andi v0, v0, 0x3f; \ + nop + LEAF(n99_cache_icache_test) .set noreorder addiu s0, s0 ,1 diff --git a/resources/soft/func/inst/utils.c b/resources/soft/func/inst/utils.c new file mode 100644 index 0000000..c940d98 --- /dev/null +++ b/resources/soft/func/inst/utils.c @@ -0,0 +1,180 @@ +#include "r4k_cache.h" + +// 0x80000000 - 0x8000007c saved reg +// 0x8000007c lfsr +// 0x80000100 - 0x80004100.data +// 0x88000000 sp +// 0x84000000 - random + +#define MAKE_ERR \ + do { \ + *(unsigned *)(0) = 0; \ + } while (0) + +void putchar(char ch) { + volatile char *virt_addr = (char *)0xbfaffff0; + *virt_addr = ch; +} + +void putstr(char *str) { + while (*str) + putchar(*str++); +} + +void puthex(unsigned x) { + char buf[11]; + char *num = &buf[2]; + unsigned mask = 0xf; + for (int i = 0; i < 8; i++) { + num[7 - i] = "0123456789ABCDEF"[x & mask]; + x >>= 4; + } + buf[0] = '0', buf[1] = 'x', buf[10] = 0; + putstr(buf); +} + +void puts(char *str) { + putstr(str); + putchar('\n'); +} + +unsigned long __ffs(unsigned long word) { + int num = 0; + + if ((word & 0xffff) == 0) { + num += 16; + word >>= 16; + } + if ((word & 0xff) == 0) { + num += 8; + word >>= 8; + } + if ((word & 0xf) == 0) { + num += 4; + word >>= 4; + } + if ((word & 0x3) == 0) { + num += 2; + word >>= 2; + } + if ((word & 0x1) == 0) + num += 1; + return num; +} + +#define ___read_32bit_c0_register(source, sel, vol) \ + ({ \ + unsigned int __res; \ + if (sel == 0) \ + __asm__ vol("mfc0\t%0, " #source "\n\t" : "=r"(__res)); \ + else \ + __asm__ vol(".set\tpush\n\t" \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tpop\n\t" \ + : "=r"(__res)); \ + __res; \ + }) + +#define __read_32bit_c0_register(source, sel) ___read_32bit_c0_register(source, sel, __volatile__) +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) + +struct cpuinfo_mips current_cpu_data; + +void probe_pcache(void) { + unsigned long icache_size; + unsigned long dcache_size; + + struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int config = read_c0_config(); + unsigned long config1; + unsigned int lsize; + + puts("init: probing cache"); + + config1 = read_c0_config1(); + + lsize = (config1 >> 19) & 7; + + /* IL == 7 is reserved */ + if (lsize == 7) { + puts("init: Invalid icache line size"); + MAKE_ERR; + return; + } + + c->icache.linesz = lsize ? 2 << lsize : 0; + + c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + + icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; + c->icache.waybit = __ffs(icache_size / c->icache.ways); + + lsize = (config1 >> 10) & 7; + + /* DL == 7 is reserved */ + if (lsize == 7) { + puts("Invalid dcache line size"); + MAKE_ERR; + return; + } + + c->dcache.linesz = lsize ? 2 << lsize : 0; + + c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); + c->dcache.ways = 1 + ((config1 >> 7) & 7); + + dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; + c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); + + /* compute a couple of other cache variables */ + c->icache.waysize = icache_size / c->icache.ways; + c->dcache.waysize = dcache_size / c->dcache.ways; + + c->icache.sets = c->icache.linesz ? icache_size / (c->icache.linesz * c->icache.ways) : 0; + c->dcache.sets = c->dcache.linesz ? dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; + + putstr("init: icache: "), puthex(icache_size >> 10), putstr("kB, linesz="), puthex(c->icache.linesz), + putstr(", ways="), puthex(c->icache.ways), putstr(", waysize="), puthex(c->icache.waysize), putstr(", waybit="), + puthex(c->icache.waybit), putstr(", sets="), puthex(c->icache.sets), putchar('\n'); + putstr("init: dcache: "), puthex(dcache_size >> 10), putstr("kB, linesz="), puthex(c->dcache.linesz), + putstr(", ways="), puthex(c->dcache.ways), putstr(", waysize="), puthex(c->dcache.waysize), putstr(", waybit="), + puthex(c->dcache.waybit), putstr(", sets="), puthex(c->dcache.sets), putchar('\n'); + // pr_info("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n", icache_size >> 10, + // c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", way_string[c->icache.ways], c->icache.linesz); + + // pr_info("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n", dcache_size >> 10, + // way_string[c->dcache.ways], + // (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", + // (c->dcache.flags & MIPS_CACHE_ALIASES) ? "cache aliases" : "no aliases", c->dcache.linesz); +} + +void srand(unsigned short seed) { + volatile unsigned short *lfsr = (unsigned short *)0x8000007c; + *lfsr = seed; +} + +inline unsigned rand16() { + volatile unsigned short *lfsr = (unsigned short *)0x8000007c; + unsigned prv = *lfsr; + + unsigned bit = ((prv >> 0) ^ (prv >> 2) ^ (prv >> 3) ^ (prv >> 5)) & 1; + *lfsr = (prv >> 1) | (bit << 15); + + return *lfsr; +} + +unsigned rand() { return (rand16() << 16) | rand16(); } + +void init_crt() { + // moved to start.S + // register volatile unsigned sp asm("sp"); + // sp = 0x88000000; + + srand(0xACE1u); + probe_pcache(); + + puts("init: crt inited"); +} diff --git a/resources/soft/func/start.S b/resources/soft/func/start.S index c099f98..fc7ddb7 100644 --- a/resources/soft/func/start.S +++ b/resources/soft/func/start.S @@ -4,7 +4,7 @@ #include -#define TEST_NUM 156 +#define TEST_NUM 155 ##s0, number @@ -309,7 +309,12 @@ locate: lui s0, 0 ## initial run number inst_test: - TEST_UNIT_CACHE(n104_linux) + lui sp, 0x8800 + jal init_crt + nop + + + TEST_C_ENV(n105_playground_test) # 155 TEST_UNIT_CACHE(n1_lui_test) # 1 2 TEST_UNIT_CACHE(n2_addu_test) @@ -419,6 +424,8 @@ inst_test: TEST_UNIT_CACHE(n96_maddu_test) TEST_UNIT_CACHE(n97_msub_msubu_test) + TEST_UNIT(n98_cache_dcache_test) # 146 + TEST_UNIT_ONLY_CACHE(n99_cache_icache_test) TEST_UNIT_CACHE(n100_movz_movn_test) # 148 149 @@ -428,8 +435,8 @@ inst_test: TEST_UNIT_ONLY_CACHE(n103_memory1_test) # 153 - TEST_UNIT(n98_cache_dcache_test) # 146 - TEST_UNIT_ONLY_CACHE(n99_cache_icache_test) + TEST_UNIT_CACHE(n104_linux) # 154 + ###check io access LI (a0, IO_SIMU_ADDR) diff --git a/resources/test_vivado.sv b/resources/test_vivado.sv index af99c24..72a41a7 100644 --- a/resources/test_vivado.sv +++ b/resources/test_vivado.sv @@ -13,12 +13,6 @@ module testbench_top (); logic clk; //gpio - logic [15:0] led; - logic [ 1:0] led_rg0; - logic [ 1:0] led_rg1; - logic [ 7:0] num_csn; - logic [ 6:0] num_a_g; - logic [ 7:0] switch; logic [ 3:0] btn_key_col; logic [ 3:0] btn_key_row; logic [ 1:0] btn_step; @@ -28,7 +22,7 @@ module testbench_top (); logic [31:0] confreg_num_reg; logic [31:0] confreg_num_reg_r; - assign switch = 8'hff; + assign switch_sim = 8'hff; assign btn_key_row = 4'd0; assign btn_step = 2'd3; assign uart_display = `CONFREG_UART_DISPLAY; @@ -36,8 +30,6 @@ module testbench_top (); assign confreg_num_reg = `CONFREG_NUM_REG; // soc clk & debug info - logic cpu_clk; - logic sys_clk; logic [31:0] debug_wb_pc; logic [ 3:0] debug_wb_rf_wen; logic [ 4:0] debug_wb_rf_wnum; @@ -47,16 +39,14 @@ module testbench_top (); logic [ 4:0] debug_wb1_rf_wnum; logic [31:0] debug_wb1_rf_wdata; logic debug_wb_pc_A; - logic dbg_0_rf_wen; + logic [ 3:0] dbg_0_rf_wen; logic [31:0] dbg_0_pc; logic [ 4:0] dbg_0_rf_wnum; logic [31:0] dbg_0_rf_wdata; - logic dbg_1_rf_wen; + logic [ 3:0] dbg_1_rf_wen; logic [31:0] dbg_1_pc; logic [ 4:0] dbg_1_rf_wnum; logic [31:0] dbg_1_rf_wdata; - assign cpu_clk = soc_lite.cpu_clk; - assign sys_clk = soc_lite.sys_clk; assign debug_wb_pc = soc_lite.debug_wb_pc; assign debug_wb_rf_wen = soc_lite.debug_wb_rf_wen; assign debug_wb_rf_wnum = soc_lite.debug_wb_rf_wnum; @@ -67,7 +57,7 @@ module testbench_top (); assign debug_wb1_rf_wdata = soc_lite.u_cpu.debug_wb1_rf_wdata; assign debug_wb_pc_A = soc_lite.u_cpu.debug_wb_pc_A; - always @(posedge cpu_clk) begin + always @(posedge clk) begin if (debug_wb_pc_A) begin dbg_0_rf_wen <= debug_wb1_rf_wen; dbg_0_pc <= debug_wb1_pc; @@ -89,19 +79,19 @@ module testbench_top (); dbg_0_rf_wnum <= debug_wb_rf_wnum; dbg_0_rf_wdata <= debug_wb_rf_wdata; end - -// if (|dbg_0_rf_wen) begin -// $display("path0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d", -// dbg_0_pc, dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen); -// end -// if (|dbg_1_rf_wen) begin -// $display("path1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d", -// dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen); -// end + + //if (|dbg_0_rf_wen & resetn) begin + // $display("path0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d", + // dbg_0_pc, dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen); + //end + //if (|dbg_1_rf_wen & resetn) begin + // $display("path1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d", + // dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen); + //end end // UART - always @(posedge sys_clk) begin + always @(posedge clk) begin if (uart_display) begin if (uart_data == 8'hff) begin ; //$finish; @@ -113,7 +103,7 @@ module testbench_top (); // Numeric Display logic [7:0] err_count; - always_ff @(posedge sys_clk) begin + always_ff @(posedge clk) begin confreg_num_reg_r <= confreg_num_reg; if (!resetn) begin err_count <= 8'd0; @@ -123,11 +113,13 @@ module testbench_top (); $display("[%t] Error(%d)! Occurred in number 8'd%02d Functional Test Point!", $time, err_count, confreg_num_reg[31:24]); $display("--------------------------------------------------------------"); err_count <= err_count + 1'b1; + $finish; end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin $display("--------------------------------------------------------------"); $display("[%t] Error(%d)! Unknown, Functional Test Point numbers are unequal!", $time, err_count); $display("--------------------------------------------------------------"); err_count <= err_count + 1'b1; + $finish; end else begin $display("----[%t] Number 8'd%02d Functional Test Point PASS!", $time, confreg_num_reg[31:24]); end @@ -137,7 +129,7 @@ module testbench_top (); //test end logic test_end; assign test_end = (dbg_0_pc == `END_PC) || (dbg_1_pc == `END_PC) || (uart_display && uart_data == 8'hff); - always @(posedge cpu_clk) + always @(posedge clk) if (test_end) begin if (err_count != 0) begin $display(""); @@ -163,7 +155,7 @@ module testbench_top (); .led (led), .led_rg0 (led_rg0), .led_rg1 (led_rg1), - .switch (switch), + .switch (switch_sim), .btn_key_col(btn_key_col), .btn_key_row(btn_key_row), .btn_step (btn_step) @@ -171,7 +163,7 @@ module testbench_top (); initial begin resetn = 1'b0; - #2000; + #200; resetn = 1'b1; end diff --git a/sim/.gitignore b/sim/.gitignore index f0ca1dc..75732cc 100644 --- a/sim/.gitignore +++ b/sim/.gitignore @@ -2,3 +2,5 @@ /logs *.gtkw *.mif +nohup.out +logs.txt diff --git a/sim/Makefile b/sim/Makefile index 6ca0302..07fd816 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -24,7 +24,9 @@ VERILATOR_BUILD_FLAGS += --assert # Generate coverage analysis VERILATOR_BUILD_FLAGS += --coverage # Run make to compile model, with as many CPUs as are free -VERILATOR_BUILD_FLAGS += --compiler clang -CFLAGS "-Wno-parentheses-equality" -j +VERILATOR_BUILD_FLAGS += -CFLAGS "-Wno-parentheses-equality" -j +# Report UNOPTFLAT +VERILATOR_BUILD_FLAGS += --report-unoptflat # Simulation Defines VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC @@ -52,7 +54,7 @@ FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resour #################### .phony: lint verilate func_soft tlb_soft build coverage run clean -default: run +default: build lint: $(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top @@ -61,13 +63,13 @@ verilate: $(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT) func_soft: - cd ../resources/soft/func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim + cd ../resources/soft/func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim tlb_soft: - cd ../resources/soft/tlb_func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim + cd ../resources/soft/tlb_func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim build: verilate - make -C obj_dir -f Vtestbench_top.mk -j + make -C obj_dir -f Vtestbench_top.mk -j 10 coverage: @rm -rf logs/annotated @@ -76,7 +78,7 @@ coverage: run: build @rm -rf logs obj_dir/Vtestbench_top - gtkwave logs/trace.fst + # gtkwave logs/trace.fst clean: -rm -rf obj_dir logs diff --git a/sim/config.vlt b/sim/config.vlt index 25e137a..2bf0d5d 100644 --- a/sim/config.vlt +++ b/sim/config.vlt @@ -1,13 +1,16 @@ `verilator_config lint_off -rule TIMESCALEMOD lint_off -rule DECLFILENAME -lint_off -rule INITIALDLY +lint_off -rule UNUSEDSIGNAL lint_off -file "model/*.v" lint_off -file "../resources/func_test/*.v" -lint_off -rule UNOPTFLAT -file "model/axi_crossbar_addr.v" -lint_off -rule UNOPTFLAT -file "model/priority_encoder.v" +lint_off -rule UNOPTFLAT -file "model/axi_crossbar_addr.v" +lint_off -rule UNOPTFLAT -file "model/priority_encoder.v" +lint_off -rule INITIALDLY -file "model/axi_crossbar_addr.v" lint_off -rule BLKSEQ -file "../src/CP0/CP0.sv" -lint_off -rule UNOPTFLAT -file "../src/Core/Datapath.sv" -lint_off -rule UNOPTFLAT -file "../src/Gadgets/mux3.sv" + +//lint_off -rule UNOPTFLAT -file "../src/Core/Datapath.sv" +//lint_off -rule UNOPTFLAT -file "../src/Gadgets/mux3.sv" +//lint_off -rule UNOPTFLAT -file "../src/Core/Controller.sv" diff --git a/sim/model/axi_crossbar.v b/sim/model/axi_crossbar.v index 314be3d..6b72acc 100644 --- a/sim/model/axi_crossbar.v +++ b/sim/model/axi_crossbar.v @@ -77,7 +77,7 @@ module axi_crossbar # parameter M_BASE_ADDR = {{32'h1fc00000, 32'h20000000, 32'h40000000, 32'h80000000, 32'h0}, {32'h1faf0000, 32'hffffffff, 32'hffffffff, 32'hffffffff, 32'hffffffff}}, // Master interface address widths // M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits - parameter M_ADDR_WIDTH = {{32'd22, 32'd29, 32'd30, 32'd31, 32'd28}, {32'd16, 32'd0, 32'd0, 32'd0, 32'd0}}, //{M_COUNT{{M_REGIONS{32'd24}}}}, + parameter M_ADDR_WIDTH = {{32'd22, 32'd29, 32'd30, 32'd28, 32'd28}, {32'd16, 32'd0, 32'd0, 32'd0, 32'd0}}, //{M_COUNT{{M_REGIONS{32'd24}}}}, // Read connections between interfaces // M_COUNT concatenated fields of S_COUNT bits parameter M_CONNECT_READ = {M_COUNT{{S_COUNT{1'b1}}}}, diff --git a/sim/model/axi_ram.v b/sim/model/axi_ram.v index 64e1b10..f9b999d 100644 --- a/sim/model/axi_ram.v +++ b/sim/model/axi_ram.v @@ -31,7 +31,7 @@ module axi_ram # // Width of data bus in bits parameter DATA_WIDTH = 32, // Width of address bus in bits - parameter ADDR_WIDTH = 20, + parameter ADDR_WIDTH = 28, // Width of wstrb (width of data bus in words) parameter STRB_WIDTH = (DATA_WIDTH/8), // Width of ID signal @@ -135,9 +135,36 @@ reg s_axi_rvalid_pipe_reg = 1'b0; // (* RAM_STYLE="BLOCK" *) reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0]; initial begin - $display("[%0t] Loading ram.mif", $time); - $readmemb("axi_ram.mif", mem); - $display("[%0t] ram.mif[0] = 0x%0h", $time, mem[0]); + // ADDR_WIDTH = 28 + // (28 - 4) + // | + // v + // 1ff0_0000: 0001 1111 1111 0000 0000 0000 0000 0000 -> 0x3fc0000 + // bfc0_0000: 1011 1111 1100 0000 0000 0000 0000 0000 -> 0x3f00000 + // 1fc0_0000: 0001 1111 1100 0000 0000 0000 0000 0000 -> 0x3f00000 + // 9fc0_0000: 1001 1111 1100 0000 0000 0000 0000 0000 -> 0x3f00000 + // 8800_0000: 1000 1000 0000 0000 0000 0000 0000 0000 -> 0x2000000 + // 8000_0000: 1000 0000 0000 0000 0000 0000 0000 0000 -> 0x0000000 + // |------------------------------| + + $display("[%0t] Loading inst_ram.mif", $time); + $readmemb("inst_ram.mif", mem, 'h3f00000); + + $display("[%0t] Loading data_ram.mif", $time); + $readmemb("data_ram.mif", mem, 'h40); + + $display("[%0t] ram[0x3f00000] = 0x%0h", $time, mem['h3f00000]); + $display("[%0t] ram[0x3f00001] = 0x%0h", $time, mem['h3f00001]); + $display("[%0t] ram[0x3f00002] = 0x%0h", $time, mem['h3f00002]); + $display("[%0t] ram[0x40] = 0x%0h", $time, mem['h40]); +end + +reg [31:0] trace_before = 0; +always @(posedge s_aclk) begin + if (mem['h1000000] != trace_before) begin + trace_before <= mem['h1000000]; + $display("[%0t] ram['h1000000] = 0x%0h, before = 0x%0h", $time, mem['h1000000], trace_before); + end end wire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH); diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index 5245a60..45003d3 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -1015,6 +1015,12 @@ module Datapath ( : cache_op.op.dcache_op ? {E_I1_ADDR[32-`DC_INDEXL-1:0], `DC_INDEXL'b0} : {E_I1_ADDR[32-`IC_INDEXL-1:0], `IC_INDEXL'b0}; + always_ff @(posedge clk) begin + if (cache_op.req) begin + $display("<< dp index_or_hit=%0h writeback=%0h addr=0x%0h >>", cache_op.op.index_or_hit, cache_op.op.writeback, cache_op.addr); + end + end + assign E.en = E_go & M.en; assign E_go = (~mem.req | mem.addr_ok) & (~cache_op.req | cache_op.addr_ok); diff --git a/src/IP/div_signed/div_signed.xci b/src/IP/div_signed/div_signed.xci index 92d1caa..876585a 100644 --- a/src/IP/div_signed/div_signed.xci +++ b/src/IP/div_signed/div_signed.xci @@ -1,289 +1,208 @@ - - - xilinx.com - xci - unknown - 1.0 - - - div_signed - - - - - 1000000 - 0 - 0 - 0.0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.0 - 8 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.0 - 4 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.0 - 4 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 16 - 64 - 1 - 32 - 1 - 32 - 1 - 3 - 0 - artix7 - 1 - 32 - 32 - 0 - 32 - 1 - false - false - div_signed - NonBlocking - Performance - Null - false - Radix2 - 1 - false - 32 - false - false - 1 - false - false - 1 - 32 - 32 - 16 - Manual - Signed - Remainder - artix7 - - - xc7a200t - fbg676 - VERILOG - - MIXED - -2 - - - TRUE - TRUE - IP_Flow - 19 - TRUE - . - - . - 2022.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "div_signed", + "component_reference": "xilinx.com:ip:div_gen:5.1", + "ip_revision": "19", + "gen_directory": ".", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "div_signed", "resolve_type": "user", "usage": "all" } ], + "algorithm_type": [ { "value": "Radix2", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "dividend_and_quotient_width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "dividend_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "dividend_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "dividend_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "divisor_width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "divisor_has_tuser": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "divisor_tuser_width": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "divisor_has_tlast": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "remainder_type": [ { "value": "Remainder", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "fractional_width": [ { "value": "32", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "operand_sign": [ { "value": "Signed", "resolve_type": "user", "usage": "all" } ], + "clocks_per_division": [ { "value": "1", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "divide_by_zero_detect": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "FlowControl": [ { "value": "NonBlocking", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "OptimizeGoal": [ { "value": "Performance", "resolve_type": "user", "usage": "all" } ], + "OutTready": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "OutTLASTBehv": [ { "value": "Null", "resolve_type": "user", "usage": "all" } ], + "latency_configuration": [ { "value": "Manual", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "latency": [ { "value": "16", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ACLKEN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "ARESETN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ] + }, + "model_parameters": { + "C_XDEVICEFAMILY": [ { "value": "artix7", "resolve_type": "generated", "usage": "all" } ], + "C_HAS_ARESETN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_ACLKEN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_LATENCY": [ { "value": "16", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "ALGORITHM_TYPE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DIVISOR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DIVIDEND_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SIGNED_B": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "DIVCLK_SEL": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRACTIONAL_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "FRACTIONAL_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_DIV_BY_ZERO": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_THROTTLE_SCHEME": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_TLAST_RESOLUTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_S_AXIS_DIVISOR_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_S_AXIS_DIVISOR_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXIS_DIVISOR_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXIS_DIVISOR_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_S_AXIS_DIVIDEND_TUSER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_HAS_S_AXIS_DIVIDEND_TLAST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXIS_DIVIDEND_TDATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXIS_DIVIDEND_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_M_AXIS_DOUT_TDATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_M_AXIS_DOUT_TUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "artix7" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7a200t" } ], + "PACKAGE": [ { "value": "fbg676" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Flow" } ], + "IPREVISION": [ { "value": "19" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "." } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "." } ], + "SWVERSION": [ { "value": "2022.2" } ], + "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] + } + }, + "boundary": { + "ports": { + "aclk": [ { "direction": "in", "driver_value": "0x1" } ], + "s_axis_divisor_tvalid": [ { "direction": "in", "driver_value": "0x0" } ], + "s_axis_divisor_tdata": [ { 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file diff --git a/src/MU/DCache.sv b/src/MU/DCache.sv index 84ddf2b..5a4a971 100644 --- a/src/MU/DCache.sv +++ b/src/MU/DCache.sv @@ -34,10 +34,10 @@ module DCache ( DCTag_t tag[`DC_WAYS]; DCData_t data[`DC_WAYS]; - logic [`DC_WAYS-1:0] hitway; - logic [`DC_WAYS-1:0] victim; - DCTagL_t dirt_tag; - logic [`DC_WAYS-1:0] wen; + logic [`DC_WAYS-1:0] hitway/*verilator split_var*/; + logic [`DC_WAYS-1:0] victim/*verilator split_var*/; + DCTagL_t dirt_tag/*verilator split_var*/; + logic [`DC_WAYS-1:0] wen/*verilator split_var*/; // ============================== @@ -153,6 +153,27 @@ module DCache ( end + logic [31:0] magic_counter = 0; + always_ff @(posedge clk) magic_counter <= magic_counter + 1; + + // 0x04000000 + // 0000 0100 0000 0000 0000 0000 0000 0000 + // tag = 0x04000 + // index = 0 + // offset = 0 + for (genvar i = 0; i < `DC_WAYS; i++) + always_ff @(posedge clk) begin + if (TagRAM[i].wen) begin + if (TagRAM[i].addr == 0 && TagRAM[i].wdata.tag[19:4] == 'h0400) begin + $display("<< counter=0x%0h way=0x%0h tag=0x%0h index=0x%0h addr=0x%0h dirty=0x%0h valid=0x%0h data=0x%0h read_and_hit=%0h read_but_replace=%0h write_and_hit=%0h write_but_replace=%0h cache_index_invalidate=%0h cache_index_writeback=%0h cache_hit_invalidate=%0h cache_hit_writeback=%0h >>", + magic_counter, i, TagRAM[i].wdata.tag, TagRAM[i].addr, {TagRAM[i].wdata.tag, TagRAM[i].addr, `DC_INDEXL'b0}, + TagRAM[i].wdata.dirty, TagRAM[i].wdata.valid, DataRAM[i].wdata, + port.ctrl.read_and_hit, port.ctrl.read_but_replace, port.ctrl.write_and_hit, port.ctrl.write_but_replace, port.ctrl.cache_index_invalidate, port.ctrl.cache_index_writeback, port.ctrl.cache_hit_invalidate, port.ctrl.cache_hit_writeback + ); + end + end + end + // BRAM 实例 for (genvar i = 0; i < `DC_WAYS; i++) begin : dbram bram #(.DATA_WIDTH(32-`DC_TAGL+2), .DATA_DEPTH(2 ** (`DC_TAGL-`DC_INDEXL))) diff --git a/src/MU/MU.sv b/src/MU/MU.sv index a9d55d6..bc3d30a 100644 --- a/src/MU/MU.sv +++ b/src/MU/MU.sv @@ -358,7 +358,8 @@ module MU ( : mem_rdata_source_data[{stored_memory_addr[`DC_INDEXL-1:2], 5'b0}+:32]; logic mem_wstrb_direct; - DCData_t mem_wdata_source_data, mem_wdata_output; + DCData_t mem_wdata_source_data/*verilator split_var*/; + DCData_t mem_wdata_output; word_t mem_wdata_data; logic [`DC_INDEXL-3:0] base; assign base = stored_memory_addr[`DC_INDEXL-1:2]; @@ -375,6 +376,9 @@ module MU ( // == Memory Control State Machine == // ================================== + logic [31:0] wb_magic_counter = 0; + always_ff @(posedge clk) wb_magic_counter <= wb_magic_counter + 1; + typedef enum bit [1:0] { MEM_LOOKUP, MEM_READ, @@ -434,7 +438,6 @@ module MU ( dcache.index_for_lookup = cacheop.addr[`DC_TAGL-1:`DC_INDEXL]; end else if (~memory_valid) begin in_mem_ready = 1; - end else if (mem_req & memory_cached & dcache.hit) begin // Cached + Hit if (~memory.wr) begin @@ -612,6 +615,9 @@ module MU ( dcache.ctrl.cache_hit_writeback = stored_cacheop_op.index_or_hit; if (dcache.dirt) begin + $display("<< wb: cnt=0x%0h op.hit=%0h dc.hit=%0h dc.index=%0h dc.tag=%0h dc.dirt=%0h dc.dirt_addr=0x%0h dc.data=%0h >>", + wb_magic_counter, stored_cacheop_op.index_or_hit, dcache.hit, dcache.index, dcache.tag, dcache.dirt, dcache.dirt_addr, dcache.dirt_row); + mem_nxt_state = MEM_WRITE; amw_call = 1'b1; diff --git a/src/include/defines.svh b/src/include/defines.svh index 8685a79..f17de42 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -12,6 +12,7 @@ `ifdef SIMULATION_VERILATOR `undef ENABLE_CpU + `undef ILA_DEBUG `endif `ifndef ENABLE_CACHEOP