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1. tlb: add soft

Browse Source 
2. datapath OFA fix2
3. datapath C0 hazard
4. MMU buffer

Co-authored-by: cxy004 <cxy004@qq.com>
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
This commit is contained in:
Paul Pan 2021-08-12 21:38:30 +08:00
parent d923ba69c5
commit 22e469ceec
27 changed files with 1849 additions and 112 deletions
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63
resources/2021/soft/tlb_func/Makefile Normal file
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TOPDIR=$(shell pwd)
#export LD_PRELOAD =
CFLAGS := -D_KERNEL -fno-builtin -mips1 -DMEMSTART=0x80000000 -DMEMSIZE=0x04000 -DCPU_COUNT_PER_US=1000 -I $(TOPDIR)/include
CFLAGS += -fno-reorder-blocks -fno-reorder-functions
OBJDIR = ./obj
export TOPDIR AR CFLAGS
export CROSS_COMPILE ?= mipsel-linux-gnu-
all:
make compile
compile:main.bin main.data convert
./convert
mkdir -p $(OBJDIR)
mv main.elf $(OBJDIR)/.
mv test.s $(OBJDIR)/.
mv main.bin $(OBJDIR)/.
mv main.data $(OBJDIR)/.
mv *.coe $(OBJDIR)/.
mv *.mif $(OBJDIR)/.
cp $(OBJDIR)/inst_ram.mif $(OBJDIR)/axi_ram.mif
main.bin:main.elf
${CROSS_COMPILE}objcopy -O binary -j .text $< $@
main.data:main.elf
${CROSS_COMPILE}objcopy -O binary -j .data $< $@
main.elf: start.o libinst.a
${CROSS_COMPILE}gcc -E -P -Umips -D_LOADER -U_MAIN $(CFLAGS) bin.lds.S -o bin.lds
${CROSS_COMPILE}ld -g -T bin.lds -o $@ start.o -L . -linst
${CROSS_COMPILE}objdump -alD $@ > test.s
libinst.a:
make -C inst $(TOPDIR)/$@
convert:convert.c
gcc $(ALIGNED) -o convert convert.c
clean:
rm -f *.o *.a
rm -rf obj
make -C inst clean
reset:
make clean
rm -f bin.lds convert
help:
@echo "################################################################"
@echo "### help for compiling func"
@echo "################################################################"
@echo "### options:"
@echo "### make : get compiled result, which is saved in ./obj"
@echo "### make clean: remove *.o, *.a, and ./obj"
@echo "### make reset: "make clean" and remove convert, bin.lds"
@echo "### make help : show help information"
@echo "###############################################################"
-include rules.make

2
resources/2021/soft/tlb_func/README.txt Normal file
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本目录包括了tlb测试程序的所有代码。
查看帮助信息，请linux命令行下输入make help。

91
resources/2021/soft/tlb_func/bin.lds.S Normal file
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OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = 0xbfc00000;
.text :
{
_ftext = . ;
*(.text)
*(.rodata*)
*(.reginfo)
*(.init)
*(.stub)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
rodata_end = .;
} =0
_etext = .;
PROVIDE (etext = .);
.fini : { *(.fini) } =0
. = MEMSTART;
.data : AT(rodata_end)
{
_fdata = . ;
_stack = _fdata + MEMSIZE -32;
*(.data)
*(.data*)
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
*(.ctors)
LONG(0)
__CTOR_END__ = .;
__DTOR_LIST__ = .;
LONG((__DTOR_END__ - __DTOR_LIST__) / 4 - 2)
*(.dtors)
LONG(0)
__DTOR_END__ = .;
_gp = ALIGN(16) + 0x7ff0;
*(.got.plt) *(.got)
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
*(.sdata)
*(.lit8)
*(.lit4)
}
_edata = .;
PROVIDE (edata = .);
data_size = SIZEOF(.data);
data_load_start = LOADADDR(.data);
__bss_start = .;
_fbss = .;
.sbss : { *(.sbss) *(.scommon) }
.bss :
{
*(.dynbss)
*(.bss)
*(COMMON)
}
. = ALIGN(8);
_end = . ;
PROVIDE (end = .);
. = ALIGN(32);
.bigdata : { *(.bigdata) }
. = ALIGN(256);
_heap = . ;
/* These are needed for ELF backends which have not yet been
converted to the new style linker. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
/* DWARF debug sections.
Symbols in the .debug DWARF section are relative to the beginning of the
section so we begin .debug at 0. It's not clear yet what needs to happen
for the others. */
.debug 0 : { *(.debug) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.line 0 : { *(.line) }
/* These must appear regardless of . */
.gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
.gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
.MIPS.abiflags : { *(.MIPS.abiflags) } =0
}

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resources/2021/soft/tlb_func/convert.c Normal file
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#include <stdio.h>
#include <stdlib.h>
void binary_out(FILE* out,unsigned char* mem)
{
char tmp;
unsigned char num[8];
num[0] = 1;
num[1] = 2;
num[2] = 4;
num[3] = 8;
num[4] = 16;
num[5] = 32;
num[6] = 64;
num[7] = 128;
for(int i=3;i>=0;i--)
{
for(int j=7;j>=0;j--)
{
if( (mem[i] & num[j] ) != 0)
tmp = '1';
else
tmp = '0';
fprintf(out,"%c",tmp);
}
}
fprintf(out,"\n");
return;
}
int main(void)
{
FILE *in;
FILE *out;
int i,j,k;
unsigned char mem[32];
in = fopen("main.bin", "rb");
out = fopen("inst_ram.coe","w");
fprintf(out, "memory_initialization_radix = 16;\n");
fprintf(out, "memory_initialization_vector =\n");
while(!feof(in)) {
if(fread(mem,1,4,in)!=4) {
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1], mem[0]);
break;
}
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1],mem[0]);
}
fclose(in);
fclose(out);
in = fopen("main.data", "rb");
out = fopen("data_ram.coe","w");
fprintf(out, "memory_initialization_radix = 16;\n");
fprintf(out, "memory_initialization_vector =\n");
while(!feof(in)) {
if(fread(mem,1,4,in)!=4) {
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1], mem[0]);
break;
}
fprintf(out, "%02x%02x%02x%02x\n", mem[3], mem[2], mem[1],mem[0]);
}
fclose(in);
fclose(out);
in = fopen("main.data", "rb");
out = fopen("data_ram.mif","w");
while(!feof(in)) {
if(fread(mem,1,4,in)!=4) {
binary_out(out,mem);
break;
}
binary_out(out,mem);
}
fclose(in);
fclose(out);
in = fopen("main.bin", "rb");
out = fopen("inst_ram.mif","w");
while(!feof(in)) {
if(fread(mem,1,4,in)!=4) {
binary_out(out,mem);
break;
}
binary_out(out,mem);
}
fclose(in);
fclose(out);
return 0;
}

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resources/2021/soft/tlb_func/include/asm.h Normal file
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/* $OpenBSD: asm.h,v 1.2 1998/03/16 09:03:02 pefo Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* Copyright (C) 1989 Digital Equipment Corporation.
* Permission to use, copy, modify, and distribute this software and
* its documentation for any purpose and without fee is hereby granted,
* provided that the above copyright notice appears in all copies.
* Digital Equipment Corporation makes no representations about the
* suitability of this software for any purpose. It is provided "as is"
* without express or implied warranty.
*/
#ifndef _MIPS_ASM_H
#define _MIPS_ASM_H
#include <regdef.h>
#ifndef ABICALLS
#define ABICALLS .abicalls
#endif
#if defined(ABICALLS) && !defined(_KERNEL)
ABICALLS
#endif
#define RCSID(x)
/*
* Define how to access unaligned data word
*/
#if defined(__MIPSEL__)
#define LWLO lwl
#define LWHI lwr
#define SWLO swl
#define SWHI swr
#else
#if defined(__MIPSEB__)
#define LWLO lwr
#define LWHI lwl
#define SWLO swr
#define SWHI swl
#else
#error "__MIPSEL__ or __MIPSEB__ must be defined"
#endif
#endif
/*
* Code for setting gp reg if abicalls are used.
*/
#if defined(ABICALLS) && !defined(_KERNEL)
#define ABISETUP \
.set noreorder; \
.cpload t9; \
.set reorder;
#else
#define ABISETUP
#endif
/*
* Define -pg profile entry code.
*/
#if defined(GPROF) || defined(PROF)
#define MCOUNT \
subu sp, sp, 32; \
.cprestore 16; \
sw ra, 28(sp); \
sw gp, 24(sp); \
.set noat; \
.set noreorder; \
move AT, ra; \
jal _mcount; \
subu sp, sp, 8; \
lw ra, 28(sp); \
addu sp, sp, 32; \
.set reorder; \
.set at;
#else
#define MCOUNT
#endif
/*
* LEAF(x)
*
* Declare a leaf routine.
*/
#define LEAF(x) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, 0, ra; \
ABISETUP \
MCOUNT
#define ALEAF(x) \
.globl x; \
x:
/*
* NLEAF(x)
*
* Declare a non-profiled leaf routine.
*/
#define NLEAF(x) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, 0, ra; \
ABISETUP
/*
* NON_LEAF(x)
*
* Declare a non-leaf routine (a routine that makes other C calls).
*/
#define NON_LEAF(x, fsize, retpc) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, fsize, retpc; \
ABISETUP \
MCOUNT
/*
* NNON_LEAF(x)
*
* Declare a non-profiled non-leaf routine
* (a routine that makes other C calls).
*/
#define NNON_LEAF(x, fsize, retpc) \
.align 3; \
.globl x; \
.ent x, 0; \
x: ; \
.frame sp, fsize, retpc \
ABISETUP
/*
* END(x)
*
* Mark end of a procedure.
*/
#define END(x) \
.end x
/*
* Macros to panic and printf from assembly language.
*/
#define PANIC(msg) \
la a0, 9f; \
jal panic; \
MSG(msg)
#define PRINTF(msg) \
la a0, 9f; \
jal printf; \
MSG(msg)
#define MSG(msg) \
.rdata; \
9: .asciiz msg; \
.text
#define ASMSTR(str) \
.asciiz str; \
.align 3
#if (_MIPS_SZPTR == 32)
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_LI li
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
#define PTRSIZE 4
#define PTRLOG 2
#endif
#if (_MIPS_SZPTR == 64)
#define PTR_ADD dadd
#define PTR_ADDU daddu
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_L ld
#define PTR_S sd
#define PTR_LA dla
#define PTR_LI dli
#define PTR_SLL dsll
#define PTR_SLLV dsllv
#define PTR_SRL dsrl
#define PTR_SRLV dsrlv
#define PTR_SRA dsra
#define PTR_SRAV dsrav
#define PTR_SCALESHIFT 3
#define PTR .dword
#define PTRSIZE 8
#define PTRLOG 3
#endif
#endif /* !_MIPS_ASM_H */

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/* $OpenBSD: regdef.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */
/*
* Copyright (c) 1992, 1993
* The Regents of the University of California. All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* Ralph Campbell. This file is derived from the MIPS RISC
* Architecture book by Gerry Kane.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* @(#)regdef.h 8.1 (Berkeley) 6/10/93
*/
#ifndef _MIPS_REGDEF_H_
#define _MIPS_REGDEF_H_
#define zero $0 /* always zero */
#define AT $at /* assembler temp */
#define v0 $2 /* return value */
#define v1 $3
#define a0 $4 /* argument registers */
#define a1 $5
#define a2 $6
#define a3 $7
#define t0 $8 /* temp registers (not saved across subroutine calls) */
#define t1 $9
#define t2 $10
#define t3 $11
#define t4 $12
#define t5 $13
#define t6 $14
#define t7 $15
#define s0 $16 /* saved across subroutine calls (callee saved) */
#define s1 $17
#define s2 $18
#define s3 $19
#define s4 $20
#define s5 $21
#define s6 $22
#define s7 $23
#define t8 $24 /* two more temp registers */
#define t9 $25
#define k0 $26 /* kernel temporary */
#define k1 $27
#define gp $28 /* global pointer */
#define sp $29 /* stack pointer */
#define s8 $30 /* one more callee saved */
#define ra $31 /* return address */
#define fp $30
#define c0_index $0
#define c0_random $1
#define c0_entrylo0 $2
#define c0_entrylo1 $3
#define c0_conf $3
#define c0_context $4
#define c0_pagemask $5
#define c0_wired $6
#define c0_info $7
#define c0_badvaddr $8
#define c0_count $9
#define c0_entryhi $10
#define c0_compare $11
#define c0_status $12
#define c0_cause $13
#define c0_epc $14
#define c0_prid $15
#define c0_config $16
#define c0_lladdr $17
#define c0_watchlo $18
#define c0_watchhi $19
#define c0_xcontext $20
#define c0_framemask $21
#define c0_diagnostic $22
#define c0_debug $23
#define c0_depc $24
#define c0_performance $25
#define c0_ecc $26
#define c0_cacheerr $27
#define c0_taglo $28
#define c0_taghi $29
#define c0_errorepc $30
#define c0_desave $31
#endif /* !_MIPS_REGDEF_H_ */

105
resources/2021/soft/tlb_func/include/ucas_cde.h Normal file
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//soc confreg
#define CONFREG_NULL 0xbfaf8ffc
#define CONFREG_CR0 0xbfaf8000
#define CONFREG_CR1 0xbfaf8004
#define CONFREG_CR2 0xbfaf8008
#define CONFREG_CR3 0xbfaf800c
#define CONFREG_CR4 0xbfaf8010
#define CONFREG_CR5 0xbfaf8014
#define CONFREG_CR6 0xbfaf8018
#define CONFREG_CR7 0xbfaf801c
#define UART_ADDR 0xbfaffff0
#define SIMU_FLAG_ADDR 0xbfaffff4
#define OPEN_TRACE_ADDR 0xbfaffff8
#define NUM_MONITOR_ADDR 0xbfaffffc
#define LED_ADDR 0xbfaff000
#define LED_RG0_ADDR 0xbfaff004
#define LED_RG1_ADDR 0xbfaff008
#define NUM_ADDR 0xbfaff010
#define SWITCH_ADDR 0xbfaff020
#define BTN_KEY_ADDR 0xbfaff024
#define BTN_STEP_ADDR 0xbfaff028
#define TIMER_ADDR 0xbfafe000
#define SOC_LED (* (volatile unsigned *) LED_ADDR )
#define SOC_LED_RG0 (* (volatile unsigned *) LED_RG0_ADDR )
#define SOC_LED_RG1 (* (volatile unsigned *) LED_RG1_ADDR )
#define SOC_NUM (* (volatile unsigned *) NUM_ADDR )
#define SOC_SWITCHE (* (volatile unsigned *) SWITCH_ADDR )
#define SOC_BTN_KEY (* (volatile unsigned *) BTN_KEY_ADDR )
#define SOC_BTN_STEP (* (volatile unsigned *) BTN_STEP_ADDR )
#define SOC_TIMER (* (volatile unsigned *) TIMER_ADDR )
//#define disable_trace_cmp *((volatile int *)OPEN_TRACE_ADDR) = 0; \
// *((volatile int *)CONFREG_NULL ) = 0; \
// *((volatile int *)CONFREG_NULL ) = 0
//#define enable_trace_cmp *((volatile int *)OPEN_TRACE_ADDR) = 1; \
// *((volatile int *)CONFREG_NULL ) = 0; \
*((volatile int *)CONFREG_NULL ) = 0
#define trace_cmp_flag (*((volatile int *)OPEN_TRACE_ADDR))
#define disable_trace_cmp asm volatile( \
".set noreorder;" \
"lui $25,0xbfb0\n\t" \
"sw $0,-0x7004($25)\n\t" \
"sw $0,-0x7004($25)\n\t" \
"sw $0,-0x8($25)\n\t" \
"sw $0,-0x7004($25)\n\t" \
"sw $0,-0x7004($25)\n\t" \
"lw $0,-0x7004($25)\n\t" \
"lw $25,-0x8($25)\n\t" \
".set reorder" \
:::"$25" \
)
#define disable_trace_cmp_s .set noreorder; \
lui k1,0xbfb0; \
sw $0,-0x7004(k1); \
sw $0,-0x7004(k1); \
sw $0,-0x8(k1); \
sw $0,-0x7004(k1); \
sw $0,-0x7004(k1); \
lw $0,-0x7004(k1); \
lw k1,-0x8(k1); \
.set reorder; \
#define disable_num_monitor_s .set noreorder; \
lui k1,0xbfb0; \
sw $0,-0x7004(k1); \
sw $0,-0x7004(k1); \
sw $0,-0x4(k1); \
sw $0,-0x7004(k1); \
sw $0,-0x7004(k1); \
lw $0,-0x7004(k1); \
lw k1,-0x4(k1); \
.set reorder; \
#define enable_trace_cmp asm volatile( \
".set noreorder;" \
"lui $25,0xbfb0\n\t" \
"sw $0,-0x7004($25)\n\t" \
"sw $0,-0x7004($25)\n\t" \
"sw $25,-8($25)\n\t" \
"sw $0,-0x7004($25)\n\t" \
"sw $0,-0x7004($25)\n\t" \
"lw $0,-0x7004($25)\n\t" \
"lw $25,-0x8($25)\n\t" \
".set reorder" \
:::"$25" \
)
#define enable_trace_cmp_s .set noreorder; \
lui k1,0xbfb0; \
sw $0,-0x7004(k1); \
sw $0,-0x7004(k1); \
sw k1,-8(k1); \
sw $0,-0x7004(k1); \
sw $0,-0x7004(k1); \
lw $0,-0x7004(k1); \
lw k1,-0x8(k1); \
.set reorder; \
#define write_confreg_cr(num,data) *((volatile int *)(CONFREG_CR0+4*num)) = data
#define read_confreg_cr(num,data) data=*((volatile int *)(CONFREG_CR0+4*num))
#define NOP4
#define LI(reg, imm) \
li reg, imm

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srcs = $(wildcard *.S)
objs = $(patsubst %.S, %.o, $(srcs))
$(TOPDIR)/libinst.a: $(objs)
$(CROSS_COMPILE)$(AR) -cr $@ $?
clean:
rm -f *.o *.a *.s
#print:
# @echo $(srcs)
# @echo $(objs)
-include $(TOPDIR)/rules.make

41
resources/2021/soft/tlb_func/inst/n10_fetch_tlb_ex.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n10_fetch_tlb_ex_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x3
lui t2, 0x1
###test inst
#if 1
#refill: load
la t0,fetch_tlb_pc_2
andi a0, t0, 0xfff
li a1, 0x33333000
or a1, a1, a0
jr a1 //refill, invalid
nop
.global fetch_tlb_pc_2
fetch_tlb_pc_2:
la t1, fetch_tlb_pc_3
jr t1
nop
b inst_error
nop
fetch_tlb_pc_3:
#endif
nop
###detect exception
li t1, 0x3333
bne s2, t1, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n10_fetch_tlb_ex_test)

54
resources/2021/soft/tlb_func/inst/n1_index.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n1_index_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x0
lui t2, 0x1
###test inst
#if 1
li t1, 0x3
li t2, 0x0
mtc0 t1, c0_index
nop
mfc0 t2, c0_index
bne t1, t2, inst_error
nop
li t1, 0x1f
li t2, 0x0
mtc0 t1, c0_index
nop
mfc0 t2, c0_index
bne t1, t2, inst_error
nop
li t1, 0x3a
li t2, 0x0
mtc0 t1, c0_index
nop
mfc0 t2, c0_index
li t1, 0x1a
bne t1, t2, inst_error
nop
li t1, 0xfffffff0
li t2, 0x0
mtc0 t1, c0_index
nop
mfc0 t2, c0_index
li t1, 0x10
bne t1, t2, inst_error
#endif
nop
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n1_index_test)

54
resources/2021/soft/tlb_func/inst/n2_entryhi.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n2_entryhi_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x0
lui t2, 0x1
###test inst
#if 1
li t1, 0xffffe0ff
li t2, 0x0
mtc0 t1, c0_entryhi
nop
mfc0 t2, c0_entryhi
bne t1, t2, inst_error
nop
li t1, 0x10000001
li t2, 0x0
mtc0 t1, c0_entryhi
nop
mfc0 t2, c0_entryhi
bne t1, t2, inst_error
nop
li t1, 0xffffffff
li t2, 0x0
mtc0 t1, c0_entryhi
nop
mfc0 t2, c0_entryhi
li t1, 0xffffe0ff
bne t1, t2, inst_error
nop
li t1, 0x00001f00
li t2, 0x1
mtc0 t1, c0_entryhi
nop
mfc0 t2, c0_entryhi
li t1, 0x0
bne t1, t2, inst_error
#endif
nop
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n2_entryhi_test)

54
resources/2021/soft/tlb_func/inst/n3_entrylo0.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n3_entrylo0_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x0
lui t2, 0x1
###test inst
#if 1
li t1, 0x03ffffff
li t2, 0x0
mtc0 t1, c0_entrylo0
nop
mfc0 t2, c0_entrylo0
bne t1, t2, inst_error
nop
li t1, 0x1f
li t2, 0x0
mtc0 t1, c0_entrylo0
nop
mfc0 t2, c0_entrylo0
bne t1, t2, inst_error
nop
li t1, 0xffffffff
li t2, 0x0
mtc0 t1, c0_entrylo0
nop
mfc0 t2, c0_entrylo0
li t1, 0x03ffffff
bne t1, t2, inst_error
nop
li t1, 0xfc000000
li t2, 0x1
mtc0 t1, c0_entrylo0
nop
mfc0 t2, c0_entrylo0
li t1, 0x0
bne t1, t2, inst_error
#endif
nop
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n3_entrylo0_test)

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resources/2021/soft/tlb_func/inst/n4_entrylo1.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n4_entrylo1_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x0
lui t2, 0x1
###test inst
#if 1
li t1, 0x03ffffff
li t2, 0x0
mtc0 t1, c0_entrylo1
nop
mfc0 t2, c0_entrylo1
bne t1, t2, inst_error
nop
li t1, 0x1f
li t2, 0x0
mtc0 t1, c0_entrylo1
nop
mfc0 t2, c0_entrylo1
bne t1, t2, inst_error
nop
li t1, 0xffffffff
li t2, 0x0
mtc0 t1, c0_entrylo1
nop
mfc0 t2, c0_entrylo1
li t1, 0x03ffffff
bne t1, t2, inst_error
nop
li t1, 0xfc000000
li t2, 0x1
mtc0 t1, c0_entrylo1
nop
mfc0 t2, c0_entrylo1
li t1, 0x0
bne t1, t2, inst_error
#endif
nop
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n4_entrylo1_test)

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resources/2021/soft/tlb_func/inst/n5_pagemask.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n5_pagemask_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x0
lui t2, 0x1
###test inst
#if 1
li t1, 0x0
li t2, 0x1
mtc0 t1, c0_pagemask
nop
mfc0 t2, c0_pagemask
bne t1, t2, inst_error
nop
#endif
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n5_pagemask_test)

153
resources/2021/soft/tlb_func/inst/n6_tlbwi_tlbr.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n6_tlbwi_tlbr_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x0
lui t2, 0x1
###test inst
#if 1
mtc0 zero, c0_pagemask
li t1, 0x00234500
mtc0 t1, c0_entrylo0
li t2, 0x00789a00
mtc0 t2, c0_entrylo1
li v0 , 0
li v1 , 29
li t0, 0xbfc00010
#tlb 0~28
1:
mtc0 t0, c0_entryhi
mtc0 v0, c0_index
tlbwi
li t3, 0xffffffff
mtc0 t3, c0_pagemask
mtc0 t3, c0_entryhi
mtc0 t3, c0_entrylo0
mtc0 t3, c0_entrylo1
tlbr
mfc0 a3, c0_pagemask
mfc0 a0, c0_entryhi
mfc0 a1, c0_entrylo0
mfc0 a2, c0_entrylo1
nop
bne a3, zero, inst_error
nop
bne a0, t0, inst_error
nop
bne a1, t1, inst_error
nop
bne a2, t2, inst_error
nop
addiu v0, v0, 1
addiu t0, t0, 1<<13
bne v0, v1, 1b
nop
#tlb 29
li t1, 0x00234500
mtc0 t1, c0_entrylo0
li t2, 0x00789a01
mtc0 t2, c0_entrylo1
li t2, 0x00789a00
mtc0 t0, c0_entryhi
mtc0 v0, c0_index
tlbwi
li t3, 0xffffffff
mtc0 t3, c0_pagemask
mtc0 t3, c0_entryhi
mtc0 t3, c0_entrylo0
mtc0 t3, c0_entrylo1
tlbr
mfc0 a3, c0_pagemask
mfc0 a0, c0_entryhi
mfc0 a1, c0_entrylo0
mfc0 a2, c0_entrylo1
nop
bne a3, zero, inst_error
nop
bne a0, t0, inst_error
nop
bne a1, t1, inst_error
nop
bne a2, t2, inst_error
nop
addiu v0, v0, 1
addiu t0, t0, 1<<13
nop
#tlb 30
li t1, 0x00234501
mtc0 t1, c0_entrylo0
li t1, 0x00234500
li t2, 0x00789a1c
mtc0 t2, c0_entrylo1
mtc0 t0, c0_entryhi
mtc0 v0, c0_index
tlbwi
li t3, 0xffffffff
mtc0 t3, c0_pagemask
mtc0 t3, c0_entryhi
mtc0 t3, c0_entrylo0
mtc0 t3, c0_entrylo1
tlbr
mfc0 a3, c0_pagemask
mfc0 a0, c0_entryhi
mfc0 a1, c0_entrylo0
mfc0 a2, c0_entrylo1
nop
bne a3, zero, inst_error
nop
bne a0, t0, inst_error
nop
bne a1, t1, inst_error
nop
bne a2, t2, inst_error
nop
addiu v0, v0, 1
addiu t0, t0, 1<<13
nop
#tlb 31
li t1, 0x00234505
mtc0 t1, c0_entrylo0
li t2, 0x00789a11
mtc0 t2, c0_entrylo1
mtc0 t0, c0_entryhi
mtc0 v0, c0_index
tlbwi
li t3, 0xffffffff
mtc0 t3, c0_pagemask
mtc0 t3, c0_entryhi
mtc0 t3, c0_entrylo0
mtc0 t3, c0_entrylo1
tlbr
mfc0 a3, c0_pagemask
mfc0 a0, c0_entryhi
mfc0 a1, c0_entrylo0
mfc0 a2, c0_entrylo1
nop
bne a3, zero, inst_error
nop
bne a0, t0, inst_error
nop
bne a1, t1, inst_error
nop
bne a2, t2, inst_error
nop
addiu v0, v0, 1
addiu t0, t0, 1<<13
nop
#endif
nop
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n6_tlbwi_tlbr_test)

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resources/2021/soft/tlb_func/inst/n7_tlbp.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n7_tlbp_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x0
lui t2, 0x1
###test inst
#if 1
#tlbp: G=0
mtc0 zero, c0_index
li t0, 0xbfc00010+(1<<13)*2
mtc0 t0, c0_entryhi
tlbp
mfc0 a0, c0_index
li t0, 2
bne t0, a0, inst_error
nop
#tlbp: G=1
mtc0 zero, c0_index
li t0, 0xbfc00010+(1<<13)*31+1
mtc0 t0, c0_entryhi
tlbp
mfc0 a0, c0_index
li t0, 31
bne t0, a0, inst_error
nop
#tlbp: G=0
mtc0 zero, c0_index
li t0, 0xbfc00010+(1<<13)*30+3
mtc0 t0, c0_entryhi
tlbp
mfc0 a0, c0_index
srl a0, 31
li t0, 1
bne t0, a0, inst_error
nop
#endif
nop
###detect exception
bne s2, zero, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n7_tlbp_test)

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resources/2021/soft/tlb_func/inst/n8_load_tlb_ex.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n8_load_tlb_ex_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x1
lui t2, 0x1
###test inst
#if 1
#refill: load
li t0, 0x12345678
li a0, 0xbfcd0080
li a1, 0x11111080
sw t0, 0(a0)
.global load_tlb_pc_1
load_tlb_pc_1:
lw t1, 0(a1) //refill, invalid
b inst_error
nop
lw t1, 0(a1)
bne t1, t0, inst_error
nop
#endif
nop
###detect exception
li t1, 0x1111
bne s2, t1, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n8_load_tlb_ex_test)

40
resources/2021/soft/tlb_func/inst/n9_store_tlb_ex.S Normal file
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#include <asm.h>
#include <regdef.h>
LEAF(n9_store_tlb_ex_test)
.set noreorder
addiu s0, s0 ,1
addiu s2, zero, 0x2
lui t2, 0x1
###test inst
#if 1
#refill: load
li t0, 0x23456789
li a0, 0xbfcd1040
li a1, 0x22222040
.global store_tlb_pc_1
store_tlb_pc_1:
sw t0, 0(a1) //refill, invalid, modified
b inst_error
nop
sw t0, 0(a1)
nop
lw t1, 0(a0)
bne t1, t0, inst_error
nop
#endif
nop
###detect exception
li t1, 0x2222
bne s2, t1, inst_error
nop
###score ++
addiu s3, s3, 1
###output (s0<<24)|s3
inst_error:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
END(n9_store_tlb_ex_test)

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resources/2021/soft/tlb_func/rules.make Normal file
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.S.o:
${CROSS_COMPILE}gcc -O2 $(CFLAGS) -fno-pic -mno-abicalls -g -DGUEST -I include -I . -c $< -nostdinc -nostdlib
.c.o:
${CROSS_COMPILE}gcc -O2 $(CFLAGS) -fno-pic -mno-abicalls -g -DGUEST -I include -I . -c $< -nostdinc -nostdlib
.S.s:
${CROSS_COMPILE}gcc -O2 $(CFLAGS) -fno-pic -mno-abicalls -g -DGUEST -I include -I . -S -fverbose-asm -o $@ $< -nostdinc -nostdlib
.c.s:
${CROSS_COMPILE}gcc -O2 $(CFLAGS) -fno-pic -mno-abicalls -g -DGUEST -I include -I . -S -fverbose-asm -o $@ $< -nostdinc -nostdlib

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resources/2021/soft/tlb_func/start.S Normal file
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#include <asm.h>
#include <regdef.h>
#include <ucas_cde.h>
#define TEST_TLB_EXCEPTION 1
#if TEST_TLB_EXCEPTION
#define TEST_NUM 10
#else
#define TEST_NUM 7
#endif
##s0, number
##s1, number adress
##s2, exception use
##s3, score
##s4, exception pc
.set noreorder
.globl _start
.globl start
.globl __main
_start:
start:
disable_trace_cmp_s
j locate
nop
##avoid "j locate" not taken
lui t0, 0x8000
addiu t1, t1, 1
or t2, t0, zero
addu t3, t5, t6
lw t4, 0(t0)
nop
##avoid cpu run error
.org 0x0e8
lui t0, 0x8000
addiu t1, t1, 1
or t2, t0, zero
addu t3, t5, t6
lw t4, 0(t0)
nop
.org 0x100
test_finish:
addiu t0, t0, 1
b test_finish
nop
##avoid cpu run error
lui t0, 0x8000
addiu t1, t1, 1
or t2, t0, zero
addu t3, t5, t6
lw t4, 0(t0)
/*
* exception handle
*/
.org 0x200
tlb_refill:
mfc0 k0, c0_cause
andi k0, k0, 0x7c # 6..2
li k1, 1
beq s2, k1, load_refill_ex
nop
li k1, 2
beq s2, k1, store_refill_ex
nop
li k1, 3
beq s2, k1, fetch_refill_ex
nop
b tlb_fail
nop
load_refill_ex:
li k1, 2<<2 # exception: tlbl
bne k0, k1, tlb_fail
nop
mfc0 k0, c0_epc
la k1, load_tlb_pc_1
bne k0, k1, tlb_fail
nop
li t1, 0x00234500
mtc0 t1, c0_entrylo0
li t2, 0x00789a00
mtc0 t2, c0_entrylo1
li t3, 0x1
mtc0 t3, c0_index
tlbwi
nop
.set mips32
eret
.set mips0
store_refill_ex:
li k1, 3<<2 # exception: tlbs
bne k0, k1, tlb_fail
nop
mfc0 k0, c0_epc
la k1, store_tlb_pc_1
bne k0, k1, tlb_fail
nop
li t1, 0x00234500
mtc0 t1, c0_entrylo0
li t2, 0x00789a00
mtc0 t2, c0_entrylo1
li t3, 0x2
mtc0 t3, c0_index
tlbwi
nop
.set mips32
eret
.set mips0
fetch_refill_ex:
li k1, 2<<2 # exception: tlbl
bne k0, k1, tlb_fail
nop
la k1,fetch_tlb_pc_2
andi k1, k1, 0xfff
li k0, 0x33333000
or k1, k1, k0
mfc0 k0, c0_epc
bne k0, k1, tlb_fail
nop
li t1, 0x00234500
mtc0 t1, c0_entrylo0
li t2, 0x00789a00
mtc0 t2, c0_entrylo1
li t3, 0x3
mtc0 t3, c0_index
tlbwi
nop
.set mips32
eret
.set mips0
.org 0x380
1:
mfc0 k0, c0_cause
andi k0, k0, 0x7c # 6..2
li k1, 1
beq s2, k1, load_inv_ex
nop
li k1, 2
beq s2, k1, store_inv_mod_ex
nop
li k1, 3
beq s2, k1, fetch_inv_ex
nop
b tlb_fail
nop
load_inv_ex:
li k1, 2<<2 # exception: tlbl
beq k0, k1, load_tlb_invalid
nop
b tlb_fail
nop
load_tlb_invalid:
tlbp
mfc0 k0, c0_epc
la k1, load_tlb_pc_1
bne k0, k1, tlb_fail
nop
addiu k0, k0, 8
mtc0 k0, c0_epc
li k0, (0xbfcdf<<6)|2 #valid
mtc0 k0, c0_entrylo0
li k1, (0xbfcd0<<6)|2 #valid
mtc0 k1, c0_entrylo1
tlbwi
li s2, 0x1111
.set mips32
eret
.set mips0
store_inv_mod_ex:
li k1, 3<<2 # exception: tlbs
beq k0, k1, store_tlb_invalid
nop
li k1, 1<<2 # exception: mod
beq k0, k1, store_tlb_modified
nop
b tlb_fail
nop
store_tlb_invalid:
tlbp
mfc0 k0, c0_epc
la k1, store_tlb_pc_1
bne k0, k1, tlb_fail
nop
li k0, (0xbfcd1<<6)|2 #valid
mtc0 k0, c0_entrylo0
li k1, (0xbfc20<<6)|2 #valid
mtc0 k1, c0_entrylo1
tlbwi
.set mips32
eret
.set mips0
store_tlb_modified:
mfc0 k0, c0_epc
la k1, store_tlb_pc_1
bne k0, k1, tlb_fail
nop
addiu k0, k0, 8
mtc0 k0, c0_epc
li k0, (0xbfcd1<<6)|6 #dirty,valid
mtc0 k0, c0_entrylo0
li k1, (0xbfc20<<6)|2 #valid
mtc0 k1, c0_entrylo1
tlbwi
li s2, 0x2222
.set mips32
eret
.set mips0
fetch_inv_ex:
li k1, 2<<2 # exception: tlbl
beq k0, k1, fetch_tlb_invalid
nop
b tlb_fail
nop
fetch_tlb_invalid:
tlbp
la k1,fetch_tlb_pc_2
andi k1, k1, 0xfff
li k0, 0x33333000
or k1, k1, k0
mfc0 k0, c0_epc
bne k0, k1, tlb_fail
nop
li k0, (0xbfcdf<<6)|2 #valid
mtc0 k0, c0_entrylo0
la k1, fetch_tlb_pc_2
srl k1, 12
sll k1, 6
ori k1, k1, 2 #valid
mtc0 k1, c0_entrylo1
tlbwi
nop
nop
li s2, 0x3333
.set mips32
eret
.set mips0
tlb_fail:
sll t1, s0, 24
or t0, t1, s3
sw t0, 0(s1)
jr ra
nop
locate:
.set noreorder
LI (a0, LED_RG1_ADDR)
LI (a1, LED_RG0_ADDR)
LI (a2, LED_ADDR)
LI (s1, NUM_ADDR)
LI (t1, 0x0002)
LI (t2, 0x0001)
LI (t3, 0x0000ffff)
lui s3, 0
sw t1, 0(a0)
sw t2, 0(a1)
sw t3, 0(a2)
sw s3, 0(s1)
lui s0, 0
inst_test:
jal n1_index_test
nop
jal wait_1s
nop
jal n2_entryhi_test
nop
jal wait_1s
nop
jal n3_entrylo0_test
nop
jal wait_1s
nop
jal n4_entrylo1_test
nop
jal wait_1s
nop
jal n5_pagemask_test
nop
jal wait_1s
nop
jal n6_tlbwi_tlbr_test
nop
jal wait_1s
nop
jal n7_tlbp_test
nop
jal wait_1s
nop
#if TEST_TLB_EXCEPTION
jal n8_load_tlb_ex_test
nop
jal wait_1s
nop
jal n9_store_tlb_ex_test
nop
jal wait_1s
nop
jal n10_fetch_tlb_ex_test
nop
jal wait_1s
nop
#endif
test_end:
LI (s0, TEST_NUM)
beq s0, s3, 1f
nop
LI (a0, LED_ADDR)
LI (a1, LED_RG1_ADDR)
LI (a2, LED_RG0_ADDR)
LI (t1, 0x0002)
sw zero, 0(a0)
sw t1, 0(a1)
sw t1, 0(a2)
b 2f
nop
1:
LI (t1, 0x0001)
LI (a0, LED_RG1_ADDR)
LI (a1, LED_RG0_ADDR)
sw t1, 0(a0)
sw t1, 0(a1)
2:
j test_finish
nop
wait_1s:
LI (t1,SIMU_FLAG_ADDR)
lui t0, 0x0
lw t2, 0x0(t1)
bne t2, zero, 1f
nop
LI (t0,SWITCH_ADDR)
lw t0, 0x0(t0) #switch[7:0]
LI (t1, 0xff)
xor t0, t0, t1
sll t0, t0, 16 #t0 = switch<<16
1:
addiu t0, 1
2:
addiu t0, -1
bne t0,zero, 2b
nop
jr ra
nop

8
src/Core/Controller.sv
View File

@ -62,10 +62,12 @@ module Controller (
assign ctrl.MCtrl0.HW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | ~inst[1] & inst[0]);
assign ctrl.MCtrl0.LW = ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[4] & (inst[3] | inst[1] & inst[0]);
assign ctrl.MCtrl0.HLS = HLS_t'({~inst[27] & ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & inst[4] & inst[3] | inst[29] & inst[30]), ~inst[30] & inst[1], inst[0]});
// assign ctrl.MCtrl0.HLS = HLS_t'({~inst[27] & ~inst[26] & (~inst[29] & ~inst[30] & ~inst[28] & inst[4] & inst[3] | inst[29] & inst[30]), ~inst[30] & inst[1], inst[0]});
assign ctrl.MCtrl0.HLS = HLS_t'({~inst[27] & ~inst[26] & (~inst[30] & ~inst[31] & ~inst[29] & ~inst[28] & inst[4] & inst[3] | inst[30] & inst[29]), ~inst[30] & inst[1], inst[0]});
assign ctrl.MCtrl0.C0D = inst[15:11];
assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
assign ctrl.MCtrl0.RS0 = RS0_t'({~inst[30] & (inst[29] | inst[26] | ~inst[4]), inst[30], ~inst[29] & (inst[30] | ~inst[1])});
// assign ctrl.MCtrl0.C0W = inst[30] & inst[23];
assign ctrl.MCtrl0.C0W = inst[30] & ~inst[29] & inst[23] & ~inst[3];
assign ctrl.MCtrl0.RS0 = RS0_t'({ctrl.DP1, inst[30], ~inst[29] & (inst[30] | ~inst[1])});
assign ctrl.MCtrl1.MR = inst[31];
assign ctrl.MCtrl1.MWR = inst[29];

173
src/Core/Datapath.sv
View File

@ -13,9 +13,10 @@ module Datapath (
input logic dTLBRefill,
input logic dTLBInvalid,
input logic dTLBModified,
output logic tlbr,
output logic tlbwi,
output logic tlbp,
output logic tlb_tlbwi,
output logic tlb_tlbp,
output logic c0_tlbr,
output logic c0_tlbp,
// CP0
input logic C0_int,
@ -24,7 +25,7 @@ module Datapath (
output logic C0_we,
output word_t C0_wdata,
output EXCEPTION_t C0_exception,
input word_t C0_EPC,
input word_t C0_ERETPC,
//debug interface
output wire [31:0] debug_wb_pc,
@ -119,8 +120,8 @@ module Datapath (
logic D_IB_TLBRefill;
logic D_IB_TLBInvalid;
logic D_IA_DataHazard;
logic D_IB_DataHazard;
logic D_IA_Hazard;
logic D_IB_Hazard;
// Execute
logic E_valid;
@ -182,6 +183,7 @@ module Datapath (
logic M_I1_go;
EXCEPTION_t M_exception;
logic M_exception_REFILL;
logic [ 7:0] M_I1_Byte;
logic [15:0] M_I1_Half;
@ -255,17 +257,18 @@ module Datapath (
assign PF_pc0 = (D.IA.B ? PF_pcb : 32'b0)
| (D.IA.JR ? PF_pcjr : 32'b0)
| (D.IA.J ? PF_pcj : 32'b0);
prio_mux4 #(32) PF_pc_mux (
prio_mux5 #(32) PF_pc_mux (
PF_pc0,
PF_pcp8,
`PCEXC,
C0_EPC,
{M_exception.ERET, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
`PCREF,
C0_ERETPC,
{M_exception.ERET, M_exception_REFILL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
PF.pc
);
assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo;
assign rstM = C0_exception.ExcValid;
assign rstM = C0_exception.ExcValid | tlb_tlbwi & M.en;
assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF
& (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
@ -415,19 +418,17 @@ module Datapath (
);
assign D.IA_ExcValid = D_IA_valid & (D.IA_pc[1:0] != 2'b00 | D_IA_TLBRefill | D_IA_TLBInvalid | ~D_IA_iv | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET);
assign D.IA_ERET = D_IA_valid & D_IA_iv & D.IA.ERET;
assign D.IA_REFILL = D_IA_valid & D_IA_TLBRefill;
assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & D_IA_iv & D.IA.ERET;
assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill;
assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 ? `EXCCODE_ADEL
: D_IA_TLBRefill ? `EXCCODE_TLBL
: D_IA_TLBInvalid ? `EXCCODE_TLBL
: ~D_IA_iv ? `EXCCODE_RI
: D.IA_inst[0] ? `EXCCODE_BP : `EXCCODE_SYS;
assign D.IA_OFA = D_IA_valid & D.IA.OFA;
assign D.IB_ExcValid = D_IB_valid & (D.IB_pc[1:0] != 2'b00 | D_IB_TLBRefill | D_IB_TLBInvalid | ~D_IB_iv | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.BJRJ);
assign D.IB_ERET = D_IB_valid & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
assign D.IB_REFILL = D_IB_valid & D_IB_TLBRefill;
assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & D_IB_iv & D.IB.ERET & ~D.IB_Delay;
assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill;
assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 ? `EXCCODE_ADEL
: D_IB_TLBRefill ? `EXCCODE_TLBL
: D_IB_TLBInvalid ? `EXCCODE_TLBL
@ -436,36 +437,66 @@ module Datapath (
: D.IB_Delay & D.IB.BJRJ ? `EXCCODE_RI
: D.IB_inst[0] ? `EXCCODE_BP : `EXCCODE_SYS;
assign D.IB_Delay = D.IA.BJRJ;
assign D.IB_OFA = D_IB_valid & D.IB.OFA;
// D.Dispatch
assign D_IA_DataHazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl.RS0[2]
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl.RS0[2]
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT
| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl.RS0[2]
| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR
| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl.RS0[2]
| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR;
// Not Arith -> Arith
assign D_IA_Hazard = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl.RS0[2]
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl.RS0[2]
// Load -> Arith
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR
// Arith -> B / JR
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.DS
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.DT
// Not Arith -> B / JR
| M.I0.WCtrl.RW & D.IA.RS == M.I0.RD & D.IA.DS & ~M.I0.MCtrl.RS0[2]
| M.I0.WCtrl.RW & D.IA.RT == M.I0.RD & D.IA.DT & ~M.I0.MCtrl.RS0[2]
// Load -> B / JR
| M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR
| M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR
;
assign D_IB_DataHazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl.RS0[2]
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl.RS0[2]
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & ~D.IB.DP1 & D.IB.MCtrl0.HLS[2] & ~D.IA.DP0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & ~D.IB.DP1 & D.IB.MCtrl0.C0W & ~D.IA.DP0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1 & ~D.IA.MCtrl0.RS0[2];
// Not Arith -> Arith
assign D_IB_Hazard = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl.RS0[2]
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl.RS0[2]
// Load -> Arith
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
// Arith -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
// Load -> MulDiv
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.MCtrl0.HLS[2] & ~D.IA.DP0
// Load -> C0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
// Not Arith -> Store
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.MCtrl0.RS0[2]
// CP0 Execution Hazards
// Hazards Related to the TLB
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBR & D.IA.MCtrl0.C0D == C0_ENTRYHI
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYHI
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYLO0
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_ENTRYLO1
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_INDEX
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBWI & D.IA.MCtrl0.C0D == C0_PAGEMASK
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.TLBP & D.IA.MCtrl0.C0D == C0_ENTRYHI
| D.IA.MCtrl0.C0W & D.IB.MCtrl1.MR & D.IA.MCtrl0.C0D == C0_ENTRYHI
// TODO: CACHE
| D.IA.MCtrl1.TLBP & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_INDEX
| D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_ENTRYHI
| D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_ENTRYLO0
| D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_ENTRYLO1
| D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_PAGEMASK
// Hazards Related to Exceptions or Interrupts
| D.IA.MCtrl0.C0W & D.IB.ERET & D.IA.MCtrl0.C0D == C0_EPC
;
assign D.A = (D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IB.DP0 : D.IA.DP1;
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_DataHazard & (~D.IA.BJRJ | D_IB_valid);
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid | ~D_IB_DataHazard & ~D.IB.BJRJ & (D.A ? D.IB.DP0 : D.IB.DP1);
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_Hazard & (~D.IA.BJRJ | D_IB_valid);
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid & ~(D.IB.ERET & ~D.IB_Delay) | ~D_IB_Hazard & ~D.IB.BJRJ & (D.A ? D.IB.DP0 : D.IB.DP1);
assign D_readygo = ~D_IA_valid | ~D_IB_valid | D_IA_can_dispatch & E.en;
assign D_readygo1 = ~D_IA_valid | D_IB_can_dispatch & D_IA_can_dispatch & E.en;
@ -484,7 +515,7 @@ module Datapath (
assign D.I0.REFILL = D.A ? D.IB_REFILL : D.IA_REFILL;
assign D.I0.ExcCode = D.A ? D.IB_ExcCode : D.IA_ExcCode;
assign D.I0.Delay = D.A ? D.IB_Delay : D.IA_Delay;
assign D.I0.OFA = D.A ? D.IB_OFA : D.IA_OFA;
assign D.I0.OFA = D.A ? D.IB.OFA : D.IA.OFA;
assign D.I0.RS = D.A ? D.IB.RS : D.IA.RS;
assign D.I0.RT = D.A ? D.IB.RT : D.IA.RT;
assign D.I0.S = D.A ? D_IB_ForwardS : D_IA_ForwardS;
@ -503,7 +534,7 @@ module Datapath (
assign D.I1.REFILL = D.A ? D.IA_REFILL : D.IB_REFILL;
assign D.I1.ExcCode = D.A ? D.IA_ExcCode : D.IB_ExcCode;
assign D.I1.Delay = D.A ? D.IA_Delay : D.IB_Delay;
assign D.I1.OFA = D.A ? D.IA_OFA : D.IB_OFA;
assign D.I1.OFA = D.A ? D.IA.OFA : D.IB.OFA;
assign D.I1.RS = D.A ? D.IA.RS : D.IB.RS;
assign D.I1.RT = D.A ? D.IA.RT : D.IB.RT;
assign D.I1.S = D.A ? D_IA_ForwardS : D_IB_ForwardS;
@ -572,9 +603,9 @@ module Datapath (
ffenr #(1) E_valid_ff (
clk,
rst | rstM,
D_go & D_IA_valid,
D_IA_valid,
E.en,
E_valid
E_valid // just pc valid
);
ffen #(1) E_A_ff (
clk,
@ -588,13 +619,21 @@ module Datapath (
E.en,
E.I0.pc
);
ffenrc #(1 + 1 + 1 + 5 + 1 + 1) E_I0_Exc_ff (
ffenrc #(1 + 1 + 1 + 5 + 1) E_I0_Exc_ff (
clk,
rst | rstM,
{D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.Delay, D.I0.OFA},
{D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.Delay},
E.en,
~D_go,
{E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.Delay, E.I0.OFA}
{E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.Delay}
);
ffenrc #(1) E_I0_ExcCtrl_ff (
clk,
rst | rstM,
D.I0.OFA,
E.en,
~D_go | ~D_I0_go,
E.I0.OFA
);
ffen #(5 + 5) E_I0_RST_ff (
clk,
@ -643,13 +682,21 @@ module Datapath (
E.en,
E.I1.pc
);
ffenrc #(1 + 1 + 1 + 5 + 1 + 1) E_I1_Exc_ff (
ffenrc #(1 + 1 + 1 + 5 + 1) E_I1_Exc_ff (
clk,
rst | rstM,
{D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.Delay, D.I1.OFA},
{D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.Delay},
E.en,
~D_go,
{E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.Delay, E.I1.OFA}
{E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.Delay}
);
ffenrc #(1) E_I1_ExcCtrl_ff (
clk,
rst | rstM,
D.I1.OFA,
E.en,
~D_go | ~D_I1_go,
E.I1.OFA
);
ffen #(5 + 5) E_I1_RST_ff (
clk,
@ -807,7 +854,9 @@ module Datapath (
E_I1_STRBERROR
);
assign mem_i.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
assign tlb_tlbwi = E.I1.MCtrl.TLBWI & E_I1_go & M.en & ~rstM;
assign tlb_tlbp = E.I1.MCtrl.TLBP & E_I1_go & M.en & ~rstM;
assign mem_i.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
assign mem_i.addr = E_I1_ForwardS + E.I1.imm;
// assign mem_i.addr = E.I1.ALUOut;
@ -992,10 +1041,10 @@ module Datapath (
assign M_I0_go = ~M.A | ~M_I1_NowExcValid;
assign M_I1_go = ~M_I1_NowExcValid;
assign M_exception = {
assign {M_exception, M_exception_REFILL} = {
M.I1.ExcValid | M.I0.ExcValid,
~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET}
: {M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET}
~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL}
: {M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL}
};
assign C0_exception = {
M_exception.ExcValid & M.en,
@ -1056,21 +1105,23 @@ module Datapath (
ffen #(32) HI_ff (
clk,
M_I0_HI,
M.I0.MCtrl.HW,
M.I0.MCtrl.HW & M_I0_go,
HI
);
ffen #(32) LO_ff (
clk,
M_I0_LO,
M.I0.MCtrl.LW,
M.I0.MCtrl.LW & M_I0_go,
LO
);
assign C0_addr = M.I0.MCtrl.C0D;
assign C0_we = M.I0.MCtrl.C0W;
assign C0_addr = M.I0.MCtrl.C0D;
assign C0_we = M.I0.MCtrl.C0W & M_I0_go;
assign C0_wdata = M_I0_ForwardT;
// M.I1.MEM
assign c0_tlbr = M.I1.MCtrl.TLBR;
assign c0_tlbp = M.I1.MCtrl.TLBP;
assign mem_i.wr = M.I1.MCtrl.MWR;
memoutput M_I1_memoutput (
M.I1.ALUOut[1:0],
@ -1131,7 +1182,7 @@ module Datapath (
assign M_go = (M.I0.MCtrl.HLS[2:1] != 2'b10 | M_I0_MULT_bvalid)
& (M.I0.MCtrl.HLS != DIV | M_I0_DIV_bvalid)
& (M.I0.MCtrl.HLS != DIVU | M_I0_DIVU_bvalid)
& (~M.I1.MCtrl.MR | M_I1_DataR_OK)
& (~M.I1.MCtrl.MR | M_I1_NowExcValid | M_I1_DataR_OK)
& (~M_exception.ExcValid | fetch_i.req & fetch_i.addr_ok);
// M.Forwarding
@ -1198,7 +1249,7 @@ module Datapath (
rst,
{M.I0.RD, M.I0.WCtrl},
W.en,
~M_go,
~M_go | ~M_I0_go,
{W.I0.RD, W.I0.WCtrl}
);
ffen #(32) W_I1_RDataW_ff (
@ -1212,7 +1263,7 @@ module Datapath (
rst,
{M.I1.RD, M.I1.WCtrl},
W.en,
~M_go,
~M_go | ~M_I1_go,
{W.I1.RD, W.I1.WCtrl}
);

68
src/MMU/MMU.sv
View File

@ -48,13 +48,13 @@ module MMU (
word_t iVA;
logic iEn;
logic iEn, iEn2;
logic iReq1;
logic iHit1;
logic iCached1;
logic iMValid1;
logic iValid1;
word_t iPA1;
word_t iPA1, iPA2;
word_t iD1, iD2, iD3, iD4, iD5, iD6, iD7;
@ -85,19 +85,23 @@ module MMU (
always_comb begin
iEn = 0;
iEn2 = 0;
iNextState = iState;
inst.data_ok = 0;
inst_axi.req = 0;
case (iState)
I_IDLE: begin
if (~iValid1) iEn = 1;
else if (iCached1 & ic.hit) begin
iEn = 1;
inst.data_ok = 1;
end else begin
inst_axi.req = 1;
if (~inst_axi.addr_ok) iNextState = I_WA;
else iNextState = I_WD1;
else begin
iEn2 = 1;
if (iCached1 & ic.hit) begin
iEn = 1;
inst.data_ok = 1;
end else begin
inst_axi.req = 1;
if (~inst_axi.addr_ok) iNextState = I_WA;
else iNextState = I_WD1;
end
end
end
I_WA: begin
@ -156,6 +160,12 @@ module MMU (
iEn,
iReq1
);
ffen #(32) iPA_ff (
clk,
iPA1,
iEn2,
iPA2
);
ffen #(32) id1_ff (
clk,
@ -233,7 +243,7 @@ module MMU (
ic.rdata
);
assign inst_axi.addr = iPA1;
assign inst_axi.addr = iEn2 ? iPA1 : iPA2;
assign inst_axi.size = iCached1 ? 3'b111 : 3'b001;
assign iTLBRefill = iReq1 & ~iHit1;
@ -252,9 +262,9 @@ module MMU (
logic dDirty1;
logic dMValid1;
logic dValid1;
word_t dPA1;
word_t dPA1, dPA2;
logic dwEn;
logic dEn2;
logic dwr1;
logic [3:0] dWstrb1;
word_t dWdata1;
@ -276,22 +286,28 @@ module MMU (
dEn,
dReq1
);
ffen #(32) dPA_ff (
clk,
dPA1,
dEn2,
dPA2
);
ffen #(1) dwr_ff (
clk,
data.wr,
dwEn,
dEn2,
dwr1
);
ffen #(4) dwstrb_ff (
clk,
data.wstrb,
dwEn,
dEn2,
dWstrb1
);
ffen #(32) dwdata_ff (
clk,
data.wdata,
dwEn,
dEn2,
dWdata1
);
@ -329,7 +345,7 @@ module MMU (
always_comb begin
dEn = 0;
dwEn = 0;
dEn2 = 0;
drNextState = drState;
data.data_ok = 0;
rdata_axi.req = 0;
@ -337,7 +353,7 @@ module MMU (
DR_IDLE: begin
if (~dValid1) dEn = 1;
else begin
dwEn = 1;
dEn2 = 1;
if (data.wr) data.data_ok = 1;
if (data.wr & (~dCached1 | dc.hit)) drNextState = DR_REFILL;
else if (dCached1 & dc.hit) begin
@ -441,11 +457,11 @@ module MMU (
{drD3, drD2, drD1, rdata_axi.rdata},
{drD2, drD1, rdata_axi.rdata, drD3},
{drD1, rdata_axi.rdata, drD3, drD2},
dPA1[3:2],
(dEn2 ? dPA1[3:2] : dPA2[3:2]),
dc.rdata
);
assign rdata_axi.addr = dPA1;
assign rdata_axi.addr = dEn2 ? dPA1 : dPA2;
assign rdata_axi.size = dCached1 ? 3'b011 : 3'b000;
// =================================
@ -479,7 +495,7 @@ module MMU (
case (dwState)
DW_IDLE: begin
if (dwEn & (~dCached1 & data.wr | dCached1 & ~dc.hit & dc.dirt_valid)) begin
if (dEn2 & (~dCached1 & data.wr | dCached1 & ~dc.hit & dc.dirt_valid)) begin
if (dCached1) begin
wdata_axi.wdata = dc.dirt_data[31:0];
wdata_axi.wstrb = 4'b1111;
@ -592,7 +608,7 @@ module MMU (
case (dwaState)
DWA_IDLE: begin
if (dwEn & (~dCached1 & data.wr | dCached1 & ~dc.hit & dc.dirt_valid)) begin
if (dEn2 & (~dCached1 & data.wr | dCached1 & ~dc.hit & dc.dirt_valid)) begin
wdata_axi.req = 1'b1;
if (~wdata_axi.addr_ok) dwaNextState = DWA_WA;
end
@ -625,11 +641,11 @@ module MMU (
// ========== dwFunction ==========
// ================================
assign wdata_axi.addr = dCached1 ? (dwaState == DWA_IDLE) ? dc.dirt_addr : ddAddr1 : dPA1;
assign wdata_axi.addr = dCached1 ? (dwaState == DWA_IDLE) ? dc.dirt_addr : ddAddr1 : dEn2 ? dPA1 : dPA2;
assign wdata_axi.size = dCached1 ? 2'b11 : 2'b00;
assign dc.wvalid = dValid1 & dCached1 & (dwEn ? data.wr : dwr1) & (drState != DR_REFILL);
assign dc.wdata = dwEn ? data.wdata : dWdata1;
assign dc.wstrb = dwEn ? data.wstrb : dWstrb1;
assign dc.wvalid = dValid1 & dCached1 & (dEn2 ? data.wr : dwr1) & (drState != DR_REFILL);
assign dc.wdata = dEn2 ? data.wdata : dWdata1;
assign dc.wstrb = dEn2 ? data.wstrb : dWstrb1;
// ==============================
// ========== VA -> PA ==========
@ -638,8 +654,6 @@ module MMU (
TLB TLB (
.clk(clk),
.rst(rst),
.iEn(iEn),
.dEn(dEn),
.K0 (K0),
.tlbwi (tlbwi),

10
src/MMU/TLB.sv
View File

@ -3,8 +3,6 @@
module TLB (
input clk,
input rst,
input logic iEn,
input logic dEn,
// CP0
input logic [2:0] K0,
@ -37,6 +35,7 @@ module TLB (
output logic dDirty, // TLB Modified
output logic dValid // TLB Invalid
);
logic tlbwi1;
word_t fVAddr1;
logic [19:0] fPAddr;
@ -56,10 +55,11 @@ module TLB (
TLB_t entry;
// CP0(TLBWI) EntryHi PageMask EntryLo0 EntryLo1 -> TLB[Index]
ffenr #(1) tlbwi_ff(clk, rst, tlbwi, 1'b1, tlbwi1);
always_ff @(posedge clk) begin
if (rst) begin
TLB_entries <= 2880'b0;
end else if (tlbwi)
end else if (tlbwi1)
TLB_entries[c0_Index.Index] <= {c0_EntryHi.VPN2, c0_EntryHi.ASID,
c0_PageMask.Mask,
c0_EntryLo0.G & c0_EntryLo1.G,
@ -102,7 +102,7 @@ module TLB (
ffen #(32) mVAddr_ff (
clk,
{mVAddr, dVAddr[11:0]},
dEn,
1'b1,
mVAddr1
);
TLB_Lookup Lookup_M(
@ -122,7 +122,7 @@ module TLB (
ffen #(32) fVAddr_ff (
clk,
iVAddr,
iEn,
1'b1,
fVAddr1
);
TLB_Lookup Lookup_F (

28
src/MyCPU.sv
View File

@ -86,7 +86,7 @@ module mycpu_top (
logic C0_we;
word_t C0_wdata;
EXCEPTION_t C0_exception;
word_t C0_EPC;
word_t C0_ERETPC;
logic [2:0] K0;
Index_t c0_Index;
EntryHi_t c0_EntryHi;
@ -104,9 +104,10 @@ module mycpu_top (
logic dTLBRefill;
logic dTLBInvalid;
logic dTLBModified;
logic tlbr;
logic tlbwi;
logic tlbp;
logic tlb_tlbwi;
logic tlb_tlbp;
logic c0_tlbr;
logic c0_tlbp;
AXI axi (
@ -130,8 +131,8 @@ module mycpu_top (
.rdata_axi (rdata_axi.master),
.wdata_axi (wdata_axi.master),
.K0 (K0),
.tlbwi (tlbwi),
.tlbp (tlbp),
.tlbwi (tlb_tlbwi),
.tlbp (tlb_tlbp),
.c0_Index (c0_Index),
.c0_EntryHi (c0_EntryHi),
.c0_PageMask (c0_PageMask),
@ -169,11 +170,11 @@ module mycpu_top (
.en (C0_we),
.wdata (C0_wdata),
.exception (C0_exception),
.EPC (C0_EPC),
.EPC (C0_ERETPC),
.ext_int (ext_int),
.interrupt (C0_int),
.tlbr (tlbr),
.tlbp (tlbp),
.tlbr (c0_tlbr),
.tlbp (c0_tlbp),
.K0 (K0),
.Index (c0_Index),
.EntryHi (c0_EntryHi),
@ -198,9 +199,10 @@ module mycpu_top (
.dTLBRefill (dTLBRefill),
.dTLBInvalid (dTLBInvalid),
.dTLBModified(dTLBModified),
.tlbr (tlbr),
.tlbwi (tlbwi),
.tlbp (tlbp),
.tlb_tlbwi (tlb_tlbwi),
.tlb_tlbp (tlb_tlbp),
.c0_tlbr (c0_tlbr),
.c0_tlbp (c0_tlbp),
.C0_int (C0_int),
.C0_addr (C0_addr),
@ -208,7 +210,7 @@ module mycpu_top (
.C0_we (C0_we),
.C0_wdata (C0_wdata),
.C0_exception(C0_exception),
.C0_EPC (C0_EPC),
.C0_ERETPC (C0_ERETPC),
.debug_wb_pc (debug_wb_pc),
.debug_wb_rf_wen (debug_wb_rf_wen),

2
src/include/defines.svh
View File

@ -149,7 +149,6 @@ typedef struct packed {
logic IA_REFILL;
logic [4:0] IA_ExcCode;
logic IA_Delay;
logic IA_OFA;
word_t IA_S;
word_t IA_T;
word_t IA_imm;
@ -162,7 +161,6 @@ typedef struct packed {
logic IB_REFILL;
logic [4:0] IB_ExcCode;
logic IB_Delay;
logic IB_OFA;
word_t IB_S;
word_t IB_T;
word_t IB_imm;

2
tools/global.txt
View File

@ -1,6 +1,6 @@
////-------------------------------- ERET DP0 DP1
32'b00000000000???????????????000010 0 1 1 // SRL
32'b00000000000???????????????000000 0 1 1 // SLL
32'b00000000000???????????????000010 0 1 1 // SRL
32'b00000000000???????????????000011 0 1 1 // SRA
32'b000000???????????????00000000100 0 1 1 // SLLV
32'b000000???????????????00000000110 0 1 1 // SRLV