Code Cleanup
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f0e20f4337
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11e24a8451
@ -1015,11 +1015,6 @@ module Datapath (
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: cache_op.op.dcache_op ? {E_I1_ADDR[32-`DC_INDEXL-1:0], `DC_INDEXL'b0}
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: {E_I1_ADDR[32-`IC_INDEXL-1:0], `IC_INDEXL'b0};
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always_ff @(posedge clk) begin
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if (cache_op.req) begin
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$display("<< dp index_or_hit=%0h writeback=%0h addr=0x%0h >>", cache_op.op.index_or_hit, cache_op.op.writeback, cache_op.addr);
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end
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end
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assign E.en = E_go & M.en;
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assign E_go = (~mem.req | mem.addr_ok) & (~cache_op.req | cache_op.addr_ok);
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@ -1,3 +1,5 @@
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`include "defines.svh"
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module addr_virt_to_phy (
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input logic [ 2:0] K0,
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input word_t virt_addr,
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@ -166,11 +166,7 @@ module DCache (
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always_ff @(posedge clk) begin
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if (TagRAM[i].wen) begin
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if (TagRAM[i].addr == 0 && TagRAM[i].wdata.tag[19:4] == 'h0400) begin
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$display("<< counter=0x%0h way=0x%0h tag=0x%0h index=0x%0h addr=0x%0h dirty=0x%0h valid=0x%0h data=0x%0h read_and_hit=%0h read_but_replace=%0h write_and_hit=%0h write_but_replace=%0h cache_index_invalidate=%0h cache_index_writeback=%0h cache_hit_invalidate=%0h cache_hit_writeback=%0h >>",
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magic_counter, i, TagRAM[i].wdata.tag, TagRAM[i].addr, {TagRAM[i].wdata.tag, TagRAM[i].addr, `DC_INDEXL'b0},
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TagRAM[i].wdata.dirty, TagRAM[i].wdata.valid, DataRAM[i].wdata,
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port.ctrl.read_and_hit, port.ctrl.read_but_replace, port.ctrl.write_and_hit, port.ctrl.write_but_replace, port.ctrl.cache_index_invalidate, port.ctrl.cache_index_writeback, port.ctrl.cache_hit_invalidate, port.ctrl.cache_hit_writeback
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);
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$display("<< bram write target counter = 0x%0h, i = 0x%0h, wen = 0x%0h >>", magic_counter, i, wen);
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end
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end
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end
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@ -376,9 +376,6 @@ module MU (
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// == Memory Control State Machine ==
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// ==================================
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logic [31:0] wb_magic_counter = 0;
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always_ff @(posedge clk) wb_magic_counter <= wb_magic_counter + 1;
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typedef enum bit [1:0] {
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MEM_LOOKUP,
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MEM_READ,
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@ -615,9 +612,6 @@ module MU (
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dcache.ctrl.cache_hit_writeback = stored_cacheop_op.index_or_hit;
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if (dcache.dirt) begin
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$display("<< wb: cnt=0x%0h op.hit=%0h dc.hit=%0h dc.index=%0h dc.tag=%0h dc.dirt=%0h dc.dirt_addr=0x%0h dc.data=%0h >>",
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wb_magic_counter, stored_cacheop_op.index_or_hit, dcache.hit, dcache.index, dcache.tag, dcache.dirt, dcache.dirt_addr, dcache.dirt_row);
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mem_nxt_state = MEM_WRITE;
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amw_call = 1'b1;
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