diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv
index 45003d3..61e68ff 100644
--- a/src/Core/Datapath.sv
+++ b/src/Core/Datapath.sv
@@ -1015,11 +1015,6 @@ module Datapath (
                        : cache_op.op.dcache_op    ? {E_I1_ADDR[32-`DC_INDEXL-1:0], `DC_INDEXL'b0}
                        :                            {E_I1_ADDR[32-`IC_INDEXL-1:0], `IC_INDEXL'b0};
 
-  always_ff @(posedge clk) begin
-    if (cache_op.req) begin
-      $display("<< dp index_or_hit=%0h writeback=%0h addr=0x%0h >>", cache_op.op.index_or_hit, cache_op.op.writeback, cache_op.addr);
-    end
-  end
 
   assign E.en = E_go & M.en;
   assign E_go = (~mem.req | mem.addr_ok) & (~cache_op.req | cache_op.addr_ok);
diff --git a/src/Gadgets/addr_virt_to_phy.sv b/src/Gadgets/addr_virt_to_phy.sv
index 8eaa681..7aaa55b 100644
--- a/src/Gadgets/addr_virt_to_phy.sv
+++ b/src/Gadgets/addr_virt_to_phy.sv
@@ -1,3 +1,5 @@
+`include "defines.svh"
+
 module addr_virt_to_phy (
   input  logic [ 2:0] K0,
   input  word_t       virt_addr,
diff --git a/src/MU/DCache.sv b/src/MU/DCache.sv
index 84cd4a5..6fb8bfe 100644
--- a/src/MU/DCache.sv
+++ b/src/MU/DCache.sv
@@ -166,11 +166,7 @@ module DCache (
     always_ff @(posedge clk) begin
       if (TagRAM[i].wen) begin
         if (TagRAM[i].addr == 0 && TagRAM[i].wdata.tag[19:4] == 'h0400) begin
-          $display("<< counter=0x%0h way=0x%0h tag=0x%0h index=0x%0h addr=0x%0h dirty=0x%0h valid=0x%0h data=0x%0h read_and_hit=%0h read_but_replace=%0h write_and_hit=%0h write_but_replace=%0h cache_index_invalidate=%0h cache_index_writeback=%0h cache_hit_invalidate=%0h cache_hit_writeback=%0h >>",
-                    magic_counter, i, TagRAM[i].wdata.tag, TagRAM[i].addr, {TagRAM[i].wdata.tag, TagRAM[i].addr, `DC_INDEXL'b0},
-                    TagRAM[i].wdata.dirty, TagRAM[i].wdata.valid, DataRAM[i].wdata,
-                    port.ctrl.read_and_hit, port.ctrl.read_but_replace, port.ctrl.write_and_hit, port.ctrl.write_but_replace, port.ctrl.cache_index_invalidate, port.ctrl.cache_index_writeback, port.ctrl.cache_hit_invalidate, port.ctrl.cache_hit_writeback
-                  );
+          $display("<< bram write target counter = 0x%0h, i = 0x%0h, wen = 0x%0h >>", magic_counter, i, wen);
         end
       end
     end
diff --git a/src/MU/MU.sv b/src/MU/MU.sv
index bc3d30a..93c24bc 100644
--- a/src/MU/MU.sv
+++ b/src/MU/MU.sv
@@ -376,9 +376,6 @@ module MU (
   // == Memory Control State Machine ==
   // ==================================
 
-  logic [31:0] wb_magic_counter = 0;
-  always_ff @(posedge clk) wb_magic_counter <= wb_magic_counter + 1;
-
   typedef enum bit [1:0] {
     MEM_LOOKUP,
     MEM_READ,
@@ -615,9 +612,6 @@ module MU (
           dcache.ctrl.cache_hit_writeback   =  stored_cacheop_op.index_or_hit;
 
           if (dcache.dirt) begin
-            $display("<< wb: cnt=0x%0h op.hit=%0h dc.hit=%0h dc.index=%0h dc.tag=%0h dc.dirt=%0h dc.dirt_addr=0x%0h dc.data=%0h >>",
-                    wb_magic_counter, stored_cacheop_op.index_or_hit, dcache.hit, dcache.index, dcache.tag, dcache.dirt, dcache.dirt_addr, dcache.dirt_row);
-
             mem_nxt_state = MEM_WRITE;
 
             amw_call      = 1'b1;