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update CpU and TLB

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This commit is contained in:
Paul Pan 2022-08-04 21:13:23 +08:00
parent cb31fcd0db
commit 054e4611de
1 changed files with 10 additions and 0 deletions
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10
src/Core/Gadgets/decoder2.sv
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@ -9,10 +9,14 @@ module decoder2 (
output logic [1:0] ce output logic [1:0] ce
); );
`ifdef ENABLE_CpU
logic [3:0] CU2; logic [3:0] CU2;
assign CU2 = {CU[3:1], CU[0] | kernel}; assign CU2 = {CU[3:1], CU[0] | kernel};
`endif
always_comb begin always_comb begin
ri = 1'b1; ri = 1'b1;
`ifdef ENABLE_CpU
ce = instr[27:26]; ce = instr[27:26];
cpu = ce != 2'b11 cpu = ce != 2'b11
& ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx & ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx
@ -21,6 +25,10 @@ module decoder2 (
| instr[31:28] == 4'b1110 // SWCx | instr[31:28] == 4'b1110 // SWCx
| instr[31:28] == 4'b1111 // SDCx | instr[31:28] == 4'b1111 // SDCx
); // TODO: Cache instruction ); // TODO: Cache instruction
`else
ce = 2'b0;
cpu = 1'b0;
`endif
casez (instr) casez (instr)
32'b00000000000???????????????000000: ri = 1'b0; // SLL 32'b00000000000???????????????000000: ri = 1'b0; // SLL
32'b00000000000???????????????000010: ri = 1'b0; // SRL 32'b00000000000???????????????000010: ri = 1'b0; // SRL
@ -89,10 +97,12 @@ module decoder2 (
32'b00111100000?????????????????????: ri = 1'b0; // LUI 32'b00111100000?????????????????????: ri = 1'b0; // LUI
32'b01000000000??????????00000000???: ri = 1'b0; // MFC0 32'b01000000000??????????00000000???: ri = 1'b0; // MFC0
32'b01000000100??????????00000000???: ri = 1'b0; // MTC0 32'b01000000100??????????00000000???: ri = 1'b0; // MTC0
`ifdef ENABLE_TLB
32'b01000010000000000000000000000001: ri = 1'b0; // TLBR 32'b01000010000000000000000000000001: ri = 1'b0; // TLBR
32'b01000010000000000000000000000010: ri = 1'b0; // TLBWI 32'b01000010000000000000000000000010: ri = 1'b0; // TLBWI
32'b01000010000000000000000000000110: ri = 1'b0; // TLBWR 32'b01000010000000000000000000000110: ri = 1'b0; // TLBWR
32'b01000010000000000000000000001000: ri = 1'b0; // TLBP 32'b01000010000000000000000000001000: ri = 1'b0; // TLBP
`endif
32'b01000010000000000000000000011000: ri = 1'b0; // ERET 32'b01000010000000000000000000011000: ri = 1'b0; // ERET
`ifdef ENABLE_MADD `ifdef ENABLE_MADD
32'b011100??????????0000000000000000: ri = 1'b0; // MADD 32'b011100??????????0000000000000000: ri = 1'b0; // MADD