From 054e4611de14e52fd8a5b61c641787953ef969a6 Mon Sep 17 00:00:00 2001
From: Paul Pan <panyuxuan@hotmail.com>
Date: Thu, 4 Aug 2022 21:13:23 +0800
Subject: [PATCH] update CpU and TLB

---
 src/Core/Gadgets/decoder2.sv | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/src/Core/Gadgets/decoder2.sv b/src/Core/Gadgets/decoder2.sv
index bcfd031..7f0f524 100644
--- a/src/Core/Gadgets/decoder2.sv
+++ b/src/Core/Gadgets/decoder2.sv
@@ -9,10 +9,14 @@ module decoder2 (
   output logic [1:0] ce
 );
 
+`ifdef ENABLE_CpU
   logic [3:0] CU2;
   assign CU2 = {CU[3:1], CU[0] | kernel};
+`endif
+
   always_comb begin
     ri  = 1'b1;
+`ifdef ENABLE_CpU
     ce = instr[27:26];
     cpu = ce != 2'b11
         & ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx
@@ -21,6 +25,10 @@ module decoder2 (
                      | instr[31:28] == 4'b1110 // SWCx
                      | instr[31:28] == 4'b1111 // SDCx
                      ); // TODO: Cache instruction
+`else
+    ce  = 2'b0;
+    cpu = 1'b0;
+`endif
     casez (instr)
       32'b00000000000???????????????000000: ri = 1'b0;  // SLL
       32'b00000000000???????????????000010: ri = 1'b0;  // SRL
@@ -89,10 +97,12 @@ module decoder2 (
       32'b00111100000?????????????????????: ri = 1'b0;  // LUI
       32'b01000000000??????????00000000???: ri = 1'b0;  // MFC0
       32'b01000000100??????????00000000???: ri = 1'b0;  // MTC0
+`ifdef ENABLE_TLB
       32'b01000010000000000000000000000001: ri = 1'b0;  // TLBR
       32'b01000010000000000000000000000010: ri = 1'b0;  // TLBWI
       32'b01000010000000000000000000000110: ri = 1'b0;  // TLBWR
       32'b01000010000000000000000000001000: ri = 1'b0;  // TLBP
+`endif
       32'b01000010000000000000000000011000: ri = 1'b0;  // ERET
 `ifdef ENABLE_MADD
       32'b011100??????????0000000000000000: ri = 1'b0;  // MADD