2022-07-27 15:07:16 +08:00
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`timescale 1ns / 1ps
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module soc_axi_lite_top #(parameter SIMULATION=1'b0)
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(
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2022-07-29 17:44:11 +08:00
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input resetn,
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input clk,
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//------gpio-------
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output [15:0] led,
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output [1 :0] led_rg0,
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output [1 :0] led_rg1,
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output [7 :0] num_csn,
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output [6 :0] num_a_g,
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input [7 :0] switch,
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output [3 :0] btn_key_col,
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input [3 :0] btn_key_row,
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input [1 :0] btn_step
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2022-07-27 15:07:16 +08:00
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);
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2022-07-29 17:44:11 +08:00
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//debug signals
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wire [31:0] debug_wb_pc;
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wire [3 :0] debug_wb_rf_wen;
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wire [4 :0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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wire [31:0] debug_wb1_pc;
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wire [3 :0] debug_wb1_rf_wen;
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wire [4 :0] debug_wb1_rf_wnum;
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wire [31:0] debug_wb1_rf_wdata;
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wire debug_wb_pc_A;
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//cpu axi
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wire [3 :0] cpu_arid ;
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wire [31:0] cpu_araddr ;
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wire [3 :0] cpu_arlen ;
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wire [2 :0] cpu_arsize ;
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wire [1 :0] cpu_arburst;
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wire [1 :0] cpu_arlock ;
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wire [3 :0] cpu_arcache;
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wire [2 :0] cpu_arprot ;
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wire cpu_arvalid;
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wire cpu_arready;
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wire [3 :0] cpu_rid ;
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wire [31:0] cpu_rdata ;
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wire [1 :0] cpu_rresp ;
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wire cpu_rlast ;
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wire cpu_rvalid ;
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wire cpu_rready ;
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wire [3 :0] cpu_awid ;
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wire [31:0] cpu_awaddr ;
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wire [3 :0] cpu_awlen ;
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wire [2 :0] cpu_awsize ;
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wire [1 :0] cpu_awburst;
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wire [1 :0] cpu_awlock ;
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wire [3 :0] cpu_awcache;
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wire [2 :0] cpu_awprot ;
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wire cpu_awvalid;
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wire cpu_awready;
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wire [3 :0] cpu_wid ;
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wire [31:0] cpu_wdata ;
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wire [3 :0] cpu_wstrb ;
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wire cpu_wlast ;
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wire cpu_wvalid ;
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wire cpu_wready ;
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wire [3 :0] cpu_bid ;
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wire [1 :0] cpu_bresp ;
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wire cpu_bvalid ;
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wire cpu_bready ;
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//cpu axi wrap
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wire cpu_wrap_aresetn;
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wire [3 :0] cpu_wrap_arid ;
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wire [31:0] cpu_wrap_araddr ;
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wire [3 :0] cpu_wrap_arlen ;
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wire [2 :0] cpu_wrap_arsize ;
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wire [1 :0] cpu_wrap_arburst;
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wire [1 :0] cpu_wrap_arlock ;
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wire [3 :0] cpu_wrap_arcache;
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wire [2 :0] cpu_wrap_arprot ;
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wire cpu_wrap_arvalid;
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wire cpu_wrap_arready;
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wire [3 :0] cpu_wrap_rid ;
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wire [31:0] cpu_wrap_rdata ;
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wire [1 :0] cpu_wrap_rresp ;
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wire cpu_wrap_rlast ;
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wire cpu_wrap_rvalid ;
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wire cpu_wrap_rready ;
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wire [3 :0] cpu_wrap_awid ;
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wire [31:0] cpu_wrap_awaddr ;
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wire [3 :0] cpu_wrap_awlen ;
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wire [2 :0] cpu_wrap_awsize ;
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wire [1 :0] cpu_wrap_awburst;
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wire [1 :0] cpu_wrap_awlock ;
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wire [3 :0] cpu_wrap_awcache;
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wire [2 :0] cpu_wrap_awprot ;
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wire cpu_wrap_awvalid;
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wire cpu_wrap_awready;
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wire [3 :0] cpu_wrap_wid ;
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wire [31:0] cpu_wrap_wdata ;
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wire [3 :0] cpu_wrap_wstrb ;
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wire cpu_wrap_wlast ;
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wire cpu_wrap_wvalid ;
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wire cpu_wrap_wready ;
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wire [3 :0] cpu_wrap_bid ;
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wire [1 :0] cpu_wrap_bresp ;
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wire cpu_wrap_bvalid ;
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wire cpu_wrap_bready ;
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//axi ram
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wire [3 :0] ram_arid ;
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wire [31:0] ram_araddr ;
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wire [7 :0] ram_arlen ;
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wire [2 :0] ram_arsize ;
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wire [1 :0] ram_arburst;
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wire [1 :0] ram_arlock ;
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wire [3 :0] ram_arcache;
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wire [2 :0] ram_arprot ;
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wire ram_arvalid;
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wire ram_arready;
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wire [3 :0] ram_rid ;
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wire [31:0] ram_rdata ;
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wire [1 :0] ram_rresp ;
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wire ram_rlast ;
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wire ram_rvalid ;
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wire ram_rready ;
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wire [3 :0] ram_awid ;
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wire [31:0] ram_awaddr ;
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wire [7 :0] ram_awlen ;
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wire [2 :0] ram_awsize ;
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wire [1 :0] ram_awburst;
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wire [1 :0] ram_awlock ;
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wire [3 :0] ram_awcache;
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wire [2 :0] ram_awprot ;
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wire ram_awvalid;
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wire ram_awready;
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wire [3 :0] ram_wid ;
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wire [31:0] ram_wdata ;
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wire [3 :0] ram_wstrb ;
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wire ram_wlast ;
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wire ram_wvalid ;
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wire ram_wready ;
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wire [3 :0] ram_bid ;
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wire [1 :0] ram_bresp ;
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wire ram_bvalid ;
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wire ram_bready ;
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//conf
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wire [3 :0] conf_arid ;
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wire [31:0] conf_araddr ;
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wire [7 :0] conf_arlen ;
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wire [2 :0] conf_arsize ;
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wire [1 :0] conf_arburst;
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wire [1 :0] conf_arlock ;
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wire [3 :0] conf_arcache;
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wire [2 :0] conf_arprot ;
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wire conf_arvalid;
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wire conf_arready;
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wire [3 :0] conf_rid ;
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wire [31:0] conf_rdata ;
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wire [1 :0] conf_rresp ;
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wire conf_rlast ;
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wire conf_rvalid ;
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wire conf_rready ;
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wire [3 :0] conf_awid ;
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wire [31:0] conf_awaddr ;
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wire [7 :0] conf_awlen ;
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wire [2 :0] conf_awsize ;
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wire [1 :0] conf_awburst;
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wire [1 :0] conf_awlock ;
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wire [3 :0] conf_awcache;
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wire [2 :0] conf_awprot ;
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wire conf_awvalid;
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wire conf_awready;
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wire [3 :0] conf_wid ;
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wire [31:0] conf_wdata ;
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wire [3 :0] conf_wstrb ;
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wire conf_wlast ;
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wire conf_wvalid ;
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wire conf_wready ;
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wire [3 :0] conf_bid ;
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wire [1 :0] conf_bresp ;
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wire conf_bvalid ;
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wire conf_bready ;
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//for lab6
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wire [4 :0] ram_random_mask;
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//cpu axi
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mycpu_top u_cpu(
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2022-07-27 15:07:16 +08:00
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.ext_int (6'd0 ), //high active
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2022-07-29 17:44:11 +08:00
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.aclk (clk ),
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.aresetn (resetn ), //low active
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2022-07-27 15:07:16 +08:00
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.arid (cpu_arid ),
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.araddr (cpu_araddr ),
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.arlen (cpu_arlen ),
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.arsize (cpu_arsize ),
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.arburst (cpu_arburst ),
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.arlock (cpu_arlock ),
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.arcache (cpu_arcache ),
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.arprot (cpu_arprot ),
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.arvalid (cpu_arvalid ),
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.arready (cpu_arready ),
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.rid (cpu_rid ),
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.rdata (cpu_rdata ),
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.rresp (cpu_rresp ),
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.rlast (cpu_rlast ),
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.rvalid (cpu_rvalid ),
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.rready (cpu_rready ),
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2022-07-29 17:44:11 +08:00
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2022-07-27 15:07:16 +08:00
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.awid (cpu_awid ),
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.awaddr (cpu_awaddr ),
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.awlen (cpu_awlen ),
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.awsize (cpu_awsize ),
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.awburst (cpu_awburst ),
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.awlock (cpu_awlock ),
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.awcache (cpu_awcache ),
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.awprot (cpu_awprot ),
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.awvalid (cpu_awvalid ),
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.awready (cpu_awready ),
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2022-07-29 17:44:11 +08:00
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2022-07-27 15:07:16 +08:00
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.wid (cpu_wid ),
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.wdata (cpu_wdata ),
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.wstrb (cpu_wstrb ),
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.wlast (cpu_wlast ),
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.wvalid (cpu_wvalid ),
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.wready (cpu_wready ),
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2022-07-29 17:44:11 +08:00
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2022-07-27 15:07:16 +08:00
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.bid (cpu_bid ),
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.bresp (cpu_bresp ),
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.bvalid (cpu_bvalid ),
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.bready (cpu_bready ),
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//debug interface
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_wen (debug_wb_rf_wen ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata (debug_wb_rf_wdata ),
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.debug_wb1_pc (debug_wb1_pc ),
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.debug_wb1_rf_wen (debug_wb1_rf_wen ),
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.debug_wb1_rf_wnum (debug_wb1_rf_wnum ),
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.debug_wb1_rf_wdata(debug_wb1_rf_wdata),
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.debug_wb_pc_A (debug_wb_pc_A )
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2022-07-29 17:44:11 +08:00
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);
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2022-07-27 15:07:16 +08:00
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2022-07-29 17:44:11 +08:00
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//cpu axi wrap
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axi_wrap u_cpu_axi_wrap(
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.m_aclk ( clk ),
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.m_aresetn ( resetn ),
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//ar
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.m_arid ( cpu_arid ),
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.m_araddr ( cpu_araddr ),
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.m_arlen ( cpu_arlen ),
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.m_arsize ( cpu_arsize ),
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.m_arburst ( cpu_arburst ),
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.m_arlock ( cpu_arlock ),
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.m_arcache ( cpu_arcache ),
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.m_arprot ( cpu_arprot ),
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.m_arvalid ( cpu_arvalid ),
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.m_arready ( cpu_arready ),
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//r
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.m_rid ( cpu_rid ),
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.m_rdata ( cpu_rdata ),
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.m_rresp ( cpu_rresp ),
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.m_rlast ( cpu_rlast ),
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.m_rvalid ( cpu_rvalid ),
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.m_rready ( cpu_rready ),
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//aw
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.m_awid ( cpu_awid ),
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.m_awaddr ( cpu_awaddr ),
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.m_awlen ( cpu_awlen ),
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.m_awsize ( cpu_awsize ),
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.m_awburst ( cpu_awburst ),
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.m_awlock ( cpu_awlock ),
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.m_awcache ( cpu_awcache ),
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.m_awprot ( cpu_awprot ),
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.m_awvalid ( cpu_awvalid ),
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.m_awready ( cpu_awready ),
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//w
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.m_wid ( cpu_wid ),
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.m_wdata ( cpu_wdata ),
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.m_wstrb ( cpu_wstrb ),
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.m_wlast ( cpu_wlast ),
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.m_wvalid ( cpu_wvalid ),
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.m_wready ( cpu_wready ),
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//b
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.m_bid ( cpu_bid ),
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.m_bresp ( cpu_bresp ),
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.m_bvalid ( cpu_bvalid ),
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.m_bready ( cpu_bready ),
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.s_aclk ( cpu_wrap_aclk ),
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.s_aresetn ( cpu_wrap_aresetn ),
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//ar
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.s_arid ( cpu_wrap_arid ),
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.s_araddr ( cpu_wrap_araddr ),
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.s_arlen ( cpu_wrap_arlen ),
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.s_arsize ( cpu_wrap_arsize ),
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.s_arburst ( cpu_wrap_arburst ),
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.s_arlock ( cpu_wrap_arlock ),
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.s_arcache ( cpu_wrap_arcache ),
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.s_arprot ( cpu_wrap_arprot ),
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.s_arvalid ( cpu_wrap_arvalid ),
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.s_arready ( cpu_wrap_arready ),
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|
|
|
|
//r
|
|
|
|
|
.s_rid ( cpu_wrap_rid ),
|
|
|
|
|
.s_rdata ( cpu_wrap_rdata ),
|
|
|
|
|
.s_rresp ( cpu_wrap_rresp ),
|
|
|
|
|
.s_rlast ( cpu_wrap_rlast ),
|
|
|
|
|
.s_rvalid ( cpu_wrap_rvalid ),
|
|
|
|
|
.s_rready ( cpu_wrap_rready ),
|
|
|
|
|
//aw
|
|
|
|
|
.s_awid ( cpu_wrap_awid ),
|
|
|
|
|
.s_awaddr ( cpu_wrap_awaddr ),
|
|
|
|
|
.s_awlen ( cpu_wrap_awlen ),
|
|
|
|
|
.s_awsize ( cpu_wrap_awsize ),
|
|
|
|
|
.s_awburst ( cpu_wrap_awburst ),
|
|
|
|
|
.s_awlock ( cpu_wrap_awlock ),
|
|
|
|
|
.s_awcache ( cpu_wrap_awcache ),
|
|
|
|
|
.s_awprot ( cpu_wrap_awprot ),
|
|
|
|
|
.s_awvalid ( cpu_wrap_awvalid ),
|
|
|
|
|
.s_awready ( cpu_wrap_awready ),
|
|
|
|
|
//w
|
|
|
|
|
.s_wid ( cpu_wrap_wid ),
|
|
|
|
|
.s_wdata ( cpu_wrap_wdata ),
|
|
|
|
|
.s_wstrb ( cpu_wrap_wstrb ),
|
|
|
|
|
.s_wlast ( cpu_wrap_wlast ),
|
|
|
|
|
.s_wvalid ( cpu_wrap_wvalid ),
|
|
|
|
|
.s_wready ( cpu_wrap_wready ),
|
|
|
|
|
//b
|
|
|
|
|
.s_bid ( cpu_wrap_bid ),
|
|
|
|
|
.s_bresp ( cpu_wrap_bresp ),
|
|
|
|
|
.s_bvalid ( cpu_wrap_bvalid ),
|
|
|
|
|
.s_bready ( cpu_wrap_bready )
|
|
|
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|
);
|
|
|
|
|
|
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|
|
|
axi_crossbar u_axi_crossbar_1x2(
|
|
|
|
|
.clk ( clk ), // i, 1
|
|
|
|
|
.rst ( ~resetn ), // i, 1
|
|
|
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|
|
|
|
.s_axi_arid ( cpu_wrap_arid ),
|
|
|
|
|
.s_axi_araddr ( cpu_wrap_araddr ),
|
|
|
|
|
.s_axi_arlen ( cpu_wrap_arlen[3:0] ),
|
|
|
|
|
.s_axi_arsize ( cpu_wrap_arsize ),
|
|
|
|
|
.s_axi_arburst ( cpu_wrap_arburst ),
|
|
|
|
|
.s_axi_arlock ( cpu_wrap_arlock ),
|
|
|
|
|
.s_axi_arcache ( cpu_wrap_arcache ),
|
|
|
|
|
.s_axi_arprot ( cpu_wrap_arprot ),
|
|
|
|
|
.s_axi_arqos ( 4'd0 ),
|
|
|
|
|
.s_axi_arvalid ( cpu_wrap_arvalid ),
|
|
|
|
|
.s_axi_arready ( cpu_wrap_arready ),
|
|
|
|
|
.s_axi_rid ( cpu_wrap_rid ),
|
|
|
|
|
.s_axi_rdata ( cpu_wrap_rdata ),
|
|
|
|
|
.s_axi_rresp ( cpu_wrap_rresp ),
|
|
|
|
|
.s_axi_rlast ( cpu_wrap_rlast ),
|
|
|
|
|
.s_axi_rvalid ( cpu_wrap_rvalid ),
|
|
|
|
|
.s_axi_rready ( cpu_wrap_rready ),
|
|
|
|
|
.s_axi_awid ( cpu_wrap_awid ),
|
|
|
|
|
.s_axi_awaddr ( cpu_wrap_awaddr ),
|
|
|
|
|
.s_axi_awlen ( cpu_wrap_awlen[3:0] ),
|
|
|
|
|
.s_axi_awsize ( cpu_wrap_awsize ),
|
|
|
|
|
.s_axi_awburst ( cpu_wrap_awburst ),
|
|
|
|
|
.s_axi_awlock ( cpu_wrap_awlock ),
|
|
|
|
|
.s_axi_awcache ( cpu_wrap_awcache ),
|
|
|
|
|
.s_axi_awprot ( cpu_wrap_awprot ),
|
|
|
|
|
.s_axi_awqos ( 4'd0 ),
|
|
|
|
|
.s_axi_awvalid ( cpu_wrap_awvalid ),
|
|
|
|
|
.s_axi_awready ( cpu_wrap_awready ),
|
|
|
|
|
//.s_axi_wid ( cpu_wrap_wid ),
|
|
|
|
|
.s_axi_wdata ( cpu_wrap_wdata ),
|
|
|
|
|
.s_axi_wstrb ( cpu_wrap_wstrb ),
|
|
|
|
|
.s_axi_wlast ( cpu_wrap_wlast ),
|
|
|
|
|
.s_axi_wvalid ( cpu_wrap_wvalid ),
|
|
|
|
|
.s_axi_wready ( cpu_wrap_wready ),
|
|
|
|
|
.s_axi_bid ( cpu_wrap_bid ),
|
|
|
|
|
.s_axi_bresp ( cpu_wrap_bresp ),
|
|
|
|
|
.s_axi_bvalid ( cpu_wrap_bvalid ),
|
|
|
|
|
.s_axi_bready ( cpu_wrap_bready ),
|
|
|
|
|
|
|
|
|
|
.m_axi_arid ( {ram_arid ,conf_arid } ),
|
|
|
|
|
.m_axi_araddr ( {ram_araddr ,conf_araddr } ),
|
|
|
|
|
.m_axi_arlen ( {ram_arlen ,conf_arlen } ),
|
|
|
|
|
.m_axi_arsize ( {ram_arsize ,conf_arsize } ),
|
|
|
|
|
.m_axi_arburst ( {ram_arburst,conf_arburst} ),
|
|
|
|
|
.m_axi_arlock ( {ram_arlock ,conf_arlock } ),
|
|
|
|
|
.m_axi_arcache ( {ram_arcache,conf_arcache} ),
|
|
|
|
|
.m_axi_arprot ( {ram_arprot ,conf_arprot } ),
|
|
|
|
|
.m_axi_arqos ( ),
|
|
|
|
|
.m_axi_arvalid ( {ram_arvalid,conf_arvalid} ),
|
|
|
|
|
.m_axi_arready ( {ram_arready,conf_arready} ),
|
|
|
|
|
.m_axi_rid ( {ram_rid ,conf_rid } ),
|
|
|
|
|
.m_axi_rdata ( {ram_rdata ,conf_rdata } ),
|
|
|
|
|
.m_axi_rresp ( {ram_rresp ,conf_rresp } ),
|
|
|
|
|
.m_axi_rlast ( {ram_rlast ,conf_rlast } ),
|
|
|
|
|
.m_axi_rvalid ( {ram_rvalid ,conf_rvalid } ),
|
|
|
|
|
.m_axi_rready ( {ram_rready ,conf_rready } ),
|
|
|
|
|
.m_axi_awid ( {ram_awid ,conf_awid } ),
|
|
|
|
|
.m_axi_awaddr ( {ram_awaddr ,conf_awaddr } ),
|
|
|
|
|
.m_axi_awlen ( {ram_awlen ,conf_awlen } ),
|
|
|
|
|
.m_axi_awsize ( {ram_awsize ,conf_awsize } ),
|
|
|
|
|
.m_axi_awburst ( {ram_awburst,conf_awburst} ),
|
|
|
|
|
.m_axi_awlock ( {ram_awlock ,conf_awlock } ),
|
|
|
|
|
.m_axi_awcache ( {ram_awcache,conf_awcache} ),
|
|
|
|
|
.m_axi_awprot ( {ram_awprot ,conf_awprot } ),
|
|
|
|
|
.m_axi_awqos ( ),
|
|
|
|
|
.m_axi_awvalid ( {ram_awvalid,conf_awvalid} ),
|
|
|
|
|
.m_axi_awready ( {ram_awready,conf_awready} ),
|
|
|
|
|
//.m_axi_wid ( {ram_wid ,conf_wid } ),
|
|
|
|
|
.m_axi_wdata ( {ram_wdata ,conf_wdata } ),
|
|
|
|
|
.m_axi_wstrb ( {ram_wstrb ,conf_wstrb } ),
|
|
|
|
|
.m_axi_wlast ( {ram_wlast ,conf_wlast } ),
|
|
|
|
|
.m_axi_wvalid ( {ram_wvalid ,conf_wvalid } ),
|
|
|
|
|
.m_axi_wready ( {ram_wready ,conf_wready } ),
|
|
|
|
|
.m_axi_bid ( {ram_bid ,conf_bid } ),
|
|
|
|
|
.m_axi_bresp ( {ram_bresp ,conf_bresp } ),
|
|
|
|
|
.m_axi_bvalid ( {ram_bvalid ,conf_bvalid } ),
|
|
|
|
|
.m_axi_bready ( {ram_bready ,conf_bready } )
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
//axi ram
|
|
|
|
|
axi_wrap_ram u_axi_ram
|
|
|
|
|
(
|
|
|
|
|
.aclk ( clk ),
|
|
|
|
|
.aresetn ( resetn ),
|
2022-07-27 15:07:16 +08:00
|
|
|
//ar
|
|
|
|
|
.axi_arid ( ram_arid ),
|
|
|
|
|
.axi_araddr ( ram_araddr ),
|
|
|
|
|
.axi_arlen ( ram_arlen ),
|
|
|
|
|
.axi_arsize ( ram_arsize ),
|
|
|
|
|
.axi_arburst ( ram_arburst ),
|
|
|
|
|
.axi_arlock ( ram_arlock ),
|
|
|
|
|
.axi_arcache ( ram_arcache ),
|
|
|
|
|
.axi_arprot ( ram_arprot ),
|
|
|
|
|
.axi_arvalid ( ram_arvalid ),
|
|
|
|
|
.axi_arready ( ram_arready ),
|
|
|
|
|
//r
|
|
|
|
|
.axi_rid ( ram_rid ),
|
|
|
|
|
.axi_rdata ( ram_rdata ),
|
|
|
|
|
.axi_rresp ( ram_rresp ),
|
|
|
|
|
.axi_rlast ( ram_rlast ),
|
|
|
|
|
.axi_rvalid ( ram_rvalid ),
|
|
|
|
|
.axi_rready ( ram_rready ),
|
|
|
|
|
//aw
|
|
|
|
|
.axi_awid ( ram_awid ),
|
|
|
|
|
.axi_awaddr ( ram_awaddr ),
|
|
|
|
|
.axi_awlen ( {4'd0,ram_awlen[3:0]} ),
|
|
|
|
|
.axi_awsize ( ram_awsize ),
|
|
|
|
|
.axi_awburst ( ram_awburst ),
|
|
|
|
|
.axi_awlock ( ram_awlock ),
|
|
|
|
|
.axi_awcache ( ram_awcache ),
|
|
|
|
|
.axi_awprot ( ram_awprot ),
|
|
|
|
|
.axi_awvalid ( ram_awvalid ),
|
|
|
|
|
.axi_awready ( ram_awready ),
|
|
|
|
|
//w
|
|
|
|
|
.axi_wid ( ram_wid ),
|
|
|
|
|
.axi_wdata ( ram_wdata ),
|
|
|
|
|
.axi_wstrb ( ram_wstrb ),
|
|
|
|
|
.axi_wlast ( ram_wlast ),
|
|
|
|
|
.axi_wvalid ( ram_wvalid ),
|
|
|
|
|
.axi_wready ( ram_wready ),
|
|
|
|
|
//b ram
|
|
|
|
|
.axi_bid ( ram_bid ),
|
|
|
|
|
.axi_bresp ( ram_bresp ),
|
|
|
|
|
.axi_bvalid ( ram_bvalid ),
|
|
|
|
|
.axi_bready ( ram_bready ),
|
|
|
|
|
|
|
|
|
|
//random mask
|
|
|
|
|
.ram_random_mask ( ram_random_mask )
|
2022-07-29 17:44:11 +08:00
|
|
|
);
|
2022-07-27 15:07:16 +08:00
|
|
|
|
2022-07-29 17:44:11 +08:00
|
|
|
//confreg
|
|
|
|
|
confreg #(.SIMULATION(SIMULATION)) u_confreg
|
|
|
|
|
(
|
|
|
|
|
.timer_clk ( clk ), // i, 1
|
|
|
|
|
.aclk ( clk ), // i, 1
|
|
|
|
|
.aresetn ( resetn ), // i, 1
|
2022-07-27 15:07:16 +08:00
|
|
|
|
|
|
|
|
.arid (conf_arid ),
|
|
|
|
|
.araddr (conf_araddr ),
|
|
|
|
|
.arlen (conf_arlen ),
|
|
|
|
|
.arsize (conf_arsize ),
|
|
|
|
|
.arburst (conf_arburst ),
|
|
|
|
|
.arlock (conf_arlock ),
|
|
|
|
|
.arcache (conf_arcache ),
|
|
|
|
|
.arprot (conf_arprot ),
|
|
|
|
|
.arvalid (conf_arvalid ),
|
|
|
|
|
.arready (conf_arready ),
|
|
|
|
|
.rid (conf_rid ),
|
|
|
|
|
.rdata (conf_rdata ),
|
|
|
|
|
.rresp (conf_rresp ),
|
|
|
|
|
.rlast (conf_rlast ),
|
|
|
|
|
.rvalid (conf_rvalid ),
|
|
|
|
|
.rready (conf_rready ),
|
|
|
|
|
.awid (conf_awid ),
|
|
|
|
|
.awaddr (conf_awaddr ),
|
|
|
|
|
.awlen (conf_awlen ),
|
|
|
|
|
.awsize (conf_awsize ),
|
|
|
|
|
.awburst (conf_awburst ),
|
|
|
|
|
.awlock (conf_awlock ),
|
|
|
|
|
.awcache (conf_awcache ),
|
|
|
|
|
.awprot (conf_awprot ),
|
|
|
|
|
.awvalid (conf_awvalid ),
|
|
|
|
|
.awready (conf_awready ),
|
|
|
|
|
.wid (conf_wid ),
|
|
|
|
|
.wdata (conf_wdata ),
|
|
|
|
|
.wstrb (conf_wstrb ),
|
|
|
|
|
.wlast (conf_wlast ),
|
|
|
|
|
.wvalid (conf_wvalid ),
|
|
|
|
|
.wready (conf_wready ),
|
|
|
|
|
.bid (conf_bid ),
|
|
|
|
|
.bresp (conf_bresp ),
|
|
|
|
|
.bvalid (conf_bvalid ),
|
|
|
|
|
.bready (conf_bready ),
|
|
|
|
|
|
|
|
|
|
.ram_random_mask ( ram_random_mask ),
|
|
|
|
|
.led ( led ), // o, 16
|
|
|
|
|
.led_rg0 ( led_rg0 ), // o, 2
|
|
|
|
|
.led_rg1 ( led_rg1 ), // o, 2
|
|
|
|
|
.num_csn ( num_csn ), // o, 8
|
|
|
|
|
.num_a_g ( num_a_g ), // o, 7
|
|
|
|
|
.switch ( switch ), // i, 8
|
|
|
|
|
.btn_key_col ( btn_key_col), // o, 4
|
|
|
|
|
.btn_key_row ( btn_key_row), // i, 4
|
|
|
|
|
.btn_step ( btn_step ) // i, 2
|
2022-07-29 17:44:11 +08:00
|
|
|
);
|
2022-07-27 15:07:16 +08:00
|
|
|
|
|
|
|
|
endmodule
|
|
|
|
|
|
