151 lines
4.3 KiB
C
151 lines
4.3 KiB
C
#include "bflb_mtimer.h"
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#include "bflb_i2c.h"
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#include "bflb_dma.h"
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#include "board.h"
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#define EEPROM_TRANSFER_LENGTH 32
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#define EEPROM_SELECT_PAGE0 (0 << 5)
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struct bflb_device_s *i2c0;
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struct bflb_device_s *dma0_ch0;
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struct bflb_device_s *dma0_ch1;
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static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t send_buffer[8];
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static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t receive_buffer[8];
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static volatile uint32_t dma_tc_flag0 = 0;
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static volatile uint32_t dma_tc_flag1 = 0;
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void dma0_ch0_isr(void *arg)
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{
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dma_tc_flag0++;
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printf("Send done\r\n");
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}
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void dma0_ch1_isr(void *arg)
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{
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dma_tc_flag1++;
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printf("Receive done\r\n");
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}
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int main(void)
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{
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struct bflb_i2c_msg_s msgs[2];
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uint8_t subaddr[2] = { 0x00, EEPROM_SELECT_PAGE0};
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board_init();
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board_i2c0_gpio_init();
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/* Send and receive buffer init */
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for (size_t i = 0; i < 32; i++) {
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((uint8_t *)send_buffer)[i] = i;
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((uint8_t *)receive_buffer)[i] = 0;
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}
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i2c0 = bflb_device_get_by_name("i2c0");
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bflb_i2c_init(i2c0, 400000);
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bflb_i2c_link_txdma(i2c0, true);
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bflb_i2c_link_rxdma(i2c0, true);
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/* Write page 0 */
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dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
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struct bflb_dma_channel_config_s tx_config;
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tx_config.direction = DMA_MEMORY_TO_PERIPH;
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tx_config.src_req = DMA_REQUEST_NONE;
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tx_config.dst_req = DMA_REQUEST_I2C0_TX;
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tx_config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
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tx_config.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
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tx_config.src_burst_count = DMA_BURST_INCR1;
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tx_config.dst_burst_count = DMA_BURST_INCR1;
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tx_config.src_width = DMA_DATA_WIDTH_32BIT;
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tx_config.dst_width = DMA_DATA_WIDTH_32BIT;
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bflb_dma_channel_init(dma0_ch0, &tx_config);
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bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
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struct bflb_dma_channel_lli_pool_s tx_llipool[20]; /* max trasnfer size 4064 * 20 */
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struct bflb_dma_channel_lli_transfer_s tx_transfers[1];
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tx_transfers[0].src_addr = (uint32_t)send_buffer;
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tx_transfers[0].dst_addr = (uint32_t)DMA_ADDR_I2C0_TDR;
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tx_transfers[0].nbytes = 32;
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bflb_dma_channel_lli_reload(dma0_ch0, tx_llipool, 20, tx_transfers, 1);
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msgs[0].addr = 0x50;
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msgs[0].flags = I2C_M_NOSTOP;
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msgs[0].buffer = subaddr;
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msgs[0].length = 2;
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msgs[1].addr = 0x50;
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msgs[1].flags = I2C_M_DMA;
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msgs[1].buffer = NULL;
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msgs[1].length = 32;
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bflb_i2c_transfer(i2c0, msgs, 2);
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bflb_dma_channel_start(dma0_ch0);
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while (dma_tc_flag0 == 0) {
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}
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while ((bflb_i2c_get_intstatus(i2c0) & I2C_INT_END) == 0) {
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}
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bflb_i2c_deinit(i2c0);
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printf("write over\r\n");
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bflb_mtimer_delay_ms(100);
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/* Read page 0 */
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dma0_ch1 = bflb_device_get_by_name("dma0_ch1");
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struct bflb_dma_channel_config_s rx_config;
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rx_config.direction = DMA_PERIPH_TO_MEMORY;
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rx_config.src_req = DMA_REQUEST_I2C0_RX;
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rx_config.dst_req = DMA_REQUEST_NONE;
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rx_config.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
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rx_config.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
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rx_config.src_burst_count = DMA_BURST_INCR1;
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rx_config.dst_burst_count = DMA_BURST_INCR1;
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rx_config.src_width = DMA_DATA_WIDTH_32BIT;
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rx_config.dst_width = DMA_DATA_WIDTH_32BIT;
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bflb_dma_channel_init(dma0_ch1, &rx_config);
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bflb_dma_channel_irq_attach(dma0_ch1, dma0_ch1_isr, NULL);
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struct bflb_dma_channel_lli_pool_s rx_llipool[20];
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struct bflb_dma_channel_lli_transfer_s rx_transfers[1];
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rx_transfers[0].src_addr = (uint32_t)DMA_ADDR_I2C0_RDR;
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rx_transfers[0].dst_addr = (uint32_t)receive_buffer;
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rx_transfers[0].nbytes = 32;
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bflb_dma_channel_lli_reload(dma0_ch1, rx_llipool, 20, rx_transfers, 1);
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msgs[1].addr = 0x50;
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msgs[1].flags = I2C_M_DMA | I2C_M_READ;
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msgs[1].buffer = NULL;
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msgs[1].length = 32;
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bflb_i2c_transfer(i2c0, msgs, 2);
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bflb_dma_channel_start(dma0_ch1);
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while (dma_tc_flag1 == 0) {
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}
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while ((bflb_i2c_get_intstatus(i2c0) & I2C_INT_END) == 0) {
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}
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bflb_i2c_deinit(i2c0);
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printf("read over\r\n");
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/* Check read data */
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for (uint8_t i = 0; i < 32; i++) {
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if (((uint8_t *)send_buffer)[i] != ((uint8_t *)receive_buffer)[i]) {
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printf("check fail, %d write: %02x, read: %02x\r\n", i, ((uint8_t *)send_buffer)[i], ((uint8_t *)receive_buffer)[i]);
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}
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}
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printf("check over\r\n");
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printf("end\r\n");
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while(1){
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}
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}
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