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[update] update lhal, soc and demos

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This commit is contained in:
jzlv 2022-11-05 10:44:08 +08:00
parent d44726c783
commit c70a3cd8f0
80 changed files with 2206 additions and 323 deletions
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1
bsp/board/bl602dk/board.c
View File

@ -1,5 +1,4 @@
#include "bflb_uart.h"
#include "bflb_irq.h"
#include "bflb_gpio.h"
#include "bflb_clock.h"
#include "bflb_rtc.h"

8
bsp/board/bl616dk/bl616_flash.ld
View File

@ -141,13 +141,12 @@ SECTIONS
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
.nocache_ram_region : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
*(.noncacheable)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
@ -225,12 +224,13 @@ SECTIONS
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
__nocache_noinit_ram_data_start__ = .;
*(.nocache_noinit_ram)
*(.noncacheable)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
__nocache_noinit_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):

2
bsp/board/bl616dk/board.c
View File

@ -1,5 +1,4 @@
#include "bflb_uart.h"
#include "bflb_irq.h"
#include "bflb_gpio.h"
#include "bflb_clock.h"
#include "bflb_rtc.h"
@ -62,6 +61,7 @@ static void peripheral_clock_init(void)
GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
#ifdef CONFIG_BSP_SDH_SDCARD
PERIPHERAL_CLOCK_SDH_ENABLE();
GLB_Set_SDH_CLK(ENABLE, GLB_SDH_CLK_WIFIPLL_96M, 0);

1
bsp/board/bl702dk/board.c
View File

@ -1,5 +1,4 @@
#include "bflb_uart.h"
#include "bflb_irq.h"
#include "bflb_gpio.h"
#include "bflb_clock.h"
#include "bflb_rtc.h"

8
bsp/board/bl808dk/bl808_flash.ld
View File

@ -151,13 +151,12 @@ SECTIONS
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
.nocache_ram_region : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
*(.noncacheable)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
@ -235,12 +234,13 @@ SECTIONS
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
__nocache_noinit_ram_data_start__ = .;
*(.nocache_noinit_ram)
*(.noncacheable)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
__nocache_noinit_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):

2
bsp/board/bl808dk/board.c
View File

@ -1,5 +1,4 @@
#include "bflb_uart.h"
#include "bflb_irq.h"
#include "bflb_gpio.h"
#include "bflb_clock.h"
#include "bflb_rtc.h"
@ -73,6 +72,7 @@ static void peripheral_clock_init(void)
GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
#ifdef CONFIG_BSP_SDH_SDCARD
PERIPHERAL_CLOCK_SDH_ENABLE();
uint32_t tmp_val;

1
drivers/lhal/CMakeLists.txt
View File

@ -22,6 +22,7 @@ sdk_library_add_sources(src/bflb_sec_trng.c)
sdk_library_add_sources(src/bflb_timer.c)
sdk_library_add_sources(src/bflb_wdg.c)
sdk_library_add_sources(src/bflb_cks.c)
sdk_library_add_sources(src/bflb_mjpeg.c)
# sdk_library_add_sources(src/bflb_clock.c)
if(("${CHIP}" STREQUAL "bl702") OR ("${CHIP}" STREQUAL "bl602"))

2
drivers/lhal/config/bl602/device_table.c
View File

@ -44,7 +44,7 @@ struct bflb_device_s bl602_device_table[] = {
.idx = 0,
.dev_type = BFLB_DEVICE_TYPE_SPI,
.user_data = NULL },
{ .name = "pwm",
{ .name = "pwm0",
.reg_base = PWM_BASE,
.irq_num = BL602_IRQ_PWM,
.idx = 0,

14
drivers/lhal/config/bl616/device_table.c
View File

@ -177,6 +177,20 @@ struct bflb_device_s bl616_device_table[] = {
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_TIMER,
.user_data = NULL },
{ .name = "cks",
.reg_base = CKS_BASE,
.irq_num = 0,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CKS,
.user_data = NULL },
{ .name = "mjpeg",
.reg_base = MJPEG_BASE,
.irq_num = BL616_IRQ_MJPEG,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_MJPEG,
.user_data = NULL },
};
struct bflb_device_s *bflb_device_get_by_name(const char *name)

2
drivers/lhal/config/bl702/device_table.c
View File

@ -44,7 +44,7 @@ struct bflb_device_s bl702_device_table[] = {
.idx = 0,
.dev_type = BFLB_DEVICE_TYPE_SPI,
.user_data = NULL },
{ .name = "pwm",
{ .name = "pwm0",
.reg_base = PWM_BASE,
.irq_num = BL702_IRQ_PWM,
.idx = 0,

14
drivers/lhal/config/bl808/device_table.c
View File

@ -184,6 +184,20 @@ struct bflb_device_s bl808_device_table[] = {
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_IR,
.user_data = NULL },
{ .name = "cks",
.reg_base = CKS_BASE,
.irq_num = 0,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CKS,
.user_data = NULL },
{ .name = "mjpeg",
.reg_base = MJPEG_BASE,
.irq_num = BL808_IRQ_MJPEG,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_MJPEG,
.user_data = NULL },
};
struct bflb_device_s *bflb_device_get_by_name(const char *name)

43
drivers/lhal/include/bflb_adc.h
View File

@ -6,22 +6,33 @@
/** @defgroup ADC_CHANNEL adc channel definition
* @{
*/
#define ADC_CHANNEL_0 0
#define ADC_CHANNEL_1 1
#define ADC_CHANNEL_2 2
#define ADC_CHANNEL_3 3
#define ADC_CHANNEL_4 4
#define ADC_CHANNEL_5 5
#define ADC_CHANNEL_6 6
#define ADC_CHANNEL_7 7
#define ADC_CHANNEL_8 8
#define ADC_CHANNEL_9 9
#define ADC_CHANNEL_10 10
#define ADC_CHANNEL_11 11
#define ADC_CHAN_TSEN_P 14
#define ADC_CHAN_TSEN_N 15
#define ADC_CHAN_VABT_HALF 18
#define ADC_CHANNEL_GND 23
#define ADC_CHANNEL_0 0
#define ADC_CHANNEL_1 1
#define ADC_CHANNEL_2 2
#define ADC_CHANNEL_3 3
#define ADC_CHANNEL_4 4
#define ADC_CHANNEL_5 5
#define ADC_CHANNEL_6 6
#define ADC_CHANNEL_7 7
#if !defined(BL702L)
#define ADC_CHANNEL_8 8
#define ADC_CHANNEL_9 9
#define ADC_CHANNEL_10 10
#define ADC_CHANNEL_11 11
#define ADC_CHANNEL_DACA 12
#define ADC_CHANNEL_DACB 13
#define ADC_CHANNEL_TSEN_P 14
#define ADC_CHANNEL_TSEN_N 15
#define ADC_CHANNEL_VABT_HALF 18
#define ADC_CHANNEL_GND 23
#else
#define ADC_CHANNEL_DACA 8
#define ADC_CHANNEL_DACB 9
#define ADC_CHANNEL_VBAT 10
#define ADC_CHANNEL_TSEN 11
#define ADC_CHANNEL_VREF 12
#define ADC_CHANNEL_GND 13
#endif
/**
* @}
*/

2
drivers/lhal/include/bflb_core.h
View File

@ -13,6 +13,7 @@
#include <compiler/compiler_ld.h>
#include "bflb_list.h"
#include "bflb_mtimer.h"
#include "bflb_irq.h"
#include "bflb_common.h"
#if !defined(BL602) && !defined(BL702) && !defined(BL702L) && \
@ -61,6 +62,7 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin
#define BFLB_DEVICE_TYPE_TRNG 31
#define BFLB_DEVICE_TYPE_PKA 32
#define BFLB_DEVICE_TYPE_CKS 33
#define BFLB_DEVICE_TYPE_MJPEG 34
struct bflb_device_s {
const char *name;

20
drivers/lhal/include/bflb_dma.h
View File

@ -44,22 +44,28 @@
* @}
*/
#if defined(BL702)
#if defined(BL702) || defined(BL602) || defined(BL702L)
/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
* @{
*/
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
#if !defined(BL702L)
#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C)
#endif
#define DMA_ADDR_I2C0_TDR (0x4000A300 + 0x88)
#define DMA_ADDR_I2C0_RDR (0x4000A300 + 0x8C)
#define DMA_ADDR_SPI0_TDR (0x4000A200 + 0x88)
#define DMA_ADDR_SPI0_RDR (0x4000A200 + 0x8C)
#if !defined(BL702L)
#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
#endif
#define DMA_ADDR_ADC_RDR (0x40002000 + 0x04)
#define DMA_ADDR_DAC_TDR (0x40002000 + 0X48)
#if !defined(BL702L)
#define DMA_ADDR_DAC_TDR (0x40002000 + 0x48)
#endif
/**
* @}
*/
@ -70,16 +76,22 @@
#define DMA_REQUEST_NONE 0x00000000
#define DMA_REQUEST_UART0_RX 0x00000000
#define DMA_REQUEST_UART0_TX 0x00000001
#if !defined(BL702L)
#define DMA_REQUEST_UART1_RX 0x00000002
#define DMA_REQUEST_UART1_TX 0x00000003
#endif
#define DMA_REQUEST_I2C0_RX 0x00000006
#define DMA_REQUEST_I2C0_TX 0x00000007
#define DMA_REQUEST_SPI0_RX 0x0000000A
#define DMA_REQUEST_SPI0_TX 0x0000000B
#if !defined(BL702L)
#define DMA_REQUEST_I2S_RX 0x00000014
#define DMA_REQUEST_I2S_TX 0x00000015
#endif
#define DMA_REQUEST_ADC 0x00000016
#if !defined(BL702L)
#define DMA_REQUEST_DAC 0x00000017
#endif
/**
* @}
*/
@ -249,6 +261,10 @@
*/
#define DMA_CMD_SET_SRCADDR_INCREMENT (0x01)
#define DMA_CMD_SET_DSTADDR_INCREMENT (0x02)
#if !defined(BL602)
#define DMA_CMD_SET_ADD_MODE (0x03)
#define DMA_CMD_SET_REDUCE_MODE (0x04)
#endif
/**
* @}
*/

2
drivers/lhal/include/bflb_irq.h
View File

@ -1,7 +1,7 @@
#ifndef _BFLB_IRQ_H
#define _BFLB_IRQ_H
#include "bflb_core.h"
#include "stdint.h"
typedef void (*irq_callback)(int irq, void *arg);

85
drivers/lhal/include/bflb_mjpeg.h Normal file
View File

@ -0,0 +1,85 @@
#ifndef _BFLB_MJPEG_H
#define _BFLB_MJPEG_H
#include "bflb_core.h"
/** @defgroup MJPEG_FORMAT mjpeg format definition
* @{
*/
#define MJPEG_FORMAT_YUV422_YUYV 0
#define MJPEG_FORMAT_YUV422_YVYU 1
#define MJPEG_FORMAT_YUV422_UYVY 2
#define MJPEG_FORMAT_YUV422_VYUY 3
#define MJPEG_FORMAT_YUV422SP_NV16 4
#define MJPEG_FORMAT_YUV422SP_NV61 5
#define MJPEG_FORMAT_YUV420SP_NV12 6
#define MJPEG_FORMAT_YUV420SP_NV21 7
#define MJPEG_FORMAT_GRAY 8
/**
* @}
*/
/** @defgroup MJPEG_INTSTS mjpeg interrupt status definition
* @{
*/
#define MJPEG_INTSTS_ONE_FRAME (1 << 4)
/**
* @}
*/
/** @defgroup MJPEG_INTCLR mjpeg interrupt clear definition
* @{
*/
#define MJPEG_INTCLR_ONE_FRAME (1 << 8)
/**
* @}
*/
#define MJPEG_MAX_FRAME_COUNT 4
/**
* @brief MJPEG configuration structure
*
* @param format MJPEG format, use @ref MJPEG_FORMAT
* @param resolution_x MJPEG width, must be a multiple of 8 or a multiple of 16
* @param resolution_y MJPEG higth, must be a multiple of 8 or a multiple of 16
* @param input_bufaddr0 MJPEG input buffer address 0 for yy , must be align 16
* @param input_bufaddr1 MJPEG input buffer address 0 for yy , must be align 16
* @param output_bufaddr MJPEG output buffer address , must be align 16
* @param output_bufsize MJPEG output buffer size, must be larger than resolution_x*resolution_y*2*MJPEG_MAX_FRAME_COUNT
*/
struct bflb_mjpeg_config_s {
uint8_t format;
uint16_t resolution_x;
uint16_t resolution_y;
uint32_t input_bufaddr0;
uint32_t input_bufaddr1;
uint32_t output_bufaddr;
uint32_t output_bufsize;
};
#ifdef __cplusplus
extern "C" {
#endif
void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s *config);
void bflb_mjpeg_start(struct bflb_device_s *dev);
void bflb_mjpeg_stop(struct bflb_device_s *dev);
void bflb_mjpeg_sw_run(struct bflb_device_s *dev, uint8_t frame_count);
void bflb_mjpeg_tcint_mask(struct bflb_device_s *dev, bool mask);
void bflb_mjpeg_errint_mask(struct bflb_device_s *dev, bool mask);
uint32_t bflb_mjpeg_get_intstatus(struct bflb_device_s *dev);
void bflb_mjpeg_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
uint8_t bflb_mjpeg_get_frame_count(struct bflb_device_s *dev);
void bflb_mjpeg_pop_one_frame(struct bflb_device_s *dev);
uint32_t bflb_mjpeg_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
void bflb_mjpeg_calculate_quantize_table(uint8_t quality, uint16_t *input_table, uint16_t *output_table);
void bflb_mjpeg_fill_quantize_table(struct bflb_device_s *dev, uint16_t *input_yy, uint16_t *input_uv);
void bflb_mjpeg_fill_jpeg_header_tail(struct bflb_device_s *dev, uint8_t *header, uint32_t header_len);
void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, uint8_t uv);
#ifdef __cplusplus
}
#endif
#endif

7
drivers/lhal/include/bflb_sec_aes.h
View File

@ -9,10 +9,13 @@
#define AES_MODE_XTS 3
#define AES_LINK_KEY_128BITS 0
#define AES_LINK_KEY_192BITS 1
#define AES_LINK_KEY_256BITS 2
#define AES_LINK_KEY_192BITS 2
#define AES_LINK_KEY_256BITS 1
#define AES_LINK_KEY_DOUBLE_128BITS 3
#define AES_LINK_XTS_MODE1 0
#define AES_LINK_XTS_MODE2 1
struct bflb_aes_link_s {
uint32_t : 3; /*!< [2:0]Reserved */
uint32_t aes_key : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */

39
drivers/lhal/include/bflb_sec_dsa.h Normal file
View File

@ -0,0 +1,39 @@
#ifndef _BFLB_SEC_DSA_H
#define _BFLB_SEC_DSA_H
#include "bflb_core.h"
struct bflb_dsa_crt_s {
uint32_t *dP;
uint32_t *dQ;
uint32_t *qInv;
uint32_t *p;
uint32_t *invR_p;
uint32_t *primeN_p;
uint32_t *q;
uint32_t *invR_q;
uint32_t *primeN_q;
};
struct bflb_dsa_s {
uint32_t size;
uint32_t crtSize;
uint32_t *n;
uint32_t *e;
uint32_t *d;
struct bflb_dsa_crt_s crtCfg;
};
#ifdef __cplusplus
extern "C" {
#endif
int bflb_sec_dsa_init(struct bflb_dsa_s *handle, uint32_t size);
int bflb_sec_dsa_sign(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
int bflb_sec_dsa_verify(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
#ifdef __cplusplus
}
#endif
#endif

49
drivers/lhal/include/bflb_sec_sha.h
View File

@ -32,6 +32,27 @@ struct bflb_sha512_ctx_s {
uint8_t sha_feed; /*!< Sha has feed data */
};
struct bflb_sha1_link_ctx_s {
uint32_t total[2]; /*!< Number of bytes processed */
__attribute__((aligned(32))) uint8_t sha_buf[64]; /*!< Data not processed but in this temp buffer */
__attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
uint32_t link_addr; /*!< Link configure address */
};
struct bflb_sha256_link_ctx_s {
uint32_t total[2]; /*!< Number of bytes processed */
__attribute__((aligned(32))) uint8_t sha_buf[64]; /*!< Data not processed but in this temp buffer */
__attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
uint32_t link_addr; /*!< Link configure address */
};
struct bflb_sha512_link_ctx_s {
uint64_t total[2]; /*!< Number of bytes processed */
__attribute__((aligned(32))) uint8_t sha_buf[128]; /*!< Data not processed but in this temp buffer */
__attribute__((aligned(32))) uint8_t sha_padding[128]; /*!< Padding data */
uint32_t link_addr; /*!< Link configure address */
};
struct bflb_sha_link_s {
uint32_t : 2; /*!< [1:0]Reserved */
uint32_t sha_mode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */
@ -58,42 +79,36 @@ void bflb_sha256_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx)
void bflb_sha512_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx);
int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, const uint8_t *input, uint32_t len);
int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, const uint8_t *input, uint32_t len);
int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint32_t len);
int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint64_t len);
void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, uint8_t *output);
void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output);
void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output);
void bflb_sha_link_init(struct bflb_device_s *dev);
void bflb_sha_link_deinit(struct bflb_device_s *dev);
void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx);
void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx);
void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx);
void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_link_ctx_s *ctx, struct bflb_sha_link_s *link);
void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_link_ctx_s *ctx, struct bflb_sha_link_s *link);
void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_link_ctx_s *ctx, struct bflb_sha_link_s *link);
int bflb_sha1_link_update(struct bflb_device_s *dev,
struct bflb_sha1_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha1_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len);
int bflb_sha256_link_update(struct bflb_device_s *dev,
struct bflb_sha256_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha256_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len);
int bflb_sha512_link_update(struct bflb_device_s *dev,
struct bflb_sha512_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha512_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len);
uint64_t len);
void bflb_sha1_link_finish(struct bflb_device_s *dev,
struct bflb_sha1_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha1_link_ctx_s *ctx,
uint8_t *output);
void bflb_sha256_link_finish(struct bflb_device_s *dev,
struct bflb_sha256_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha256_link_ctx_s *ctx,
uint8_t *output);
void bflb_sha512_link_finish(struct bflb_device_s *dev,
struct bflb_sha512_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha512_link_ctx_s *ctx,
uint8_t *output);
void bflb_group0_request_sha_access(struct bflb_device_s *dev);

11
drivers/lhal/include/bflb_uart.h
View File

@ -133,6 +133,7 @@
#define UART_CMD_SET_TX_RS485_POLARITY (0x12)
#define UART_CMD_SET_ABR_ALLOWABLE_ERROR (0x13)
#define UART_CMD_SET_SW_RTS_CONTROL (0x14)
#define UART_CMD_IR_CONFIG (0x15)
/**
* @}
*/
@ -140,6 +141,16 @@
#define UART_AUTO_BAUD_START 0
#define UART_AUTO_BAUD_0X55 1
struct bflb_uart_ir_config_s {
bool tx_en;
bool rx_en;
bool tx_inverse;
bool rx_inverse;
uint16_t tx_pluse_start;
uint16_t tx_pluse_stop;
uint16_t rx_pluse_start;
};
/**
* @brief UART configuration structure
*

17
drivers/lhal/include/hardware/dma_reg.h
View File

@ -137,17 +137,34 @@
#define DMA_TRANSFERSIZE_SHIFT (0U)
#define DMA_TRANSFERSIZE_MASK (0xfff << DMA_TRANSFERSIZE_SHIFT)
#define DMA_SBSIZE_SHIFT (12U)
#if defined(BL602)
#define DMA_SBSIZE_MASK (0x7 << DMA_SBSIZE_SHIFT)
#else
#define DMA_SBSIZE_MASK (0x3 << DMA_SBSIZE_SHIFT)
#define DMA_DST_MIN_MODE (1 << 14U)
#endif
#define DMA_DBSIZE_SHIFT (15U)
#if defined(BL602)
#define DMA_DBSIZE_MASK (0x7 << DMA_DBSIZE_SHIFT)
#else
#define DMA_DBSIZE_MASK (0x3 << DMA_DBSIZE_SHIFT)
#define DMA_DST_ADD_MODE (1 << 17U)
#endif
#define DMA_SWIDTH_SHIFT (18U)
#if defined(BL602)
#define DMA_SWIDTH_MASK (0x7 << DMA_SWIDTH_SHIFT)
#else
#define DMA_SWIDTH_MASK (0x3 << DMA_SWIDTH_SHIFT)
#endif
#define DMA_DWIDTH_SHIFT (21U)
#if defined(BL602)
#define DMA_DWIDTH_MASK (0x7 << DMA_DWIDTH_SHIFT)
#define DMA_SLARGERD (1 << 24U)
#else
#define DMA_DWIDTH_MASK (0x3 << DMA_DWIDTH_SHIFT)
#define DMA_FIX_CNT_SHIFT (23U)
#define DMA_FIX_CNT_MASK (0x7 << DMA_FIX_CNT_SHIFT)
#endif
#define DMA_SI (1 << 26U)
#define DMA_DI (1 << 27U)
#define DMA_PROT_SHIFT (28U)

319
drivers/lhal/include/hardware/mjpeg_reg.h Normal file
View File

@ -0,0 +1,319 @@
/**
******************************************************************************
* @file mjpeg_reg.h
* @version V1.0
* @date 2022-11-01
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_MJPEG_REG_H__
#define __HARDWARE_MJPEG_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define MJPEG_CONTROL_1_OFFSET (0x0)/* mjpeg_control_1 */
#define MJPEG_CONTROL_2_OFFSET (0x4)/* mjpeg_control_2 */
#define MJPEG_YY_FRAME_ADDR_OFFSET (0x08)/* mjpeg_yy_frame_addr */
#define MJPEG_UV_FRAME_ADDR_OFFSET (0x0C)/* mjpeg_uv_frame_addr */
#define MJPEG_YUV_MEM_OFFSET (0x10)/* mjpeg_yuv_mem */
#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14)/* jpeg_frame_addr */
#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18)/* jpeg_store_memory */
#define MJPEG_CONTROL_3_OFFSET (0x1C)/* mjpeg_control_3 */
#define MJPEG_FRAME_FIFO_POP_OFFSET (0x20)/* mjpeg_frame_fifo_pop */
#define MJPEG_FRAME_SIZE_OFFSET (0x24)/* mjpeg_frame_size */
#define MJPEG_HEADER_BYTE_OFFSET (0x28)/* mjpeg_header_byte */
#define MJPEG_SWAP_MODE_OFFSET (0x30)/* mjpeg_swap_mode */
#define MJPEG_SWAP_BIT_CNT_OFFSET (0x34)/* mjpeg_swap_bit_cnt */
#define MJPEG_YUV_MEM_SW_OFFSET (0x38)/* mjpeg_yuv_mem_sw */
#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40)/* mjpeg_Y_frame_read_status_1 */
#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44)/* mjpeg_Y_frame_read_status_2 */
#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48)/* mjpeg_Y_frame_write_status */
#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C)/* mjpeg_UV_frame_read_status_1 */
#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50)/* mjpeg_UV_frame_read_status_2 */
#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54)/* mjpeg_UV_frame_write_status */
#define MJPEG_FRAME_W_HBLK_STATUS_OFFSET (0x58)/* mjpeg_frame_w_hblk_status */
#define MJPEG_START_ADDR0_OFFSET (0x80)/* mjpeg_start_addr0 */
#define MJPEG_BIT_CNT0_OFFSET (0x84)/* mjpeg_bit_cnt0 */
#define MJPEG_START_ADDR1_OFFSET (0x88)/* mjpeg_start_addr1 */
#define MJPEG_BIT_CNT1_OFFSET (0x8C)/* mjpeg_bit_cnt1 */
#define MJPEG_START_ADDR2_OFFSET (0x90)/* mjpeg_start_addr2 */
#define MJPEG_BIT_CNT2_OFFSET (0x94)/* mjpeg_bit_cnt2 */
#define MJPEG_START_ADDR3_OFFSET (0x98)/* mjpeg_start_addr3 */
#define MJPEG_BIT_CNT3_OFFSET (0x9C)/* mjpeg_bit_cnt3 */
#define MJPEG_Q_ENC_OFFSET (0x100)/* mjpeg_q_enc */
#define MJPEG_FRAME_ID_10_OFFSET (0x110)/* mjpeg_frame_id_10 */
#define MJPEG_FRAME_ID_32_OFFSET (0x114)/* mjpeg_frame_id_32 */
#define MJPEG_DEBUG_OFFSET (0x1F0)/* mjpeg_debug */
#define MJPEG_DUMMY_REG_OFFSET (0x1FC)/* mjpeg_dummy_reg */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : mjpeg_control_1 */
#define MJPEG_REG_MJPEG_ENABLE (1<<0U)
#define MJPEG_REG_MJPEG_BIT_ORDER (1<<1U)
#define MJPEG_REG_ORDER_U_EVEN (1<<2U)
#define MJPEG_REG_HW_MODE_SWEN (1<<3U)
#define MJPEG_REG_LAST_HF_WBLK_DMY (1<<4U)
#define MJPEG_REG_LAST_HF_HBLK_DMY (1<<5U)
#define MJPEG_REG_REFLECT_DMY (1<<6U)
#define MJPEG_REG_READ_FWRAP (1<<7U)
#define MJPEG_REG_W_XLEN_SHIFT (8U)
#define MJPEG_REG_W_XLEN_MASK (0x7<<MJPEG_REG_W_XLEN_SHIFT)
#define MJPEG_REG_YUV_MODE_SHIFT (12U)
#define MJPEG_REG_YUV_MODE_MASK (0x3<<MJPEG_REG_YUV_MODE_SHIFT)
#define MJPEG_REG_MJPEG_HW_FRAME_SHIFT (24U)
#define MJPEG_REG_MJPEG_HW_FRAME_MASK (0x3f<<MJPEG_REG_MJPEG_HW_FRAME_SHIFT)
/* 0x4 : mjpeg_control_2 */
#define MJPEG_REG_SW_FRAME_SHIFT (0U)
#define MJPEG_REG_SW_FRAME_MASK (0x1f<<MJPEG_REG_SW_FRAME_SHIFT)
#define MJPEG_REG_SW_KICK (1<<6U)
#define MJPEG_REG_SW_KICK_MODE (1<<7U)
#define MJPEG_REG_MJPEG_SW_MODE (1<<8U)
#define MJPEG_REG_MJPEG_SW_RUN (1<<9U)
#define MJPEG_REG_YY_DVP2AXI_SEL_SHIFT (10U)
#define MJPEG_REG_YY_DVP2AXI_SEL_MASK (0x7<<MJPEG_REG_YY_DVP2AXI_SEL_SHIFT)
#define MJPEG_REG_UV_DVP2AXI_SEL_SHIFT (13U)
#define MJPEG_REG_UV_DVP2AXI_SEL_MASK (0x7<<MJPEG_REG_UV_DVP2AXI_SEL_SHIFT)
#define MJPEG_REG_MJPEG_WAIT_CYCLE_SHIFT (16U)
#define MJPEG_REG_MJPEG_WAIT_CYCLE_MASK (0xffff<<MJPEG_REG_MJPEG_WAIT_CYCLE_SHIFT)
/* 0x08 : mjpeg_yy_frame_addr */
#define MJPEG_REG_YY_ADDR_START_SHIFT (0U)
#define MJPEG_REG_YY_ADDR_START_MASK (0xffffffff<<MJPEG_REG_YY_ADDR_START_SHIFT)
/* 0x0C : mjpeg_uv_frame_addr */
#define MJPEG_REG_UV_ADDR_START_SHIFT (0U)
#define MJPEG_REG_UV_ADDR_START_MASK (0xffffffff<<MJPEG_REG_UV_ADDR_START_SHIFT)
/* 0x10 : mjpeg_yuv_mem */
#define MJPEG_REG_YY_MEM_HBLK_SHIFT (0U)
#define MJPEG_REG_YY_MEM_HBLK_MASK (0x1fff<<MJPEG_REG_YY_MEM_HBLK_SHIFT)
#define MJPEG_REG_UV_MEM_HBLK_SHIFT (16U)
#define MJPEG_REG_UV_MEM_HBLK_MASK (0x1fff<<MJPEG_REG_UV_MEM_HBLK_SHIFT)
/* 0x14 : jpeg_frame_addr */
#define MJPEG_REG_W_ADDR_START_SHIFT (0U)
#define MJPEG_REG_W_ADDR_START_MASK (0xffffffff<<MJPEG_REG_W_ADDR_START_SHIFT)
/* 0x18 : jpeg_store_memory */
#define MJPEG_REG_W_BURST_CNT_SHIFT (0U)
#define MJPEG_REG_W_BURST_CNT_MASK (0xffffffff<<MJPEG_REG_W_BURST_CNT_SHIFT)
/* 0x1C : mjpeg_control_3 */
#define MJPEG_REG_INT_NORMAL_EN (1<<0U)
#define MJPEG_REG_INT_CAM_EN (1<<1U)
#define MJPEG_REG_INT_MEM_EN (1<<2U)
#define MJPEG_REG_INT_FRAME_EN (1<<3U)
#define MJPEG_STS_NORMAL_INT (1<<4U)
#define MJPEG_STS_CAM_INT (1<<5U)
#define MJPEG_STS_MEM_INT (1<<6U)
#define MJPEG_STS_FRAME_INT (1<<7U)
#define MJPEG_IDLE (1<<8U)
#define MJPEG_FUNC (1<<9U)
#define MJPEG_WAIT (1<<10U)
#define MJPEG_FLSH (1<<11U)
#define MJPEG_MANS (1<<12U)
#define MJPEG_MANF (1<<13U)
#define MJPEG_AXI_READ_IDLE (1<<14U)
#define MJPEG_AXI_WRITE_IDLE (1<<15U)
#define MJPEG_REG_FRAME_CNT_TRGR_INT_SHIFT (16U)
#define MJPEG_REG_FRAME_CNT_TRGR_INT_MASK (0x1f<<MJPEG_REG_FRAME_CNT_TRGR_INT_SHIFT)
#define MJPEG_REG_INT_IDLE_EN (1<<21U)
#define MJPEG_STS_IDLE_INT (1<<22U)
#define MJPEG_FRAME_VALID_CNT_SHIFT (24U)
#define MJPEG_FRAME_VALID_CNT_MASK (0x1f<<MJPEG_FRAME_VALID_CNT_SHIFT)
#define MJPEG_REG_INT_SWAP_EN (1<<29U)
#define MJPEG_STS_SWAP_INT (1<<30U)
/* 0x20 : mjpeg_frame_fifo_pop */
#define MJPEG_RFIFO_POP (1<<0U)
#define MJPEG_REG_W_SWAP_CLR (1<<1U)
#define MJPEG_REG_INT_NORMAL_CLR (1<<8U)
#define MJPEG_REG_INT_CAM_CLR (1<<9U)
#define MJPEG_REG_INT_MEM_CLR (1<<10U)
#define MJPEG_REG_INT_FRAME_CLR (1<<11U)
#define MJPEG_REG_INT_IDLE_CLR (1<<12U)
#define MJPEG_REG_INT_SWAP_CLR (1<<13U)
/* 0x24 : mjpeg_frame_size */
#define MJPEG_REG_FRAME_WBLK_SHIFT (0U)
#define MJPEG_REG_FRAME_WBLK_MASK (0xfff<<MJPEG_REG_FRAME_WBLK_SHIFT)
#define MJPEG_REG_FRAME_HBLK_SHIFT (16U)
#define MJPEG_REG_FRAME_HBLK_MASK (0xfff<<MJPEG_REG_FRAME_HBLK_SHIFT)
/* 0x28 : mjpeg_header_byte */
#define MJPEG_REG_HEAD_BYTE_SHIFT (0U)
#define MJPEG_REG_HEAD_BYTE_MASK (0xfff<<MJPEG_REG_HEAD_BYTE_SHIFT)
#define MJPEG_REG_TAIL_EXP (1<<16U)
#define MJPEG_REG_Y0_ORDER_SHIFT (24U)
#define MJPEG_REG_Y0_ORDER_MASK (0x3<<MJPEG_REG_Y0_ORDER_SHIFT)
#define MJPEG_REG_U0_ORDER_SHIFT (26U)
#define MJPEG_REG_U0_ORDER_MASK (0x3<<MJPEG_REG_U0_ORDER_SHIFT)
#define MJPEG_REG_Y1_ORDER_SHIFT (28U)
#define MJPEG_REG_Y1_ORDER_MASK (0x3<<MJPEG_REG_Y1_ORDER_SHIFT)
#define MJPEG_REG_V0_ORDER_SHIFT (30U)
#define MJPEG_REG_V0_ORDER_MASK (0x3<<MJPEG_REG_V0_ORDER_SHIFT)
/* 0x30 : mjpeg_swap_mode */
#define MJPEG_REG_W_SWAP_MODE (1<<0U)
#define MJPEG_STS_SWAP0_FULL (1<<8U)
#define MJPEG_STS_SWAP1_FULL (1<<9U)
#define MJPEG_STS_READ_SWAP_IDX (1<<10U)
#define MJPEG_STS_SWAP_FSTART (1<<11U)
#define MJPEG_STS_SWAP_FEND (1<<12U)
/* 0x34 : mjpeg_swap_bit_cnt */
#define MJPEG_FRAME_SWAP_END_BIT_CNT_SHIFT (0U)
#define MJPEG_FRAME_SWAP_END_BIT_CNT_MASK (0xffffffff<<MJPEG_FRAME_SWAP_END_BIT_CNT_SHIFT)
/* 0x38 : mjpeg_yuv_mem_sw */
#define MJPEG_REG_SW_KICK_HBLK_SHIFT (0U)
#define MJPEG_REG_SW_KICK_HBLK_MASK (0x1fff<<MJPEG_REG_SW_KICK_HBLK_SHIFT)
/* 0x40 : mjpeg_Y_frame_read_status_1 */
#define MJPEG_YY_MEM_HBLK_R_SHIFT (0U)
#define MJPEG_YY_MEM_HBLK_R_MASK (0x1fff<<MJPEG_YY_MEM_HBLK_R_SHIFT)
#define MJPEG_YY_FRM_HBLK_R_SHIFT (16U)
#define MJPEG_YY_FRM_HBLK_R_MASK (0x1fff<<MJPEG_YY_FRM_HBLK_R_SHIFT)
/* 0x44 : mjpeg_Y_frame_read_status_2 */
#define MJPEG_YY_WBLK_R_SHIFT (0U)
#define MJPEG_YY_WBLK_R_MASK (0x1fff<<MJPEG_YY_WBLK_R_SHIFT)
#define MJPEG_YY_MEM_RND_R_SHIFT (16U)
#define MJPEG_YY_MEM_RND_R_MASK (0xff<<MJPEG_YY_MEM_RND_R_SHIFT)
#define MJPEG_YY_FRM_CNT_R_SHIFT (24U)
#define MJPEG_YY_FRM_CNT_R_MASK (0xff<<MJPEG_YY_FRM_CNT_R_SHIFT)
/* 0x48 : mjpeg_Y_frame_write_status */
#define MJPEG_YY_MEM_HBLK_W_SHIFT (0U)
#define MJPEG_YY_MEM_HBLK_W_MASK (0x1fff<<MJPEG_YY_MEM_HBLK_W_SHIFT)
#define MJPEG_YY_MEM_RND_W_SHIFT (16U)
#define MJPEG_YY_MEM_RND_W_MASK (0xff<<MJPEG_YY_MEM_RND_W_SHIFT)
#define MJPEG_YY_FRM_CNT_W_SHIFT (24U)
#define MJPEG_YY_FRM_CNT_W_MASK (0xff<<MJPEG_YY_FRM_CNT_W_SHIFT)
/* 0x4C : mjpeg_UV_frame_read_status_1 */
#define MJPEG_UV_MEM_HBLK_R_SHIFT (0U)
#define MJPEG_UV_MEM_HBLK_R_MASK (0x1fff<<MJPEG_UV_MEM_HBLK_R_SHIFT)
#define MJPEG_UV_FRM_HBLK_R_SHIFT (16U)
#define MJPEG_UV_FRM_HBLK_R_MASK (0x1fff<<MJPEG_UV_FRM_HBLK_R_SHIFT)
/* 0x50 : mjpeg_UV_frame_read_status_2 */
#define MJPEG_UV_WBLK_R_SHIFT (0U)
#define MJPEG_UV_WBLK_R_MASK (0x1fff<<MJPEG_UV_WBLK_R_SHIFT)
#define MJPEG_UV_MEM_RND_R_SHIFT (16U)
#define MJPEG_UV_MEM_RND_R_MASK (0xff<<MJPEG_UV_MEM_RND_R_SHIFT)
#define MJPEG_UV_FRM_CNT_R_SHIFT (24U)
#define MJPEG_UV_FRM_CNT_R_MASK (0xff<<MJPEG_UV_FRM_CNT_R_SHIFT)
/* 0x54 : mjpeg_UV_frame_write_status */
#define MJPEG_UV_MEM_HBLK_W_SHIFT (0U)
#define MJPEG_UV_MEM_HBLK_W_MASK (0x1fff<<MJPEG_UV_MEM_HBLK_W_SHIFT)
#define MJPEG_UV_MEM_RND_W_SHIFT (16U)
#define MJPEG_UV_MEM_RND_W_MASK (0xff<<MJPEG_UV_MEM_RND_W_SHIFT)
#define MJPEG_UV_FRM_CNT_W_SHIFT (24U)
#define MJPEG_UV_FRM_CNT_W_MASK (0xff<<MJPEG_UV_FRM_CNT_W_SHIFT)
/* 0x58 : mjpeg_frame_w_hblk_status */
#define MJPEG_YY_FRM_HBLK_W_SHIFT (0U)
#define MJPEG_YY_FRM_HBLK_W_MASK (0x1fff<<MJPEG_YY_FRM_HBLK_W_SHIFT)
#define MJPEG_UV_FRM_HBLK_W_SHIFT (16U)
#define MJPEG_UV_FRM_HBLK_W_MASK (0x1fff<<MJPEG_UV_FRM_HBLK_W_SHIFT)
/* 0x80 : mjpeg_start_addr0 */
#define MJPEG_FRAME_START_ADDR_0_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_0_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_0_SHIFT)
/* 0x84 : mjpeg_bit_cnt0 */
#define MJPEG_FRAME_BIT_CNT_0_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_0_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_0_SHIFT)
/* 0x88 : mjpeg_start_addr1 */
#define MJPEG_FRAME_START_ADDR_1_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_1_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_1_SHIFT)
/* 0x8C : mjpeg_bit_cnt1 */
#define MJPEG_FRAME_BIT_CNT_1_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_1_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_1_SHIFT)
/* 0x90 : mjpeg_start_addr2 */
#define MJPEG_FRAME_START_ADDR_2_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_2_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_2_SHIFT)
/* 0x94 : mjpeg_bit_cnt2 */
#define MJPEG_FRAME_BIT_CNT_2_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_2_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_2_SHIFT)
/* 0x98 : mjpeg_start_addr3 */
#define MJPEG_FRAME_START_ADDR_3_SHIFT (0U)
#define MJPEG_FRAME_START_ADDR_3_MASK (0xffffffff<<MJPEG_FRAME_START_ADDR_3_SHIFT)
/* 0x9C : mjpeg_bit_cnt3 */
#define MJPEG_FRAME_BIT_CNT_3_SHIFT (0U)
#define MJPEG_FRAME_BIT_CNT_3_MASK (0xffffffff<<MJPEG_FRAME_BIT_CNT_3_SHIFT)
/* 0x100 : mjpeg_q_enc */
#define MJPEG_FRAME_Q_SRAM_0 (1<<0U)
#define MJPEG_FRAME_Q_SRAM_1 (1<<1U)
#define MJPEG_FRAME_Q_SRAM_2 (1<<2U)
#define MJPEG_FRAME_Q_SRAM_3 (1<<3U)
#define MJPEG_REG_Q_SRAM_SW (1<<24U)
#define MJPEG_STS_Q_SRAM_ENC (1<<25U)
/* 0x110 : mjpeg_frame_id_10 */
#define MJPEG_FRAME_ID_0_SHIFT (0U)
#define MJPEG_FRAME_ID_0_MASK (0xffff<<MJPEG_FRAME_ID_0_SHIFT)
#define MJPEG_FRAME_ID_1_SHIFT (16U)
#define MJPEG_FRAME_ID_1_MASK (0xffff<<MJPEG_FRAME_ID_1_SHIFT)
/* 0x114 : mjpeg_frame_id_32 */
#define MJPEG_FRAME_ID_2_SHIFT (0U)
#define MJPEG_FRAME_ID_2_MASK (0xffff<<MJPEG_FRAME_ID_2_SHIFT)
#define MJPEG_FRAME_ID_3_SHIFT (16U)
#define MJPEG_FRAME_ID_3_MASK (0xffff<<MJPEG_FRAME_ID_3_SHIFT)
/* 0x1F0 : mjpeg_debug */
#define MJPEG_REG_MJPEG_DBG_EN (1<<0U)
#define MJPEG_REG_MJPEG_DBG_SEL_SHIFT (4U)
#define MJPEG_REG_MJPEG_DBG_SEL_MASK (0xf<<MJPEG_REG_MJPEG_DBG_SEL_SHIFT)
#define MJPEG_REG_ID_LATCH_HBLK_SHIFT (8U)
#define MJPEG_REG_ID_LATCH_HBLK_MASK (0xf<<MJPEG_REG_ID_LATCH_HBLK_SHIFT)
/* 0x1FC : mjpeg_dummy_reg */
#define MJPEG_DUMMY_REG_SHIFT (0U)
#define MJPEG_DUMMY_REG_MASK (0xffffffff<<MJPEG_DUMMY_REG_SHIFT)
#endif /* __HARDWARE_MJPEG_REG_H__ */

7
drivers/lhal/include/hardware/pwm_v1_reg.h
View File

@ -41,8 +41,11 @@
****************************************************************************/
/* Register offsets *********************************************************/
#define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */
#if defined(BL702L)
#define PWM_INT_CONFIG_OFFSET (-0x20) /* pwm_int_config */
#else
#define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */
#endif
#define PWM0_CLKDIV_OFFSET (0x20) /* pwm0_clkdiv */
#define PWM0_THRE1_OFFSET (0x24) /* pwm0_thre1 */
#define PWM0_THRE2_OFFSET (0x28) /* pwm0_thre2 */

50
drivers/lhal/src/bflb_dma.c
View File

@ -1,6 +1,5 @@
#include "bflb_dma.h"
#include "bflb_l1c.h"
#include "bflb_irq.h"
#include "hardware/dma_reg.h"
struct bflb_dma_irq_callback {
@ -73,9 +72,9 @@ void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_chan
channel_base = dev->reg_base;
/* dma global disable */
/* dma global enable */
regval = getreg32(dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
regval &= ~DMA_E;
regval |= DMA_E;
putreg32(regval, dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
/* dma channel disable */
@ -83,7 +82,12 @@ void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_chan
regval &= ~DMA_E;
putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
#if defined(BL602)
regval = 0;
#else
regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
regval &= DMA_DST_ADD_MODE | DMA_DST_MIN_MODE | DMA_FIX_CNT_MASK;
#endif
if (config->src_addr_inc) {
regval |= DMA_SI;
@ -108,10 +112,18 @@ void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_chan
regval |= (config->direction << DMA_FLOWCNTRL_SHIFT);
putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
/* dma global enable */
regval = getreg32(dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
regval |= DMA_E;
putreg32(regval, dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
/* disable dma error and tc interrupt */
regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
regval |= (DMA_ITC | DMA_IE);
putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
regval &= ~DMA_I;
putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
/* clear irq status */
putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTTCCLEAR_OFFSET);
putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTERRCLR_OFFSET);
#if (defined(BL606P) || defined(BL808)) && (defined(CPU_M0) || defined(CPU_LP))
bflb_irq_attach(31, dma0_isr, NULL);
@ -394,6 +406,30 @@ int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
break;
#if !defined(BL602)
case DMA_CMD_SET_ADD_MODE:
regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
if (arg) {
regval |= DMA_DST_ADD_MODE;
} else {
regval &= ~DMA_DST_ADD_MODE;
}
putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
break;
case DMA_CMD_SET_REDUCE_MODE:
regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
if (arg) {
regval |= DMA_DST_MIN_MODE;
regval &= ~DMA_FIX_CNT_MASK;
regval |= (arg & 0x7) << DMA_FIX_CNT_SHIFT;
} else {
regval &= ~DMA_DST_MIN_MODE;
}
putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
break;
#endif
default:
ret = -EPERM;
break;

1
drivers/lhal/src/bflb_irq.c
View File

@ -1,4 +1,5 @@
#include "bflb_irq.h"
#include "bflb_core.h"
#if defined(BL602) || defined(BL702) || defined(BL702L)
#include <risc-v/e24/clic.h>
#else

452
drivers/lhal/src/bflb_mjpeg.c Normal file
View File

@ -0,0 +1,452 @@
#include "bflb_mjpeg.h"
#include "hardware/mjpeg_reg.h"
static void bflb_mjpeg_set_yuv422_interleave_order(struct bflb_device_s *dev, uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
regval &= ~MJPEG_REG_Y0_ORDER_MASK;
regval &= ~MJPEG_REG_U0_ORDER_MASK;
regval &= ~MJPEG_REG_Y1_ORDER_MASK;
regval &= ~MJPEG_REG_V0_ORDER_MASK;
regval |= (y0 << MJPEG_REG_Y0_ORDER_SHIFT);
regval |= (u0 << MJPEG_REG_U0_ORDER_SHIFT);
regval |= (y1 << MJPEG_REG_Y1_ORDER_SHIFT);
regval |= (v0 << MJPEG_REG_V0_ORDER_SHIFT);
putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
}
static void bflb_mjpeg_set_framesize(struct bflb_device_s *dev, uint16_t x, uint16_t y)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = 0;
regval |= (x << MJPEG_REG_FRAME_WBLK_SHIFT);
regval |= (y << MJPEG_REG_FRAME_HBLK_SHIFT);
putreg32(regval, reg_base + MJPEG_FRAME_SIZE_OFFSET);
}
void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s *config)
{
uint32_t regval;
uint32_t reg_base;
uint32_t rows;
uint32_t min_framesize = 0;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
regval &= ~MJPEG_REG_MJPEG_ENABLE;
putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
regval = 0;
regval |= (3 << MJPEG_REG_W_XLEN_SHIFT); /* burst count 16 increment */
regval |= MJPEG_REG_READ_FWRAP;
regval |= MJPEG_REG_MJPEG_BIT_ORDER;
switch (config->format) {
case MJPEG_FORMAT_YUV422_YUYV:
regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
bflb_mjpeg_set_yuv422_interleave_order(dev, 0, 1, 2, 3);
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
break;
case MJPEG_FORMAT_YUV422_YVYU:
regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
bflb_mjpeg_set_yuv422_interleave_order(dev, 0, 3, 2, 1);
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
break;
case MJPEG_FORMAT_YUV422_UYVY:
regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
bflb_mjpeg_set_yuv422_interleave_order(dev, 1, 0, 3, 2);
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
break;
case MJPEG_FORMAT_YUV422_VYUY:
regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
bflb_mjpeg_set_yuv422_interleave_order(dev, 1, 2, 3, 0);
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
break;
case MJPEG_FORMAT_YUV422SP_NV16:
regval |= (2 << MJPEG_REG_YUV_MODE_SHIFT);
regval |= MJPEG_REG_ORDER_U_EVEN;
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
break;
case MJPEG_FORMAT_YUV422SP_NV61:
regval |= (2 << MJPEG_REG_YUV_MODE_SHIFT);
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
break;
case MJPEG_FORMAT_YUV420SP_NV12:
regval |= (0 << MJPEG_REG_YUV_MODE_SHIFT);
regval |= MJPEG_REG_ORDER_U_EVEN;
if (config->resolution_x % 16) {
regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
}
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 15) >> 4);
break;
case MJPEG_FORMAT_YUV420SP_NV21:
regval |= (0 << MJPEG_REG_YUV_MODE_SHIFT);
if (config->resolution_x % 16) {
regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
}
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 15) >> 3);
break;
case MJPEG_FORMAT_GRAY:
regval |= (1 << MJPEG_REG_YUV_MODE_SHIFT);
if (config->resolution_x % 16) {
regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
}
if (config->resolution_y % 16) {
regval |= MJPEG_REG_LAST_HF_HBLK_DMY;
}
bflb_mjpeg_set_framesize(dev, (config->resolution_x + 7) >> 3, (config->resolution_y + 7) >> 3);
break;
default:
break;
}
putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
regval &= ~MJPEG_REG_MJPEG_WAIT_CYCLE_MASK;
regval |= (0x100 << MJPEG_REG_MJPEG_WAIT_CYCLE_SHIFT);
regval &= ~MJPEG_REG_MJPEG_SW_MODE;
putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
regval = getreg32(reg_base + MJPEG_SWAP_MODE_OFFSET);
regval &= ~MJPEG_REG_W_SWAP_MODE;
putreg32(regval, reg_base + MJPEG_SWAP_MODE_OFFSET);
putreg32(config->input_bufaddr0, reg_base + MJPEG_YY_FRAME_ADDR_OFFSET);
putreg32(config->input_bufaddr1, reg_base + MJPEG_UV_FRAME_ADDR_OFFSET);
rows = MJPEG_MAX_FRAME_COUNT * config->resolution_y / 8; /* with 4 frames default */
switch (config->format) {
case MJPEG_FORMAT_YUV422_YUYV:
case MJPEG_FORMAT_YUV422_YVYU:
case MJPEG_FORMAT_YUV422_UYVY:
case MJPEG_FORMAT_YUV422_VYUY:
putreg32((0 << 16) + rows, reg_base + MJPEG_YUV_MEM_OFFSET); /* uv << 16 + yy */
min_framesize = config->resolution_x * config->resolution_y * 2 * MJPEG_MAX_FRAME_COUNT;
break;
case MJPEG_FORMAT_YUV422SP_NV16:
case MJPEG_FORMAT_YUV422SP_NV61:
putreg32((rows << 16) + rows, reg_base + MJPEG_YUV_MEM_OFFSET);
min_framesize = config->resolution_x * config->resolution_y * 2 * MJPEG_MAX_FRAME_COUNT;
break;
case MJPEG_FORMAT_YUV420SP_NV12:
case MJPEG_FORMAT_YUV420SP_NV21:
putreg32((rows << 16) + rows, reg_base + MJPEG_YUV_MEM_OFFSET);
min_framesize = config->resolution_x * config->resolution_y * 3 / 2 * MJPEG_MAX_FRAME_COUNT;
break;
case MJPEG_FORMAT_GRAY:
putreg32((0 << 16) + rows, reg_base + MJPEG_YUV_MEM_OFFSET);
min_framesize = config->resolution_x * config->resolution_y * 1 * MJPEG_MAX_FRAME_COUNT;
break;
default:
break;
}
if (min_framesize > config->output_bufsize) {
printf("mjpeg output size is too small\r\n");
while (1) {
}
}
putreg32(config->output_bufaddr, reg_base + MJPEG_JPEG_FRAME_ADDR_OFFSET);
putreg32(config->output_bufsize / 128, reg_base + MJPEG_JPEG_STORE_MEMORY_OFFSET);
regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
regval &= ~MJPEG_REG_INT_NORMAL_EN;
regval &= ~MJPEG_REG_INT_CAM_EN;
regval &= ~MJPEG_REG_INT_MEM_EN;
regval &= ~MJPEG_REG_INT_FRAME_EN;
regval &= ~MJPEG_REG_INT_IDLE_EN;
regval &= ~MJPEG_REG_INT_SWAP_EN;
regval &= ~MJPEG_REG_FRAME_CNT_TRGR_INT_MASK;
regval |= (1 << MJPEG_REG_FRAME_CNT_TRGR_INT_SHIFT); /* trigger int with one frame */
putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
regval &= ~MJPEG_REG_HEAD_BYTE_MASK;
regval &= ~MJPEG_REG_TAIL_EXP;
putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
/* Clear interrupt */
putreg32(0x3F00, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
}
void bflb_mjpeg_start(struct bflb_device_s *dev)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
regval |= MJPEG_REG_MJPEG_ENABLE;
putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
}
void bflb_mjpeg_stop(struct bflb_device_s *dev)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
regval &= ~MJPEG_REG_MJPEG_ENABLE;
putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
}
void bflb_mjpeg_sw_run(struct bflb_device_s *dev, uint8_t frame_count)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
regval &= ~MJPEG_REG_SW_KICK_MODE;
regval &= ~MJPEG_REG_SW_FRAME_MASK;
regval |= (frame_count << MJPEG_REG_SW_FRAME_SHIFT);
regval |= MJPEG_REG_MJPEG_SW_MODE;
putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
regval &= ~MJPEG_REG_MJPEG_SW_MODE;
putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
regval |= MJPEG_REG_MJPEG_SW_RUN;
putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
regval &= ~MJPEG_REG_MJPEG_SW_RUN;
putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
}
void bflb_mjpeg_tcint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
if (mask) {
regval &= ~MJPEG_REG_INT_NORMAL_EN;
} else {
regval |= MJPEG_REG_INT_NORMAL_EN;
}
putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
}
void bflb_mjpeg_errint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
if (mask) {
regval &= ~MJPEG_REG_INT_CAM_EN;
regval &= ~MJPEG_REG_INT_MEM_EN;
regval &= ~MJPEG_REG_INT_FRAME_EN;
regval &= ~MJPEG_REG_INT_IDLE_EN;
regval &= ~MJPEG_REG_INT_SWAP_EN;
} else {
regval |= MJPEG_REG_INT_CAM_EN;
regval |= MJPEG_REG_INT_MEM_EN;
regval |= MJPEG_REG_INT_FRAME_EN;
regval |= MJPEG_REG_INT_IDLE_EN;
regval |= MJPEG_REG_INT_SWAP_EN;
}
putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
}
uint32_t bflb_mjpeg_get_intstatus(struct bflb_device_s *dev)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
regval &= 0xf0;
return regval;
}
void bflb_mjpeg_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
{
uint32_t reg_base;
reg_base = dev->reg_base;
putreg32(int_clear, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
}
uint8_t bflb_mjpeg_get_frame_count(struct bflb_device_s *dev)
{
uint32_t reg_base;
reg_base = dev->reg_base;
return ((getreg32(reg_base + MJPEG_CONTROL_3_OFFSET) & MJPEG_FRAME_VALID_CNT_MASK) >> MJPEG_FRAME_VALID_CNT_SHIFT);
}
void bflb_mjpeg_pop_one_frame(struct bflb_device_s *dev)
{
uint32_t reg_base;
reg_base = dev->reg_base;
putreg32(1, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
}
uint32_t bflb_mjpeg_get_frame_info(struct bflb_device_s *dev, uint8_t **pic)
{
uint32_t bytes;
uint32_t reg_base;
reg_base = dev->reg_base;
*pic = (uint8_t *)getreg32(reg_base + MJPEG_START_ADDR0_OFFSET);
bytes = (getreg32(reg_base + MJPEG_BIT_CNT0_OFFSET) + 7) >> 3;
return bytes;
}
void bflb_mjpeg_calculate_quantize_table(uint8_t quality, uint16_t *input_table, uint16_t *output_table)
{
uint32_t scale_factor, i;
if (quality == 0) {
quality = 1;
} else if (quality > 100) {
quality = 100;
}
if (quality < 50) {
scale_factor = 5000000 / quality;
} else {
scale_factor = 200000 - quality * 2000;
}
for (i = 0; i < 64; i++) {
output_table[i] = (input_table[i] * scale_factor + 50000) / 100000;
if (output_table[i] == 0) {
output_table[i] = 1;
} else if (output_table[i] > 0xff) {
output_table[i] = 0xff;
}
}
}
void bflb_mjpeg_fill_quantize_table(struct bflb_device_s *dev, uint16_t *input_yy, uint16_t *input_uv)
{
#define MJPEG_Q_PARAM_00_OFFSET (0x400)
#define MJPEG_Q_PARAM_40_OFFSET (0x480)
uint8_t i, j;
uint16_t tmp1;
uint16_t tmp2;
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
for (i = 0; i < 8; i++) {
for (j = 0; j < 4; j++) {
tmp1 = 2048 / input_yy[16 * j + i];
tmp2 = 2048 / input_yy[16 * j + i + 8];
if (20480 / input_yy[16 * j + i] % 10 > 4) {
tmp1++;
}
if (20480 / input_yy[16 * j + i + 8] % 10 > 4) {
tmp2++;
}
putreg32(tmp1 | tmp2 << 16, reg_base + MJPEG_Q_PARAM_00_OFFSET + (i * 4 + j) * 4);
}
}
for (i = 0; i < 8; i++) {
for (j = 0; j < 4; j++) {
tmp1 = 2048 / input_uv[16 * j + i];
tmp2 = 2048 / input_uv[16 * j + i + 8];
if (20480 / input_uv[16 * j + i] % 10 > 4) {
tmp1++;
}
if (20480 / input_uv[16 * j + i + 8] % 10 > 4) {
tmp2++;
}
putreg32(tmp1 | tmp2 << 16, reg_base + MJPEG_Q_PARAM_40_OFFSET + (i * 4 + j) * 4);
}
}
regval = getreg32(reg_base + MJPEG_Q_ENC_OFFSET);
regval |= MJPEG_REG_Q_SRAM_SW;
putreg32(regval, reg_base + MJPEG_Q_ENC_OFFSET);
}
void bflb_mjpeg_fill_jpeg_header_tail(struct bflb_device_s *dev, uint8_t *header, uint32_t header_len)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
arch_memcpy_fast((void *)(reg_base + 0x800), header, header_len);
regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
regval &= ~MJPEG_REG_HEAD_BYTE_MASK;
regval |= (header_len << MJPEG_REG_HEAD_BYTE_SHIFT);
regval |= MJPEG_REG_TAIL_EXP;
putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
}
void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, uint8_t uv)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
regval &= ~MJPEG_REG_YY_DVP2AXI_SEL_MASK;
regval &= ~MJPEG_REG_UV_DVP2AXI_SEL_MASK;
regval |= (yy << MJPEG_REG_YY_DVP2AXI_SEL_SHIFT);
regval |= (uv << MJPEG_REG_UV_DVP2AXI_SEL_SHIFT);
putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
}

1
drivers/lhal/src/bflb_mtimer.c
View File

@ -1,6 +1,5 @@
#include "bflb_mtimer.h"
#include "bflb_core.h"
#include "bflb_irq.h"
#if defined(BL602) || defined(BL702) || defined(BL702L)
#include <risc-v/e24/clic.h>
#else

136
drivers/lhal/src/bflb_sec_sha.c
View File

@ -172,7 +172,7 @@ int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx,
return bflb_sha1_update(dev, (struct bflb_sha1_ctx_s *)ctx, input, len);
}
int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint32_t len)
int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint64_t len)
{
uint32_t regval;
uint32_t reg_base;
@ -267,6 +267,7 @@ void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, ui
uint8_t msgLen[8];
uint32_t regval;
uint32_t reg_base;
uint8_t mode;
uint8_t *p = (uint8_t *)output;
reg_base = dev->reg_base;
@ -311,6 +312,29 @@ void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, ui
*p++ = ((regval >> 16) & 0xff);
*p++ = ((regval >> 24) & 0xff);
mode = (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_MODE_MASK) >> SEC_ENG_SE_SHA_0_MODE_SHIFT;
if ((mode == SHA_MODE_SHA224) || (mode == SHA_MODE_SHA256)) {
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET);
*p++ = (regval & 0xff);
*p++ = ((regval >> 8) & 0xff);
*p++ = ((regval >> 16) & 0xff);
*p++ = ((regval >> 24) & 0xff);
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET);
*p++ = (regval & 0xff);
*p++ = ((regval >> 8) & 0xff);
*p++ = ((regval >> 16) & 0xff);
*p++ = ((regval >> 24) & 0xff);
if (mode == SHA_MODE_SHA256) {
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET);
*p++ = (regval & 0xff);
*p++ = ((regval >> 8) & 0xff);
*p++ = ((regval >> 16) & 0xff);
*p++ = ((regval >> 24) & 0xff);
}
}
/* Disable SHA engine*/
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
@ -474,26 +498,27 @@ void bflb_sha_link_deinit(struct bflb_device_s *dev)
putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
}
void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx)
void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_link_ctx_s *ctx, struct bflb_sha_link_s *link)
{
memset(ctx, 0, sizeof(struct bflb_sha1_ctx_s));
memset(ctx, 0, sizeof(struct bflb_sha1_link_ctx_s));
ctx->sha_padding[0] = 0x80;
ctx->link_addr = (uint32_t)(uintptr_t)link;
}
void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx)
void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_link_ctx_s *ctx, struct bflb_sha_link_s *link)
{
return bflb_sha1_link_start(dev, (struct bflb_sha1_ctx_s *)ctx);
return bflb_sha1_link_start(dev, (struct bflb_sha1_link_ctx_s *)ctx, link);
}
void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx)
void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_link_ctx_s *ctx, struct bflb_sha_link_s *link)
{
memset(ctx, 0, sizeof(struct bflb_sha512_ctx_s));
memset(ctx, 0, sizeof(struct bflb_sha512_link_ctx_s));
ctx->sha_padding[0] = 0x80;
ctx->link_addr = (uint32_t)(uintptr_t)link;
}
int bflb_sha1_link_update(struct bflb_device_s *dev,
struct bflb_sha1_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha1_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len)
{
@ -509,7 +534,7 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
reg_base = dev->reg_base;
/* Set link address */
putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
left = ctx->total[0] & 0x3F;
fill = 64 - left;
@ -524,17 +549,17 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
if (left && len >= fill) {
arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
/* Set data source address */
*(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
*(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
/* Set data length */
*((uint16_t *)(uintptr_t)link_addr + 1) = 1;
*((uint16_t *)(uintptr_t)ctx->link_addr + 1) = 1;
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
/* Choose accumulating last hash in the next time */
*((uint32_t *)(uintptr_t)link_addr) |= 0x40;
*((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
input += fill;
len -= fill;
left = 0;
@ -548,8 +573,8 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
}
/* Fill data */
*(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)input;
*((uint16_t *)(uintptr_t)link_addr + 1) = fill;
*(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)input;
*((uint16_t *)(uintptr_t)ctx->link_addr + 1) = fill;
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
@ -557,7 +582,7 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
input += (fill * 64);
/* Choose accumulating last hash in the next time */
*((uint32_t *)(uintptr_t)link_addr) |= 0x40;
*((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
}
if (len > 0) {
@ -574,19 +599,17 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
}
int bflb_sha256_link_update(struct bflb_device_s *dev,
struct bflb_sha256_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha256_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len)
{
return bflb_sha1_link_update(dev, (struct bflb_sha1_ctx_s *)ctx, link_addr, input, len);
return bflb_sha1_link_update(dev, (struct bflb_sha1_link_ctx_s *)ctx, input, len);
}
int bflb_sha512_link_update(struct bflb_device_s *dev,
struct bflb_sha512_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha512_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len)
uint64_t len)
{
uint32_t regval;
uint32_t reg_base;
@ -600,7 +623,7 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
reg_base = dev->reg_base;
/* Set link address */
putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
left = ctx->total[0] & 0x7F;
fill = 128 - left;
@ -614,17 +637,17 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
if (left && len >= fill) {
arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
/* Set data source address */
*(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
*(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
/* Set data length */
*((uint16_t *)(uintptr_t)link_addr + 1) = 1;
*((uint16_t *)(uintptr_t)ctx->link_addr + 1) = 1;
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
/* Choose accumulating last hash in the next time */
*((uint32_t *)(uintptr_t)link_addr) |= 0x40;
*((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
input += fill;
len -= fill;
left = 0;
@ -638,8 +661,8 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
}
/* Fill data */
*(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)input;
*((uint16_t *)(uintptr_t)link_addr + 1) = fill;
*(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)input;
*((uint16_t *)(uintptr_t)ctx->link_addr + 1) = fill;
regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
@ -647,7 +670,7 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
input += (fill * 128);
/* Choose accumulating last hash in the next time */
*((uint32_t *)(uintptr_t)link_addr) |= 0x40;
*((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
}
if (len > 0) {
@ -664,8 +687,7 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
}
void bflb_sha1_link_finish(struct bflb_device_s *dev,
struct bflb_sha1_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha1_link_ctx_s *ctx,
uint8_t *output)
{
uint32_t last, padn;
@ -673,12 +695,12 @@ void bflb_sha1_link_finish(struct bflb_device_s *dev,
uint8_t msgLen[8];
uint32_t reg_base;
uint32_t sha_mode = (*(uint32_t *)(uintptr_t)link_addr) >> 2 & 0x7;
uint32_t sha_mode = (*(uint32_t *)(uintptr_t)ctx->link_addr) >> 2 & 0x7;
reg_base = dev->reg_base;
/* Set link address */
putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
high = (ctx->total[0] >> 29) | (ctx->total[1] << 3);
low = (ctx->total[0] << 3);
@ -689,25 +711,25 @@ void bflb_sha1_link_finish(struct bflb_device_s *dev,
last = ctx->total[0] & 0x3F;
padn = (last < 56) ? (56 - last) : (120 - last);
bflb_sha1_link_update(dev, ctx, link_addr, (uint8_t *)ctx->sha_padding, padn);
bflb_sha1_link_update(dev, ctx, link_addr, msgLen, 8);
bflb_sha1_link_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
bflb_sha1_link_update(dev, ctx, msgLen, 8);
/* Get result according to SHA mode,result is placed in (link address + offset:8) */
switch (sha_mode) {
case 0:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 32);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 32);
break;
case 1:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 28);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 28);
break;
case 2:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 20);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 20);
break;
case 3:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 20);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 20);
break;
default:
@ -715,62 +737,60 @@ void bflb_sha1_link_finish(struct bflb_device_s *dev,
}
/* Choose new hash in the next time */
*((uint32_t *)(uintptr_t)link_addr) &= ~0x40;
*((uint32_t *)(uintptr_t)ctx->link_addr) &= ~0x40;
}
void bflb_sha256_link_finish(struct bflb_device_s *dev,
struct bflb_sha256_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha256_link_ctx_s *ctx,
uint8_t *output)
{
return bflb_sha1_link_finish(dev, (struct bflb_sha1_ctx_s *)ctx, link_addr, output);
return bflb_sha1_link_finish(dev, (struct bflb_sha1_link_ctx_s *)ctx, output);
}
void bflb_sha512_link_finish(struct bflb_device_s *dev,
struct bflb_sha512_ctx_s *ctx,
uint32_t link_addr,
struct bflb_sha512_link_ctx_s *ctx,
uint8_t *output)
{
uint32_t last, padn;
uint32_t high, low;
uint64_t last, padn;
uint64_t high, low;
uint8_t msgLen[16];
uint32_t reg_base;
uint32_t sha_mode = (*(uint32_t *)(uintptr_t)link_addr) >> 2 & 0x7;
uint32_t sha_mode = (*(uint32_t *)(uintptr_t)ctx->link_addr) >> 2 & 0x7;
reg_base = dev->reg_base;
/* Set link address */
putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
high = (ctx->total[0] >> 61) | (ctx->total[1] << 3);
low = (ctx->total[0] << 3);
PUT_UINT32_BE(high, msgLen, 0);
PUT_UINT32_BE(low, msgLen, 8);
PUT_UINT64_BE(high, msgLen, 0);
PUT_UINT64_BE(low, msgLen, 8);
last = ctx->total[0] & 0x7F;
padn = (last < 112) ? (112 - last) : (240 - last);
bflb_sha512_link_update(dev, ctx, link_addr, (uint8_t *)ctx->sha_padding, padn);
bflb_sha512_link_update(dev, ctx, link_addr, msgLen, 16);
bflb_sha512_link_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
bflb_sha512_link_update(dev, ctx, msgLen, 16);
/* Get result according to SHA mode,result is placed in (link address + offset:8) */
switch (sha_mode) {
case 4:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 64);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 64);
break;
case 5:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 48);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 48);
break;
case 6:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 28);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 28);
break;
case 7:
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 32);
arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 32);
break;
default:
@ -778,7 +798,7 @@ void bflb_sha512_link_finish(struct bflb_device_s *dev,
}
/* Choose new hash in the next time */
*((uint32_t *)(uintptr_t)link_addr) &= ~0x40;
*((uint32_t *)(uintptr_t)ctx->link_addr) &= ~0x40;
}
void bflb_group0_request_sha_access(struct bflb_device_s *dev)

22
drivers/lhal/src/bflb_timer.c
View File

@ -1,4 +1,5 @@
#include "bflb_timer.h"
#include "bflb_gpio.h"
#include "hardware/timer_reg.h"
void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s *config)
@ -89,7 +90,6 @@ void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s
void bflb_timer_deinit(struct bflb_device_s *dev)
{
}
void bflb_timer_start(struct bflb_device_s *dev)
@ -191,22 +191,4 @@ void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no)
regval = getreg32(reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx);
regval |= (1 << cmp_no);
putreg32(regval, reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx);
}
#if !defined(BL702) || !defined(BL602)
void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
regval = getreg32(reg_base + TIMER_GPIO_OFFSET);
/* polarity: 1->neg, 0->pos */
if (config->polarity == TIMER_CAPTURE_POLARITY_FALLING) {
regval |= (1 << (5 + dev->idx));
} else {
regval &= ~(1 << (5 + dev->idx));
}
putreg32(regval, reg_base + TIMER_GPIO_OFFSET);
}
#endif
}

36
drivers/lhal/src/bflb_uart.c
View File

@ -429,7 +429,7 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
case UART_CMD_SET_RTO_VALUE:
/* Set rx time-out value */
putreg32(arg, reg_base + UART_CR_URX_RTO_VALUE_SHIFT);
putreg32(arg, reg_base + UART_URX_RTO_TIMER_OFFSET);
break;
case UART_CMD_SET_RTS_VALUE:
@ -586,6 +586,40 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
}
#endif
break;
#if !defined(BL702L)
case UART_CMD_IR_CONFIG: {
struct bflb_uart_ir_config_s *ir_config = (struct bflb_uart_ir_config_s *)arg;
tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
if (ir_config->tx_en) {
tx_tmp |= UART_CR_UTX_IR_EN;
} else {
tx_tmp &= ~UART_CR_UTX_IR_EN;
}
if (ir_config->tx_inverse) {
tx_tmp |= UART_CR_UTX_IR_INV;
} else {
tx_tmp &= ~UART_CR_UTX_IR_INV;
}
putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
if (ir_config->rx_en) {
rx_tmp |= UART_CR_URX_IR_EN;
} else {
rx_tmp &= ~UART_CR_URX_IR_EN;
}
if (ir_config->rx_inverse) {
rx_tmp |= UART_CR_URX_IR_INV;
} else {
rx_tmp &= ~UART_CR_URX_IR_INV;
}
putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
/* Configure tx ir pulse start and stop position */
putreg32((ir_config->tx_pluse_stop << 16) | ir_config->tx_pluse_start, reg_base + UART_UTX_IR_POSITION_OFFSET);
/* Configure rx ir pulse start position */
putreg32(ir_config->rx_pluse_start, reg_base + UART_URX_IR_POSITION_OFFSET);
} break;
#endif
default:
ret = -EPERM;
break;

1
drivers/lhal/src/bflb_usb_v1.c
View File

@ -1,5 +1,4 @@
#include "bflb_core.h"
#include "bflb_irq.h"
#include "bflb_gpio.h"
#include "usbd_core.h"
#include "hardware/usb_v1_reg.h"

1
drivers/lhal/src/bflb_usb_v2.c
View File

@ -1,5 +1,4 @@
#include "bflb_core.h"
#include "bflb_irq.h"
#include "usbd_core.h"
#include "usbh_core.h"
#include "hardware/usb_v2_reg.h"

BIN
drivers/lhal/src/pka/libpka.a
View File

Binary file not shown.

2
drivers/soc/bl602/startup/interrupt.c
View File

@ -20,7 +20,7 @@
* under the License.
*
*/
#include "bflb_irq.h"
#include "bflb_core.h"
typedef void (*pFunc)(void);

2
drivers/soc/bl616/startup/interrupt.c
View File

@ -20,7 +20,7 @@
* under the License.
*
*/
#include "bflb_irq.h"
#include "bflb_core.h"
#include <csi_core.h>
#include "irq_ctx.h"

11
drivers/soc/bl616/startup/start_load.c
View File

@ -9,6 +9,7 @@ extern uint32_t __itcm_load_addr;
extern uint32_t __dtcm_load_addr;
extern uint32_t __system_ram_load_addr;
extern uint32_t __ram_load_addr;
extern uint32_t __nocache_ram_load_addr;
extern uint32_t __text_code_start__;
extern uint32_t __text_code_end__;
@ -24,6 +25,8 @@ extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __noinit_data_start__;
extern uint32_t __noinit_data_end__;
extern uint32_t __nocache_ram_data_start__;
extern uint32_t __nocache_ram_data_end__;
extern uint32_t __StackTop;
extern uint32_t __StackLimit;
@ -72,6 +75,14 @@ void start_load(void)
*pDest++ = *pSrc++;
}
/* BF Add no cache ram data copy */
pSrc = &__nocache_ram_load_addr;
pDest = &__nocache_ram_data_start__;
for (; pDest < &__nocache_ram_data_end__;) {
*pDest++ = *pSrc++;
}
#ifdef __STARTUP_CLEAR_BSS
/* Single BSS section scheme.
*

1
drivers/soc/bl616/startup/system_bl616.c
View File

@ -79,6 +79,7 @@ void SystemInit(void)
/* Every interrupt should be clear by software*/
for (i = 0; i < IRQn_LAST; i++) {
CLIC->CLICINT[i].IE = 0;
CLIC->CLICINT[i].IP = 0;
CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
}

60
drivers/soc/bl616/startup/vector.S
View File

@ -48,7 +48,34 @@ g_irq_sp:
/* FreeRTOS will define tspend_handler for context switch */
.type default_interrupt_handler, %function
default_interrupt_handler:
ipush
/* ipush */
addi sp, sp, -76
/* save x5 x6 then save mepc mcause */
sw x5, 4(sp)
sw x6, 8(sp)
csrr t0, mepc
csrr t1, mcause
sw t1, 64(sp)
sw t0, 68(sp)
csrr t0, mscratch
sw t0, 72(sp)
/* save regs */
sw x1, 0(sp)
sw x7, 12(sp)
sw x10, 16(sp)
sw x11, 20(sp)
sw x12, 24(sp)
sw x13, 28(sp)
sw x14, 32(sp)
sw x15, 36(sp)
sw x16, 40(sp)
sw x17, 44(sp)
sw x28, 48(sp)
sw x29, 52(sp)
sw x30, 56(sp)
sw x31, 60(sp)
/*
* IRQ stack contents after ipush:
* ~mem addr high:
@ -144,7 +171,36 @@ default_interrupt_handler:
.F_RegNotLoad:
addi sp, sp, 88
/* mret included, and IRQ tail-chain may happen */
ipop
/* ipop */
csrc mstatus, 8
/* restore mepc mcause mscrath */
lw t0, 68(sp)
csrw mepc, t0
lw t0, 64(sp)
csrw mcause, t0
lw t0, 72(sp)
csrw mscratch, t0
/* restore regs */
lw x1, 0(sp)
lw x5, 4(sp)
lw x6, 8(sp)
lw x7, 12(sp)
lw x10, 16(sp)
lw x11, 20(sp)
lw x12, 24(sp)
lw x13, 28(sp)
lw x14, 32(sp)
lw x15, 36(sp)
lw x16, 40(sp)
lw x17, 44(sp)
lw x28, 48(sp)
lw x29, 52(sp)
lw x30, 56(sp)
lw x31, 60(sp)
addi sp, sp, 76
mret
.size default_interrupt_handler, . - default_interrupt_handler

2
drivers/soc/bl702/startup/interrupt.c
View File

@ -20,7 +20,7 @@
* under the License.
*
*/
#include "bflb_irq.h"
#include "bflb_core.h"
typedef void (*pFunc)(void);

26
drivers/soc/bl808/startup/m0/interrupt.c
View File

@ -20,7 +20,7 @@
* under the License.
*
*/
#include "bflb_irq.h"
#include "bflb_core.h"
#include <csi_core.h>
#include "irq_ctx.h"
@ -115,7 +115,7 @@ const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = {
default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */
};
void exception_entry(void)
void exception_entry(uintptr_t *regs)
{
unsigned long cause;
unsigned long epc;
@ -152,7 +152,29 @@ void exception_entry(void)
};
printf("%s\r\n", mcause_str[cause & 0xf]);
// clang-format off
#ifndef CONFIG_ERR_NOT_DUMP_ALL_REGS
printf("ra = 0x%08x ", regs[REG_RA]); printf("sp = 0x%08x ", regs[REG_SP]); printf("gp = 0x%08x ", regs[REG_GP]);
printf("tp = 0x%08x ", regs[REG_TP]); printf("\n\r");
printf("t0 = 0x%08x ", regs[REG_T0]); printf("t1 = 0x%08x ", regs[REG_T1]); printf("t2 = 0x%08x ", regs[REG_T2]);
printf("t3 = 0x%08x ", regs[REG_T3]); printf("\n\r");
printf("t4 = 0x%08x ", regs[REG_T4]); printf("t5 = 0x%08x ", regs[REG_T5]); printf("t6 = 0x%08x ", regs[REG_T6]);
printf("\n\r");
printf("a0 = 0x%08x ", regs[REG_A0]); printf("a1 = 0x%08x ", regs[REG_A1]); printf("a2 = 0x%08x ", regs[REG_A2]);
printf("a3 = 0x%08x ", regs[REG_A3]); printf("\n\r");
printf("a4 = 0x%08x ", regs[REG_A4]); printf("a5 = 0x%08x ", regs[REG_A5]); printf("a6 = 0x%08x ", regs[REG_A6]);
printf("a7 = 0x%08x ", regs[REG_A7]); printf("\n\r");
printf("s0 = 0x%08x ", regs[REG_S0]); printf("s1 = 0x%08x ", regs[REG_S1]); printf("s2 = 0x%08x ", regs[REG_S2]);
printf("s3 = 0x%08x ", regs[REG_S3]); printf("\n\r");
printf("s4 = 0x%08x ", regs[REG_S4]); printf("s5 = 0x%08x ", regs[REG_S5]); printf("s6 = 0x%08x ", regs[REG_S6]);
printf("s7 = 0x%08x ", regs[REG_S7]); printf("\n\r");
printf("s8 = 0x%08x ", regs[REG_S8]); printf("s9 = 0x%08x ", regs[REG_S9]); printf("s10 = 0x%08x ", regs[REG_S10]);
printf("s11 = 0x%08x ", regs[REG_S11]); printf("\n\r");
#endif
// clang-format on
if ((cause == 8) || (cause == 11)) {
epc += 4;
WRITE_CSR(CSR_MEPC, epc);

11
drivers/soc/bl808/startup/m0/start_load.c
View File

@ -9,6 +9,7 @@ extern uint32_t __itcm_load_addr;
extern uint32_t __dtcm_load_addr;
extern uint32_t __system_ram_load_addr;
extern uint32_t __ram_load_addr;
extern uint32_t __nocache_ram_load_addr;
extern uint32_t __text_code_start__;
extern uint32_t __text_code_end__;
@ -24,6 +25,8 @@ extern uint32_t __bss_start__;
extern uint32_t __bss_end__;
extern uint32_t __noinit_data_start__;
extern uint32_t __noinit_data_end__;
extern uint32_t __nocache_ram_data_start__;
extern uint32_t __nocache_ram_data_end__;
extern uint32_t __StackTop;
extern uint32_t __StackLimit;
@ -72,6 +75,14 @@ void start_load(void)
*pDest++ = *pSrc++;
}
/* BF Add no cache ram data copy */
pSrc = &__nocache_ram_load_addr;
pDest = &__nocache_ram_data_start__;
for (; pDest < &__nocache_ram_data_end__;) {
*pDest++ = *pSrc++;
}
#ifdef __STARTUP_CLEAR_BSS
/* Single BSS section scheme.
*

1
drivers/soc/bl808/startup/m0/system_bl808.c
View File

@ -79,6 +79,7 @@ void SystemInit(void)
/* Every interrupt should be clear by software*/
for (i = 0; i < IRQn_LAST; i++) {
CLIC->CLICINT[i].IE = 0;
CLIC->CLICINT[i].IP = 0;
CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
}

60
drivers/soc/bl808/startup/m0/vector.S
View File

@ -48,7 +48,34 @@ g_irq_sp:
/* FreeRTOS will define tspend_handler for context switch */
.type default_interrupt_handler, %function
default_interrupt_handler:
ipush
/* ipush */
addi sp, sp, -76
/* save x5 x6 then save mepc mcause */
sw x5, 4(sp)
sw x6, 8(sp)
csrr t0, mepc
csrr t1, mcause
sw t1, 64(sp)
sw t0, 68(sp)
csrr t0, mscratch
sw t0, 72(sp)
/* save regs */
sw x1, 0(sp)
sw x7, 12(sp)
sw x10, 16(sp)
sw x11, 20(sp)
sw x12, 24(sp)
sw x13, 28(sp)
sw x14, 32(sp)
sw x15, 36(sp)
sw x16, 40(sp)
sw x17, 44(sp)
sw x28, 48(sp)
sw x29, 52(sp)
sw x30, 56(sp)
sw x31, 60(sp)
/*
* IRQ stack contents after ipush:
* ~mem addr high:
@ -144,7 +171,36 @@ default_interrupt_handler:
.F_RegNotLoad:
addi sp, sp, 88
/* mret included, and IRQ tail-chain may happen */
ipop
/* ipop */
csrc mstatus, 8
/* restore mepc mcause mscrath */
lw t0, 68(sp)
csrw mepc, t0
lw t0, 64(sp)
csrw mcause, t0
lw t0, 72(sp)
csrw mscratch, t0
/* restore regs */
lw x1, 0(sp)
lw x5, 4(sp)
lw x6, 8(sp)
lw x7, 12(sp)
lw x10, 16(sp)
lw x11, 20(sp)
lw x12, 24(sp)
lw x13, 28(sp)
lw x14, 32(sp)
lw x15, 36(sp)
lw x16, 40(sp)
lw x17, 44(sp)
lw x28, 48(sp)
lw x29, 52(sp)
lw x30, 56(sp)
lw x31, 60(sp)
addi sp, sp, 76
mret
.size default_interrupt_handler, . - default_interrupt_handler

2
examples/peripherals/adc/adc_oneshot_1ch_dma/main.c
View File

@ -12,7 +12,7 @@ static uint8_t dma_tc_flag0 = 0;
#define ADC_CONVERT_COUNT 16
ATTR_NOCACHE_RAM_SECTION uint32_t raw_data[ADC_CONVERT_COUNT];
ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t raw_data[ADC_CONVERT_COUNT];
void dma0_ch0_isr(void *arg)
{

2
examples/peripherals/adc/adc_tsen/main.c
View File

@ -24,7 +24,7 @@ int main(void)
struct bflb_adc_channel_s chan;
chan.pos_chan = ADC_CHAN_TSEN_P;
chan.pos_chan = ADC_CHANNEL_TSEN_P;
chan.neg_chan = ADC_CHANNEL_GND;
bflb_adc_init(adc, &cfg);

2
examples/peripherals/adc/adc_vbat/main.c
View File

@ -21,7 +21,7 @@ int main(void)
struct bflb_adc_channel_s chan;
chan.pos_chan = ADC_CHAN_VABT_HALF;
chan.pos_chan = ADC_CHANNEL_VABT_HALF;
chan.neg_chan = ADC_CHANNEL_GND;
bflb_adc_init(adc, &cfg);

2
examples/peripherals/dma/CMakeLists.txt → examples/peripherals/dma/dma_normal/CMakeLists.txt
View File

@ -6,4 +6,4 @@ find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
sdk_set_main_file(main.c)
project(dma)
project(dma_normal)

2
examples/peripherals/dma/Makefile → examples/peripherals/dma/dma_normal/Makefile
View File

@ -1,5 +1,5 @@
SDK_DEMO_PATH ?= .
BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../..
BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../..
export BL_SDK_BASE

103
examples/peripherals/dma/dma_normal/main.c Normal file
View File

@ -0,0 +1,103 @@
#include "bflb_mtimer.h"
#include "bflb_dma.h"
#define DMA_BUFFER_LENGTH 4100
extern void board_init(void);
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t src1_buffer[DMA_BUFFER_LENGTH];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t src2_buffer[DMA_BUFFER_LENGTH];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t src3_buffer[DMA_BUFFER_LENGTH];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t dst1_buffer[DMA_BUFFER_LENGTH];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t dst2_buffer[DMA_BUFFER_LENGTH];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t dst3_buffer[DMA_BUFFER_LENGTH];
static uint8_t dma_tc_flag0 = 0;
struct bflb_device_s *dma0_ch0;
void dma0_ch0_isr(void *arg)
{
dma_tc_flag0++;
printf("tc done\r\n");
}
void sram_init()
{
uint32_t i;
for (i = 0; i < DMA_BUFFER_LENGTH; i++) {
src1_buffer[i] = i & 0xff;
src2_buffer[i] = (i * 0x07) & 0xff;
src3_buffer[i] = (i * 0x0b) & 0xff;
}
memset(dst1_buffer, 0, DMA_BUFFER_LENGTH);
memset(dst2_buffer, 0, DMA_BUFFER_LENGTH);
memset(dst3_buffer, 0, DMA_BUFFER_LENGTH);
}
int main(void)
{
uint32_t i;
board_init();
sram_init();
printf("dma memory case:\r\n");
dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
struct bflb_dma_channel_config_s config;
config.direction = DMA_MEMORY_TO_MEMORY;
config.src_req = 0;
config.dst_req = 0;
config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
config.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
config.src_burst_count = DMA_BURST_INCR1;
config.dst_burst_count = DMA_BURST_INCR1;
config.src_width = DMA_DATA_WIDTH_32BIT;
config.dst_width = DMA_DATA_WIDTH_32BIT;
bflb_dma_channel_init(dma0_ch0, &config);
bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
struct bflb_dma_channel_lli_pool_s lli[20]; /* max trasnfer size 4064 * 20 */
struct bflb_dma_channel_lli_transfer_s transfers[3];
transfers[0].src_addr = (uint32_t)src1_buffer;
transfers[0].dst_addr = (uint32_t)dst1_buffer;
transfers[0].nbytes = DMA_BUFFER_LENGTH;
transfers[1].src_addr = (uint32_t)src2_buffer;
transfers[1].dst_addr = (uint32_t)dst2_buffer;
transfers[1].nbytes = DMA_BUFFER_LENGTH;
transfers[2].src_addr = (uint32_t)src3_buffer;
transfers[2].dst_addr = (uint32_t)dst3_buffer;
transfers[2].nbytes = DMA_BUFFER_LENGTH;
bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 3);
bflb_dma_channel_start(dma0_ch0);
while (dma_tc_flag0 != 3) {
bflb_mtimer_delay_ms(1);
}
/* Check data */
for (i = 0; i < DMA_BUFFER_LENGTH; i++) {
if (src1_buffer[i] != dst1_buffer[i]) {
printf("Error! index: %ld, src1: 0x%02x, dst1: 0x%02x\r\n", i, src1_buffer[i], dst1_buffer[i]);
}
if (src2_buffer[i] != dst2_buffer[i]) {
printf("Error! index: %ld, src2: 0x%02x, dst2: 0x%02x\r\n", i, src2_buffer[i], dst2_buffer[i]);
}
if (src3_buffer[i] != dst3_buffer[i]) {
printf("Error! index: %ld, src3: 0x%02x, dst3: 0x%02x\r\n", i, src3_buffer[i], dst3_buffer[i]);
}
}
printf("end\r\n");
while (1) {
}
}

0
examples/peripherals/dma/proj.conf → examples/peripherals/dma/dma_normal/proj.conf
View File

9
examples/peripherals/dma/dma_reduce_or_add/CMakeLists.txt Normal file
View File

@ -0,0 +1,9 @@
cmake_minimum_required(VERSION 3.15)
include(proj.conf)
find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
sdk_set_main_file(main.c)
project(dma_reduce_or_add)

13
examples/peripherals/dma/dma_reduce_or_add/Makefile Normal file
View File

@ -0,0 +1,13 @@
SDK_DEMO_PATH ?= .
BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../..
export BL_SDK_BASE
CHIP ?= bl616
BOARD ?= bl616dk
CROSS_COMPILE ?= riscv64-unknown-elf-
# add custom cmake definition
#cmake_definition+=-Dxxx=sss
include $(BL_SDK_BASE)/project.build

188
examples/peripherals/dma/dma_reduce_or_add/main.c Normal file
View File

@ -0,0 +1,188 @@
#include "bflb_mtimer.h"
#include "bflb_dma.h"
#define DMA_BUFFER_MAX_LENGTH 128
#define DMA_TRANSFER_LENGTH 64
extern void board_init(void);
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t src_buffer[DMA_BUFFER_MAX_LENGTH];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t dst_buffer[DMA_BUFFER_MAX_LENGTH];
static uint8_t dma_tc_flag0 = 0;
struct bflb_device_s *dma0_ch0;
void dma0_ch0_isr(void *arg)
{
dma_tc_flag0++;
printf("tc done\r\n");
}
void sram_init()
{
uint32_t i;
for (i = 0; i < DMA_BUFFER_MAX_LENGTH; i++) {
src_buffer[i] = i & 0xff;
}
memset(dst_buffer, 0, DMA_BUFFER_MAX_LENGTH);
}
int main(void)
{
uint32_t i;
struct bflb_dma_channel_lli_pool_s lli[20];
struct bflb_dma_channel_lli_transfer_s transfers[3];
board_init();
sram_init();
printf("dma memory case:\r\n");
dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
struct bflb_dma_channel_config_s config;
config.direction = DMA_MEMORY_TO_MEMORY;
config.src_req = 0;
config.dst_req = 0;
config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
config.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
config.src_burst_count = DMA_BURST_INCR1;
config.dst_burst_count = DMA_BURST_INCR4;
config.src_width = DMA_DATA_WIDTH_32BIT;
config.dst_width = DMA_DATA_WIDTH_8BIT;
bflb_dma_channel_init(dma0_ch0, &config);
bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
/* Disable reduce mode, transfer length = nbytes = 64 byte */
transfers[0].src_addr = (uint32_t)src_buffer;
transfers[0].dst_addr = (uint32_t)dst_buffer;
transfers[0].nbytes = DMA_TRANSFER_LENGTH;
bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 1);
bflb_dma_channel_start(dma0_ch0);
while (dma_tc_flag0 == 0) {
bflb_mtimer_delay_ms(1);
}
/* Check 0~63 data */
for (i = 0; i < DMA_TRANSFER_LENGTH; i++) {
if (src_buffer[i] != dst_buffer[i]) {
printf("Error! index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
/* Check 64~127 data, should be 0 */
for (i = DMA_TRANSFER_LENGTH; i < DMA_BUFFER_MAX_LENGTH; i++) {
if (dst_buffer[i] != 0) {
printf("Error! Dst should be 0. index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
printf("Check over\r\n\r\n");
memset(dst_buffer, 0, DMA_BUFFER_MAX_LENGTH);
dma_tc_flag0 = 0;
/* Enable reduce mode, src_width = 32bit, dst_width = 8bit, nbytes = 64, transfer length = (nbytes - 1 * dst_width) = 63 byte */
bflb_dma_feature_control(dma0_ch0, DMA_CMD_SET_REDUCE_MODE, 1);
bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 1);
bflb_dma_channel_start(dma0_ch0);
while (dma_tc_flag0 == 0) {
bflb_mtimer_delay_ms(1);
}
/* Check 0~62 data */
for (i = 0; i < DMA_TRANSFER_LENGTH - 1; i++) {
if (src_buffer[i] != dst_buffer[i]) {
printf("Error! index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
/* Check 63~127 data, should be 0 */
for (i = DMA_TRANSFER_LENGTH - 1; i < DMA_BUFFER_MAX_LENGTH; i++) {
if (dst_buffer[i] != 0) {
printf("Error! Dst should be 0. index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
printf("Check over\r\n\r\n");
memset(dst_buffer, 0, DMA_BUFFER_MAX_LENGTH);
dma_tc_flag0 = 0;
/* Disable reduce mode and enable add mode, src_width = 8bit, dst_width = 32bit, nbytes = 65, transfer length = nbytes + 3 = 68 byte, multiple of dst_width */
bflb_dma_feature_control(dma0_ch0, DMA_CMD_SET_REDUCE_MODE, 0);
bflb_dma_feature_control(dma0_ch0, DMA_CMD_SET_ADD_MODE, 1);
config.src_burst_count = DMA_BURST_INCR4;
config.dst_burst_count = DMA_BURST_INCR1;
config.src_width = DMA_DATA_WIDTH_8BIT;
config.dst_width = DMA_DATA_WIDTH_32BIT;
bflb_dma_channel_init(dma0_ch0, &config);
transfers[0].nbytes = DMA_TRANSFER_LENGTH + 1;
bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 1);
bflb_dma_channel_start(dma0_ch0);
while (dma_tc_flag0 == 0) {
bflb_mtimer_delay_ms(1);
}
/* Check 0~64 data */
for (i = 0; i < DMA_TRANSFER_LENGTH + 1; i++) {
if (src_buffer[i] != dst_buffer[i]) {
printf("Error! index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
/* Check 65~67 data */
for (i = DMA_TRANSFER_LENGTH + 1; i < DMA_TRANSFER_LENGTH + 4; i++) {
if (dst_buffer[i] == 0) {
printf("Error! Dst should not be 0. index: %ld\r\n", i);
} else {
printf("Correct, meaningless data. index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
/* Check 68~127 data, should be 0 */
for (i = DMA_TRANSFER_LENGTH + 4; i < DMA_BUFFER_MAX_LENGTH; i++) {
if (dst_buffer[i] != 0) {
printf("Error! Dst should be 0. index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
printf("Check over\r\n\r\n");
memset(dst_buffer, 0, DMA_BUFFER_MAX_LENGTH);
dma_tc_flag0 = 0;
/* Disable add mode, src_width = 8bit, dst_width = 32bit, nbytes = 65, transfer length = nbytes - 1 = 64 byte, multiple of dst_width */
bflb_dma_feature_control(dma0_ch0, DMA_CMD_SET_ADD_MODE, 0);
bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 1);
bflb_dma_channel_start(dma0_ch0);
while (dma_tc_flag0 == 0) {
bflb_mtimer_delay_ms(1);
}
/* Check 0~63 data */
for (i = 0; i < DMA_TRANSFER_LENGTH; i++) {
if (src_buffer[i] != dst_buffer[i]) {
printf("Error! index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
/* Check 64~127 data, should be 0 */
for (i = DMA_TRANSFER_LENGTH; i < DMA_BUFFER_MAX_LENGTH; i++) {
if (dst_buffer[i] != 0) {
printf("Error! Dst should be 0. index: %ld, src: 0x%02x, dst: 0x%02x\r\n", i, src_buffer[i], dst_buffer[i]);
}
}
printf("Check over\r\n\r\n");
printf("end\r\n");
while (1) {
}
}

1
examples/peripherals/dma/dma_reduce_or_add/proj.conf Normal file
View File

@ -0,0 +1 @@
#set(CONFIG_XXX 1)

84
examples/peripherals/dma/main.c
View File

@ -1,84 +0,0 @@
#include "bflb_mtimer.h"
#include "bflb_dma.h"
extern void board_init(void);
static ATTR_NOCACHE_RAM_SECTION uint8_t src_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t src2_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t src3_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t dst_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t dst2_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t dst3_buffer[4100];
static uint8_t dma_tc_flag0 = 0;
struct bflb_device_s *dma0_ch0;
void dma0_ch0_isr(void *arg)
{
dma_tc_flag0++;
printf("tc done\r\n");
}
void sram_init()
{
memset(src_buffer, 'a', 4100);
src_buffer[3999] = 'B';
src_buffer[4095] = 'A';
src_buffer[4096] = 'B';
src_buffer[4097] = 'C';
src_buffer[4098] = 'D';
src_buffer[4099] = 'E';
memset(src2_buffer, 'c', 512);
memset(src3_buffer, 'd', 256);
}
int main(void)
{
board_init();
sram_init();
printf("dma memory test\r\n");
dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
struct bflb_dma_channel_config_s config;
config.direction = DMA_MEMORY_TO_MEMORY;
config.src_req = 0;
config.dst_req = 0;
config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
config.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
config.src_burst_count = DMA_BURST_INCR1;
config.dst_burst_count = DMA_BURST_INCR1;
config.src_width = DMA_DATA_WIDTH_32BIT;
config.dst_width = DMA_DATA_WIDTH_32BIT;
bflb_dma_channel_init(dma0_ch0, &config);
bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
struct bflb_dma_channel_lli_pool_s lli[20]; /* max trasnfer size 4064 * 20 */
struct bflb_dma_channel_lli_transfer_s transfers[3];
transfers[0].src_addr = (uint32_t)src_buffer;
transfers[0].dst_addr = (uint32_t)dst_buffer;
transfers[0].nbytes = 4100;
transfers[1].src_addr = (uint32_t)src2_buffer;
transfers[1].dst_addr = (uint32_t)dst2_buffer;
transfers[1].nbytes = 4100;
transfers[2].src_addr = (uint32_t)src3_buffer;
transfers[2].dst_addr = (uint32_t)dst3_buffer;
transfers[2].nbytes = 4100;
bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 3);
bflb_dma_channel_start(dma0_ch0);
while (dma_tc_flag0 != 3) {
bflb_mtimer_delay_ms(1);
}
while (1) {
}
}

2
examples/peripherals/emac/emac_basic/main.c
View File

@ -19,7 +19,7 @@ static const uint8_t test_frame[42] = {
0xc0, 0xa8, 0x7b, 0xb2 // dst ip 192.168.123.178
};
#define TEST_PATTERN_LEN (ETH_MAX_PACKET_SIZE - 32)
ATTR_NOCACHE_RAM_SECTION static uint8_t test_pattern[TEST_PATTERN_LEN] = { 0 };
ATTR_NOCACHE_NOINIT_RAM_SECTION static uint8_t test_pattern[TEST_PATTERN_LEN] = { 0 };
static volatile uint32_t tx_pkg_cnt = 0;
static volatile uint32_t tx_err_cnt = 0;

26
examples/peripherals/i2c/i2c_eeprom_dma/main.c
View File

@ -10,8 +10,8 @@ struct bflb_device_s *i2c0;
struct bflb_device_s *dma0_ch0;
struct bflb_device_s *dma0_ch1;
static ATTR_NOCACHE_RAM_SECTION uint32_t send_buffer[8];
static ATTR_NOCACHE_RAM_SECTION uint32_t receive_buffer[8];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t send_buffer[8];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t receive_buffer[8];
static volatile uint32_t dma_tc_flag0 = 0;
static volatile uint32_t dma_tc_flag1 = 0;
@ -46,12 +46,12 @@ int main(void)
bflb_i2c_init(i2c0, 400000);
bflb_i2c_link_txdma(i2c0, true);
bflb_i2c_link_rxdma(i2c0, true);
/* Write page 0 */
dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
struct bflb_dma_channel_config_s tx_config;
tx_config.direction = DMA_MEMORY_TO_PERIPH;
tx_config.src_req = DMA_REQUEST_NONE;
tx_config.dst_req = DMA_REQUEST_I2C0_TX;
@ -90,13 +90,13 @@ int main(void)
while ((bflb_i2c_get_intstatus(i2c0) & I2C_INT_END) == 0) {
}
bflb_i2c_deinit(i2c0);
printf("write over\r\n");
bflb_mtimer_delay_ms(100);
/* Read page 0 */
dma0_ch1 = bflb_device_get_by_name("dma0_ch1");
struct bflb_dma_channel_config_s rx_config;
rx_config.direction = DMA_PERIPH_TO_MEMORY;
@ -109,31 +109,31 @@ int main(void)
rx_config.src_width = DMA_DATA_WIDTH_32BIT;
rx_config.dst_width = DMA_DATA_WIDTH_32BIT;
bflb_dma_channel_init(dma0_ch1, &rx_config);
bflb_dma_channel_irq_attach(dma0_ch1, dma0_ch1_isr, NULL);
struct bflb_dma_channel_lli_pool_s rx_llipool[20];
struct bflb_dma_channel_lli_transfer_s rx_transfers[1];
rx_transfers[0].src_addr = (uint32_t)DMA_ADDR_I2C0_RDR;
rx_transfers[0].dst_addr = (uint32_t)receive_buffer;
rx_transfers[0].nbytes = 32;
bflb_dma_channel_lli_reload(dma0_ch1, rx_llipool, 20, rx_transfers, 1);
msgs[1].addr = 0x50;
msgs[1].flags = I2C_M_DMA | I2C_M_READ;
msgs[1].buffer = NULL;
msgs[1].length = 32;
bflb_i2c_transfer(i2c0, msgs, 2);
bflb_dma_channel_start(dma0_ch1);
while (dma_tc_flag1 == 0) {
}
while ((bflb_i2c_get_intstatus(i2c0) & I2C_INT_END) == 0) {
}
bflb_i2c_deinit(i2c0);
printf("read over\r\n");
/* Check read data */

8
examples/peripherals/pwm_v1/pwm_all_channels/main.c
View File

@ -9,12 +9,12 @@ int main(void)
board_init();
board_pwm_gpio_init();
pwm = bflb_device_get_by_name("pwm");
pwm = bflb_device_get_by_name("pwm0");
/* period = .PBCLK / .clk_div / .period = 80MHz / 80 / 1000 = 1KHz */
/* period = .XCLK / .clk_div / .period = 32MHz / 32 / 1000 = 1KHz */
struct bflb_pwm_v1_channel_config_s cfg = {
.clk_source = BFLB_SYSTEM_PBCLK,
.clk_div = 80,
.clk_source = BFLB_SYSTEM_XCLK,
.clk_div = 32,
.period = 1000,
};

8
examples/peripherals/pwm_v1/pwm_basic/main.c
View File

@ -9,12 +9,12 @@ int main(void)
board_init();
board_pwm_gpio_init();
pwm = bflb_device_get_by_name("pwm");
pwm = bflb_device_get_by_name("pwm0");
/* period = .PBCLK / .clk_div / .period = 80MHz / 80 / 1000 = 1KHz */
/* period = .XCLK / .clk_div / .period = 32MHz / 32 / 1000 = 1KHz */
struct bflb_pwm_v1_channel_config_s cfg = {
.clk_source = BFLB_SYSTEM_PBCLK,
.clk_div = 80,
.clk_source = BFLB_SYSTEM_XCLK,
.clk_div = 32,
.period = 1000,
};

10
examples/peripherals/pwm_v1/pwm_int/main.c
View File

@ -42,16 +42,16 @@ int main(void)
board_init();
board_pwm_gpio_init();
pwm = bflb_device_get_by_name("pwm");
pwm = bflb_device_get_by_name("pwm0");
/* period = .PBCLK / .clk_div / .period = 80MHz / 80 / 1000 = 1kHz */
/* period = .XCLK / .clk_div / .period = 32MHz / 32 / 1000 = 1KHz */
struct bflb_pwm_v1_channel_config_s cfg = {
.clk_source = BFLB_SYSTEM_PBCLK,
.clk_div = 80,
.clk_source = BFLB_SYSTEM_XCLK,
.clk_div = 32,
.period = 1000,
};
for (uint8_t i = 0; i <= PWM_V1_CH_MAX; i++) {
for (uint8_t i = 0; i < PWM_V1_CH_MAX; i++) {
bflb_pwm_v1_channel_init(pwm, i, &cfg);
bflb_pwm_v1_channel_set_threshold(pwm, i, 100, 500 + i * 100); /* duty = ((500 + i *100)-100)/1000 */

2
examples/peripherals/pwm_v2/pwm_int/main.c
View File

@ -71,7 +71,7 @@ void pwm_isr(int irq, void *arg)
int main(void)
{
board_init();
// board_pwm0_gpio_init();
board_pwm0_gpio_init();
pwm0 = bflb_device_get_by_name("pwm0");

32
examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/main.c
View File

@ -84,7 +84,7 @@ const uint8_t aes_xts_256bit_ct[64] = {
0x66, 0xb2, 0x7f, 0x06, 0x46, 0xbb, 0xb2, 0x46, 0x00, 0xf8, 0x6b, 0x0c, 0xc0, 0x5f, 0xb5, 0x20
};
static struct bflb_aes_link_s aes_ecb_link = {
ATTR_NOCACHE_RAM_SECTION struct bflb_aes_link_s aes_ecb_link = {
.aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */
.aes_dec_en = 0, /* Encode */
.aes_newkey_dis = 0, /* Use new key */
@ -111,7 +111,7 @@ static struct bflb_aes_link_s aes_ecb_link = {
.aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */
};
static struct bflb_aes_link_s aes_cbc_link = {
ATTR_NOCACHE_RAM_SECTION struct bflb_aes_link_s aes_cbc_link = {
.aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */
.aes_dec_en = 0, /* Encode */
.aes_newkey_dis = 0, /* Use new key */
@ -138,7 +138,7 @@ static struct bflb_aes_link_s aes_cbc_link = {
.aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */
};
static struct bflb_aes_link_s aes_cbc_link2 = {
ATTR_NOCACHE_RAM_SECTION struct bflb_aes_link_s aes_cbc_link2 = {
.aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */
.aes_dec_en = 0, /* Encode */
.aes_newkey_dis = 0, /* Use new key */
@ -165,7 +165,7 @@ static struct bflb_aes_link_s aes_cbc_link2 = {
.aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */
};
static struct bflb_aes_link_s aes_ctr_link = {
ATTR_NOCACHE_RAM_SECTION struct bflb_aes_link_s aes_ctr_link = {
.aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */
.aes_dec_en = 0, /* Encode */
.aes_newkey_dis = 0, /* Use new key */
@ -192,7 +192,7 @@ static struct bflb_aes_link_s aes_ctr_link = {
.aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */
};
static struct bflb_aes_xts_link_s aes_xts_link1 = {
ATTR_NOCACHE_RAM_SECTION struct bflb_aes_xts_link_s aes_xts_link1 = {
.aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */
.aes_dec_en = 0, /* Encode */
.aes_newkey_dis = 0, /* Use new key */
@ -201,7 +201,7 @@ static struct bflb_aes_xts_link_s aes_xts_link1 = {
.aes_intset = 0, /* Not set interrupt */
.aes_mode = AES_MODE_XTS, /* ECB mode select */
.aes_newiv_dis = 0, /* Use new iv */
.aes_xts = 0, /* XTS mode select */
.aes_xts = AES_LINK_XTS_MODE1, /* XTS mode select */
.aes_msglen = 1, /* Number of 128-bit block */
.aes_srcaddr = 0, /* Message source address */
.aes_dstaddr = 0, /* Message destination address */
@ -228,7 +228,7 @@ static struct bflb_aes_xts_link_s aes_xts_link1 = {
.aes_key27 = 0x00000000 /* Big endian aes key2(aes-256 key LSB) */
};
static struct bflb_aes_xts_link_s aes_xts_link2 = {
ATTR_NOCACHE_RAM_SECTION struct bflb_aes_xts_link_s aes_xts_link2 = {
.aes_key = AES_LINK_KEY_192BITS, /* 128-bit key mode select */
.aes_dec_en = 0, /* Encode */
.aes_newkey_dis = 0, /* Use new key */
@ -237,7 +237,7 @@ static struct bflb_aes_xts_link_s aes_xts_link2 = {
.aes_intset = 0, /* Not set interrupt */
.aes_mode = AES_MODE_XTS, /* ECB mode select */
.aes_newiv_dis = 0, /* Use new iv */
.aes_xts = 0, /* XTS mode select */
.aes_xts = AES_LINK_XTS_MODE1, /* XTS mode select */
.aes_msglen = 1, /* Number of 128-bit block */
.aes_srcaddr = 0, /* Message source address */
.aes_dstaddr = 0, /* Message destination address */
@ -264,7 +264,7 @@ static struct bflb_aes_xts_link_s aes_xts_link2 = {
.aes_key27 = 0x00000000 /* Big endian aes key2(aes-256 key LSB) */
};
static struct bflb_aes_xts_link_s aes_xts_link3 = {
ATTR_NOCACHE_RAM_SECTION struct bflb_aes_xts_link_s aes_xts_link3 = {
.aes_key = AES_LINK_KEY_256BITS, /* 128-bit key mode select */
.aes_dec_en = 0, /* Encode */
.aes_newkey_dis = 0, /* Use new key */
@ -273,7 +273,7 @@ static struct bflb_aes_xts_link_s aes_xts_link3 = {
.aes_intset = 0, /* Not set interrupt */
.aes_mode = AES_MODE_XTS, /* ECB mode select */
.aes_newiv_dis = 0, /* Use new iv */
.aes_xts = 0, /* XTS mode select */
.aes_xts = AES_LINK_XTS_MODE1, /* XTS mode select */
.aes_msglen = 1, /* Number of 128-bit block */
.aes_srcaddr = 0, /* Message source address */
.aes_dstaddr = 0, /* Message destination address */
@ -314,8 +314,8 @@ static uint32_t bflb_data_compare(const uint8_t *expected, uint8_t *input, uint3
return 0;
}
ATTR_NOCACHE_RAM_SECTION uint8_t aes_enc_buf[512];
ATTR_NOCACHE_RAM_SECTION uint8_t aes_dec_buf[512];
ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t aes_enc_buf[512];
ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t aes_dec_buf[512];
int main(void)
{
@ -349,12 +349,12 @@ int main(void)
bflb_data_compare(aes_xts_128bit_ct, aes_enc_buf, 16);
printf("aes link xts 128 success\r\n");
bflb_aes_link_update(aes, (uint32_t)&aes_xts_link2, aes_xts_192bit_pt, aes_enc_buf, 16);
bflb_data_compare(aes_xts_192bit_ct, aes_enc_buf, 16);
bflb_aes_link_update(aes, (uint32_t)&aes_xts_link2, aes_xts_192bit_pt, aes_enc_buf, 32);
bflb_data_compare(aes_xts_192bit_ct, aes_enc_buf, 32);
printf("aes link xts 192 success\r\n");
bflb_aes_link_update(aes, (uint32_t)&aes_xts_link3, aes_xts_256bit_pt, aes_enc_buf, 16);
bflb_data_compare(aes_xts_256bit_ct, aes_enc_buf, 16);
bflb_aes_link_update(aes, (uint32_t)&aes_xts_link3, aes_xts_256bit_pt, aes_enc_buf, 32);
bflb_data_compare(aes_xts_256bit_ct, aes_enc_buf, 32);
printf("aes link xts 256 success\r\n");
printf("aes link success\r\n");

4
examples/peripherals/sec_eng/sec_eng_aes_sw_key/main.c
View File

@ -465,8 +465,8 @@ const uint8_t aes_xts_256bit_ct[3][64] = {
const uint8_t aes_xts_256bit_len[3] = { 64, 64, 64 };
ATTR_NOCACHE_RAM_SECTION uint8_t aes_enc_buf[512];
ATTR_NOCACHE_RAM_SECTION uint8_t aes_dec_buf[512];
ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t aes_enc_buf[512];
ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t aes_dec_buf[512];
static uint32_t bflb_data_compare(const uint8_t *expected, uint8_t *input, uint32_t len)
{

9
examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/CMakeLists.txt Normal file
View File

@ -0,0 +1,9 @@
cmake_minimum_required(VERSION 3.15)
include(proj.conf)
find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
sdk_set_main_file(main.c)
project(sec_eng_aes_sw_key_costtime)

13
examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/Makefile Normal file
View File

@ -0,0 +1,13 @@
SDK_DEMO_PATH ?= .
BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../..
export BL_SDK_BASE
CHIP ?= bl616
BOARD ?= bl616dk
CROSS_COMPILE ?= riscv64-unknown-elf-
# add custom cmake definition
#cmake_definition+=-Dxxx=sss
include $(BL_SDK_BASE)/project.build

131
examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/main.c Normal file
View File

@ -0,0 +1,131 @@
#include "bflb_mtimer.h"
#include "bflb_sec_aes.h"
#include "board.h"
const uint8_t aes_256bit_key[32] = {
0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
};
uint8_t aes_iv[16] = { 0 };
ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t aes_input_buf[16 * 1024];
ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t aes_enc_buf[16 * 1024];
ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t aes_dec_buf[16 * 1024];
int main(void)
{
uint64_t start_time;
board_init();
struct bflb_device_s *aes;
aes = bflb_device_get_by_name("aes");
bflb_group0_request_aes_access(aes);
for (uint32_t i = 0; i < 16 * 1024; i++) {
aes_input_buf[i] = i & 0xff;
}
bflb_aes_init(aes);
bflb_mtimer_delay_ms(500);
for (uint32_t i = 1; i <= 1024; i++) {
printf("test aes ecb 128 \r\n");
bflb_aes_set_mode(aes, AES_MODE_ECB);
bflb_aes_setkey(aes, aes_256bit_key, 128);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes ecb 128 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes ecb 128 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
printf("test aes ecb 256 \r\n");
bflb_aes_set_mode(aes, AES_MODE_ECB);
bflb_aes_setkey(aes, aes_256bit_key, 256);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes ecb 256 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes ecb 256 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
for (uint32_t i = 1; i <= 1024; i++) {
printf("test aes cbc 128 \r\n");
bflb_aes_set_mode(aes, AES_MODE_CBC);
bflb_aes_setkey(aes, aes_256bit_key, 128);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes cbc 128 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes cbc 128 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
printf("test aes cbc 256 \r\n");
bflb_aes_set_mode(aes, AES_MODE_CBC);
bflb_aes_setkey(aes, aes_256bit_key, 256);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes cbc 256 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes cbc 256 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
for (uint32_t i = 1; i <= 1024; i++) {
printf("test aes ctr 128 \r\n");
bflb_aes_set_mode(aes, AES_MODE_CTR);
bflb_aes_setkey(aes, aes_256bit_key, 128);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes ctr 128 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes ctr 128 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
printf("test aes ctr 256 \r\n");
bflb_aes_set_mode(aes, AES_MODE_CTR);
bflb_aes_setkey(aes, aes_256bit_key, 256);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes ctr 256 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes ctr 256 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
for (uint32_t i = 1; i <= 1024; i++) {
printf("test aes xts 128 \r\n");
bflb_aes_set_mode(aes, AES_MODE_XTS);
bflb_aes_setkey(aes, aes_256bit_key, 128);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes xts 128 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes xts 128 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
printf("test aes xts 256 \r\n");
bflb_aes_set_mode(aes, AES_MODE_XTS);
bflb_aes_setkey(aes, aes_256bit_key, 256);
start_time = bflb_mtimer_get_time_us();
bflb_aes_encrypt(aes, aes_input_buf, aes_iv, aes_enc_buf, 16 * i);
printf("aes xts 256 block:%d enc cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
start_time = bflb_mtimer_get_time_us();
bflb_aes_decrypt(aes, aes_enc_buf, aes_iv, aes_dec_buf, 16 * i);
printf("aes xts 256 block:%d dec cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
printf("aes success\r\n");
bflb_group0_release_aes_access(aes);
while (1) {
bflb_mtimer_delay_ms(2000);
}
}

1
examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/proj.conf Normal file
View File

@ -0,0 +1 @@
#set(CONFIG_XXX 1)

9
examples/peripherals/sec_eng/sec_eng_dsa/CMakeLists.txt Normal file
View File

@ -0,0 +1,9 @@
cmake_minimum_required(VERSION 3.15)
include(proj.conf)
find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
sdk_set_main_file(main.c)
project(sec_eng_dsa)

13
examples/peripherals/sec_eng/sec_eng_dsa/Makefile Normal file
View File

@ -0,0 +1,13 @@
SDK_DEMO_PATH ?= .
BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../..
export BL_SDK_BASE
CHIP ?= bl616
BOARD ?= bl616dk
CROSS_COMPILE ?= riscv64-unknown-elf-
# add custom cmake definition
#cmake_definition+=-Dxxx=sss
include $(BL_SDK_BASE)/project.build

145
examples/peripherals/sec_eng/sec_eng_dsa/main.c Normal file
View File

@ -0,0 +1,145 @@
#include "bflb_mtimer.h"
#include "bflb_sec_dsa.h"
#include "board.h"
int main(void)
{
board_init();
#if 0
p=int("00c952a3180f7bca497bc5ad1e9b5818b233702ac9ab43f744f451a4a241fcda5b9eff815351c45d046ee4262ac28f7f3df226ac2e949d1fe8d5b6923f33f1a641",16)
q=int("00c225091c9a663843dd18cce92409581c2365d0fcbc956bf1152e11004bde53c99843f1f149a76a33fb46edb957f19e8720003b0345633f2840b35e3b302dec79",16)
n=int("98adbfb43467d4a5df25d388e5605f12840ea66299cbdf3a807bbd99817798eb4a64a6885ba5494dba2fc00005fe87f5ec6585d1ba53dea9d48e48cfe6031843d84057a0c6233a598cb8a7d399eea7bce81e07ea574c26e44b4a925db3a9372d73c97bbe143c747ffc1123c2e0e57681e95462a81b7224e814270363bbe880b9",16)
e=65537
d=int("2a99a039b9bd96d9c94f969c45d403f2f8a1d5cf01369f4c857901480995c3373384adeab217864287c6b6fdcaae60653fd67be62ee523e5a307284dc9d1e73ce88bbd38e711536e48b181c1b5735d76675700fc2ddd89b7df67a8fb16eb4c1dde354fbc04f7c4c18975f5cba4f36ec7120b00bdd838d488ce37a9452e574401",16)
dP=int("c2a434aed4797890272c6d3e042ede619bbdbc809226f9f01eceb87f6f9109843f6b041c0c17ef5e93dfdccec6a07a02e8155faf015c1037ca37e3995b9d2c81",16)
dQ=int("161295dd9da43f835fb0c1234488976ee38b60de4b2685d62bfd47cb8bd4a41c0866b92c209e9b117be10d8803faa176656a014b96e8f8b63fdce4babff888a9",16)
qInv=int("49727f7416d2e019b5436ffeb01b817cd57bb67aece0e56a7777db1547c197d1b00d088c436721a31eba5387b8d48394e47c806d3d1b546b03fd3e6c3ead5fda",16)
#endif
uint8_t p[64] = { 0xc9, 0x52, 0xa3, 0x18, 0x0f, 0x7b, 0xca, 0x49, 0x7b, 0xc5, 0xad, 0x1e, 0x9b, 0x58, 0x18, 0xb2,
0x33, 0x70, 0x2a, 0xc9, 0xab, 0x43, 0xf7, 0x44, 0xf4, 0x51, 0xa4, 0xa2, 0x41, 0xfc, 0xda, 0x5b,
0x9e, 0xff, 0x81, 0x53, 0x51, 0xc4, 0x5d, 0x04, 0x6e, 0xe4, 0x26, 0x2a, 0xc2, 0x8f, 0x7f, 0x3d,
0xf2, 0x26, 0xac, 0x2e, 0x94, 0x9d, 0x1f, 0xe8, 0xd5, 0xb6, 0x92, 0x3f, 0x33, 0xf1, 0xa6, 0x41 };
uint8_t q[64] = { 0xc2, 0x25, 0x09, 0x1c, 0x9a, 0x66, 0x38, 0x43, 0xdd, 0x18, 0xcc, 0xe9, 0x24, 0x09, 0x58, 0x1c,
0x23, 0x65, 0xd0, 0xfc, 0xbc, 0x95, 0x6b, 0xf1, 0x15, 0x2e, 0x11, 0x00, 0x4b, 0xde, 0x53, 0xc9,
0x98, 0x43, 0xf1, 0xf1, 0x49, 0xa7, 0x6a, 0x33, 0xfb, 0x46, 0xed, 0xb9, 0x57, 0xf1, 0x9e, 0x87,
0x20, 0x00, 0x3b, 0x03, 0x45, 0x63, 0x3f, 0x28, 0x40, 0xb3, 0x5e, 0x3b, 0x30, 0x2d, 0xec, 0x79 };
uint8_t n[128] = { 0x98, 0xad, 0xbf, 0xb4, 0x34, 0x67, 0xd4, 0xa5, 0xdf, 0x25, 0xd3, 0x88, 0xe5, 0x60, 0x5f, 0x12,
0x84, 0x0e, 0xa6, 0x62, 0x99, 0xcb, 0xdf, 0x3a, 0x80, 0x7b, 0xbd, 0x99, 0x81, 0x77, 0x98, 0xeb,
0x4a, 0x64, 0xa6, 0x88, 0x5b, 0xa5, 0x49, 0x4d, 0xba, 0x2f, 0xc0, 0x00, 0x05, 0xfe, 0x87, 0xf5,
0xec, 0x65, 0x85, 0xd1, 0xba, 0x53, 0xde, 0xa9, 0xd4, 0x8e, 0x48, 0xcf, 0xe6, 0x03, 0x18, 0x43,
0xd8, 0x40, 0x57, 0xa0, 0xc6, 0x23, 0x3a, 0x59, 0x8c, 0xb8, 0xa7, 0xd3, 0x99, 0xee, 0xa7, 0xbc,
0xe8, 0x1e, 0x07, 0xea, 0x57, 0x4c, 0x26, 0xe4, 0x4b, 0x4a, 0x92, 0x5d, 0xb3, 0xa9, 0x37, 0x2d,
0x73, 0xc9, 0x7b, 0xbe, 0x14, 0x3c, 0x74, 0x7f, 0xfc, 0x11, 0x23, 0xc2, 0xe0, 0xe5, 0x76, 0x81,
0xe9, 0x54, 0x62, 0xa8, 0x1b, 0x72, 0x24, 0xe8, 0x14, 0x27, 0x03, 0x63, 0xbb, 0xe8, 0x80, 0xb9 };
uint8_t e[128] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01 };
uint8_t d[128] = { 0x2a, 0x99, 0xa0, 0x39, 0xb9, 0xbd, 0x96, 0xd9, 0xc9, 0x4f, 0x96, 0x9c, 0x45, 0xd4, 0x03, 0xf2,
0xf8, 0xa1, 0xd5, 0xcf, 0x01, 0x36, 0x9f, 0x4c, 0x85, 0x79, 0x01, 0x48, 0x09, 0x95, 0xc3, 0x37,
0x33, 0x84, 0xad, 0xea, 0xb2, 0x17, 0x86, 0x42, 0x87, 0xc6, 0xb6, 0xfd, 0xca, 0xae, 0x60, 0x65,
0x3f, 0xd6, 0x7b, 0xe6, 0x2e, 0xe5, 0x23, 0xe5, 0xa3, 0x07, 0x28, 0x4d, 0xc9, 0xd1, 0xe7, 0x3c,
0xe8, 0x8b, 0xbd, 0x38, 0xe7, 0x11, 0x53, 0x6e, 0x48, 0xb1, 0x81, 0xc1, 0xb5, 0x73, 0x5d, 0x76,
0x67, 0x57, 0x00, 0xfc, 0x2d, 0xdd, 0x89, 0xb7, 0xdf, 0x67, 0xa8, 0xfb, 0x16, 0xeb, 0x4c, 0x1d,
0xde, 0x35, 0x4f, 0xbc, 0x04, 0xf7, 0xc4, 0xc1, 0x89, 0x75, 0xf5, 0xcb, 0xa4, 0xf3, 0x6e, 0xc7,
0x12, 0x0b, 0x00, 0xbd, 0xd8, 0x38, 0xd4, 0x88, 0xce, 0x37, 0xa9, 0x45, 0x2e, 0x57, 0x44, 0x01 };
uint8_t dP[64] = { 0xc2, 0xa4, 0x34, 0xae, 0xd4, 0x79, 0x78, 0x90, 0x27, 0x2c, 0x6d, 0x3e, 0x04, 0x2e, 0xde, 0x61,
0x9b, 0xbd, 0xbc, 0x80, 0x92, 0x26, 0xf9, 0xf0, 0x1e, 0xce, 0xb8, 0x7f, 0x6f, 0x91, 0x09, 0x84,
0x3f, 0x6b, 0x04, 0x1c, 0x0c, 0x17, 0xef, 0x5e, 0x93, 0xdf, 0xdc, 0xce, 0xc6, 0xa0, 0x7a, 0x02,
0xe8, 0x15, 0x5f, 0xaf, 0x01, 0x5c, 0x10, 0x37, 0xca, 0x37, 0xe3, 0x99, 0x5b, 0x9d, 0x2c, 0x81 };
uint8_t dQ[64] = { 0x16, 0x12, 0x95, 0xdd, 0x9d, 0xa4, 0x3f, 0x83, 0x5f, 0xb0, 0xc1, 0x23, 0x44, 0x88, 0x97, 0x6e,
0xe3, 0x8b, 0x60, 0xde, 0x4b, 0x26, 0x85, 0xd6, 0x2b, 0xfd, 0x47, 0xcb, 0x8b, 0xd4, 0xa4, 0x1c,
0x08, 0x66, 0xb9, 0x2c, 0x20, 0x9e, 0x9b, 0x11, 0x7b, 0xe1, 0x0d, 0x88, 0x03, 0xfa, 0xa1, 0x76,
0x65, 0x6a, 0x01, 0x4b, 0x96, 0xe8, 0xf8, 0xb6, 0x3f, 0xdc, 0xe4, 0xba, 0xbf, 0xf8, 0x88, 0xa9 };
uint8_t qInv[64] = { 0x49, 0x72, 0x7f, 0x74, 0x16, 0xd2, 0xe0, 0x19, 0xb5, 0x43, 0x6f, 0xfe, 0xb0, 0x1b, 0x81, 0x7c,
0xd5, 0x7b, 0xb6, 0x7a, 0xec, 0xe0, 0xe5, 0x6a, 0x77, 0x77, 0xdb, 0x15, 0x47, 0xc1, 0x97, 0xd1,
0xb0, 0x0d, 0x08, 0x8c, 0x43, 0x67, 0x21, 0xa3, 0x1e, 0xba, 0x53, 0x87, 0xb8, 0xd4, 0x83, 0x94,
0xe4, 0x7c, 0x80, 0x6d, 0x3d, 0x1b, 0x54, 0x6b, 0x03, 0xfd, 0x3e, 0x6c, 0x3e, 0xad, 0x5f, 0xda };
uint8_t invR_p[64] = { 0x74, 0xc9, 0x11, 0x9b, 0x94, 0x7c, 0xc7, 0x0c, 0xd9, 0x39, 0x31, 0x06, 0x2c, 0x89, 0x7f, 0x90,
0x83, 0xec, 0xdd, 0x9e, 0xd1, 0x53, 0x85, 0xb1, 0x2e, 0x01, 0xc0, 0x7a, 0xce, 0x44, 0x56, 0x77,
0x4d, 0xbe, 0x96, 0xbe, 0xf2, 0x1d, 0x03, 0x09, 0x97, 0x7a, 0xd5, 0xa5, 0x5f, 0x2e, 0x32, 0xdb,
0xd9, 0xdd, 0x80, 0x3c, 0x08, 0x52, 0x8e, 0x72, 0x14, 0xfd, 0x09, 0x6c, 0x6a, 0x0a, 0x40, 0x91 };
uint8_t primeN_p[64] = { 0x94, 0x80, 0xcd, 0xff, 0x86, 0x44, 0x04, 0x7a, 0xa9, 0x62, 0x10, 0x8c, 0x4f, 0x9d, 0xee, 0x0e,
0x70, 0x56, 0xfc, 0xaf, 0x12, 0xaa, 0x05, 0xb0, 0x3c, 0x0c, 0x8c, 0xc1, 0xef, 0xc5, 0x70, 0xc8,
0x40, 0x76, 0xa2, 0xca, 0x4e, 0xe0, 0xae, 0x6d, 0x3c, 0xbc, 0x3b, 0xed, 0x85, 0xdf, 0x44, 0x39,
0xcd, 0x89, 0x45, 0x2a, 0x3b, 0x4b, 0x12, 0x2d, 0x34, 0xef, 0xa5, 0x05, 0x04, 0x9e, 0x96, 0x3f };
uint8_t invR_q[64] = { 0x07, 0x2d, 0x7c, 0xa1, 0x7d, 0xe7, 0xab, 0x44, 0x8d, 0xf0, 0xe1, 0xf0, 0xd0, 0x54, 0xb1, 0x7b,
0x74, 0x74, 0xac, 0x42, 0xc2, 0x49, 0x56, 0xab, 0xbd, 0x94, 0xe7, 0x5c, 0x6b, 0x06, 0x39, 0x2e,
0xc7, 0x75, 0xd3, 0xdc, 0x6c, 0x8b, 0xd8, 0x19, 0x7e, 0x6d, 0x59, 0x58, 0xc7, 0x95, 0x71, 0x9e,
0x10, 0x1a, 0xab, 0x07, 0x6f, 0xf1, 0x81, 0x37, 0x68, 0x88, 0x6c, 0xdd, 0x9d, 0xd8, 0x74, 0x82 };
uint8_t primeN_q[64] = { 0x09, 0x76, 0xeb, 0x06, 0xf9, 0x4b, 0xb4, 0xb8, 0xef, 0x02, 0x17, 0xf3, 0xa5, 0xa1, 0x12, 0xbc,
0x85, 0xda, 0x82, 0x91, 0x31, 0xd4, 0x07, 0x49, 0xdf, 0xef, 0x6a, 0x4a, 0x71, 0x0e, 0xe0, 0x8f,
0x14, 0xc7, 0x71, 0x3f, 0x92, 0xa8, 0x40, 0xd2, 0x9c, 0xf8, 0x76, 0x51, 0xaf, 0xe0, 0xbd, 0xbc,
0x09, 0x21, 0x2a, 0x68, 0xab, 0x4a, 0xfa, 0x5a, 0xeb, 0x6f, 0xb6, 0x65, 0x67, 0xc3, 0x42, 0x37 };
uint8_t c[32] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x34, 0x56, 0x78 };
uint8_t m[128] = { 0x94, 0x56, 0x39, 0x91, 0x66, 0x79, 0x4b, 0x55, 0x36, 0x55, 0x13, 0x90, 0x9d, 0x6c, 0x40, 0x02,
0xf8, 0xd5, 0xb3, 0xae, 0x15, 0x90, 0xcd, 0xcf, 0x7b, 0x18, 0xe2, 0x03, 0x2b, 0xf2, 0x65, 0x08,
0xfc, 0xc8, 0xbf, 0xc2, 0x47, 0xc4, 0x72, 0x55, 0x8a, 0x50, 0x26, 0x5e, 0x73, 0x7f, 0x18, 0x1e,
0x6f, 0x64, 0x8f, 0x42, 0xd0, 0x1b, 0x92, 0x0e, 0xe3, 0x1e, 0x39, 0xea, 0x38, 0x76, 0x0b, 0xf8,
0x0f, 0x25, 0x5d, 0x5d, 0x5d, 0x52, 0xf4, 0x7f, 0x74, 0x27, 0xdf, 0x4a, 0x89, 0xc4, 0xa3, 0xa7,
0xf8, 0xd3, 0xf9, 0x3a, 0xaa, 0x6a, 0x34, 0x42, 0xb3, 0x5e, 0x5b, 0x68, 0x96, 0xc7, 0xc4, 0xfa,
0x22, 0x95, 0x8a, 0xbf, 0xa6, 0xf3, 0x54, 0x2e, 0xcf, 0x66, 0x0f, 0x62, 0xef, 0xac, 0x11, 0xc1,
0x69, 0xb2, 0x64, 0xf9, 0xcc, 0x75, 0x68, 0x50, 0x8f, 0xf1, 0xfe, 0x5c, 0xfa, 0x27, 0x6c, 0x7b };
uint32_t dsa_tmp[32];
uint32_t i = 0;
uint8_t *k;
struct bflb_dsa_s dsa_handle;
uint32_t time = 0;
printf("DSA Case\r\n");
bflb_sec_dsa_init(&dsa_handle, 1024);
dsa_handle.n = (uint32_t *)n;
dsa_handle.e = (uint32_t *)e;
dsa_handle.d = (uint32_t *)d;
dsa_handle.crtCfg.dP = (uint32_t *)dP;
dsa_handle.crtCfg.dQ = (uint32_t *)dQ;
dsa_handle.crtCfg.qInv = (uint32_t *)qInv;
dsa_handle.crtCfg.p = (uint32_t *)p;
dsa_handle.crtCfg.invR_p = (uint32_t *)invR_p;
dsa_handle.crtCfg.primeN_p = (uint32_t *)primeN_p;
dsa_handle.crtCfg.q = (uint32_t *)q;
dsa_handle.crtCfg.invR_q = (uint32_t *)invR_q;
dsa_handle.crtCfg.primeN_q = (uint32_t *)primeN_q;
time = (unsigned int)bflb_mtimer_get_time_ms();
if (0 != bflb_sec_dsa_sign(&dsa_handle, (uint32_t *)c, 8, dsa_tmp)) {
printf("Sign Fail\r\n");
}
printf("DSA sign time=%dms\r\n", (unsigned int)bflb_mtimer_get_time_ms() - time);
printf("Check sign\r\n");
k = (uint8_t *)(dsa_tmp);
for (i = 0; i < sizeof(m); i++) {
if (k[i] != m[i]) {
printf("DSA sign fail\r\n");
while(1)
{}
}
}
time = (unsigned int)bflb_mtimer_get_time_ms();
if (0 != bflb_sec_dsa_verify(&dsa_handle, (uint32_t *)c, 8, (uint32_t *)m)) {
printf("DSA verify fail\r\n");
}
printf("DSA verify time=%dms\r\n", (unsigned int)bflb_mtimer_get_time_ms()- time);
printf("Finished\r\n");
while (1) {
bflb_mtimer_delay_ms(2000);
}
}

1
examples/peripherals/sec_eng/sec_eng_dsa/proj.conf Normal file
View File

@ -0,0 +1 @@
#set(CONFIG_XXX 1)

16
examples/peripherals/sec_eng/sec_eng_sha/main.c
View File

@ -126,13 +126,13 @@ static const unsigned char sha512_test_sum[6][64] = {
0x4E, 0xAD, 0xB2, 0x17, 0xAD, 0x8C, 0xC0, 0x9B }
};
ATTR_NOCACHE_RAM_SECTION __attribute__((aligned(32))) uint8_t sha_input_buf[1000]; /* input addr must be align 32 */
ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((aligned(32))) uint8_t sha_input_buf[1000]; /* input addr must be align 32 */
uint8_t sha_output_buf[128];
ATTR_NOCACHE_RAM_SECTION struct bflb_sha1_ctx_s ctx_sha1;
ATTR_NOCACHE_RAM_SECTION struct bflb_sha256_ctx_s ctx_sha256;
ATTR_NOCACHE_RAM_SECTION struct bflb_sha512_ctx_s ctx_sha512;
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha1_ctx_s ctx_sha1;
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha256_ctx_s ctx_sha256;
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha512_ctx_s ctx_sha512;
static uint32_t bflb_data_compare(const uint8_t *expected, uint8_t *input, uint32_t len)
{
@ -192,7 +192,7 @@ int main(void)
}
bflb_sha256_finish(sha, &ctx_sha256, sha_output_buf);
bflb_data_compare(sha256_test_sum[i], sha_output_buf, 20);
bflb_data_compare(sha256_test_sum[i], sha_output_buf, 28);
}
printf("sha224 success\r\n");
@ -210,7 +210,7 @@ int main(void)
}
bflb_sha256_finish(sha, &ctx_sha256, sha_output_buf);
bflb_data_compare(sha256_test_sum[i + 3], sha_output_buf, 20);
bflb_data_compare(sha256_test_sum[i + 3], sha_output_buf, 32);
}
printf("sha256 success\r\n");
@ -228,7 +228,7 @@ int main(void)
}
bflb_sha512_finish(sha, &ctx_sha512, sha_output_buf);
bflb_data_compare(sha512_test_sum[i], sha_output_buf, 20);
bflb_data_compare(sha512_test_sum[i], sha_output_buf, 48);
}
printf("sha384 success\r\n");
@ -246,7 +246,7 @@ int main(void)
}
bflb_sha512_finish(sha, &ctx_sha512, sha_output_buf);
bflb_data_compare(sha512_test_sum[i + 3], sha_output_buf, 20);
bflb_data_compare(sha512_test_sum[i + 3], sha_output_buf, 64);
}
printf("sha512 success\r\n");
bflb_group0_release_sha_access(sha);

9
examples/peripherals/sec_eng/sec_eng_sha_costtime/CMakeLists.txt Normal file
View File

@ -0,0 +1,9 @@
cmake_minimum_required(VERSION 3.15)
include(proj.conf)
find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE})
sdk_set_main_file(main.c)
project(sec_eng_sha_costtime)

13
examples/peripherals/sec_eng/sec_eng_sha_costtime/Makefile Normal file
View File

@ -0,0 +1,13 @@
SDK_DEMO_PATH ?= .
BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../..
export BL_SDK_BASE
CHIP ?= bl616
BOARD ?= bl616dk
CROSS_COMPILE ?= riscv64-unknown-elf-
# add custom cmake definition
#cmake_definition+=-Dxxx=sss
include $(BL_SDK_BASE)/project.build

81
examples/peripherals/sec_eng/sec_eng_sha_costtime/main.c Normal file
View File

@ -0,0 +1,81 @@
#include "bflb_mtimer.h"
#include "bflb_sec_sha.h"
#include "board.h"
ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((aligned(32))) uint8_t sha_input_buf[16 * 1024]; /* input addr must be align 32 */
uint8_t sha_output_buf[128];
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha1_ctx_s ctx_sha1;
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha256_ctx_s ctx_sha256;
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha512_ctx_s ctx_sha512;
int main(void)
{
uint64_t start_time;
board_init();
struct bflb_device_s *sha;
sha = bflb_device_get_by_name("sha");
bflb_group0_request_sha_access(sha);
for (uint32_t i = 0; i < 16 * 1024; i++) {
sha_input_buf[i] = i & 0xff;
}
bflb_sha_init(sha, SHA_MODE_SHA1);
for (uint32_t i = 1; i <= 1024; i++) {
start_time = bflb_mtimer_get_time_us();
bflb_sha1_start(sha, &ctx_sha1);
bflb_sha1_update(sha, &ctx_sha1, sha_input_buf, 16 * i);
bflb_sha1_finish(sha, &ctx_sha1, sha_output_buf);
printf("sha1 block:%d cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
printf("sha1 success\r\n");
bflb_sha_init(sha, SHA_MODE_SHA224);
for (uint32_t i = 1; i <= 1024; i++) {
start_time = bflb_mtimer_get_time_us();
bflb_sha256_start(sha, &ctx_sha256);
bflb_sha256_update(sha, &ctx_sha256, sha_input_buf, 16 * i);
bflb_sha256_finish(sha, &ctx_sha256, sha_output_buf);
printf("sha224 block:%d cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
bflb_sha_init(sha, SHA_MODE_SHA256);
for (uint32_t i = 1; i <= 1024; i++) {
start_time = bflb_mtimer_get_time_us();
bflb_sha256_start(sha, &ctx_sha256);
bflb_sha256_update(sha, &ctx_sha256, sha_input_buf, 16 * i);
bflb_sha256_finish(sha, &ctx_sha256, sha_output_buf);
printf("sha256 block:%d cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
bflb_sha_init(sha, SHA_MODE_SHA384);
for (uint32_t i = 1; i <= 1024; i++) {
start_time = bflb_mtimer_get_time_us();
bflb_sha512_start(sha, &ctx_sha512);
bflb_sha512_update(sha, &ctx_sha512, sha_input_buf, 16 * i);
bflb_sha512_finish(sha, &ctx_sha512, sha_output_buf);
printf("sha384 block:%d cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
bflb_sha_init(sha, SHA_MODE_SHA512);
for (uint32_t i = 1; i <= 1024; i++) {
start_time = bflb_mtimer_get_time_us();
bflb_sha512_start(sha, &ctx_sha512);
bflb_sha512_update(sha, &ctx_sha512, sha_input_buf, 16 * i);
bflb_sha512_finish(sha, &ctx_sha512, sha_output_buf);
printf("sha512 block:%d cost time:%d us\r\n", i, (uint32_t)(bflb_mtimer_get_time_us() - start_time));
}
bflb_group0_release_sha_access(sha);
while (1) {
bflb_mtimer_delay_ms(2000);
}
}

1
examples/peripherals/sec_eng/sec_eng_sha_costtime/proj.conf Normal file
View File

@ -0,0 +1 @@
#set(CONFIG_XXX 1)

27
examples/peripherals/sec_eng/sec_eng_sha_link/main.c
View File

@ -45,7 +45,7 @@ const uint8_t sha512_testsum[2][128] = {
0x84, 0x21, 0xc5, 0x75, 0x9c, 0x85, 0xc3, 0x37 }
};
static struct bflb_sha_link_s sha256_link = {
ATTR_NOCACHE_RAM_SECTION struct bflb_sha_link_s sha256_link = {
.sha_mode = SHA_MODE_SHA256, /* Sha-256 */
.sha_newhash_dis = 0, /* New hash */
.sha_intclr = 0, /* Not clear interrupt */
@ -56,7 +56,7 @@ static struct bflb_sha_link_s sha256_link = {
{ 0 } /* Result of SHA */
};
static struct bflb_sha_link_s sha512_link = {
ATTR_NOCACHE_RAM_SECTION struct bflb_sha_link_s sha512_link = {
.sha_mode = SHA_MODE_SHA512, /* Sha-512 */
.sha_newhash_dis = 0, /* New hash */
.sha_intclr = 0, /* Not clear interrupt */
@ -67,12 +67,12 @@ static struct bflb_sha_link_s sha512_link = {
{ 0 } /* Result of SHA */
};
ATTR_NOCACHE_RAM_SECTION __attribute__((aligned(32))) uint8_t sha_input_buf[1000];
ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((aligned(32))) uint8_t sha_input_buf[1000];
uint8_t sha_output_buf[128];
ATTR_NOCACHE_RAM_SECTION struct bflb_sha256_ctx_s ctx_sha256;
ATTR_NOCACHE_RAM_SECTION struct bflb_sha512_ctx_s ctx_sha512;
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha256_link_ctx_s ctx_sha256;
ATTR_NOCACHE_NOINIT_RAM_SECTION struct bflb_sha512_link_ctx_s ctx_sha512;
static uint32_t bflb_data_compare(const uint8_t *expected, uint8_t *input, uint32_t len)
{
@ -100,22 +100,21 @@ int main(void)
bflb_sha_link_init(sha);
bflb_sha256_link_start(sha, &ctx_sha256);
bflb_sha256_link_start(sha, &ctx_sha256, &sha256_link);
memcpy(sha_input_buf, sha256_testbuf[0], 104);
bflb_sha256_link_update(sha, &ctx_sha256, (uint32_t)&sha256_link, sha_input_buf, 80);
bflb_sha256_link_update(sha, &ctx_sha256, (uint32_t)&sha256_link, &sha_input_buf[80], 104 - 80);
bflb_sha256_link_finish(sha, &ctx_sha256, (uint32_t)&sha256_link, sha_output_buf);
bflb_sha256_link_update(sha, &ctx_sha256, sha_input_buf, 80);
bflb_sha256_link_update(sha, &ctx_sha256, &sha_input_buf[80], 104 - 80);
bflb_sha256_link_finish(sha, &ctx_sha256, sha_output_buf);
bflb_data_compare(sha256_testsum[0], sha_output_buf, 32);
printf("sha256 link success\r\n");
bflb_sha512_link_start(sha, &ctx_sha512);
bflb_sha512_link_start(sha, &ctx_sha512, &sha512_link);
memcpy(sha_input_buf, sha512_testbuf[0], 208);
bflb_sha512_link_update(sha, &ctx_sha512, (uint32_t)&sha512_link, sha_input_buf, 160);
bflb_sha512_link_update(sha, &ctx_sha512, (uint32_t)&sha512_link, &sha_input_buf[160], 208 - 80);
bflb_sha512_link_finish(sha, &ctx_sha512, (uint32_t)&sha512_link, sha_output_buf);
bflb_sha512_link_update(sha, &ctx_sha512, sha_input_buf, 160);
bflb_sha512_link_update(sha, &ctx_sha512, &sha_input_buf[160], 208 - 160);
bflb_sha512_link_finish(sha, &ctx_sha512, sha_output_buf);
bflb_data_compare(sha512_testsum[0], sha_output_buf, 64);
printf("sha512 link success\r\n");
bflb_group0_release_sha_access(sha);
while (1) {
bflb_mtimer_delay_ms(2000);

4
examples/peripherals/spi/spi_dma/main.c
View File

@ -11,8 +11,8 @@ struct bflb_device_s *spi0;
struct bflb_device_s *dma0_ch0;
struct bflb_device_s *dma0_ch1;
static ATTR_NOCACHE_RAM_SECTION uint32_t tx_buffer[256];
static ATTR_NOCACHE_RAM_SECTION uint32_t rx_buffer[256];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t tx_buffer[256];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint32_t rx_buffer[256];
static volatile uint8_t dma_tc_flag0 = 0;
static volatile uint8_t dma_tc_flag1 = 0;

16
examples/peripherals/timer/timer_int/main.c
View File

@ -53,21 +53,21 @@ int main(void)
struct bflb_timer_config_s cfg0;
cfg0.counter_mode = TIMER_COUNTER_MODE_PROLOAD; /* preload when match occur */
cfg0.clock_source = TIMER_CLKSRC_XTAL;
cfg0.clock_div = 0; /* for bl616/bl808/bl606p is 39, for bl702 is 31 */
cfg0.clock_div = 39; /* for bl616/bl808/bl606p is 39, for bl702 is 31 */
cfg0.trigger_comp_id = TEST_TIMER_COMP_ID;
cfg0.comp0_val = 230000; /* match value 0 */
cfg0.comp1_val = 260000; /* match value 1 */
cfg0.comp2_val = 290000; /* match value 2 */
cfg0.comp0_val = 1000000; /* match value 0 */
cfg0.comp1_val = 1500000; /* match value 1 */
cfg0.comp2_val = 2500000; /* match value 2 */
cfg0.preload_val = 0; /* preload value */
struct bflb_timer_config_s cfg1;
cfg1.counter_mode = TIMER_COUNTER_MODE_PROLOAD;
cfg1.clock_source = TIMER_CLKSRC_XTAL;
cfg1.clock_div = 0; /* for bl616/bl808/bl606p is 39, for bl702 is 31 */
cfg1.clock_div = 39; /* for bl616/bl808/bl606p is 39, for bl702 is 31 */
cfg1.trigger_comp_id = TEST_TIMER_COMP_ID;
cfg1.comp0_val = 330000; /* match value 0 */
cfg1.comp1_val = 360000; /* match value 1 */
cfg1.comp2_val = 390000; /* match value 2 */
cfg1.comp0_val = 1000000; /* match value 0 */
cfg1.comp1_val = 1500000; /* match value 1 */
cfg1.comp2_val = 2500000; /* match value 2 */
cfg1.preload_val = 0; /* preload value */
timer0 = bflb_device_get_by_name("timer0");

8
examples/peripherals/uart/uart_dma/main.c
View File

@ -8,10 +8,10 @@ struct bflb_device_s *uart1;
struct bflb_device_s *dma0_ch0;
struct bflb_device_s *dma0_ch1;
static ATTR_NOCACHE_RAM_SECTION uint8_t src_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t src2_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t src3_buffer[4100];
static ATTR_NOCACHE_RAM_SECTION uint8_t receive_buffer[50] = { 0 };
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t src_buffer[4100];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t src2_buffer[4100];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t src3_buffer[4100];
static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t receive_buffer[50] = { 0 };
static volatile uint8_t dma_tc_flag0 = 0;
static volatile uint8_t dma_tc_flag1 = 0;