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[update][lhal] update lhal

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* update lhal api comments
* add cam driver
* add efuse driver
* add iso11898 driver
This commit is contained in:
jzlv 2022-12-21 20:20:33 +08:00
parent 185805cbbe
commit a77b0dc866
60 changed files with 8782 additions and 429 deletions
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98
drivers/lhal/CMakeLists.txt
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@ -8,42 +8,71 @@ sdk_library_add_sources(src/bflb_common.c)
endif()
endif()
sdk_library_add_sources(src/bflb_adc.c)
if((NOT ("${CHIP}" STREQUAL "bl702l")))
sdk_library_add_sources(src/bflb_dac.c)
endif()
sdk_library_add_sources(src/bflb_dma.c)
if((NOT ("${CHIP}" STREQUAL "bl602")) AND (NOT ("${CHIP}" STREQUAL "bl702l")))
sdk_library_add_sources(src/bflb_emac.c)
endif()
sdk_library_add_sources(src/bflb_gpio.c)
sdk_library_add_sources(src/bflb_i2c.c)
if((NOT ("${CHIP}" STREQUAL "bl628")))
sdk_library_add_sources(src/bflb_ir.c)
endif()
sdk_library_add_sources(src/bflb_uart.c)
sdk_library_add_sources(src/bflb_spi.c)
sdk_library_add_sources(src/bflb_rtc.c)
sdk_library_add_sources(src/bflb_sec_aes.c)
sdk_library_add_sources(src/bflb_sec_sha.c)
sdk_library_add_sources(src/bflb_sec_trng.c)
# sdk_library_add_sources(src/bflb_sec_irq.c)
sdk_library_add_sources(src/bflb_timer.c)
sdk_library_add_sources(src/bflb_wdg.c)
sdk_library_add_sources(src/bflb_cks.c)
sdk_library_add_sources(src/bflb_mjpeg.c)
if("${CHIP}" STREQUAL "bl628")
sdk_library_add_sources(src/bflb_clock.c)
endif()
sdk_library_add_sources(src/bflb_ef_ctrl.c)
sdk_library_add_sources(
src/bflb_adc.c
src/bflb_cks.c
src/bflb_ef_ctrl.c
src/bflb_gpio.c
src/bflb_i2c.c
src/bflb_dma.c
src/bflb_rtc.c
src/bflb_sec_aes.c
src/bflb_sec_sha.c
src/bflb_sec_trng.c
src/bflb_spi.c
src/bflb_timer.c
src/bflb_uart.c
src/bflb_wdg.c
)
if(("${CHIP}" STREQUAL "bl702") OR ("${CHIP}" STREQUAL "bl602"))
sdk_library_add_sources(src/bflb_pwm_v1.c)
if("${CHIP}" STREQUAL "bl602")
sdk_library_add_sources(
src/bflb_dac.c
src/bflb_ir.c
src/bflb_pwm_v1.c
)
elseif("${CHIP}" STREQUAL "bl702")
sdk_library_add_sources(
src/bflb_dac.c
src/bflb_emac.c
src/bflb_ir.c
src/bflb_pwm_v1.c
src/bflb_cam.c
)
elseif("${CHIP}" STREQUAL "bl702l")
sdk_library_add_sources(src/bflb_pwm_v1.c)
sdk_library_add_sources(src/bflb_pwm_v2.c)
else()
sdk_library_add_sources(src/bflb_pwm_v2.c)
sdk_library_add_sources(
src/bflb_kys.c
src/bflb_pwm_v1.c
src/bflb_pwm_v2.c
)
elseif("${CHIP}" STREQUAL "bl616")
sdk_library_add_sources(
src/bflb_dac.c
src/bflb_emac.c
src/bflb_ir.c
src/bflb_mjpeg.c
src/bflb_pwm_v2.c
src/bflb_cam.c
src/bflb_iso11898.c
)
elseif("${CHIP}" STREQUAL "bl628")
sdk_library_add_sources(
src/bflb_dac.c
src/bflb_emac.c
src/bflb_clock.c
src/bflb_pwm_v2.c
src/bflb_iso11898.c
)
elseif("${CHIP}" STREQUAL "bl808")
sdk_library_add_sources(
src/bflb_dac.c
src/bflb_emac.c
src/bflb_ir.c
src/bflb_mjpeg.c
src/bflb_pwm_v2.c
src/bflb_cam.c
src/bflb_iso11898.c
)
endif()
if(CONFIG_CHERRYUSB)
@ -51,6 +80,7 @@ if("${CHIP}" STREQUAL "bl702")
sdk_library_add_sources(src/bflb_usb_v1.c)
elseif(("${CHIP}" STREQUAL "bl602") OR ("${CHIP}" STREQUAL "bl702l"))
# no usb
elseif(("${CHIP}" STREQUAL "bl628"))
else()
sdk_library_add_sources(src/bflb_usb_v2.c)
endif()

2768
drivers/lhal/Doxyfile Normal file
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File diff suppressed because it is too large Load Diff

7
drivers/lhal/config/bl602/device_table.c
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@ -190,6 +190,13 @@ struct bflb_device_s bl602_device_table[] = {
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_IR,
.user_data = NULL },
{ .name = "sdio2",
.reg_base = SDU_BASE,
.irq_num = BL602_IRQ_SDIO,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_SDIO2,
.user_data = NULL },
};
struct bflb_device_s *bflb_device_get_by_name(const char *name)

4
drivers/lhal/config/bl616/bl616_irq.h
View File

@ -26,7 +26,7 @@
#define BL616_IRQ_BMX_MCU_TO (BL616_IRQ_NUM_BASE + 1)
#define BL616_IRQ_DBI (BL616_IRQ_NUM_BASE + 2)
#define BL616_IRQ_SDU_SOFT_RST (BL616_IRQ_NUM_BASE + 3)
#define BL616_IRQ_AUDIO (BL616_IRQ_NUM_BASE + 4)
#define BL616_IRQ_AUADC (BL616_IRQ_NUM_BASE + 4)
#define BL616_IRQ_RF_TOP_INT0 (BL616_IRQ_NUM_BASE + 5)
#define BL616_IRQ_RF_TOP_INT1 (BL616_IRQ_NUM_BASE + 6)
#define BL616_IRQ_SDIO (BL616_IRQ_NUM_BASE + 7)
@ -44,7 +44,7 @@
#define BL616_IRQ_WIFI_TBTT_WAKEUP (BL616_IRQ_NUM_BASE + 19)
#define BL616_IRQ_IRRX (BL616_IRQ_NUM_BASE + 20)
#define BL616_IRQ_USB (BL616_IRQ_NUM_BASE + 21)
#define BL616_IRQ_AUPDM (BL616_IRQ_NUM_BASE + 22)
#define BL616_IRQ_AUDAC (BL616_IRQ_NUM_BASE + 22)
#define BL616_IRQ_MJPEG (BL616_IRQ_NUM_BASE + 23)
#define BL616_IRQ_EMAC (BL616_IRQ_NUM_BASE + 24)
#define BL616_IRQ_GPADC_DMA (BL616_IRQ_NUM_BASE + 25)

2
drivers/lhal/config/bl616/bl616_memorymap.h
View File

@ -93,7 +93,7 @@
#define AON_BASE ((uint32_t)0x2000f000)
#define MM_MISC_BASE ((uint32_t)0x20050000)
#define PSRAM_CTRL_BASE ((uint32_t)0x20052000)
#define AUPWM_BASE ((uint32_t)0x20055000)
#define AUDAC_BASE ((uint32_t)0x20055000)
#define EFUSE_BASE ((uint32_t)0x20056000)
#define EF_DATA_BASE ((uint32_t)0x20056000)
#define EF_CTRL_BASE ((uint32_t)0x20056000)

28
drivers/lhal/config/bl616/device_table.c
View File

@ -205,6 +205,34 @@ struct bflb_device_s bl616_device_table[] = {
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_IR,
.user_data = NULL },
{ .name = "cam0",
.reg_base = DVP2AXI0_BASE,
.irq_num = BL616_IRQ_DVP2BUS_INT0,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam1",
.reg_base = DVP2AXI1_BASE,
.irq_num = BL616_IRQ_DVP2BUS_INT1,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "audac",
.reg_base = AUDAC_BASE,
.irq_num = BL616_IRQ_AUDAC,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_AUDIODAC,
.user_data = NULL },
{ .name = "sdio2",
.reg_base = SDU_BASE,
.irq_num = BL616_IRQ_SDIO,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_SDIO2,
.user_data = NULL },
};
struct bflb_device_s *bflb_device_get_by_name(const char *name)

7
drivers/lhal/config/bl702/device_table.c
View File

@ -204,6 +204,13 @@ struct bflb_device_s bl702_device_table[] = {
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_KYS,
.user_data = NULL },
{ .name = "cam0",
.reg_base = CAM_BASE,
.irq_num = BL702_IRQ_CAM,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
};
struct bflb_device_s *bflb_device_get_by_name(const char *name)

10
drivers/lhal/config/bl808/bl808_memorymap.h
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@ -1,5 +1,5 @@
#ifndef __BL616_MEMORYMAP_H
#define __BL616_MEMORYMAP_H
#ifndef __BL808_MEMORYMAP_H
#define __BL808_MEMORYMAP_H
/****************************************************************************
* Included Files
@ -118,9 +118,9 @@
#define TIMER1_BASE ((uint32_t)0x30009000)
#define PSRAM_UHS_BASE ((uint32_t)0x3000f000)
/* ISP_SUBSYS */
#define ISP_MISC_BASE ((uint32_t)0x30010000)
#define ISP_BASE ((uint32_t)0x30011000)
/* MM_SUBSYS */
#define CAM_FRONT_BASE ((uint32_t)0x30010000)
#define MM_SUBSYS_BASE ((uint32_t)0x30011000)
#define DVP0_BASE ((uint32_t)0x30012000)
#define DVP1_BASE ((uint32_t)0x30012100)
#define DVP2_BASE ((uint32_t)0x30012200)

99
drivers/lhal/config/bl808/device_table.c
View File

@ -324,6 +324,105 @@ struct bflb_device_s bl808_device_table[] = {
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_TIMER,
.user_data = NULL },
{ .name = "cam0",
.reg_base = DVP0_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT0,
#else
.irq_num = 0xff,
#endif
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam1",
.reg_base = DVP1_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT1,
#else
.irq_num = 0xff,
#endif
.idx = 1,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam2",
.reg_base = DVP2_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT2,
#else
.irq_num = 0xff,
#endif
.idx = 2,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam3",
.reg_base = DVP3_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT3,
#else
.irq_num = 0xff,
#endif
.idx = 3,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam4",
.reg_base = DVP4_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT4,
#else
.irq_num = 0xff,
#endif
.idx = 4,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam5",
.reg_base = DVP5_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT5,
#else
.irq_num = 0xff,
#endif
.idx = 5,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam6",
.reg_base = DVP6_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT6,
#else
.irq_num = 0xff,
#endif
.idx = 6,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "cam7",
.reg_base = DVP7_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_DVP2BUS_INT7,
#else
.irq_num = 0xff,
#endif
.idx = 7,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CAMERA,
.user_data = NULL },
{ .name = "csi",
.reg_base = CSI_BASE,
#if defined(CPU_D0)
.irq_num = BL808_IRQ_MIPI_CSI,
#else
.irq_num = 0xff,
#endif
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_CSI,
.user_data = NULL },
};
struct bflb_device_s *bflb_device_get_by_name(const char *name)

134
drivers/lhal/include/bflb_adc.h
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@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup ADC
* @{
*/
/** @defgroup ADC_CHANNEL adc channel definition
* @{
*/
@ -53,7 +61,7 @@
* @}
*/
/** @defgroup ADC_VREF adc reference select
/** @defgroup ADC_VREF adc reference select definition
* @{
*/
#define ADC_VREF_3P2V 0
@ -144,28 +152,152 @@ struct bflb_adc_result_s {
extern "C" {
#endif
/**
* @brief Initialize adc.
*
* @param [in] dev device handle
* @param [in] config pointer to save adc configuration
*/
void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *config);
/**
* @brief Deinitialize adc.
*
* @param [in] dev device handle
*/
void bflb_adc_deinit(struct bflb_device_s *dev);
/**
* @brief Enable adc rx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_adc_link_rxdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Config adc channels to sample.
*
* @param [in] dev device handle
* @param [in] chan pointer to the channel configurations.
* @param [in] channels pair number of channels
* @return Zero on success; a negated errno value on failure
*/
int bflb_adc_channel_config(struct bflb_device_s *dev, struct bflb_adc_channel_s *chan, uint8_t channels);
/**
* @brief Start adc conversion
*
* @param [in] dev device handle
*/
void bflb_adc_start_conversion(struct bflb_device_s *dev);
/**
* @brief Stop adc conversion
*
* @param [in] dev device handle
*/
void bflb_adc_stop_conversion(struct bflb_device_s *dev);
/**
* @brief Get adc number of completed conversions
*
* @param [in] dev device handle
* @return number of completed conversions
*/
uint8_t bflb_adc_get_count(struct bflb_device_s *dev);
/**
* @brief Read adc conversion value
*
* @param [in] dev device handle
* @return conversion value
*/
uint32_t bflb_adc_read_raw(struct bflb_device_s *dev);
/**
* @brief Enable or disable adc conversion completion interrupt.
* Triggerring when a channel conversion is completed.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_adc_rxint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable adc error interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_adc_errint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Get adc interrupt instatus.
*
* @param [in] dev device handle
* @return interrupt instatus value, use @ref ADC_INTSTS
*/
uint32_t bflb_adc_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Clear adc interrupt instatus.
*
* @param [in] dev device handle
* @param [in] int_clear interrupt clear value, use @ref ADC_INTCLR
*/
void bflb_adc_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
/**
* @brief Parse adc conversion value into millivolt and actual numerical value.
*
* @param [in] dev device handle
* @param [in] buffer pointer to adc original value from bflb_adc_read_raw api
* @param [out] result pointer to save parse result
* @param [in] count count to parse
*/
void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct bflb_adc_result_s *result, uint16_t count);
/**
* @brief Initialize adc temperature sensor
*
* @param [in] dev device handle
* @param [in] tsen_mod temperature sensor mode, use @ref ADC_TSEN_MOD
*/
void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod);
/**
* @brief Get adc temperature
*
* @param [in] dev device handle
* @return temperature
*/
float bflb_adc_tsen_get_temp(struct bflb_device_s *dev);
/**
* @brief Enable adc vbat power.
*
* @param [in] dev device handle
*/
void bflb_adc_vbat_enable(struct bflb_device_s *dev);
/**
* @brief Disable adc vbat power.
*
* @param [in] dev device handle
*/
void bflb_adc_vbat_disable(struct bflb_device_s *dev);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

325
drivers/lhal/include/bflb_cam.h Normal file
View File

@ -0,0 +1,325 @@
#ifndef _BFLB_CAM_H
#define _BFLB_CAM_H
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup CAM
* @{
*/
/** @defgroup CAM_INPUT_FORMAT CAMERA input format definition
* @{
*/
#define CAM_INPUT_FORMAT_YUV422_YUYV 0
#define CAM_INPUT_FORMAT_YUV422_YVYU 1
#define CAM_INPUT_FORMAT_YUV422_UYVY 2
#define CAM_INPUT_FORMAT_YUV422_VYUY 3
#define CAM_INPUT_FORMAT_GRAY 4
#define CAM_INPUT_FORMAT_RGB565 5
#define CAM_INPUT_FORMAT_BGR565 6
#define CAM_INPUT_FORMAT_RGB888 7
#define CAM_INPUT_FORMAT_BGR888 8
/**
* @}
*/
/** @defgroup CAM_OUTPUT_FORMAT CAMERA output format definition
* @{
*/
#define CAM_OUTPUT_FORMAT_AUTO 0
#define CAM_OUTPUT_FORMAT_YUV422 1
#define CAM_OUTPUT_FORMAT_GRAY 2
#define CAM_OUTPUT_FORMAT_YUV422_UV 3
#define CAM_OUTPUT_FORMAT_YUV420_UV 4
#define CAM_OUTPUT_FORMAT_RGB565_OR_BGR565 5
#define CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 6
#if !defined(BL702)
#define CAM_OUTPUT_FORMAT_RGB888_TO_RGB565 7
#define CAM_OUTPUT_FORMAT_RGB888_TO_BGR565 8
#define CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888 9
#endif
/**
* @}
*/
/** @defgroup CAM_INTSTS CAMERA interrupt status definition
* @{
*/
#if defined(BL702)
#define CAM_INTSTS_NORMAL (1 << 0)
#define CAM_INTSTS_MEMORY_OVERWRITE (1 << 2)
#define CAM_INTSTS_FRAME_OVERWRITE (1 << 4)
#define CAM_INTSTS_FIFO_OVERWRITE (1 << 6)
#define CAM_INTSTS_HSYNC_MISMATCH (1 << 8)
#define CAM_INTSTS_VSYNC_MISMATCH (1 << 9)
#else
#define CAM_INTSTS_NORMAL (1 << 12)
#define CAM_INTSTS_MEMORY_OVERWRITE (1 << 13)
#define CAM_INTSTS_FRAME_OVERWRITE (1 << 14)
#define CAM_INTSTS_FIFO_OVERWRITE (1 << 15)
#define CAM_INTSTS_HSYNC_MISMATCH (1 << 21)
#define CAM_INTSTS_VSYNC_MISMATCH (1 << 22)
#endif
/**
* @}
*/
/** @defgroup CAM_INTMASK CAMERA interrupt mask definition
* @{
*/
#if defined(BL702)
#define CAM_INTMASK_NORMAL (1 << 0)
#define CAM_INTMASK_MEMORY_OVERWRITE (1 << 2)
#define CAM_INTMASK_FRAME_OVERWRITE (1 << 3)
#define CAM_INTMASK_FIFO_OVERWRITE (1 << 4)
#define CAM_INTMASK_HSYNC_MISMATCH (1 << 5)
#define CAM_INTMASK_VSYNC_MISMATCH (1 << 6)
#else
#define CAM_INTMASK_NORMAL (1 << 8)
#define CAM_INTMASK_MEMORY_OVERWRITE (1 << 9)
#define CAM_INTMASK_FRAME_OVERWRITE (1 << 10)
#define CAM_INTMASK_FIFO_OVERWRITE (1 << 11)
#define CAM_INTMASK_HSYNC_MISMATCH (1 << 6)
#define CAM_INTMASK_VSYNC_MISMATCH (1 << 7)
#endif
/**
* @}
*/
/** @defgroup CAM_INTCLR CAMERA interrupt clear definition
* @{
*/
#define CAM_INTCLR_NORMAL (1 << 4)
#define CAM_INTCLR_MEMORY_OVERWRITE (1 << 5)
#define CAM_INTCLR_FRAME_OVERWRITE (1 << 6)
#define CAM_INTCLR_FIFO_OVERWRITE (1 << 7)
#define CAM_INTCLR_HSYNC_MISMATCH (1 << 8)
#define CAM_INTCLR_VSYNC_MISMATCH (1 << 9)
/**
* @}
*/
/** @defgroup CAM_POLARITY CAMERA hsync/vsync polarity active level definition
* @{
*/
#define CAM_POLARITY_ACTIVE_LOW 0
#define CAM_POLARITY_ACTIVE_HIGH 1
/**
* @}
*/
/** @defgroup CAM_INPUT_SOURCE CAMERA input source definition
* @{
*/
#define CAM_INPUT_SOURCE_DVP 0
#if defined(BL808)
#define CAM_INPUT_SOURCE_CSI 1
#endif
/**
* @}
*/
/** @defgroup CAM_BURST CAMERA burst length definition
* @{
*/
#define CAM_BURST_INCR1 0
#define CAM_BURST_INCR4 1
#define CAM_BURST_INCR8 2
#define CAM_BURST_INCR16 3
#if !defined(BL702)
#define CAM_BURST_INCR32 5
#define CAM_BURST_INCR64 6
#endif
/**
* @}
*/
/** @defgroup CAM_CMD CAMERA feature control cmd definition
* @{
*/
#define CAM_CMD_SET_VSYNC_POLARITY 1
#define CAM_CMD_SET_HSYNC_POLARITY 2
#define CAM_CMD_SET_BURST 3
#if !defined(BL702)
#define CAM_CMD_SET_RGBA8888_ALPHA 4
#define CAM_CMD_GET_FRAME_ID 5
#endif
#define CAM_CMD_WRAP_MODE 6
#define CAM_CMD_COUNT_TRIGGER_NORMAL_INT 7
#if !defined(BL702)
#define CAM_CMD_FRAME_ID_RESET 8
#define CAM_CMD_INVERSE_VSYNC_POLARITY 9
#define CAM_CMD_INVERSE_HSYNC_POLARITY 10
#endif
/**
* @}
*/
/**
* @brief CAM configuration structure
*
* @param input_format CAM input format, use @ref CAM_INPUT_FORMAT
* @param resolution_x CAM resolution x
* @param resolution_y CAM resolution y
* @param h_blank CAM Hsync blank
* @param pixel_clock CAM pixel clock
* @param with_mjpeg CAM with mjpeg or not
* @param input_source CAM input source, use @ref CAM_INPUT_SOURCE
* @param output_format CAM output format, use @ref CAM_OUTPUT_FORMAT
* @param output_bufaddr CAM output buffer address , must be align 16
* @param output_bufsize CAM output buffer size, should not be less than one frame size
*/
struct bflb_cam_config_s {
uint8_t input_format;
uint16_t resolution_x;
uint16_t resolution_y;
uint16_t h_blank;
uint32_t pixel_clock;
bool with_mjpeg;
uint8_t input_source;
uint8_t output_format;
uint32_t output_bufaddr;
uint32_t output_bufsize;
};
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief
*
* @param [in] dev
* @param [in] config
*/
void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config);
/**
* @brief
*
* @param [in] dev
*/
void bflb_cam_start(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_cam_stop(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] int_type
* @param [in] mask
*/
void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
/**
* @brief
*
* @param [in] dev
* @param [in] int_type
*/
void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type);
/**
* @brief
*
* @param [in] dev
* @param [in] start_line
* @param [in] end_line
*/
void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line);
/**
* @brief
*
* @param [in] dev
* @param [in] start_pixel
* @param [in] end_pixel
*/
void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel);
/**
* @brief
*
* @param [in] dev
*/
void bflb_cam_pop_one_frame(struct bflb_device_s *dev);
#if !defined(BL702)
/**
* @brief
*
* @param [in] dev
* @param [in] enable
*/
void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable);
/**
* @brief
*
* @param [in] dev
* @param [in] frame_count
* @param [in] frame_valid
*/
void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid);
#endif
/**
* @brief
*
* @param [in] dev
* @return uint8_t
*/
uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] pic
* @return uint32_t
*/
uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
/**
* @brief
*
* @param [in] dev
* @return uint32_t
*/
uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] cmd
* @param [in] arg
* @return int
*/
int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

37
drivers/lhal/include/bflb_cks.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup CKS
* @{
*/
/** @defgroup CKS_ENDIAN cks endian definition
* @{
*/
@ -16,12 +24,41 @@
extern "C" {
#endif
/**
* @brief Reset checksum module.
*
* @param [in] dev device handle
*/
void bflb_cks_reset(struct bflb_device_s *dev);
/**
* @brief Set checksum bitorder.
*
* @param [in] dev device handle
* @param [in] endian cks endian, use @ref CKS_ENDIAN
*/
void bflb_cks_set_endian(struct bflb_device_s *dev, uint8_t endian);
/**
* @brief Compute data with checksum.
*
* @param [in] dev device handle
* @param [in] data input data buffer
* @param [in] length data length
* @return checksum value
*/
uint16_t bflb_cks_compute(struct bflb_device_s *dev, uint8_t *data, uint32_t length);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

36
drivers/lhal/include/bflb_clock.h
View File

@ -3,11 +3,25 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup CLOCK
* @{
*/
/** @defgroup BFLB_SYSTEM_CLOCK system clock definition
* @{
*/
#define BFLB_SYSTEM_ROOT_CLOCK 0
#define BFLB_SYSTEM_CPU_CLK 1
#define BFLB_SYSTEM_PBCLK 2
#define BFLB_SYSTEM_XCLK 3
#define BFLB_SYSTEM_32K_CLK 4
/**
* @}
*/
#if defined(BL702) || defined(BL602) || defined(BL702L)
#define BFLB_GLB_CGEN1_BASE (0x40000000 + 0x24)
@ -176,11 +190,33 @@
extern "C" {
#endif
/**
* @brief Get system clock frequence
*
* @param [in] type system clock type
* @return frequence
*/
uint32_t bflb_clk_get_system_clock(uint8_t type);
/**
* @brief Get peripheral clock frequence
*
* @param [in] type peripheral type
* @param [in] idx peripheral index
* @return frequence
*/
uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

64
drivers/lhal/include/bflb_common.h
View File

@ -7,14 +7,78 @@
extern "C" {
#endif
/**
* @brief
*
* @param [in] dst
* @param [in] src
* @param [in] n
* @return void*
*/
void *arch_memcpy(void *dst, const void *src, uint32_t n);
/**
* @brief
*
* @param [in] s
* @param [in] c
* @param [in] n
* @return void*
*/
void *arch_memset(void *s, uint8_t c, uint32_t n);
/**
* @brief
*
* @param [in] s1
* @param [in] s2
* @param [in] n
* @return int
*/
int arch_memcmp(const void *s1, const void *s2, uint32_t n);
/**
* @brief
*
* @param [in] dst
* @param [in] src
* @param [in] n
* @return uint32_t*
*/
uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
/**
* @brief
*
* @param [in] pdst
* @param [in] psrc
* @param [in] n
* @return void*
*/
void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
/**
* @brief
*
* @param [in] dst
* @param [in] val
* @param [in] n
* @return uint32_t*
*/
uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n);
/**
* @brief
*
* @param [in] cnt
*/
void arch_delay_us(uint32_t cnt);
/**
* @brief
*
* @param [in] cnt
*/
void arch_delay_ms(uint32_t cnt);
#ifdef __cplusplus

50
drivers/lhal/include/bflb_core.h
View File

@ -16,6 +16,14 @@
#include "bflb_irq.h"
#include "bflb_common.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup CORE
* @{
*/
#if !defined(BL602) && !defined(BL702) && !defined(BL702L) && \
!defined(BL616) && !defined(BL606P) && !defined(BL808) && !defined(BL628)
#error please define a supported chip
@ -28,6 +36,16 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin
#define ASSERT_PARAM(expr) ((void)0U)
#endif
#if defined(BL702)
#define BFLB_PSRAM_BASE 0x26000000
#elif defined(BL616)
#define BFLB_PSRAM_BASE 0xA8000000
#elif defined(BL808)
#define BFLB_PSRAM_BASE 0x50000000
#elif defined(BL606P)
#define BFLB_PSRAM_BASE 0x54000000
#endif
#define BFLB_DEVICE_TYPE_ADC 0
#define BFLB_DEVICE_TYPE_DAC 1
#define BFLB_DEVICE_TYPE_AUDIOADC 2
@ -65,8 +83,11 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin
#define BFLB_DEVICE_TYPE_MJPEG 34
#define BFLB_DEVICE_TYPE_KYS 35
#define BFLB_DEVICE_TYPE_DBI 36
#define BFLB_DEVICE_TYPE_PEC 37
#define BFLB_DEVICE_TYPE_WDT 38
#define BFLB_DEVICE_TYPE_EF_CTRL 39
#define BFLB_DEVICE_TYPE_SDIO3 40
#define BFLB_DEVICE_TYPE_SDIO2 41
struct bflb_device_s {
const char *name;
@ -82,12 +103,41 @@ struct bflb_device_s {
extern "C" {
#endif
/**
* @brief Get device handle by name.
*
* @param [in] name device name
* @return device handle
*/
struct bflb_device_s *bflb_device_get_by_name(const char *name);
/**
* @brief Get device handle by type and index.
*
* @param [in] type device type
* @param [in] idx device index
* @return device handle
*/
struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx);
/**
* @brief Set user data into device handle.
*
* @param [in] device device handle
* @param [in] user_data pointer to user data
*/
void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

69
drivers/lhal/include/bflb_dac.h
View File

@ -3,13 +3,21 @@
#include "bflb_core.h"
/** @defgroup DAC_SAMPLING_FREQ dac sampling frequence definition
/** @addtogroup LHAL
* @{
*/
#define DAC_SAMPLING_FREQ_32K 0
#define DAC_SAMPLING_FREQ_16K 1
#define DAC_SAMPLING_FREQ_8K 3
#define DAC_SAMPLING_FREQ_512K 4
/** @addtogroup DAC
* @{
*/
/** @defgroup DAC_CLK_DIV dac clock div definition
* @{
*/
#define DAC_CLK_DIV_16 0
#define DAC_CLK_DIV_32 1
#define DAC_CLK_DIV_64 3
#define DAC_CLK_DIV_1 4
/**
* @}
*/
@ -27,15 +35,64 @@
extern "C" {
#endif
void bflb_dac_init(struct bflb_device_s *dev, uint8_t frequence);
/**
* @brief Initialize dac frequence.
*
* @param [in] dev device handle
* @param [in] frequence dac clock div, use @ref DAC_CLK_DIV
*/
void bflb_dac_init(struct bflb_device_s *dev, uint8_t clk_div);
/**
* @brief Deinitialize dac.
*
* @param [in] dev device handle
*/
void bflb_dac_deinit(struct bflb_device_s *dev);
/**
* @brief Enable dac tx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_dac_link_txdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Enable dac channel.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_dac_channel_enable(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Disable dac channel.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_dac_channel_disable(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Set dac output value
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] value output value
*/
void bflb_dac_set_value(struct bflb_device_s *dev, uint8_t ch, uint16_t value);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

180
drivers/lhal/include/bflb_dma.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup DMA
* @{
*/
/** @defgroup DMA_DIRECTION dma transfer direction definition
* @{
*/
@ -106,18 +114,20 @@
/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
* @{
*/
#define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C)
#define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88)
#define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C)
#define DMA_ADDR_I2C0_TDR (0x2000A300 + 0x88)
#define DMA_ADDR_I2C0_RDR (0x2000A300 + 0x8C)
#define DMA_ADDR_SPI0_TDR (0x2000A200 + 0x88)
#define DMA_ADDR_SPI0_RDR (0x2000A200 + 0x8C)
#define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88)
#define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C)
#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04)
#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48)
#define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C)
#define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88)
#define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C)
#define DMA_ADDR_I2C0_TDR (0x2000A300 + 0x88)
#define DMA_ADDR_I2C0_RDR (0x2000A300 + 0x8C)
#define DMA_ADDR_SPI0_TDR (0x2000A200 + 0x88)
#define DMA_ADDR_SPI0_RDR (0x2000A200 + 0x8C)
#define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88)
#define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C)
#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04)
#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48)
#define DMA_ADDR_AUDAC_TDR (0x20055000 + 0x94)
#define DMA_ADDR_AUADC_RDR (0x2000A000 + 0xC88)
/**
* @}
*/
@ -125,20 +135,29 @@
/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
* @{
*/
#define DMA_REQUEST_NONE 0x00000000
#define DMA_REQUEST_UART0_RX 0x00000000
#define DMA_REQUEST_UART0_TX 0x00000001
#define DMA_REQUEST_UART1_RX 0x00000002
#define DMA_REQUEST_UART1_TX 0x00000003
#define DMA_REQUEST_I2C0_RX 0x00000006
#define DMA_REQUEST_I2C0_TX 0x00000007
#define DMA_REQUEST_SPI0_RX 0x0000000A
#define DMA_REQUEST_SPI0_TX 0x0000000B
#define DMA_REQUEST_AUDIO_TX 0x0000000D
#define DMA_REQUEST_I2S_RX 0x00000010
#define DMA_REQUEST_I2S_TX 0x00000011
#define DMA_REQUEST_ADC 0x00000016
#define DMA_REQUEST_DAC 0x00000017
#define DMA_REQUEST_NONE 0x00000000
#define DMA_REQUEST_UART0_RX 0x00000000
#define DMA_REQUEST_UART0_TX 0x00000001
#define DMA_REQUEST_UART1_RX 0x00000002
#define DMA_REQUEST_UART1_TX 0x00000003
#define DMA_REQUEST_I2C0_RX 0x00000006
#define DMA_REQUEST_I2C0_TX 0x00000007
#define DMA_REQUEST_SPI0_RX 0x0000000A
#define DMA_REQUEST_SPI0_TX 0x0000000B
#define DMA_REQUEST_AUDIO_TX 0x0000000D
#define DMA_REQUEST_I2S_RX 0x00000010
#define DMA_REQUEST_I2S_TX 0x00000011
#define DMA_REQUEST_ADC 0x00000016
#define DMA_REQUEST_DAC 0x00000017
#define DMA_REQUEST_PEC0_SM0_RX 0x00000018
#define DMA_REQUEST_PEC0_SM1_RX 0x00000019
#define DMA_REQUEST_PEC0_SM2_RX 0x0000001A
#define DMA_REQUEST_PEC0_SM3_RX 0x0000001B
#define DMA_REQUEST_PEC0_SM0_TX 0x0000001C
#define DMA_REQUEST_PEC0_SM1_TX 0x0000001D
#define DMA_REQUEST_PEC0_SM2_TX 0x0000001E
#define DMA_REQUEST_PEC0_SM3_TX 0x0000001F
/**
* @}
*/
@ -268,10 +287,8 @@
*/
#define DMA_CMD_SET_SRCADDR_INCREMENT (0x01)
#define DMA_CMD_SET_DSTADDR_INCREMENT (0x02)
#if !defined(BL602)
#define DMA_CMD_SET_ADD_MODE (0x03)
#define DMA_CMD_SET_REDUCE_MODE (0x04)
#endif
#define DMA_CMD_SET_ADD_MODE (0x03)
#define DMA_CMD_SET_REDUCE_MODE (0x04)
/**
* @}
*/
@ -354,28 +371,127 @@ struct bflb_dma_channel_config_s {
extern "C" {
#endif
/**
* @brief Initialize dma channel.
*
* @param [in] dev device handle
* @param [in] config pointer to save dma channel configuration
*/
void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_channel_config_s *config);
/**
* @brief Deinitialize dma channel.
*
* @param [in] dev device handle
*/
void bflb_dma_channel_deinit(struct bflb_device_s *dev);
int bflb_dma_channel_start(struct bflb_device_s *dev);
int bflb_dma_channel_stop(struct bflb_device_s *dev);
/**
* @brief Start dma channel transfer.
*
* @param [in] dev device handle
*/
void bflb_dma_channel_start(struct bflb_device_s *dev);
/**
* @brief Stop dma channel transfer.
*
* @param [in] dev device handle
*/
void bflb_dma_channel_stop(struct bflb_device_s *dev);
/**
* @brief Check if dma channel is in busy.
*
* @param [in] dev device handle
* @return true means dma channel does not transfer completely, otherwise transfers completely.
*/
bool bflb_dma_channel_isbusy(struct bflb_device_s *dev);
/**
* @brief Register dma channel transmission completion interrupt callback.
*
* @param [in] dev device handle
* @param [in] callback interrupt callback
* @param [in] arg user data
*/
void bflb_dma_channel_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg), void *arg);
/**
* @brief Unregister dma channel transmission completion interrupt callback.
*
* @param [in] dev device handle
*/
void bflb_dma_channel_irq_detach(struct bflb_device_s *dev);
/**
* @brief Config dma channel lli.
*
* @param [in] dev device handle
* @param [in] lli_pool pointer to lli pool
* @param [in] max_lli_count lli pool size
* @param [in] transfer pointer to transfer structure
* @param [in] count transfer count.
* @return A negated errno value on failure, otherwise means number of used lli.
*/
int bflb_dma_channel_lli_reload(struct bflb_device_s *dev,
struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count,
struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count);
/**
* @brief Enable lli continueous mode.
*
* @param [in] dev device handle
* @param [in] lli_pool pointer to lli pool
* @param [in] used_lli_count number of used lli.
*/
void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
struct bflb_dma_channel_lli_pool_s *lli_pool,
uint32_t used_lli_count);
/**
* @brief Control dma feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command. use @ref DMA_CMD
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
/**
* @brief Enable or disable dma channel transmission completion interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Check if dma channel transfers completely.
*
* @param [in] dev device handle
* @return true means yes, false means no.
*/
bool bflb_dma_channel_get_tcint_status(struct bflb_device_s *dev);
/**
* @brief Clear dma channel transmission completion interrupt status.
*
* @param [in] dev device handle
*/
void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

98
drivers/lhal/include/bflb_ef_ctrl.h
View File

@ -7,6 +7,13 @@
extern "C" {
#endif
/** @addtogroup LHAL
* @{
*/
/** @addtogroup EF_CTRL
* @{
*/
/**
* @brief Efuse common trim config definition
@ -18,7 +25,7 @@ typedef struct
uint16_t parity_addr; /*!< parity address */
uint16_t value_addr; /*!< value address */
uint16_t value_len; /*!< value length */
} bflb_ef_ctrl_com_trim_cfg;
} bflb_ef_ctrl_com_trim_cfg_t;
/**
* @brief Efuse common trim type definition
@ -30,20 +37,103 @@ typedef struct
uint8_t empty; /*!< Trim empty */
uint8_t len; /*!< Trim value len in bit */
uint32_t value; /*!< Trim value */
} bflb_ef_ctrl_com_trim_type;
} bflb_ef_ctrl_com_trim_t;
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg **trim_list);
/**
* @brief Get efuse control common trim list.
*
* @param [in] trim_list pointer to save trim list
* @return trim list length
*/
uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list);
/**
* @brief
*
* @param [in] dev device handle
* @return int
*/
int bflb_ef_ctrl_autoload_done(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev device handle
* @param [in] offset
* @param [in] pword
* @param [in] count
* @param [in] program
*/
void bflb_ef_ctrl_write_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t program);
/**
* @brief
*
* @param [in] dev device handle
* @param [in] offset
* @param [in] pword
* @param [in] count
* @param [in] reload
*/
void bflb_ef_ctrl_read_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t reload);
void bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_type *trim, uint8_t reload);
/**
* @brief
*
* @param [in] dev device handle
* @param [in] name
* @param [in] trim
* @param [in] reload
*/
void bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_t *trim, uint8_t reload);
/**
* @brief
*
* @param [in] dev device handle
* @param [in] name
* @param [in] value
* @param [in] program
*/
void bflb_ef_ctrl_write_common_trim(struct bflb_device_s *dev, char *name, uint32_t value, uint8_t program);
/**
* @brief
*
* @param [in] val
* @param [in] start
* @param [in] len
* @return uint8_t
*/
uint8_t bflb_ef_ctrl_is_all_bits_zero(uint32_t val, uint8_t start, uint8_t len);
/**
* @brief
*
* @param [in] val
* @return uint32_t
*/
uint32_t bflb_ef_ctrl_get_byte_zero_cnt(uint8_t val);
/**
* @brief
*
* @param [in] val
* @param [in] len
* @return uint8_t
*/
uint8_t bflb_ef_ctrl_get_trim_parity(uint32_t val, uint8_t len);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

12
drivers/lhal/include/bflb_efuse.h
View File

@ -7,12 +7,22 @@
extern "C" {
#endif
void bflb_efuse_get_chipid(uint8_t chipid[8]);
uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload);
int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program);
int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
float bflb_efuse_get_adc_trim(void);
uint32_t bflb_efuse_get_adc_tsen_trim(void);
void bflb_efuse_write_secure_boot();
void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes);
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len);
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len);
void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program);
void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage);
#ifdef __cplusplus
}
#endif

284
drivers/lhal/include/bflb_emac.h
View File

@ -1,44 +1,16 @@
/**
******************************************************************************
* @file bflb_emac.h
* @version V1.0
* @date 2022-09-27
* @brief This file is the low hardware abstraction layer file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef _BFLB_EMAC_H
#define _BFLB_EMAC_H
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup EMAC
* @{
*/
#define EMAC_DO_FLUSH_DATA (1)
/* EMAC clock use external or use internal; 0: used external 1: used internal */
@ -63,8 +35,11 @@
#define EMAC_CMD_SET_MAX_FRAME (0x0D)
#define EMAC_CMD_SET_MAXRET (0x0E)
#define EMAC_CMD_SET_COLLVALID (0x0F)
/**
* @}
*/
/** @defgroup PHY state definition
/** @defgroup PHY_STATE phy state definition
* @{
*/
#define PHY_STATE_DOWN (0) /* PHY is not usable */
@ -74,6 +49,9 @@
#define PHY_STATE_NOLINK (4) /* no cable connected */
#define PHY_STATE_STOPPED (5) /* PHY has been stopped */
#define PHY_STATE_TESTING (6) /* in test mode */
/**
* @}
*/
/* EMAC PACKET */
#define EMAC_NORMAL_PACKET (uint32_t)(0)
@ -156,7 +134,7 @@ struct bflb_emac_config_s {
* @param phy_address EMAC phy address
* @param phy_id EMAC phy read phy id
*/
struct emac_phy_cfg_s {
struct bflb_emac_phy_cfg_s {
uint8_t auto_negotiation;
uint8_t full_duplex;
uint8_t phy_state;
@ -166,68 +144,200 @@ struct emac_phy_cfg_s {
uint32_t phy_id;
};
/**
* @brief Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern.
*/
struct emac_bd_desc_s {
uint32_t C_S_L; /*!< Buffer Descriptors(BD) control,status,length */
uint32_t Buffer; /*!< BD buffer address */
};
/**
* @brief emac handle type definition
* @param bd Tx descriptor header pointer
* @param tx_index_emac TX index: EMAC
* @param tx_index_cpu TX index: CPU/SW
* @param tx_buff_limit TX index max
* @param rsv0 rsv0
* @param rx_index_emac RX index: EMAC
* @param rx_index_cpu RX index: CPU/SW
* @param rx_buff_limit RX index max
* @param rsv1 rsv1
*
*/
struct emac_handle_s {
struct emac_bd_desc_s *bd;
uint8_t tx_index_emac;
uint8_t tx_index_cpu;
uint8_t tx_buff_limit;
uint8_t rsv0;
uint8_t rx_index_emac;
uint8_t rx_index_cpu;
uint8_t rx_buff_limit;
uint8_t rsv1;
};
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief
*
* @param [in] dev
* @param [in] config
*/
void bflb_emac_init(struct bflb_device_s *dev, const struct bflb_emac_config_s *config);
void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count);
int emac_bd_fragment_support(void);
int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
void bflb_emac_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable);
void bflb_emac_int_clear(struct bflb_device_s *dev, uint32_t flag);
uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev);
uint32_t bflb_emac_bd_get_cur_active(struct bflb_device_s *dev, uint8_t bdt);
void bflb_emac_bd_rx_enqueue(uint32_t index);
void bflb_emac_bd_rx_on_err(uint32_t index);
void bflb_emac_bd_tx_dequeue(uint32_t index);
void bflb_emac_bd_tx_on_err(uint32_t index);
int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in);
int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out);
int bflb_emac_phy_reg_read(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t *phy_reg_val);
int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t phy_reg_val);
/**
* @brief
*
* @param [in] dev
*/
void bflb_emac_stop(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_emac_start(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_emac_start_tx(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_emac_stop_tx(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_emac_start_rx(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_emac_stop_rx(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] eth_tx_buff
* @param [in] tx_buf_count
* @param [in] eth_rx_buff
* @param [in] rx_buf_count
*/
void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count);
/**
* @brief
*
* @param [in] dev
* @param [in] bdt
* @return uint32_t
*/
uint32_t bflb_emac_bd_get_cur_active(struct bflb_device_s *dev, uint8_t bdt);
/**
* @brief
*
* @param [in] index
*/
void bflb_emac_bd_rx_enqueue(uint32_t index);
/**
* @brief
*
* @param [in] index
*/
void bflb_emac_bd_rx_on_err(uint32_t index);
/**
* @brief
*
* @param [in] index
*/
void bflb_emac_bd_tx_dequeue(uint32_t index);
/**
* @brief
*
* @param [in] index
*/
void bflb_emac_bd_tx_on_err(uint32_t index);
/**
* @brief
*
* @param [in] flags
* @param [in] len
* @param [in] data_in
* @return int
*/
int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in);
/**
* @brief
*
* @param [in] flags
* @param [in] len
* @param [in] data_out
* @return int
*/
int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out);
/**
* @brief
*
* @return int
*/
int emac_bd_fragment_support(void);
/**
* @brief
*
* @param [in] dev
* @param [in] flag
* @param [in] enable
*/
void bflb_emac_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable);
/**
* @brief
*
* @param [in] dev
* @param [in] flag
*/
void bflb_emac_int_clear(struct bflb_device_s *dev, uint32_t flag);
/**
* @brief
*
* @param [in] dev
* @return uint32_t
*/
uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] cmd
* @param [in] arg
* @return int
*/
int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
/**
* @brief
*
* @param [in] dev
* @param [in] phy_reg
* @param [in] phy_reg_val
* @return int
*/
int bflb_emac_phy_reg_read(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t *phy_reg_val);
/**
* @brief
*
* @param [in] dev
* @param [in] phy_reg
* @param [in] phy_reg_val
* @return int
*/
int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t phy_reg_val);
#ifdef __cplusplus
}
#endif
#endif /* _BFLB_EMAC_H */
/**
* @}
*/
/**
* @}
*/
#endif

109
drivers/lhal/include/bflb_flash.h
View File

@ -3,16 +3,36 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup FLASH
* @{
*/
/** @defgroup FLASH_IOMODE flash iomode definition
* @{
*/
#define FLASH_IOMODE_NIO 0 /*!< Normal IO mode define */
#define FLASH_IOMODE_DO 1 /*!< Dual Output mode define */
#define FLASH_IOMODE_QO 2 /*!< Quad Output mode define */
#define FLASH_IOMODE_DIO 3 /*!< Dual IO mode define */
#define FLASH_IOMODE_QIO 4 /*!< Quad IO mode define */
/**
* @}
*/
/** @defgroup FLASH_AES_KEY_TYPE flash aes key type definition
* @{
*/
#define FLASH_AES_KEY_128BITS 0
#define FLASH_AES_KEY_192BITS 2
#define FLASH_AES_KEY_256BITS 1
#define FLASH_AES_KEY_DOUBLE_128BITS 3
/**
* @}
*/
#if defined(BL602) || defined(BL702) || defined(BL702L)
#define FLASH_XIP_BASE (0x23000000)
@ -37,22 +57,111 @@ struct bflb_flash_aes_config_s {
extern "C" {
#endif
/**
* @brief Initialize flash.
*
* @return Zero on success; a negated errno value on failure
*/
int bflb_flash_init(void);
/**
* @brief Get flash jedec id.
*
* @return uint32_t
*/
uint32_t bflb_flash_get_jedec_id(void);
/**
* @brief Get flash config.
*
* @param [out] cfg_addr pointer to save config
* @param [in] len flash config size
*/
void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
/**
* @brief Set flash iomode.
*
* @param [in] iomode flash iomode, use @ref FLASH_IOMODE
*/
void bflb_flash_set_iomode(uint8_t iomode);
/**
* @brief Get flash image offset.
*
* @return flash image offset
*/
uint32_t bflb_flash_get_image_offset(void);
/**
* @brief Erase flash with sectors.
*
* @param [in] addr
* @param [in] len
* @return Zero on success; a negated errno value on failure
*/
int bflb_flash_erase(uint32_t addr, uint32_t len);
/**
* @brief Write data into flash.
*
* @param [in] addr flash physical address
* @param [in] data pointer to data buffer
* @param [in] len length of data
* @return Zero on success; a negated errno value on failure
*/
int bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len);
/**
* @brief Read data from flash.
*
* @param [in] addr flash physical address
* @param [out] data pointer to data buffer
* @param [in] len length of data
* @return Zero on success; a negated errno value on failure
*/
int bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len);
/**
* @brief Config flash cache.
*
* @param [in] cont_read enable or not continuous read mode.
* @param [in] cache_enable enable cache or not
* @param [in] cache_way_disable ways of cache to disable
* @param [in] flash_offset flash image offset
* @return Zero on success; a negated errno value on failure
*/
int bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
/**
* @brief Initialize flash aes controller.
*
* @param [in] config pointer to flash aes config.
*/
void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config);
/**
* @brief Enable flash decrypt with aes.
*
*/
void bflb_flash_aes_enable(void);
/**
* @brief Disable flash decrypt with aes.
*
*/
void bflb_flash_aes_disable(void);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

158
drivers/lhal/include/bflb_gpio.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup GPIO
* @{
*/
/**
* @brief Gpio pin definitions
*
@ -19,6 +27,10 @@
* BL808D : GPIO0 ~ GPIO8, GPIO11 ~ GPIO41
*
*/
/** @defgroup GPIO_PIN gpio pin definition
* @{
*/
#define GPIO_PIN_0 0
#define GPIO_PIN_1 1
#define GPIO_PIN_2 2
@ -65,6 +77,9 @@
#define GPIO_PIN_43 43
#define GPIO_PIN_44 44
#define GPIO_PIN_45 45
/**
* @}
*/
/* cfgset list */
#define GPIO_FUNC_SHIFT (0) /* Bits 0-4: GPIO function */
@ -76,13 +91,15 @@
#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
#elif defined(BL702)
#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_EMAC (19 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CLK_OUT (0 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_EMAC (19 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CAM_MCLK (23 << GPIO_FUNC_SHIFT)
#elif defined(BL702L)
#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
@ -90,18 +107,19 @@
#define GPIO_FUNC_KEYSCAN (13 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
#elif defined(BL616)
#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_AUDAC_PWM (25 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
#elif defined(BL606P) || defined(BL808)
#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT)
@ -166,6 +184,9 @@
#define GPIO_DRV_2 (2 << GPIO_DRV_SHIFT)
#define GPIO_DRV_3 (3 << GPIO_DRV_SHIFT)
/** @defgroup GPIO_INT_TRIG_MODE gpio interrupt trigger mode definition
* @{
*/
#define GPIO_INT_TRIG_MODE_SYNC_FALLING_EDGE 0
#define GPIO_INT_TRIG_MODE_SYNC_RISING_EDGE 1
#define GPIO_INT_TRIG_MODE_SYNC_LOW_LEVEL 2
@ -182,7 +203,13 @@
#define GPIO_INT_TRIG_MODE_ASYNC_LOW_LEVEL 10
#define GPIO_INT_TRIG_MODE_ASYNC_HIGH_LEVEL 11
#endif
/**
* @}
*/
/** @defgroup GPIO_UART_FUNC gpio uart function definition
* @{
*/
#define GPIO_UART_FUNC_UART0_RTS 0
#define GPIO_UART_FUNC_UART0_CTS 1
#define GPIO_UART_FUNC_UART0_TX 2
@ -197,6 +224,9 @@
#define GPIO_UART_FUNC_UART2_TX 10
#define GPIO_UART_FUNC_UART2_RX 11
#endif
/**
* @}
*/
/** @defgroup GPIO_CMD gpio feature control cmd definition
* @{
@ -210,22 +240,112 @@
extern "C" {
#endif
/**
* @brief Initialize gpio pin.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
* @param [in] cfgset gpio config mask
*/
void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset);
/**
* @brief Deinitialize gpio pin with input float.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
*/
void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin);
/**
* @brief Write gpio pin with high level.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
*/
void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin);
/**
* @brief Write gpio pin with low level.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
*/
void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin);
/**
* @brief Read level from gpio pin.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
* @return true means high level, otherwise low level
*/
bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin);
/**
* @brief Config gpio pin interrupt.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
* @param [in] trig_mode mode to trigger interrupt
*/
void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode);
/**
* @brief Enable or disable gpio pin interrupt.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
* @param [in] mask true means disable, false means enable
*/
void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask);
/**
* @brief Get gpio pin interrupt status.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
* @return true means yes, false means no
*/
bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin);
/**
* @brief Clear gpio pin interrupt status.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
*/
void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin);
/**
* @brief Config gpio pin with uart function.
*
* @param [in] dev device handle
* @param [in] pin gpio pin, use @ref GPIO_PIN
* @param [in] uart_func uart function, use @ref GPIO_UART_FUNC
*/
void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func);
/**
* @brief Control gpio feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command, use @ref GPIO_CMD
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

113
drivers/lhal/include/bflb_i2c.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Bit definitions for the flags field in struct bflb_i2c_msg_s
*
* START/STOP Rules:
@ -40,13 +48,6 @@
#define I2C_M_NOSTOP 0x0040 /* Message should not end with a STOP */
#define I2C_M_NOSTART 0x0080 /* Message should not begin with a START */
/* I2C bus speed */
#define I2C_SPEED_STANDARD 100000 /* Standard speed (100Khz) */
#define I2C_SPEED_FAST 400000 /* Fast speed (400Khz) */
#define I2C_SPEED_FAST_PLUS 1000000 /* Fast+ speed ( 1Mhz) */
#define I2C_SPEED_HIGH 3400000 /* High speed (3.4Mhz) */
/** @defgroup I2C_INTSTS i2c interrupt status definition
* @{
*/
@ -63,20 +64,25 @@
/** @defgroup I2C_INTCLR i2c interrupt clear definition
* @{
*/
#define I2C_INTCLR_END (1 << 0) /* Transfer end interrupt */
#define I2C_INTCLR_NACK (1 << 3) /* NACK interrupt */
#define I2C_INTCLR_ARB (1 << 4) /* Arbitration lost interrupt */
#define I2C_INTCLR_END (1 << 0) /* Transfer end interrupt */
#define I2C_INTCLR_NACK (1 << 3) /* NACK interrupt */
#define I2C_INTCLR_ARB (1 << 4) /* Arbitration lost interrupt */
/**
* @}
*/
/* I2C interrupt type */
#define I2C_INT_END (1 << 0) /* Transfer end interrupt */
#define I2C_INT_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */
#define I2C_INT_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */
#define I2C_INT_NACK (1 << 3) /* NACK interrupt */
#define I2C_INT_ARB (1 << 4) /* Arbitration lost interrupt */
#define I2C_INT_FER (1 << 5) /* TX/RX FIFO error interrupt */
/** @defgroup I2C_INTEN i2c interrupt enable definition
* @{
*/
#define I2C_INTEN_END (1 << 0) /* Transfer end interrupt */
#define I2C_INTEN_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */
#define I2C_INTEN_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */
#define I2C_INTEN_NACK (1 << 3) /* NACK interrupt */
#define I2C_INTEN_ARB (1 << 4) /* Arbitration lost interrupt */
#define I2C_INTEN_FER (1 << 5) /* TX/RX FIFO error interrupt */
/**
* @}
*/
/**
* @brief I2C message structure
@ -97,19 +103,92 @@ struct bflb_i2c_msg_s {
extern "C" {
#endif
/**
* @brief Initialize i2c.
*
* @param [in] dev device handle
* @param [in] frequency i2c frequency, range from 305Hz to 400KHz
*/
void bflb_i2c_init(struct bflb_device_s *dev, uint32_t frequency);
/**
* @brief Deinitialize i2c.
*
* @param [in] dev device handle
*/
void bflb_i2c_deinit(struct bflb_device_s *dev);
/**
* @brief Enable i2c tx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_i2c_link_txdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Enable i2c rx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_i2c_link_rxdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Start transferring i2c message.
*
* @param [in] dev device handle
* @param [in] msgs pointer to i2c message
* @param [in] count message count
* @return A negated errno value on failure.
*/
int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, int count);
/**
* @brief Enable or disable i2c interrupt.
*
* @param [in] dev device handle
* @param [in] int_type interrupt type ,use @ref I2C_INTEN
* @param [in] mask true means disable, false means enable
*/
void bflb_i2c_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
/**
* @brief Clear i2c interrupt status.
*
* @param [in] dev device handle
* @param [in] int_clear clear value, use @ref I2C_INTCLR
*/
void bflb_i2c_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
/**
* @brief Get i2c interrupt status.
*
* @param [in] dev device handle
* @return interrupt status value, use @ref I2C_INTSTS
*/
uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Control i2c feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

220
drivers/lhal/include/bflb_ir.h
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@ -3,8 +3,16 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup IR
* @{
*/
#if !defined(BL616)
/** @defgroup IR TX mode definition
/** @defgroup IR_TX_MODE ir tx mode definition
* @{
*/
#define IR_TX_NEC 0
@ -15,7 +23,7 @@
* @}
*/
/** @defgroup IR TX FIFO valid width definition
/** @defgroup IR_TX_FIFO_WIDTH ir tx fifo width valid width definition
* @{
*/
#if !defined(BL602) && !defined(BL702)
@ -28,21 +36,34 @@
* @}
*/
/** @defgroup IR TX interrupt type definition
/** @defgroup IR_TX_INTEN ir tx interrupt enable definition
* @{
*/
#define IR_TX_INT_END (1 << 0)
#define IR_TX_INTEN_END (1 << 0)
#if !defined(BL602) && !defined(BL702)
#define IR_TX_INT_FIFO (1 << 1)
#define IR_TX_INT_FER (1 << 2)
#define IR_TX_INTEN_FIFO (1 << 1)
#define IR_TX_INTEN_FER (1 << 2)
#endif
/**
* @}
*/
/** @defgroup IR_TX_INTSTS ir tx interrupt status definition
* @{
*/
#define IR_TX_INTSTS_END (1 << 0)
#if !defined(BL602) && !defined(BL702)
#define IR_TX_INTSTS_FIFO (1 << 1)
#define IR_TX_INTSTS_FER (1 << 2)
#endif
/**
* @}
*/
#endif
#if !defined(BL702L)
/** @defgroup IR RX mode definition
/** @defgroup IR_RX_MODE ir rx mode definition
* @{
*/
#define IR_RX_NEC 0
@ -52,13 +73,25 @@
* @}
*/
/** @defgroup IR RX interrupt type definition
/** @defgroup IR_RX_INTEN ir rx interrupt enable definition
* @{
*/
#define IR_RX_INT_END (1 << 0)
#define IR_RX_INTEN_END (1 << 0)
#if !defined(BL602) && !defined(BL702)
#define IR_RX_INT_FIFO (1 << 1)
#define IR_RX_INT_FER (1 << 2)
#define IR_RX_INTEN_FIFO (1 << 1)
#define IR_RX_INTEN_FER (1 << 2)
#endif
/**
* @}
*/
/** @defgroup IR_RX_INTSTS ir rx interrupt status definition
* @{
*/
#define IR_RX_INTSTS_END (1 << 0)
#if !defined(BL602) && !defined(BL702)
#define IR_RX_INTSTS_FIFO (1 << 1)
#define IR_RX_INTSTS_FER (1 << 2)
#endif
/**
* @}
@ -156,36 +189,187 @@ extern "C" {
#endif
#if !defined(BL616)
/**
* @brief
*
* @param [in] dev
* @param [in] config
*/
void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config);
/**
* @brief
*
* @param [in] dev
* @param [in] data
* @param [in] length
*/
void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length);
/**
* @brief
*
* @param [in] dev
* @param [in] data
* @param [in] length
*/
void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
/**
* @brief
*
* @param [in] dev
* @param [in] enable
*/
void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable);
/**
* @brief
*
* @param [in] dev
* @param [in] int_type
* @param [in] mask
*/
void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
/**
* @brief
*
* @param [in] dev
* @return uint32_t
*/
uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_ir_txint_clear(struct bflb_device_s *dev);
uint32_t bflb_ir_txint_status(struct bflb_device_s *dev);
#if !defined(BL602) && !defined(BL702)
/**
* @brief
*
* @param [in] dev
* @param [in] enable
*/
void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable);
uint8_t bflb_ir_txfifo_cnt(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @return uint8_t
*/
uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
#endif
#endif
#if !defined(BL702L)
/**
* @brief
*
* @param [in] dev
* @param [in] config
*/
void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config);
/**
* @brief
*
* @param [in] dev
* @param [in] data
* @return uint8_t
*/
uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data);
/**
* @brief
*
* @param [in] dev
* @param [in] data
* @param [in] length
* @return uint8_t
*/
uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
/**
* @brief
*
* @param [in] dev
* @param [in] enable
*/
void bflb_ir_rx_enable(struct bflb_device_s *dev, bool enable);
void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
void bflb_ir_rxint_clear(struct bflb_device_s *dev);
uint32_t bflb_ir_rxint_status(struct bflb_device_s *dev);
uint8_t bflb_ir_rxfifo_cnt(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @return uint8_t
*/
uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_ir_rxfifo_clear(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] int_type
* @param [in] mask
*/
void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
/**
* @brief
*
* @param [in] dev
* @return uint32_t
*/
uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_ir_rxint_clear(struct bflb_device_s *dev);
#endif
void bflb_ir_feature_control();
/**
* @brief
*
* @param [in] dev
* @param [in] cmd
* @param [in] arg
* @return int
*/
int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

86
drivers/lhal/include/bflb_irq.h
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@ -3,6 +3,14 @@
#include "stdint.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup IRQ
* @{
*/
typedef void (*irq_callback)(int irq, void *arg);
/**
@ -20,20 +28,98 @@ struct bflb_irq_info_s {
extern "C" {
#endif
/**
* @brief Interrupt initialize.
*
*/
void bflb_irq_initialize(void);
/**
* @brief Disable global irq and save the previous status.
*
* @return last status
*/
uintptr_t bflb_irq_save(void);
/**
* @brief Enable global irq by the previous status.
*
* @param [in] flags previous status by bflb_irq_save
*/
void bflb_irq_restore(uintptr_t flags);
/**
* @brief Attach interrupt with callback.
*
* @param [in] irq irq number
* @param [in] isr interrupt callback
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_irq_attach(int irq, irq_callback isr, void *arg);
/**
* @brief Detach interrupt, reset interrupt callback.
*
* @param [in] irq irq number
* @return A negated errno value on failure.
*/
int bflb_irq_detach(int irq);
/**
* @brief Enable interrupt.
*
* @param [in] irq irq number
*/
void bflb_irq_enable(int irq);
/**
* @brief Disable interrupt.
*
* @param [in] irq irq number
*/
void bflb_irq_disable(int irq);
/**
* @brief Set interrupt with pending.
*
* @param [in] irq irq number
*/
void bflb_irq_set_pending(int irq);
/**
* @brief Clear interrupt pending status.
*
* @param [in] irq irq number
*/
void bflb_irq_clear_pending(int irq);
/**
* @brief Set interrupt group.
*
* @param [in] nlbits
*/
void bflb_irq_set_nlbits(uint8_t nlbits);
/**
* @brief Set interrupt priority.
*
* @param [in] irq irq number
* @param [in] preemptprio preempt priority
* @param [in] subprio sub priority
*/
void bflb_irq_set_priority(int irq, uint8_t preemptprio, uint8_t subprio);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

249
drivers/lhal/include/bflb_iso11898.h Normal file
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@ -0,0 +1,249 @@
#ifndef _BFLB_ISO11898_H
#define _BFLB_ISO11898_H
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup ISO11898
* @{
*/
#define ISO11898_TIMEOUT (320 * 1000 * 1000)
#define ISO11898_MODE_NORMAL 0 /*!< normal mode */
#define ISO11898_MODE_LOOPBACK 1 /*!< loopback mode */
#define ISO11898_MODE_SILENT 2 /*!< silent mode */
#define ISO11898_MODE_SILENT_LOOPBACK 3 /*!< loopback combined with silent mode */
#define ISO11898_SAMPLE_SINGLE 0 /*!< the bus is sampled three times, recommended for low/medium speed buses */
#define ISO11898_SAMPLE_TRIPLE 1 /*!< the bus is sampled once, recommended for high speed buses */
#define ISO11898_SJW_1TQ 0 /*!< 1 time quantum */
#define ISO11898_SJW_2TQ 1 /*!< 2 time quantum */
#define ISO11898_SJW_3TQ 2 /*!< 3 time quantum */
#define ISO11898_SJW_4TQ 3 /*!< 4 time quantum */
#define ISO11898_BS1_1TQ 0 /*!< 1 time quantum */
#define ISO11898_BS1_2TQ 1 /*!< 2 time quantum */
#define ISO11898_BS1_3TQ 2 /*!< 3 time quantum */
#define ISO11898_BS1_4TQ 3 /*!< 4 time quantum */
#define ISO11898_BS1_5TQ 4 /*!< 5 time quantum */
#define ISO11898_BS1_6TQ 5 /*!< 6 time quantum */
#define ISO11898_BS1_7TQ 6 /*!< 7 time quantum */
#define ISO11898_BS1_8TQ 7 /*!< 8 time quantum */
#define ISO11898_BS1_9TQ 8 /*!< 9 time quantum */
#define ISO11898_BS1_10TQ 9 /*!< 10 time quantum */
#define ISO11898_BS1_11TQ 10 /*!< 11 time quantum */
#define ISO11898_BS1_12TQ 11 /*!< 12 time quantum */
#define ISO11898_BS1_13TQ 12 /*!< 13 time quantum */
#define ISO11898_BS1_14TQ 13 /*!< 14 time quantum */
#define ISO11898_BS1_15TQ 14 /*!< 15 time quantum */
#define ISO11898_BS1_16TQ 15 /*!< 16 time quantum */
#define ISO11898_BS2_1TQ 0 /*!< 1 time quantum */
#define ISO11898_BS2_2TQ 1 /*!< 2 time quantum */
#define ISO11898_BS2_3TQ 2 /*!< 3 time quantum */
#define ISO11898_BS2_4TQ 3 /*!< 4 time quantum */
#define ISO11898_BS2_5TQ 4 /*!< 5 time quantum */
#define ISO11898_BS2_6TQ 5 /*!< 6 time quantum */
#define ISO11898_BS2_7TQ 6 /*!< 7 time quantum */
#define ISO11898_BS2_8TQ 7 /*!< 8 time quantum */
#define ISO11898_ID_STANDARD 0 /*!< standard ID */
#define ISO11898_ID_EXTENDED 1 /*!< extended ID */
#define ISO11898_RTR_DATA 0 /*!< data frame */
#define ISO11898_RTR_REMOTE 1 /*!< remote frame */
/** @defgroup ISO11898_INTSTS iso11898 interrupt status definition
* @{
*/
#define ISO11898_INTSTS_RX (1 << 0)
#define ISO11898_INTSTS_TX (1 << 1)
#define ISO11898_INTSTS_ERROR_WARNING (1 << 2)
#define ISO11898_INTSTS_DATA_OVERRUN (1 << 3)
#define ISO11898_INTSTS_ERROR_PASSIVE (1 << 5)
#define ISO11898_INTSTS_ARBITRATION_LOST (1 << 6)
#define ISO11898_INTSTS_BUS_ERROR (1 << 7)
/**
* @}
*/
#define ISO11898_STATUS_RX_NOT_EMPTY (1 << 0)
#define ISO11898_STATUS_RX_OVERRUN (1 << 1)
#define ISO11898_STATUS_TX_AVAILABLE (1 << 2)
#define ISO11898_STATUS_TX_COMPLETE (1 << 3)
#define ISO11898_STATUS_RX_RECEIVING (1 << 4)
#define ISO11898_STATUS_TX_SENDING (1 << 5)
#define ISO11898_STATUS_ERROR_COUNTER (1 << 6)
#define ISO11898_STATUS_BUS_OFF (1 << 7)
#define ISO11898_FILTER_TYPE_SINGLE 0
#define ISO11898_FILTER_TYPE_DUAL 1
struct bflb_iso11898_config_s {
uint8_t prescaler; /*!< specifies the length of a time quantum, ranges from 1 to 63, tq=tclk*2*(prescaler+1) */
uint8_t mode; /*!< specifies the CAN operating mode. @ref ISO11898_MODE_XXX */
uint8_t sample; /*!< specifies the number of sample times. @ref ISO11898_SAMPLE_XXX */
uint8_t sjw; /*!< specifies the maximum number of time quanta the ISO11898 hardware is allowed to lengthen or shorten a bit to perform resynchronization. @ref ISO11898_SJW_XXX */
uint8_t bs1; /*!< specifies the number of time quanta in Bit Segment 1. @ref ISO11898_BS1_XXX */
uint8_t bs2; /*!< specifies the number of time quanta in Bit Segment 2. @ref ISO11898_BS2_XXX */
};
struct bflb_iso11898_msg_s {
uint32_t std_id; /*!< specifies the standard identifier, this parameter can be a value between 0 to 0x7FF */
uint32_t ext_id; /*!< specifies the extended identifier, this parameter can be a value between 0 to 0x1FFFFFFF */
uint8_t id_type; /*!< specifies the type of identifier for the message that will be send or received. @ref ISO11898_ID_XXX */
uint8_t rtr; /*!< specifies the type of frame for the message that will be send or received, @ref ISO11898_RTR_XXX */
uint8_t dlc; /*!< specifies the length of the frame that will be send or received, this parameter can be a value between 0 to 8 */
uint8_t data[8]; /*!< contains the data to be send or received, it ranges from 0 to 0xFF */
};
struct bflb_iso11898_filter_s {
uint8_t filter_type;
uint8_t code0;
uint8_t code1;
uint8_t code2;
uint8_t code3;
uint8_t mask0;
uint8_t mask1;
uint8_t mask2;
uint8_t mask3;
};
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief
*
* @param [in] dev
* @param [in] config
*/
void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config);
/**
* @brief
*
* @param [in] dev
*/
void bflb_iso11898_deinit(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_iso11898_abort_send(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] msg
* @param [in] timeout
* @return int8_t
*/
int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout);
/**
* @brief
*
* @param [in] dev
* @param [in] msg
* @param [in] timeout
* @return int8_t
*/
int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout);
/**
* @brief
*
* @param [in] dev
* @param [in] mode
*/
void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode);
/**
* @brief
*
* @param [in] dev
* @return uint8_t
*/
uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @return uint8_t
*/
uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] filter
*/
void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter);
/**
* @brief
*
* @param [in] dev
* @param [in] mask
*/
void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief
*
* @param [in] dev
* @param [in] mask
*/
void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief
*
* @param [in] dev
* @param [in] mask
*/
void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief
*
* @param [in] dev
* @return uint32_t
*/
uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] cmd
* @param [in] arg
* @return int
*/
int bflb_iso11898_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

76
drivers/lhal/include/bflb_l1c.h
View File

@ -3,16 +3,92 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup L1C
* @{
*/
/**
* @brief
*
*/
void bflb_l1c_icache_enable(void);
/**
* @brief
*
*/
void bflb_l1c_icache_disable(void);
/**
* @brief
*
*/
void bflb_l1c_icache_invalid_all(void);
/**
* @brief
*
*/
void bflb_l1c_dcache_enable(void);
/**
* @brief
*
*/
void bflb_l1c_dcache_disable(void);
/**
* @brief
*
*/
void bflb_l1c_dcache_clean_all(void);
/**
* @brief
*
*/
void bflb_l1c_dcache_invalidate_all(void);
/**
* @brief
*
*/
void bflb_l1c_dcache_clean_invalidate_all(void);
/**
* @brief
*
* @param [in] addr
* @param [in] size
*/
void bflb_l1c_dcache_clean_range(void *addr, uint32_t size);
/**
* @brief
*
* @param [in] addr
* @param [in] size
*/
void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size);
/**
* @brief
*
* @param [in] addr
* @param [in] size
*/
void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size);
/**
* @}
*/
/**
* @}
*/
#endif

135
drivers/lhal/include/bflb_mjpeg.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup MJPEG
* @{
*/
/** @defgroup MJPEG_FORMAT mjpeg format definition
* @{
*/
@ -50,36 +58,163 @@
*/
struct bflb_mjpeg_config_s {
uint8_t format;
uint8_t quality;
uint16_t resolution_x;
uint16_t resolution_y;
uint32_t input_bufaddr0;
uint32_t input_bufaddr1;
uint32_t output_bufaddr;
uint32_t output_bufsize;
uint16_t *input_yy_table;
uint16_t *input_uv_table;
};
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize mjpeg.
*
* @param [in] dev device handle
* @param [in] config pointer to save mjpeg config
*/
void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s *config);
/**
* @brief Start mjpeg compression with camera.
*
* @param [in] dev device handle
*/
void bflb_mjpeg_start(struct bflb_device_s *dev);
/**
* @brief Stop mjpeg compression with camera.
*
* @param [in] dev device handle
*/
void bflb_mjpeg_stop(struct bflb_device_s *dev);
/**
* @brief Start mjpeg compression without camera.
*
* @param [in] dev device handle
* @param [in] frame_count frame count to compress
*/
void bflb_mjpeg_sw_run(struct bflb_device_s *dev, uint8_t frame_count);
/**
* @brief Enable or disable mjpeg one frame compression completion interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_mjpeg_tcint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable mjpeg error interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_mjpeg_errint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Get mjpeg interrupt status.
*
* @param [in] dev device handle
* @return interrupt status
*/
uint32_t bflb_mjpeg_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Clear mjpeg interrupt status.
*
* @param [in] dev device handle
* @param [in] int_clear clear value
*/
void bflb_mjpeg_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
/**
* @brief Get number of frame count that has compressed.
*
* @param [in] dev device handle
* @return compressed frame count
*/
uint8_t bflb_mjpeg_get_frame_count(struct bflb_device_s *dev);
/**
* @brief Drop one frame that has compressed.
*
* @param [in] dev device handle
*/
void bflb_mjpeg_pop_one_frame(struct bflb_device_s *dev);
/**
* @brief Get one frame information.
*
* @param [in] dev device handle
* @param [in] pic pointer to save frame address.
* @return frame length
*/
uint32_t bflb_mjpeg_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
/**
* @brief Calculate jpeg quantize table.
*
* @param [in] quality image quality
* @param [in] input_table pointer to save input table
* @param [in] output_table pointer to save output table
*/
void bflb_mjpeg_calculate_quantize_table(uint8_t quality, uint16_t *input_table, uint16_t *output_table);
/**
* @brief Fill quantize table into mjpeg register.
*
* @param [in] dev device handle
* @param [in] input_yy yy quantize table
* @param [in] input_uv uv quantize table
*/
void bflb_mjpeg_fill_quantize_table(struct bflb_device_s *dev, uint16_t *input_yy, uint16_t *input_uv);
/**
* @brief Fill jpeg header into mjpeg register and enable hardware auto adding jpeg tail.
*
* @param [in] dev device handle
* @param [in] header pointer to jpeg header
* @param [in] header_len jpeg header length
*/
void bflb_mjpeg_fill_jpeg_header_tail(struct bflb_device_s *dev, uint8_t *header, uint32_t header_len);
/**
* @brief Set mjpeg input when uses camera with yuv402sp.
*
* @param [in] dev device handle
* @param [in] yy camera id for yy
* @param [in] uv camera id for uv
*/
void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, uint8_t uv);
/**
* @brief Control mjpeg feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_mjpeg_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

52
drivers/lhal/include/bflb_mtimer.h
View File

@ -4,19 +4,71 @@
#include "stdint.h"
#include "stdio.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup MTIMER
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Config mtimer interrupt.
*
* @param [in] ticks ticks to invoke interrupt.
* @param [in] interruptfun interrupt callback
*/
void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void));
/**
* @brief Get mtimer current frequence.
*
* @return frequence
*/
uint32_t bflb_mtimer_get_freq(void);
/**
* @brief Mtimer delay with ms.
*
* @param [in] time delay time
*/
void bflb_mtimer_delay_ms(uint32_t time);
/**
* @brief Mtimer delay with us.
*
* @param [in] time delay time
*/
void bflb_mtimer_delay_us(uint32_t time);
/**
* @brief Get current mtimer time with us.
*
* @return time with us
*/
uint64_t bflb_mtimer_get_time_us();
/**
* @brief Get current mtimer time with ms.
*
* @return time with ms
*/
uint64_t bflb_mtimer_get_time_ms();
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

94
drivers/lhal/include/bflb_pwm_v1.h
View File

@ -2,7 +2,14 @@
#define _BFLB_PWM_V2_H
#include "bflb_core.h"
#include "bflb_clock.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup PWM_V1
* @{
*/
/** @defgroup PWM_CHANNEL pwm channel definition
* @{
@ -65,7 +72,7 @@
/**
* @brief PWM configuration structure
*
* @param clk_source PWM clock source, use BFLB_SYSTEM_* definition
* @param clk_source PWM clock source, use @ref BFLB_SYSTEM_CLOCK
* @param clk_div PWM clock dividor, should be in 1~65535
* @param period PWM period count, should be in 2~65535
*/
@ -79,21 +86,104 @@ struct bflb_pwm_v1_channel_config_s {
extern "C" {
#endif
/**
* @brief Initialize pwm channel.
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] config pointer to save pwm channel config
*/
void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struct bflb_pwm_v1_channel_config_s *config);
/**
* @brief Deinitialize pwm channel.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_pwm_v1_channel_deinit(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Start pwm channel output.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Stop pwm channel output.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Set pwm channel period to change pwm frequence. Frequcence(hz) = pwm source clock /div/period.
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] period pwm period
*/
void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t period);
/**
* @brief Set pwm dutycycle. Dutycycle(%) = (high_threhold - low_threhold)/period * 100%.
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] low_threhold pwm low threhold
* @param [in] high_threhold pwm high threhold
*/
void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
/**
* @brief Enable pwm interrupt.
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable);
/**
* @brief Get pwm interrupt status.
*
* @param [in] dev device handle
* @return interrupt status, use @ref PWM_INTSTS
*/
uint32_t bflb_pwm_v1_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Clear pwm interrupt status.
*
* @param [in] dev device handle
* @param [in] int_clear clear value, use @ref PWM_INTCLR
*/
void bflb_pwm_v1_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
/**
* @brief
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] cmd feature command, use @ref PWM_CMD
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

136
drivers/lhal/include/bflb_pwm_v2.h
View File

@ -2,7 +2,14 @@
#define _BFLB_PWM_V2_H
#include "bflb_core.h"
#include "bflb_clock.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup PWM_V2
* @{
*/
/** @defgroup PWM_CHANNEL pwm channel definition
* @{
@ -16,7 +23,7 @@
* @}
*/
/** @defgroup PWM_POLARITY definition
/** @defgroup PWM_POLARITY pwm polarity definition
* @{
*/
#define PWM_POLARITY_ACTIVE_LOW 0
@ -25,7 +32,7 @@
* @}
*/
/** @defgroup PWM_STATE definition
/** @defgroup PWM_STATE pwm state definition
* @{
*/
#define PWM_STATE_INACTIVE 0
@ -34,7 +41,7 @@
* @}
*/
/** @defgroup PWM_TRIG_SDC_SRC definition
/** @defgroup PWM_TRIG_SDC_SRC pwm trigger adc source definition
* @{
*/
#define PWM_TRIG_ADC_SRC_CH0_L 0
@ -142,7 +149,7 @@ struct bflb_pwm_v2_channel_config_s {
/**
* @brief PWM configuration structure
*
* @param clk_source PWM clock source, use BFLB_SYSTEM_* definition
* @param clk_source PWM clock source, use @ref BFLB_SYSTEM_CLOCK
* @param clk_div PWM clock dividor, should be in 1~65535
* @param period PWM period count, should be in 2~65535
*/
@ -156,28 +163,147 @@ struct bflb_pwm_v2_config_s {
extern "C" {
#endif
/**
* @brief Initialize pwm.
*
* @param [in] dev device handle
* @param [in] config pointer to save pwm config
*/
void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config_s *config);
/**
* @brief Deinitialize pwm.
*
* @param [in] dev device handle
*/
void bflb_pwm_v2_deinit(struct bflb_device_s *dev);
/**
* @brief Start pwm output.
*
* @param [in] dev device handle
*/
void bflb_pwm_v2_start(struct bflb_device_s *dev);
/**
* @brief Stop pwm output.
*
* @param [in] dev device handle
*/
void bflb_pwm_v2_stop(struct bflb_device_s *dev);
/**
* @brief Set pwm period to change pwm frequence. Frequcence(hz) = pwm source clock /div/period.
*
* @param [in] dev device handle
* @param [in] period pwm period
*/
void bflb_pwm_v2_set_period(struct bflb_device_s *dev, uint16_t period);
/**
* @brief Get pwm frequcency.
*
* @param [in] dev device handle
* @return frequcency
*/
float bflb_pwm_v2_get_frequency(struct bflb_device_s *dev);
/**
* @brief Config pwm channel.
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] config pointer to save pwm channel config
*/
void bflb_pwm_v2_channel_init(struct bflb_device_s *dev, uint8_t ch, struct bflb_pwm_v2_channel_config_s *config);
/**
* @brief Set pwm dutycycle. Dutycycle(%) = (high_threhold - low_threhold)/period * 100%.
*
* @param [in] dev device handle
* @param [in] ch channel number
* @param [in] low_threhold pwm low threhold
* @param [in] high_threhold pwm high threhold
*/
void bflb_pwm_v2_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
/**
* @brief Start pwm positive output.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_pwm_v2_channel_positive_start(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Start pwm negative output.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_pwm_v2_channel_negative_start(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Stop pwm positive output.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_pwm_v2_channel_positive_stop(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Stop pwm negative output.
*
* @param [in] dev device handle
* @param [in] ch channel number
*/
void bflb_pwm_v2_channel_negative_stop(struct bflb_device_s *dev, uint8_t ch);
/**
* @brief Enable pwm interrupt.
*
* @param [in] dev device handle
* @param [in] int_en interrupt type
* @param [in] enable true means enable, otherwise disable
*/
void bflb_pwm_v2_int_enable(struct bflb_device_s *dev, uint32_t int_en, bool enable);
/**
* @brief Get pwm interrupt status.
*
* @param [in] dev device handle
* @return interrupt status, use @ref PWM_INTSTS
*/
uint32_t bflb_pwm_v2_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Clear pwm interrupt status.
*
* @param [in] dev device handle
* @param [in] int_clear clear value, use @ref PWM_INTCLR
*/
void bflb_pwm_v2_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
/**
* @brief Control pwm feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command, use @ref PWM_CMD
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

29
drivers/lhal/include/bflb_rtc.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup RTC
* @{
*/
#define BFLB_RTC_SEC2TIME(s) (s * 32768)
#define BFLB_RTC_TIME2SEC(time) (time / 32768)
@ -10,11 +18,32 @@
extern "C" {
#endif
/**
* @brief Set rtc alarming time.
*
* @param [in] dev device handle
* @param [in] time alarming time, unit is (1/32768 s)
*/
void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time);
/**
* @brief Get rtc current time.
*
* @param [in] dev device handle
* @return current rtc running time
*/
uint64_t bflb_rtc_get_time(struct bflb_device_s *dev);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

124
drivers/lhal/include/bflb_sec_aes.h
View File

@ -3,15 +3,35 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup SEC_AES
* @{
*/
/** @defgroup AES_MODE aes mode definition
* @{
*/
#define AES_MODE_ECB 0
#define AES_MODE_CTR 1
#define AES_MODE_CBC 2
#define AES_MODE_XTS 3
/**
* @}
*/
/** @defgroup AES_LINK_KEYBITS aes link mode keybits definition
* @{
*/
#define AES_LINK_KEY_128BITS 0
#define AES_LINK_KEY_192BITS 2
#define AES_LINK_KEY_256BITS 1
#define AES_LINK_KEY_DOUBLE_128BITS 3
/**
* @}
*/
#define AES_LINK_XTS_MODE1 0
#define AES_LINK_XTS_MODE2 1
@ -90,36 +110,138 @@ struct bflb_aes_xts_link_s {
extern "C" {
#endif
/**
* @brief Enable aes.
*
* @param [in] dev
*/
void bflb_aes_init(struct bflb_device_s *dev);
/**
* @brief Disable aes.
*
* @param [in] dev
*/
void bflb_aes_deinit(struct bflb_device_s *dev);
/**
* @brief Set aes hardware key.
*
* @param [in] keysel hardware key mode in efuse table
*/
void bflb_aes_set_hwkey(uint8_t keysel);
/**
* @brief Set aes hardware key source.
*
* @param [in] dev device handle
* @param [in] source hardware key source
*/
void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source);
/**
* @brief Set aes mode.
*
* @param [in] dev device handle
* @param [in] mode aes mode, use @ref AES_MODE
*/
void bflb_aes_set_mode(struct bflb_device_s *dev, uint8_t mode);
/**
* @brief Set aes key.
*
* @param [in] dev device handle
* @param [in] key pointer to aes key, if NULL, means use hardware key
* @param [in] keybits aes keybits, can be 128/192/256
*/
void bflb_aes_setkey(struct bflb_device_s *dev, const uint8_t *key, uint16_t keybits);
/**
* @brief Perform aes encrypt.
*
* @param [in] dev device handle
* @param [in] input pointer to plaintext
* @param [in] iv input iv, if NULL, means use last iv.
* @param [in] output pointer to ciphertext
* @param [in] len encrypt length, muse be multiple of 16
* @return A negated errno value on failure.
*/
int bflb_aes_encrypt(struct bflb_device_s *dev,
const uint8_t *input,
const uint8_t *iv,
uint8_t *output,
uint32_t len);
/**
* @brief Perform aes decrypt.
*
* @param [in] dev device handle
* @param [in] input pointer to ciphertext
* @param [in] iv input iv, if NULL, means use last iv.
* @param [in] output pointer to plaintext
* @param [in] len decrypt length, muse be multiple of 16
* @return A negated errno value on failure.
*/
int bflb_aes_decrypt(struct bflb_device_s *dev,
const uint8_t *input,
const uint8_t *iv,
uint8_t *output,
uint32_t len);
/**
* @brief Enable aes link mode.
*
* @param [in] dev device handle
*/
void bflb_aes_link_init(struct bflb_device_s *dev);
/**
* @brief Disable aes link mode.
*
* @param [in] dev device handle
*/
void bflb_aes_link_deinit(struct bflb_device_s *dev);
/**
* @brief Perform encrypt or decrypt with link mode.
*
* @param [in] dev device handle
* @param [in] link_addr link struct pointer address, must be located in 0x2xxxxxxx
* @param [in] input pointer to plaintext or ciphertext
* @param [in] output pointer to plaintext or ciphertext
* @param [in] len update length, muse be multiple of 16
* @return A negated errno value on failure.
*/
int bflb_aes_link_update(struct bflb_device_s *dev,
uint32_t link_addr,
const uint8_t *input,
uint8_t *output,
uint32_t len);
/**
* @brief Enable aes in group0.
*
* @param [in] dev device handle
*/
void bflb_group0_request_aes_access(struct bflb_device_s *dev);
/**
* @brief Disable aes in group0.
*
* @param [in] dev device handle
*/
void bflb_group0_release_aes_access(struct bflb_device_s *dev);
void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

43
drivers/lhal/include/bflb_sec_dsa.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup SEC_DSA
* @{
*/
struct bflb_dsa_crt_s {
uint32_t *dP;
uint32_t *dQ;
@ -28,12 +36,47 @@ struct bflb_dsa_s {
extern "C" {
#endif
/**
* @brief
*
* @param [in] handle
* @param [in] size
* @return int
*/
int bflb_sec_dsa_init(struct bflb_dsa_s *handle, uint32_t size);
/**
* @brief
*
* @param [in] handle
* @param [in] hash
* @param [in] hashLenInWord
* @param [in] s
* @return int
*/
int bflb_sec_dsa_sign(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
/**
* @brief
*
* @param [in] handle
* @param [in] hash
* @param [in] hashLenInWord
* @param [in] s
* @return int
*/
int bflb_sec_dsa_verify(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

124
drivers/lhal/include/bflb_sec_ecdsa.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup SEC_ECDSA
* @{
*/
#define ECP_SECP256R1 0
#define ECP_SECP256K1 1
@ -21,23 +29,129 @@ struct bflb_ecdh_s {
extern "C" {
#endif
/**
* @brief
*
* @param [in] handle
* @param [in] id
* @return int
*/
int bflb_sec_ecdsa_init(struct bflb_ecdsa_s *handle, uint8_t id);
/**
* @brief
*
* @param [in] handle
* @return int
*/
int bflb_sec_ecdsa_deinit(struct bflb_ecdsa_s *handle);
/**
* @brief
*
* @param [in] handle
* @param [in] random_k
* @param [in] hash
* @param [in] hashLenInWord
* @param [in] r
* @param [in] s
* @return int
*/
int bflb_sec_ecdsa_sign(struct bflb_ecdsa_s *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s);
/**
* @brief
*
* @param [in] handle
* @param [in] hash
* @param [in] hashLen
* @param [in] r
* @param [in] s
* @return int
*/
int bflb_sec_ecdsa_verify(struct bflb_ecdsa_s *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s);
/**
* @brief
*
* @param [in] handle
* @param [in] private_key
* @return int
*/
int bflb_sec_ecdsa_get_private_key(struct bflb_ecdsa_s *handle, uint32_t *private_key);
/**
* @brief
*
* @param [in] handle
* @param [in] private_key
* @param [in] pRx
* @param [in] pRy
* @return int
*/
int bflb_sec_ecdsa_get_public_key(struct bflb_ecdsa_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
/**
* @brief
*
* @param [in] handle
* @param [in] id
* @return int
*/
int bflb_sec_ecdh_init(struct bflb_ecdh_s *handle, uint8_t id);
int bflb_sec_ecdh_deinit(struct bflb_ecdh_s *handle);
int bflb_sec_ecdh_get_encrypt_key(struct bflb_ecdh_s *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
int bflb_sec_ecdh_get_public_key(struct bflb_ecdh_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
int bflb_sec_ecc_get_random_value(uint32_t *data, uint32_t *max_ref, uint32_t size);
#define SEC_CODEPATH_STATE_SIGN 0x48672386
/**
* @brief
*
* @param [in] handle
* @return int
*/
int bflb_sec_ecdh_deinit(struct bflb_ecdh_s *handle);
/**
* @brief
*
* @param [in] handle
* @param [in] pkX
* @param [in] pkY
* @param [in] private_key
* @param [in] pRx
* @param [in] pRy
* @return int
*/
int bflb_sec_ecdh_get_encrypt_key(struct bflb_ecdh_s *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
/**
* @brief
*
* @param [in] handle
* @param [in] private_key
* @param [in] pRx
* @param [in] pRy
* @return int
*/
int bflb_sec_ecdh_get_public_key(struct bflb_ecdh_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
/**
* @brief
*
* @param [in] data
* @param [in] max_ref
* @param [in] size
* @return int
*/
int bflb_sec_ecc_get_random_value(uint32_t *data, uint32_t *max_ref, uint32_t size);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

29
drivers/lhal/include/bflb_sec_irq.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup SEC_IRQ
* @{
*/
#define BFLB_SEC_ENG_IRQ_TYPE_AES 0
#define BFLB_SEC_ENG_IRQ_TYPE_SHA 1
#define BFLB_SEC_ENG_IRQ_TYPE_PKA 2
@ -14,11 +22,32 @@
extern "C" {
#endif
/**
* @brief
*
* @param [in] sec_type
* @param [in] callback
* @param [in] arg
*/
void bflb_sec_irq_attach(uint8_t sec_type, void (*callback)(void *arg), void *arg);
/**
* @brief
*
* @param [in] sec_type
*/
void bflb_sec_irq_detach(uint8_t sec_type);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

16
drivers/lhal/include/bflb_sec_pka.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup SEC_PKA
* @{
*/
#define SEC_ENG_PKA_REG_SIZE_8 1
#define SEC_ENG_PKA_REG_SIZE_16 2
#define SEC_ENG_PKA_REG_SIZE_32 3
@ -266,4 +274,12 @@ void bflb_pka_mont2gf(struct bflb_device_s *dev,
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

197
drivers/lhal/include/bflb_sec_sha.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup SEC_SHA
* @{
*/
#define SHA_MODE_SHA256 0
#define SHA_MODE_SHA224 1
#define SHA_MODE_SHA1 2
@ -73,49 +81,238 @@ struct bflb_sha_link_s {
extern "C" {
#endif
/**
* @brief
*
* @param [in] dev
* @param [in] mode
*/
void bflb_sha_init(struct bflb_device_s *dev, uint8_t mode);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
*/
void bflb_sha1_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
*/
void bflb_sha256_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
*/
void bflb_sha512_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] input
* @param [in] len
* @return int
*/
int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, const uint8_t *input, uint32_t len);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] input
* @param [in] len
* @return int
*/
int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, const uint8_t *input, uint32_t len);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] input
* @param [in] len
* @return int
*/
int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint64_t len);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] output
*/
void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, uint8_t *output);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] output
*/
void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] output
*/
void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output);
/**
* @brief
*
* @param [in] dev
*/
void bflb_sha_link_init(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_sha_link_deinit(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] link
*/
void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_link_ctx_s *ctx, struct bflb_sha_link_s *link);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] link
*/
void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_link_ctx_s *ctx, struct bflb_sha_link_s *link);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] link
*/
void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_link_ctx_s *ctx, struct bflb_sha_link_s *link);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] input
* @param [in] len
* @return int
*/
int bflb_sha1_link_update(struct bflb_device_s *dev,
struct bflb_sha1_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] input
* @param [in] len
* @return int
*/
int bflb_sha256_link_update(struct bflb_device_s *dev,
struct bflb_sha256_link_ctx_s *ctx,
const uint8_t *input,
uint32_t len);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] input
* @param [in] len
* @return int
*/
int bflb_sha512_link_update(struct bflb_device_s *dev,
struct bflb_sha512_link_ctx_s *ctx,
const uint8_t *input,
uint64_t len);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] output
*/
void bflb_sha1_link_finish(struct bflb_device_s *dev,
struct bflb_sha1_link_ctx_s *ctx,
uint8_t *output);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] output
*/
void bflb_sha256_link_finish(struct bflb_device_s *dev,
struct bflb_sha256_link_ctx_s *ctx,
uint8_t *output);
/**
* @brief
*
* @param [in] dev
* @param [in] ctx
* @param [in] output
*/
void bflb_sha512_link_finish(struct bflb_device_s *dev,
struct bflb_sha512_link_ctx_s *ctx,
uint8_t *output);
/**
* @brief
*
* @param [in] dev
*/
void bflb_group0_request_sha_access(struct bflb_device_s *dev);
/**
* @brief
*
* @param [in] dev
*/
void bflb_group0_release_sha_access(struct bflb_device_s *dev);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

48
drivers/lhal/include/bflb_sec_trng.h
View File

@ -3,19 +3,67 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup TRNG
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Read trng data.
*
* @param [in] dev device handle
* @param [in] data pointer to trng data
* @return A negated errno value on failure.
*/
int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]);
/**
* @brief Read trng data with custom length.
*
* @param [in] data pointer to trng data
* @param [in] len length to read
* @return A negated errno value on failure.
*/
int bflb_trng_readlen(uint8_t *data, uint32_t len);
/**
* @brief Get trng data.
*
* @return trng data with word
*/
long random(void);
/**
* @brief Enable trng in group0.
*
* @param [in] dev device handle
*/
void bflb_group0_request_trng_access(struct bflb_device_s *dev);
/**
* @brief Disable trng in group0.
*
* @param [in] dev device handle
*/
void bflb_group0_release_trng_access(struct bflb_device_s *dev);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

118
drivers/lhal/include/bflb_spi.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup SPI
* @{
*/
#if defined(BL602) || defined(BL702)
#define SPI_FIFO_WORD_NUM_MAX 4
#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 0
@ -101,6 +109,7 @@
#define SPI_CMD_CLEAR_TX_FIFO (0x03)
#define SPI_CMD_CLEAR_RX_FIFO (0x04)
#define SPI_CMD_SET_CS_INTERVAL (0x05)
#define SPI_CMD_RX_IGNORE (0x06)
/**
* @}
*/
@ -132,24 +141,133 @@ struct bflb_spi_config_s {
extern "C" {
#endif
/**
* @brief Initialize spi.
*
* @param [in] dev device handle
* @param [in] config pointer to save spi config
*/
void bflb_spi_init(struct bflb_device_s *dev, const struct bflb_spi_config_s *config);
/**
* @brief Deinitialize spi.
*
* @param [in] dev device handle
*/
void bflb_spi_deinit(struct bflb_device_s *dev);
/**
* @brief Enable spi tx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_spi_link_txdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Enable spi rx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_spi_link_rxdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Send and receive one data on spi.
*
* @param [in] dev device handle
* @param [in] data data to send
* @return receive data
*/
uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t data);
/**
* @brief Send and receive a block of data on spi.
*
* @param [in] dev device handle
* @param [in] txbuffer pointer to send buffer
* @param [in] rxbuffer pointer to receive buffer
* @param [in] nbytes bytes to send
* @return A negated errno value on failure.
*/
int bflb_spi_poll_exchange(struct bflb_device_s *dev, const void *txbuffer, void *rxbuffer, size_t nbytes);
/**
* @brief Check if spi is busy.
*
* @param [in] dev device handle
* @return true means busy, otherwise not.
*/
bool bflb_spi_isbusy(struct bflb_device_s *dev);
/**
* @brief Enable or disable spi rx fifo threhold interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_spi_txint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable spi rx fifo threhold interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable spi transfer done interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_spi_tcint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable spi error interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Get spi interrupt status.
*
* @param [in] dev device handle
* @return interrupt status, use @ref SPI_INTSTS
*/
uint32_t bflb_spi_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Clear spi interrupt status.
*
* @param [in] dev device handle
* @param [in] int_clear clear value, use @ref SPI_INTCLR
*/
void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
/**
* @brief Control spi feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command, use @ref SPI_CMD
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

104
drivers/lhal/include/bflb_timer.h
View File

@ -2,7 +2,14 @@
#define _BFLB_TIMER_H
#include "bflb_core.h"
#include "bflb_clock.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup TIMER
* @{
*/
/** @defgroup TIMER_CLK_SOURCE timer clock source definition
* @{
@ -41,6 +48,15 @@
* @}
*/
/** @defgroup TIMER_CAPTURE_POLARITY timer capture polarity definition
* @{
*/
#define TIMER_CAPTURE_POLARITY_POSITIVE 0
#define TIMER_CAPTURE_POLARITY_NEGATIVE 1
/**
* @}
*/
/**
* @brief TIMER configuration structure
*
@ -79,19 +95,105 @@ struct bflb_timer_capture_config_s {
extern "C" {
#endif
/**
* @brief Initialize timer.
*
* @param [in] dev device handle
* @param [in] config pointer to save timer config
*/
void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s *config);
/**
* @brief Deinitialize timer.
*
* @param [in] dev device handle
*/
void bflb_timer_deinit(struct bflb_device_s *dev);
/**
* @brief Start timer.
*
* @param [in] dev device handle
*/
void bflb_timer_start(struct bflb_device_s *dev);
/**
* @brief Stop timer.
*
* @param [in] dev device handle
*/
void bflb_timer_stop(struct bflb_device_s *dev);
/**
* @brief Set timer preload value.
*
* @param [in] dev device handle
* @param [in] val preload value
*/
void bflb_timer_set_preloadvalue(struct bflb_device_s *dev, uint32_t val);
/**
* @brief Set compare value of corresponding compare id.
*
* @param [in] dev device handle
* @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
* @param [in] val compare value
*/
void bflb_timer_set_compvalue(struct bflb_device_s *dev, uint8_t cmp_no, uint32_t val);
/**
* @brief Get compare value of corresponding compare id.
*
* @param [in] dev device handle
* @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
* @return uint32_t
*/
uint32_t bflb_timer_get_compvalue(struct bflb_device_s *dev, uint8_t cmp_no);
/**
* @brief Get timer counter value.
*
* @param [in] dev device handle
* @return counter value
*/
uint32_t bflb_timer_get_countervalue(struct bflb_device_s *dev);
/**
* @brief Enable or disable timer interrupt of corresponding compare id.
*
* @param [in] dev device handle
* @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
* @param [in] mask true means disable, false means enable
*/
void bflb_timer_compint_mask(struct bflb_device_s *dev, uint8_t cmp_no, bool mask);
/**
* @brief Get timer interrupt status of corresponding compare id.
*
* @param [in] dev device handle
* @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
* @return true mean yes, otherwise no.
*/
bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no);
/**
* @brief Clear timer interrupt status of corresponding compare id.
*
* @param [in] dev device handle
* @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
*/
void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

152
drivers/lhal/include/bflb_uart.h
View File

@ -3,6 +3,14 @@
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup UART
* @{
*/
/** @defgroup UART_DIRECTION uart direction enable definition
* @{
*/
@ -188,29 +196,173 @@ struct bflb_uart_config_s {
extern "C" {
#endif
/**
* @brief Initialize uart.
*
* @param [in] dev device handle
* @param [in] config pointer to save uart config
*/
void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *config);
/**
* @brief Deinitialize uart.
*
* @param [in] dev device handle
*/
void bflb_uart_deinit(struct bflb_device_s *dev);
/**
* @brief Enable uart.
*
* @param [in] dev device handle
*/
void bflb_uart_enable(struct bflb_device_s *dev);
/**
* @brief Disable uart.
*
* @param [in] dev device handle
*/
void bflb_uart_disable(struct bflb_device_s *dev);
/**
* @brief Enable uart tx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Enable uart rx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Put one char on uart.
*
* @param [in] dev device handle
* @param [in] ch char
* @return A negated errno value on failure.
*/
int bflb_uart_putchar(struct bflb_device_s *dev, int ch);
/**
* @brief Get char from uart.
*
* @param [in] dev device handle
* @return A negated errno value on failure, otherwise received char.
*/
int bflb_uart_getchar(struct bflb_device_s *dev);
/**
* @brief Put a block of data on uart.This is a poll api.
*
* @param [in] dev device handle
* @param [in] data pointer to save send data
* @param [in] len length to send
* @return A negated errno value on failure.
*/
int bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
/**
* @brief Get a block of data from uart. This is a asynchronous api.
*
* @param [in] dev device handle
* @param [in] data pointer to save received data
* @param [in] len max length wants to receive
* @return actual received length
*/
int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
/**
* @brief Check if there is free space in tx fifo.
*
* @param [in] dev device handle
* @return Return true if the tranmsit hardware is ready to send another byte
*/
bool bflb_uart_txready(struct bflb_device_s *dev);
/**
* @brief Check if there is no data in tx fifo.
*
* @param [in] dev device handle
* @return Return true if all characters have been sent
*/
bool bflb_uart_txempty(struct bflb_device_s *dev);
/**
* @brief Check if there is data in rx fifo.
*
* @param [in] dev device handle
* @return true means yes.Otherwise there is no data in rx fifo
*/
bool bflb_uart_rxavailable(struct bflb_device_s *dev);
/**
* @brief Enable or disable uart tx fifo threhold interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable uart rx fifo threhold interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable uart error interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Get uart interrupt status.
*
* @param [in] dev device handle
* @return interrupt status, use @ref UART_INTSTS
*/
uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Clear uart interrupt status.
*
* @param [in] dev device handle
* @param [in] int_clear clear value, use @ref UART_INTCLR
*/
void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
/**
* @brief Control uart feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command, use @ref UART_CMD
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

54
drivers/lhal/include/bflb_wdg.h
View File

@ -2,7 +2,14 @@
#define _BFLB_WDG_H
#include "bflb_core.h"
#include "bflb_clock.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup WDG
* @{
*/
#if !defined(BL702L)
#define WDG_CLKSRC_BCLK 0
@ -43,15 +50,60 @@ struct bflb_wdg_config_s {
extern "C" {
#endif
/**
* @brief Initialize watchdog.
*
* @param [in] dev device handle
* @param [in] config pointer to save watchdog config
*/
void bflb_wdg_init(struct bflb_device_s *dev, const struct bflb_wdg_config_s *config);
/**
* @brief Start watchdog.
*
* @param [in] dev device handle
*/
void bflb_wdg_start(struct bflb_device_s *dev);
/**
* @brief Stop watchdog.
*
* @param [in] dev device handle
*/
void bflb_wdg_stop(struct bflb_device_s *dev);
/**
* @brief Get watchdog counter value.
*
* @param [in] dev device handle
* @return counter value
*/
uint16_t bflb_wdg_get_countervalue(struct bflb_device_s *dev);
/**
* @brief Reset watchdog counter value.
*
* @param [in] dev device handle
*/
void bflb_wdg_reset_countervalue(struct bflb_device_s *dev);
/**
* @brief Clear watchdog compare interrupt status.
*
* @param [in] dev device handle
*/
void bflb_wdg_compint_clear(struct bflb_device_s *dev);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

185
drivers/lhal/include/hardware/cam_front_reg.h Normal file
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@ -0,0 +1,185 @@
/**
******************************************************************************
* @file cam_front_reg.h
* @version V1.0
* @date 2022-12-03
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_CAM_FRONT_H__
#define __HARDWARE_CAM_FRONT_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define CAM_FRONT_CONFIG_OFFSET (0x0)/* config */
#define CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET (0x8)/* dvp2bus_src_sel_1 */
#if defined(BL616)
#define CAM_FRONT_SNSR_CTRL_OFFSET (0xC)/* snsr_ctrl */
#define CAM_FRONT_EMI_MISC_OFFSET (0x10)/* emi_misc */
#define CAM_FRONT_ISP_ID_YUV_OFFSET (0x14)/* isp_id_yuv */
#endif
#if defined(BL808)
#define CAM_FRONT_PIX_DATA_CTRL_OFFSET (0x4)/* pix_data_ctrl */
#define CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET (0x14)/* dvp2bus_src_sel_2 */
#define CAM_FRONT_ISP_ID_YUV_OFFSET (0x28)/* isp_id_yuv */
#define CAM_FRONT_ADJA_CTRL_2_OFFSET (0x108)/* adjA_ctrl_2 */
#define CAM_FRONT_Y2RA_CONFIG_0_OFFSET (0x160)/* y2rA_config_0 */
#define CAM_FRONT_Y2RA_CONFIG_1_OFFSET (0x164)/* y2rA_config_1 */
#define CAM_FRONT_Y2RA_CONFIG_2_OFFSET (0x168)/* y2rA_config_2 */
#define CAM_FRONT_Y2RA_CONFIG_3_OFFSET (0x16C)/* y2rA_config_3 */
#define CAM_FRONT_Y2RA_CONFIG_4_OFFSET (0x170)/* y2rA_config_4 */
#define CAM_FRONT_Y2RA_CONFIG_5_OFFSET (0x174)/* y2rA_config_5 */
#define CAM_FRONT_Y2RA_CONFIG_6_OFFSET (0x178)/* y2rA_config_6 */
#define CAM_FRONT_Y2RA_CONFIG_7_OFFSET (0x17C)/* y2rA_config_7 */
#endif
/* Register Bitfield definitions *****************************************************/
/* 0x0 : config */
#define CAM_FRONT_RG_DVPAS_ENABLE (1<<0U)
#define CAM_FRONT_RG_DVPAS_HS_INV (1<<1U)
#define CAM_FRONT_RG_DVPAS_VS_INV (1<<2U)
#define CAM_FRONT_RG_DVPAS_DA_ORDER (1<<3U)
#define CAM_FRONT_RG_DVPAS_FIFO_TH_SHIFT (16U)
#define CAM_FRONT_RG_DVPAS_FIFO_TH_MASK (0x7ff<<CAM_FRONT_RG_DVPAS_FIFO_TH_SHIFT)
#if defined(BL808)
/* 0x4 : pix_data_ctrl */
#define CAM_FRONT_REG_PIX_DATA_CTRL_SHIFT (0U)
#define CAM_FRONT_REG_PIX_DATA_CTRL_MASK (0xfff<<CAM_FRONT_REG_PIX_DATA_CTRL_SHIFT)
#define CAM_FRONT_REG_PIX_DATA_SHT_BIT_SHIFT (16U)
#define CAM_FRONT_REG_PIX_DATA_SHT_BIT_MASK (0xf<<CAM_FRONT_REG_PIX_DATA_SHT_BIT_SHIFT)
#define CAM_FRONT_REG_PIX_DATA_SHT_DIR (1<<20U)
#define CAM_FRONT_REG_ISP_DTSRC_SRC (1<<31U)
/* 0x8 : dvp2bus_src_sel_1 */
#define CAM_FRONT_RG_D2B_DVP_SEL_A_SHIFT (0U)
#define CAM_FRONT_RG_D2B_DVP_SEL_A_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_A_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_A (1<<7U)
#define CAM_FRONT_RG_D2B_DVP_SEL_B_SHIFT (8U)
#define CAM_FRONT_RG_D2B_DVP_SEL_B_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_B_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_B (1<<15U)
#define CAM_FRONT_RG_D2B_DVP_SEL_C_SHIFT (16U)
#define CAM_FRONT_RG_D2B_DVP_SEL_C_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_C_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_C (1<<23U)
#define CAM_FRONT_RG_D2B_DVP_SEL_D_SHIFT (24U)
#define CAM_FRONT_RG_D2B_DVP_SEL_D_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_D_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_D (1<<31U)
/* 0x14 : dvp2bus_src_sel_2 */
#define CAM_FRONT_RG_D2B_DVP_SEL_E_SHIFT (0U)
#define CAM_FRONT_RG_D2B_DVP_SEL_E_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_E_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_E (1<<7U)
#define CAM_FRONT_RG_D2B_DVP_SEL_F_SHIFT (8U)
#define CAM_FRONT_RG_D2B_DVP_SEL_F_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_F_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_F (1<<15U)
#define CAM_FRONT_RG_D2B_DVP_SEL_G_SHIFT (16U)
#define CAM_FRONT_RG_D2B_DVP_SEL_G_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_G_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_G (1<<23U)
#define CAM_FRONT_RG_D2B_DVP_SEL_H_SHIFT (24U)
#define CAM_FRONT_RG_D2B_DVP_SEL_H_MASK (0x3f<<CAM_FRONT_RG_D2B_DVP_SEL_H_SHIFT)
#define CAM_FRONT_RG_D2X_ID_SEL_H (1<<31U)
/* 0x160 : y2rA_config_0 */
#define CAM_FRONT_RG_Y2RA_PRE_0_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_PRE_0_MASK (0x1ff<<CAM_FRONT_RG_Y2RA_PRE_0_SHIFT)
#define CAM_FRONT_RG_Y2RA_POS_0_SHIFT (16U)
#define CAM_FRONT_RG_Y2RA_POS_0_MASK (0x1ff<<CAM_FRONT_RG_Y2RA_POS_0_SHIFT)
#define CAM_FRONT_RG_Y2RA_EN (1<<27U)
#define CAM_FRONT_RG_Y2RA_SEL_SHIFT (28U)
#define CAM_FRONT_RG_Y2RA_SEL_MASK (0xf<<CAM_FRONT_RG_Y2RA_SEL_SHIFT)
/* 0x164 : y2rA_config_1 */
#define CAM_FRONT_RG_Y2RA_PRE_1_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_PRE_1_MASK (0x1ff<<CAM_FRONT_RG_Y2RA_PRE_1_SHIFT)
#define CAM_FRONT_RG_Y2RA_POS_1_SHIFT (16U)
#define CAM_FRONT_RG_Y2RA_POS_1_MASK (0x1ff<<CAM_FRONT_RG_Y2RA_POS_1_SHIFT)
/* 0x168 : y2rA_config_2 */
#define CAM_FRONT_RG_Y2RA_PRE_2_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_PRE_2_MASK (0x1ff<<CAM_FRONT_RG_Y2RA_PRE_2_SHIFT)
#define CAM_FRONT_RG_Y2RA_POS_2_SHIFT (16U)
#define CAM_FRONT_RG_Y2RA_POS_2_MASK (0x1ff<<CAM_FRONT_RG_Y2RA_POS_2_SHIFT)
/* 0x16C : y2rA_config_3 */
#define CAM_FRONT_RG_Y2RA_MTX_00_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_MTX_00_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_00_SHIFT)
#define CAM_FRONT_RG_Y2RA_MTX_01_SHIFT (16U)
#define CAM_FRONT_RG_Y2RA_MTX_01_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_01_SHIFT)
/* 0x170 : y2rA_config_4 */
#define CAM_FRONT_RG_Y2RA_MTX_02_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_MTX_02_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_02_SHIFT)
#define CAM_FRONT_RG_Y2RA_MTX_10_SHIFT (16U)
#define CAM_FRONT_RG_Y2RA_MTX_10_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_10_SHIFT)
/* 0x174 : y2rA_config_5 */
#define CAM_FRONT_RG_Y2RA_MTX_11_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_MTX_11_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_11_SHIFT)
#define CAM_FRONT_RG_Y2RA_MTX_12_SHIFT (16U)
#define CAM_FRONT_RG_Y2RA_MTX_12_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_12_SHIFT)
/* 0x178 : y2rA_config_6 */
#define CAM_FRONT_RG_Y2RA_MTX_20_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_MTX_20_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_20_SHIFT)
#define CAM_FRONT_RG_Y2RA_MTX_21_SHIFT (16U)
#define CAM_FRONT_RG_Y2RA_MTX_21_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_21_SHIFT)
/* 0x17C : y2rA_config_7 */
#define CAM_FRONT_RG_Y2RA_MTX_22_SHIFT (0U)
#define CAM_FRONT_RG_Y2RA_MTX_22_MASK (0xfff<<CAM_FRONT_RG_Y2RA_MTX_22_SHIFT)
#endif
#if defined(BL616)
/* 0x8 : dvp2bus_src_sel_1 */
#define CAM_FRONT_RG_D2X_DVP_SEL (1<<0U)
/* 0xC : snsr_ctrl */
#define CAM_FRONT_RG_SNSR_RST (1<<0U)
#define CAM_FRONT_RG_SNSR_PWDN (1<<1U)
/* 0x10 : emi_misc */
#define CAM_FRONT_REG_X_WTHRE_PB_SHIFT (0U)
#define CAM_FRONT_REG_X_WTHRE_PB_MASK (0x3<<CAM_FRONT_REG_X_WTHRE_PB_SHIFT)
#define CAM_FRONT_REG_SF_HARB_MODE (1<<4U)
#endif
/* 0x14 : isp_id_yuv */
#define CAM_FRONT_REG_YUV_IDGEN_RST (1<<0U)
#define CAM_FRONT_REG_YUV_IDGEN_EDGE (1<<1U)
#define CAM_FRONT_REG_YUV_IDGEN_CNT_INCR_SHIFT (16U)
#define CAM_FRONT_REG_YUV_IDGEN_CNT_INCR_MASK (0xffff<<CAM_FRONT_REG_YUV_IDGEN_CNT_INCR_SHIFT)
#endif /* __CAM_FRONT_REG_H__ */

449
drivers/lhal/include/hardware/cam_reg.h Normal file
View File

@ -0,0 +1,449 @@
/**
******************************************************************************
* @file cam_reg.h
* @version V1.0
* @date 2022-11-30
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_CAM_H__
#define __HARDWARE_CAM_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0)/* dvp2axi_configue */
#define CAM_DVP2AXI_ADDR_START_OFFSET (0x4)/* dvp2axi_addr_start */
#define CAM_DVP2AXI_MEM_BCNT_OFFSET (0x8)/* dvp2axi_mem_bcnt */
#define CAM_DVP2AXI_HSYNC_CROP_OFFSET (0x30)/* dvp2axi_hsync_crop */
#define CAM_DVP2AXI_VSYNC_CROP_OFFSET (0x34)/* dvp2axi_vsync_crop */
#define CAM_DVP2AXI_FRAM_EXM_OFFSET (0x38)/* dvp2axi_fram_exm */
#define CAM_FRAME_START_ADDR0_OFFSET (0x40)/* frame_start_addr0 */
#define CAM_FRAME_START_ADDR1_OFFSET (0x48)/* frame_start_addr1 */
#define CAM_FRAME_START_ADDR2_OFFSET (0x50)/* frame_start_addr2 */
#define CAM_FRAME_START_ADDR3_OFFSET (0x58)/* frame_start_addr3 */
#if defined(BL702)
#define CAM_DVP2AXI_FRAME_BCNT_0_OFFSET (0xC)/* dvp2axi_frame_bcnt_0 */
#define CAM_DVP2AXI_ADDR_START_1_OFFSET (0x10)/* dvp2axi_addr_start_1 */
#define CAM_DVP2AXI_MEM_BCNT_1_OFFSET (0x14)/* dvp2axi_mem_bcnt_1 */
#define CAM_DVP2AXI_FRAME_BCNT_1_OFFSET (0x18)/* dvp2axi_frame_bcnt_1 */
#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0x1C)/* dvp_status_and_error */
#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x20)/* dvp_frame_fifo_pop */
#define CAM_SNSR_CONTROL_OFFSET (0x24)/* snsr_control */
#define CAM_INT_CONTROL_OFFSET (0x28)/* int_control */
#define CAM_FRAME_BYTE_CNT0_0_OFFSET (0x44)/* frame_byte_cnt0_0 */
#define CAM_FRAME_BYTE_CNT0_1_OFFSET (0x4C)/* frame_byte_cnt0_1 */
#define CAM_FRAME_BYTE_CNT0_2_OFFSET (0x54)/* frame_byte_cnt0_2 */
#define CAM_FRAME_BYTE_CNT0_3_OFFSET (0x5C)/* frame_byte_cnt0_3 */
#define CAM_FRAME_START_ADDR0_4_OFFSET (0x60)/* frame_start_addr0_4 */
#define CAM_FRAME_BYTE_CNT0_4_OFFSET (0x64)/* frame_byte_cnt0_4 */
#define CAM_FRAME_START_ADDR0_5_OFFSET (0x68)/* frame_start_addr0_5 */
#define CAM_FRAME_BYTE_CNT0_5_OFFSET (0x6C)/* frame_byte_cnt0_5 */
#define CAM_FRAME_START_ADDR0_6_OFFSET (0x70)/* frame_start_addr0_6 */
#define CAM_FRAME_BYTE_CNT0_6_OFFSET (0x74)/* frame_byte_cnt0_6 */
#define CAM_FRAME_START_ADDR0_7_OFFSET (0x78)/* frame_start_addr0_7 */
#define CAM_FRAME_BYTE_CNT0_7_OFFSET (0x7C)/* frame_byte_cnt0_7 */
#define CAM_FRAME_START_ADDR1_0_OFFSET (0x80)/* frame_start_addr1_0 */
#define CAM_FRAME_BYTE_CNT1_0_OFFSET (0x84)/* frame_byte_cnt1_0 */
#define CAM_FRAME_START_ADDR1_1_OFFSET (0x88)/* frame_start_addr1_1 */
#define CAM_FRAME_BYTE_CNT1_1_OFFSET (0x8C)/* frame_byte_cnt1_1 */
#define CAM_FRAME_START_ADDR1_2_OFFSET (0x90)/* frame_start_addr1_2 */
#define CAM_FRAME_BYTE_CNT1_2_OFFSET (0x94)/* frame_byte_cnt1_2 */
#define CAM_FRAME_START_ADDR1_3_OFFSET (0x98)/* frame_start_addr1_3 */
#define CAM_FRAME_BYTE_CNT1_3_OFFSET (0x9C)/* frame_byte_cnt1_3 */
#define CAM_FRAME_START_ADDR1_4_OFFSET (0xA0)/* frame_start_addr1_4 */
#define CAM_FRAME_BYTE_CNT1_4_OFFSET (0xA4)/* frame_byte_cnt1_4 */
#define CAM_FRAME_START_ADDR1_5_OFFSET (0xA8)/* frame_start_addr1_5 */
#define CAM_FRAME_BYTE_CNT1_5_OFFSET (0xAC)/* frame_byte_cnt1_5 */
#define CAM_FRAME_START_ADDR1_6_OFFSET (0xB0)/* frame_start_addr1_6 */
#define CAM_FRAME_BYTE_CNT1_6_OFFSET (0xB4)/* frame_byte_cnt1_6 */
#define CAM_FRAME_START_ADDR1_7_OFFSET (0xB8)/* frame_start_addr1_7 */
#define CAM_FRAME_BYTE_CNT1_7_OFFSET (0xBC)/* frame_byte_cnt1_7 */
#define CAM_DVP_DEBUG_OFFSET (0xFF0)/* dvp_debug */
#define CAM_DVP_DUMMY_REG_OFFSET (0xFFC)/* dvp_dummy_reg */
#else
#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0xC)/* dvp_status_and_error */
#define CAM_DVP2AXI_FRAME_BCNT_OFFSET (0x10)/* dvp2axi_frame_bcnt */
#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x14)/* dvp_frame_fifo_pop */
#define CAM_DVP2AXI_FRAME_VLD_OFFSET (0x18)/* dvp2axi_frame_vld */
#define CAM_DVP2AXI_FRAME_PERIOD_OFFSET (0x1C)/* dvp2axi_frame_period */
#define CAM_DVP2AXI_MISC_OFFSET (0x20)/* dvp2axi_misc */
#define CAM_FRAME_ID_STS01_OFFSET (0x60)/* frame_id_sts01 */
#define CAM_FRAME_ID_STS23_OFFSET (0x64)/* frame_id_sts23 */
#define CAM_DVP_DEBUG_OFFSET (0xF0)/* dvp_debug */
#define CAM_DVP_DUMMY_REG_OFFSET (0xFC)/* dvp_dummy_reg */
#endif
/* Register Bitfield definitions *****************************************************/
/* 0x0 : dvp2axi_configue */
#define CAM_REG_DVP_ENABLE (1<<0U)
#define CAM_REG_SW_MODE (1<<1U)
#define CAM_REG_FRAM_VLD_POL (1<<2U)
#define CAM_REG_LINE_VLD_POL (1<<3U)
#define CAM_REG_XLEN_SHIFT (4U)
#if defined(BL702)
#define CAM_REG_XLEN_MASK (0x3<<CAM_REG_XLEN_SHIFT)
#else
#define CAM_REG_XLEN_MASK (0x7<<CAM_REG_XLEN_SHIFT)
#endif
#define CAM_REG_DVP_MODE_SHIFT (8U)
#define CAM_REG_DVP_MODE_MASK (0x7<<CAM_REG_DVP_MODE_SHIFT)
#define CAM_REG_HW_MODE_FWRAP (1<<11U)
#define CAM_REG_DROP_EN (1<<12U)
#define CAM_REG_DROP_EVEN (1<<13U)
#if defined(BL702)
#define CAM_REG_SUBSAMPLE_EN (1<<14U)
#define CAM_REG_SUBSAMPLE_EVEN (1<<15U)
#define CAM_REG_INTERLV_MODE (1<<16U)
#else
#define CAM_REG_QOS_SW_MODE (1<<14U)
#define CAM_REG_QOS_SW (1<<15U)
#define CAM_REG_DVP_DATA_MODE_SHIFT (16U)
#define CAM_REG_DVP_DATA_MODE_MASK (0x7<<CAM_REG_DVP_DATA_MODE_SHIFT)
#define CAM_REG_DVP_DATA_BSEL (1<<19U)
#endif
#define CAM_REG_DVP_PIX_CLK_CG (1<<20U)
#if !defined(BL702)
#define CAM_REG_V_SUBSAMPLE_EN (1<<22U)
#define CAM_REG_V_SUBSAMPLE_POL (1<<23U)
#endif
#define CAM_REG_DVP_WAIT_CYCLE_SHIFT (24U)
#define CAM_REG_DVP_WAIT_CYCLE_MASK (0xff<<CAM_REG_DVP_WAIT_CYCLE_SHIFT)
/* 0x4 : dvp2axi_addr_start */
#define CAM_REG_ADDR_START_SHIFT (0U)
#define CAM_REG_ADDR_START_MASK (0xffffffff<<CAM_REG_ADDR_START_SHIFT)
/* 0x8 : dvp2axi_mem_bcnt */
#define CAM_REG_MEM_BURST_CNT_SHIFT (0U)
#define CAM_REG_MEM_BURST_CNT_MASK (0xffffffff<<CAM_REG_MEM_BURST_CNT_SHIFT)
#if defined(BL702)
/* 0xC : dvp2ahb_frame_bcnt_0 */
#define CAM_REG_FRAME_BURST_CNT_0_SHIFT (0U)
#define CAM_REG_FRAME_BURST_CNT_0_MASK (0xffffffff<<CAM_REG_FRAME_BURST_CNT_0_SHIFT)
/* 0x10 : dvp2ahb_addr_start_1 */
#define CAM_REG_ADDR_START_1_SHIFT (0U)
#define CAM_REG_ADDR_START_1_MASK (0xffffffff<<CAM_REG_ADDR_START_1_SHIFT)
/* 0x14 : dvp2ahb_mem_bcnt_1 */
#define CAM_REG_MEM_BURST_CNT_1_SHIFT (0U)
#define CAM_REG_MEM_BURST_CNT_1_MASK (0xffffffff<<CAM_REG_MEM_BURST_CNT_1_SHIFT)
/* 0x18 : dvp2ahb_frame_bcnt_1 */
#define CAM_REG_FRAME_BURST_CNT_1_SHIFT (0U)
#define CAM_REG_FRAME_BURST_CNT_1_MASK (0xffffffff<<CAM_REG_FRAME_BURST_CNT_1_SHIFT)
/* 0x1C : dvp_status_and_error */
#define CAM_STS_NORMAL_INT (1<<0U)
#define CAM_STS_NORMAL_INT_1 (1<<1U)
#define CAM_STS_MEM_INT (1<<2U)
#define CAM_STS_MEM_INT_1 (1<<3U)
#define CAM_STS_FRAME_INT (1<<4U)
#define CAM_STS_FRAME_INT_1 (1<<5U)
#define CAM_STS_FIFO_INT (1<<6U)
#define CAM_STS_FIFO_INT_1 (1<<7U)
#define CAM_STS_HCNT_INT (1<<8U)
#define CAM_STS_VCNT_INT (1<<9U)
#define CAM_AHB_IDLE_0 (1<<16U)
#define CAM_AHB_IDLE_1 (1<<17U)
#define CAM_ST_DVP_IDLE (1<<19U)
#define CAM_FRAME_VALID_CNT_SHIFT (20U)
#define CAM_FRAME_VALID_CNT_MASK (0xf<<CAM_FRAME_VALID_CNT_SHIFT)
#define CAM_FRAME_VALID_CNT_1_SHIFT (24U)
#define CAM_FRAME_VALID_CNT_1_MASK (0xf<<CAM_FRAME_VALID_CNT_1_SHIFT)
#define CAM_ST_BUS_IDLE (1<<28U)
#define CAM_ST_BUS_FUNC (1<<29U)
#define CAM_ST_BUS_WAIT (1<<30U)
#define CAM_ST_BUS_FLSH (1<<31U)
#else
/* 0xC : dvp_status_and_error */
#define CAM_REG_FRAME_CNT_TRGR_INT_SHIFT (0U)
#define CAM_REG_FRAME_CNT_TRGR_INT_MASK (0x1f<<CAM_REG_FRAME_CNT_TRGR_INT_SHIFT)
#define CAM_REG_INT_HCNT_EN (1<<6U)
#define CAM_REG_INT_VCNT_EN (1<<7U)
#define CAM_REG_INT_NORMAL_EN (1<<8U)
#define CAM_REG_INT_MEM_EN (1<<9U)
#define CAM_REG_INT_FRAME_EN (1<<10U)
#define CAM_REG_INT_FIFO_EN (1<<11U)
#define CAM_STS_NORMAL_INT (1<<12U)
#define CAM_STS_MEM_INT (1<<13U)
#define CAM_STS_FRAME_INT (1<<14U)
#define CAM_STS_FIFO_INT (1<<15U)
#define CAM_FRAME_VALID_CNT_SHIFT (16U)
#define CAM_FRAME_VALID_CNT_MASK (0x1f<<CAM_FRAME_VALID_CNT_SHIFT)
#define CAM_STS_HCNT_INT (1<<21U)
#define CAM_STS_VCNT_INT (1<<22U)
#define CAM_ST_BUS_IDLE (1<<24U)
#define CAM_ST_BUS_FUNC (1<<25U)
#define CAM_ST_BUS_WAIT (1<<26U)
#define CAM_ST_BUS_FLSH (1<<27U)
#define CAM_AXI_IDLE (1<<28U)
#define CAM_ST_DVP_IDLE (1<<29U)
/* 0x10 : dvp2axi_frame_bcnt */
#define CAM_REG_FRAME_BYTE_CNT_SHIFT (0U)
#define CAM_REG_FRAME_BYTE_CNT_MASK (0xffffffff<<CAM_REG_FRAME_BYTE_CNT_SHIFT)
#endif
/* 0x14 : dvp_frame_fifo_pop */
#define CAM_RFIFO_POP (1<<0U)
#if defined(BL702)
#define CAM_RFIFO_POP_1 (1<<1U)
#endif
#define CAM_REG_INT_NORMAL_CLR (1<<4U)
#define CAM_REG_INT_MEM_CLR (1<<5U)
#define CAM_REG_INT_FRAME_CLR (1<<6U)
#define CAM_REG_INT_FIFO_CLR (1<<7U)
#define CAM_REG_INT_HCNT_CLR (1<<8U)
#define CAM_REG_INT_VCNT_CLR (1<<9U)
#if defined(BL702)
#define CAM_REG_INT_NORMAL_CLR_1 (1<<16U)
#define CAM_REG_INT_MEM_CLR_1 (1<<17U)
#define CAM_REG_INT_FRAME_CLR_1 (1<<18U)
#define CAM_REG_INT_FIFO_CLR_1 (1<<19U)
#endif
#if defined(BL702)
/* 0x24 : snsr_control */
#define CAM_REG_CAM_RST (1<<0U)
#define CAM_REG_CAM_PWDN (1<<1U)
/* 0x28 : int_control */
#define CAM_REG_INT_NORMAL_EN (1<<0U)
#define CAM_REG_INT_NORMAL_1_EN (1<<1U)
#define CAM_REG_INT_MEM_EN (1<<2U)
#define CAM_REG_INT_FRAME_EN (1<<3U)
#define CAM_REG_INT_FIFO_EN (1<<4U)
#define CAM_REG_INT_HCNT_EN (1<<5U)
#define CAM_REG_INT_VCNT_EN (1<<6U)
#define CAM_REG_FRAME_CNT_TRGR_INT_SHIFT (28U)
#define CAM_REG_FRAME_CNT_TRGR_INT_MASK (0xf<<CAM_REG_FRAME_CNT_TRGR_INT_SHIFT)
#else
/* 0x18 : dvp2axi_frame_vld */
#define CAM_REG_FRAME_N_VLD_SHIFT (0U)
#define CAM_REG_FRAME_N_VLD_MASK (0xffffffff<<CAM_REG_FRAME_N_VLD_SHIFT)
/* 0x1C : dvp2axi_frame_period */
#define CAM_REG_FRAME_PERIOD_SHIFT (0U)
#define CAM_REG_FRAME_PERIOD_MASK (0x1f<<CAM_REG_FRAME_PERIOD_SHIFT)
/* 0x20 : dvp2axi_misc */
#define CAM_REG_ALPHA_SHIFT (0U)
#define CAM_REG_ALPHA_MASK (0xff<<CAM_REG_ALPHA_SHIFT)
#define CAM_REG_FORMAT_565_SHIFT (8U)
#define CAM_REG_FORMAT_565_MASK (0x7<<CAM_REG_FORMAT_565_SHIFT)
#endif
/* 0x30 : dvp2axi_hsync_crop */
#define CAM_REG_HSYNC_ACT_END_SHIFT (0U)
#define CAM_REG_HSYNC_ACT_END_MASK (0xffff<<CAM_REG_HSYNC_ACT_END_SHIFT)
#define CAM_REG_HSYNC_ACT_START_SHIFT (16U)
#define CAM_REG_HSYNC_ACT_START_MASK (0xffff<<CAM_REG_HSYNC_ACT_START_SHIFT)
/* 0x34 : dvp2axi_vsync_crop */
#define CAM_REG_VSYNC_ACT_END_SHIFT (0U)
#define CAM_REG_VSYNC_ACT_END_MASK (0xffff<<CAM_REG_VSYNC_ACT_END_SHIFT)
#define CAM_REG_VSYNC_ACT_START_SHIFT (16U)
#define CAM_REG_VSYNC_ACT_START_MASK (0xffff<<CAM_REG_VSYNC_ACT_START_SHIFT)
/* 0x38 : dvp2axi_fram_exm */
#define CAM_REG_TOTAL_HCNT_SHIFT (0U)
#define CAM_REG_TOTAL_HCNT_MASK (0xffff<<CAM_REG_TOTAL_HCNT_SHIFT)
#define CAM_REG_TOTAL_VCNT_SHIFT (16U)
#define CAM_REG_TOTAL_VCNT_MASK (0xffff<<CAM_REG_TOTAL_VCNT_SHIFT)
/* 0x40 : frame_start_addr0 */
#define CAM_FRAME_START_ADDR_0_SHIFT (0U)
#define CAM_FRAME_START_ADDR_0_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_SHIFT)
#if defined(BL702)
/* 0x44 : frame_byte_cnt0_0 */
#define CAM_FRAME_BYTE_CNT_0_0_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_0_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_0_SHIFT)
#endif
/* 0x48 : frame_start_addr1 */
#define CAM_FRAME_START_ADDR_1_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_SHIFT)
#if defined(BL702)
/* 0x4C : frame_byte_cnt0_1 */
#define CAM_FRAME_BYTE_CNT_0_1_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_1_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_1_SHIFT)
#endif
/* 0x50 : frame_start_addr2 */
#define CAM_FRAME_START_ADDR_2_SHIFT (0U)
#define CAM_FRAME_START_ADDR_2_MASK (0xffffffff<<CAM_FRAME_START_ADDR_2_SHIFT)
#if defined(BL702)
/* 0x54 : frame_byte_cnt0_2 */
#define CAM_FRAME_BYTE_CNT_0_2_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_2_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_2_SHIFT)
#endif
/* 0x58 : frame_start_addr3 */
#define CAM_FRAME_START_ADDR_3_SHIFT (0U)
#define CAM_FRAME_START_ADDR_3_MASK (0xffffffff<<CAM_FRAME_START_ADDR_3_SHIFT)
#if defined(BL702)
/* 0x5C : frame_byte_cnt0_3 */
#define CAM_FRAME_BYTE_CNT_0_3_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_3_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_3_SHIFT)
/* 0x60 : frame_start_addr0_4 */
#define CAM_FRAME_START_ADDR_0_4_SHIFT (0U)
#define CAM_FRAME_START_ADDR_0_4_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_4_SHIFT)
/* 0x64 : frame_byte_cnt0_4 */
#define CAM_FRAME_BYTE_CNT_0_4_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_4_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_4_SHIFT)
/* 0x68 : frame_start_addr0_5 */
#define CAM_FRAME_START_ADDR_0_5_SHIFT (0U)
#define CAM_FRAME_START_ADDR_0_5_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_5_SHIFT)
/* 0x6C : frame_byte_cnt0_5 */
#define CAM_FRAME_BYTE_CNT_0_5_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_5_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_5_SHIFT)
/* 0x70 : frame_start_addr0_6 */
#define CAM_FRAME_START_ADDR_0_6_SHIFT (0U)
#define CAM_FRAME_START_ADDR_0_6_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_6_SHIFT)
/* 0x74 : frame_byte_cnt0_6 */
#define CAM_FRAME_BYTE_CNT_0_6_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_6_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_6_SHIFT)
/* 0x78 : frame_start_addr0_7 */
#define CAM_FRAME_START_ADDR_0_7_SHIFT (0U)
#define CAM_FRAME_START_ADDR_0_7_MASK (0xffffffff<<CAM_FRAME_START_ADDR_0_7_SHIFT)
/* 0x7C : frame_byte_cnt0_7 */
#define CAM_FRAME_BYTE_CNT_0_7_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_0_7_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_0_7_SHIFT)
/* 0x80 : frame_start_addr1_0 */
#define CAM_FRAME_START_ADDR_1_0_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_0_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_0_SHIFT)
/* 0x84 : frame_byte_cnt1_0 */
#define CAM_FRAME_BYTE_CNT_1_0_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_0_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_0_SHIFT)
/* 0x88 : frame_start_addr1_1 */
#define CAM_FRAME_START_ADDR_1_1_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_1_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_1_SHIFT)
/* 0x8C : frame_byte_cnt1_1 */
#define CAM_FRAME_BYTE_CNT_1_1_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_1_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_1_SHIFT)
/* 0x90 : frame_start_addr1_2 */
#define CAM_FRAME_START_ADDR_1_2_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_2_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_2_SHIFT)
/* 0x94 : frame_byte_cnt1_2 */
#define CAM_FRAME_BYTE_CNT_1_2_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_2_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_2_SHIFT)
/* 0x98 : frame_start_addr1_3 */
#define CAM_FRAME_START_ADDR_1_3_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_3_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_3_SHIFT)
/* 0x9C : frame_byte_cnt1_3 */
#define CAM_FRAME_BYTE_CNT_1_3_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_3_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_3_SHIFT)
/* 0xA0 : frame_start_addr1_4 */
#define CAM_FRAME_START_ADDR_1_4_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_4_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_4_SHIFT)
/* 0xA4 : frame_byte_cnt1_4 */
#define CAM_FRAME_BYTE_CNT_1_4_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_4_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_4_SHIFT)
/* 0xA8 : frame_start_addr1_5 */
#define CAM_FRAME_START_ADDR_1_5_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_5_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_5_SHIFT)
/* 0xAC : frame_byte_cnt1_5 */
#define CAM_FRAME_BYTE_CNT_1_5_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_5_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_5_SHIFT)
/* 0xB0 : frame_start_addr1_6 */
#define CAM_FRAME_START_ADDR_1_6_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_6_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_6_SHIFT)
/* 0xB4 : frame_byte_cnt1_6 */
#define CAM_FRAME_BYTE_CNT_1_6_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_6_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_6_SHIFT)
/* 0xB8 : frame_start_addr1_7 */
#define CAM_FRAME_START_ADDR_1_7_SHIFT (0U)
#define CAM_FRAME_START_ADDR_1_7_MASK (0xffffffff<<CAM_FRAME_START_ADDR_1_7_SHIFT)
/* 0xBC : frame_byte_cnt1_7 */
#define CAM_FRAME_BYTE_CNT_1_7_SHIFT (0U)
#define CAM_FRAME_BYTE_CNT_1_7_MASK (0xffffffff<<CAM_FRAME_BYTE_CNT_1_7_SHIFT)
#else
/* 0x60 : frame_id_sts01 */
#define CAM_FRAME_ID_0_SHIFT (0U)
#define CAM_FRAME_ID_0_MASK (0xffff<<CAM_FRAME_ID_0_SHIFT)
#define CAM_FRAME_ID_1_SHIFT (16U)
#define CAM_FRAME_ID_1_MASK (0xffff<<CAM_FRAME_ID_1_SHIFT)
/* 0x64 : frame_id_sts23 */
#define CAM_FRAME_ID_2_SHIFT (0U)
#define CAM_FRAME_ID_2_MASK (0xffff<<CAM_FRAME_ID_2_SHIFT)
#define CAM_FRAME_ID_3_SHIFT (16U)
#define CAM_FRAME_ID_3_MASK (0xffff<<CAM_FRAME_ID_3_SHIFT)
#endif
/* 0xF0 : dvp_debug */
#define CAM_REG_DVP_DBG_EN (1<<0U)
#define CAM_REG_DVP_DBG_SEL_SHIFT (1U)
#define CAM_REG_DVP_DBG_SEL_MASK (0x7<<CAM_REG_DVP_DBG_SEL_SHIFT)
#if !defined(BL702)
#define CAM_REG_ID_LATCH_LINE_SHIFT (8U)
#define CAM_REG_ID_LATCH_LINE_MASK (0xf<<CAM_REG_ID_LATCH_LINE_SHIFT)
#endif
/* 0xFC : dvp_dummy_reg */
#endif /* __HARDWARE_CAM_H__ */

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drivers/lhal/include/hardware/iso11898_reg.h Normal file
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/**
******************************************************************************
* @file iso11898_reg.h
* @version V1.0
* @date 2022-10-31
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __ISO11898_REG_H__
#define __ISO11898_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define ISO11898_MODE_OFFSET (0x0)/* mode */
#define ISO11898_COMMAND_OFFSET (0x4)/* command */
#define ISO11898_STATUS_OFFSET (0x8)/* status */
#define ISO11898_INTERRUPT_OFFSET (0xc)/* interrupt */
#define ISO11898_INTERRUPT_ENABLE_OFFSET (0x10)/* interrupt_enable */
#define ISO11898_BUS_TIMING_0_OFFSET (0x18)/* bus_timing_0 */
#define ISO11898_BUS_TIMING_1_OFFSET (0x1c)/* bus_timing_1 */
#define ISO11898_ARB_LOST_CAPTURE_OFFSET (0x2c)/* arb_lost_capture */
#define ISO11898_ERROR_CODE_CAPTURE_OFFSET (0x30)/* error_code_capture */
#define ISO11898_ERROR_WARNING_LIMIT_OFFSET (0x34)/* error_warning_limit */
#define ISO11898_RX_ERR_COUNT_OFFSET (0x38)/* rx_err_count */
#define ISO11898_TX_ERR_COUNT_OFFSET (0x3c)/* tx_err_count */
#define ISO11898_FRAME_INFORMATION_OFFSET (0x40)/* frame_information */
#define ISO11898_ACCEPTANCE_CODE_0_OFFSET (0x40)/* acceptance_code_0 */
#define ISO11898_SFF_ID1_OFFSET (0x44)/* sff_id1 */
#define ISO11898_EFF_ID1_OFFSET (0x44)/* eff_id1 */
#define ISO11898_ACCEPTANCE_CODE_1_OFFSET (0x44)/* acceptance_code_1 */
#define ISO11898_SFF_ID2_OFFSET (0x48)/* sff_id2 */
#define ISO11898_EFF_ID2_OFFSET (0x48)/* eff_id2 */
#define ISO11898_ACCEPTANCE_CODE_2_OFFSET (0x48)/* acceptance_code_2 */
#define ISO11898_SFF_DATA1_OFFSET (0x4c)/* sff_data1 */
#define ISO11898_EFF_ID3_OFFSET (0x4c)/* eff_id3 */
#define ISO11898_ACCEPTANCE_CODE_3_OFFSET (0x4c)/* acceptance_code_3 */
#define ISO11898_SFF_DATA2_OFFSET (0x50)/* sff_data2 */
#define ISO11898_EFF_ID4_OFFSET (0x50)/* eff_id4 */
#define ISO11898_ACCEPTANCE_MASK_0_OFFSET (0x50)/* acceptance_mask_0 */
#define ISO11898_SFF_DATA3_OFFSET (0x54)/* sff_data3 */
#define ISO11898_EFF_DATA1_OFFSET (0x54)/* eff_data1 */
#define ISO11898_ACCEPTANCE_MASK_1_OFFSET (0x54)/* acceptance_mask_1 */
#define ISO11898_SFF_DATA4_OFFSET (0x58)/* sff_data4 */
#define ISO11898_EFF_DATA2_OFFSET (0x58)/* eff_data2 */
#define ISO11898_ACCEPTANCE_MASK_2_OFFSET (0x58)/* acceptance_mask_2 */
#define ISO11898_SFF_DATA5_OFFSET (0x5c)/* sff_data5 */
#define ISO11898_EFF_DATA3_OFFSET (0x5c)/* eff_data3 */
#define ISO11898_ACCEPTANCE_MASK_3_OFFSET (0x5c)/* acceptance_mask_3 */
#define ISO11898_SFF_DATA6_OFFSET (0x60)/* sff_data6 */
#define ISO11898_EFF_DATA4_OFFSET (0x60)/* eff_data4 */
#define ISO11898_SFF_DATA7_OFFSET (0x64)/* sff_data7 */
#define ISO11898_EFF_DATA5_OFFSET (0x64)/* eff_data5 */
#define ISO11898_SFF_DATA8_OFFSET (0x68)/* sff_data8 */
#define ISO11898_EFF_DATA6_OFFSET (0x68)/* eff_data6 */
#define ISO11898_EFF_DATA7_OFFSET (0x6c)/* eff_data7 */
#define ISO11898_EFF_DATA8_OFFSET (0x70)/* eff_data8 */
#define ISO11898_RX_MESSAGE_COUNT_OFFSET (0x74)/* rx_message_count */
#define ISO11898_CLOCK_DIVIDER_OFFSET (0x7c)/* clock_divider */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : mode */
#define ISO11898_RESET_REQUEST (1<<0U)
#define ISO11898_LISTEN_ONLY (1<<1U)
#define ISO11898_SELF_TEST (1<<2U)
#define ISO11898_FILTER_TYPE (1<<3U)
/* 0x4 : command */
#define ISO11898_TRANSMIT_REQUEST (1<<0U)
#define ISO11898_ABORT_TRANSMISSION (1<<1U)
#define ISO11898_RELEASE_RECEIVE_BUFFER (1<<2U)
#define ISO11898_CLEAR_DATA_OVERRUN (1<<3U)
#define ISO11898_SELF_REQUEST (1<<4U)
/* 0x8 : status */
#define ISO11898_RECEIVE_BUFFER_STS (1<<0U)
#define ISO11898_DATA_OVERRUN_STS (1<<1U)
#define ISO11898_TRANSMIT_BUFFER_STS (1<<2U)
#define ISO11898_TRANSMIT_COMPLETE_STS (1<<3U)
#define ISO11898_RECEIVE_STS (1<<4U)
#define ISO11898_TRANSMIT_STS (1<<5U)
#define ISO11898_ERROR_STS (1<<6U)
#define ISO11898_BUS_STS (1<<7U)
/* 0xc : interrupt */
#define ISO11898_RECEIVE_INT (1<<0U)
#define ISO11898_TRANSMIT_INT (1<<1U)
#define ISO11898_ERROR_INT (1<<2U)
#define ISO11898_DATA_OVERRUN_INT (1<<3U)
#define ISO11898_ERROR_PASSIVE_INT (1<<5U)
#define ISO11898_ARB_LOST_INT (1<<6U)
#define ISO11898_BUS_ERROR_INT (1<<7U)
/* 0x10 : interrupt_enable */
#define ISO11898_RECEIVE_INT_EN (1<<0U)
#define ISO11898_TRANSMIT_INT_EN (1<<1U)
#define ISO11898_ERROR_INT_EN (1<<2U)
#define ISO11898_DATA_OVERRUN_INT_EN (1<<3U)
#define ISO11898_ERROR_PASSIVE_INT_EN (1<<5U)
#define ISO11898_ARB_LOST_INT_EN (1<<6U)
#define ISO11898_BUS_ERROR_INT_EN (1<<7U)
/* 0x18 : bus_timing_0 */
#define ISO11898_BAUD_RATE_PRESCALER_SHIFT (0U)
#define ISO11898_BAUD_RATE_PRESCALER_MASK (0x3f<<ISO11898_BAUD_RATE_PRESCALER_SHIFT)
#define ISO11898_SYNC_JUMP_WIDTH_SHIFT (6U)
#define ISO11898_SYNC_JUMP_WIDTH_MASK (0x3<<ISO11898_SYNC_JUMP_WIDTH_SHIFT)
/* 0x1c : bus_timing_1 */
#define ISO11898_TIME_SEGMENT_1_SHIFT (0U)
#define ISO11898_TIME_SEGMENT_1_MASK (0xf<<ISO11898_TIME_SEGMENT_1_SHIFT)
#define ISO11898_TIME_SEGMENT_2_SHIFT (4U)
#define ISO11898_TIME_SEGMENT_2_MASK (0x7<<ISO11898_TIME_SEGMENT_2_SHIFT)
#define ISO11898_SAMPLING (1<<7U)
/* 0x2c : arb_lost_capture */
#define ISO11898_ALC4_0_SHIFT (0U)
#define ISO11898_ALC4_0_MASK (0x1f<<ISO11898_ALC4_0_SHIFT)
/* 0x30 : error_code_capture */
#define ISO11898_SEGMENT4_0_SHIFT (0U)
#define ISO11898_SEGMENT4_0_MASK (0x1f<<ISO11898_SEGMENT4_0_SHIFT)
#define ISO11898_DIR (1<<5U)
#define ISO11898_ERR_CODE_SHIFT (6U)
#define ISO11898_ERR_CODE_MASK (0x3<<ISO11898_ERR_CODE_SHIFT)
/* 0x34 : error_warning_limit */
#define ISO11898_ERR_WARNING_LIMIT_SHIFT (0U)
#define ISO11898_ERR_WARNING_LIMIT_MASK (0xff<<ISO11898_ERR_WARNING_LIMIT_SHIFT)
/* 0x38 : rx_err_count */
#define ISO11898_RX_ERR_CNT_SHIFT (0U)
#define ISO11898_RX_ERR_CNT_MASK (0xff<<ISO11898_RX_ERR_CNT_SHIFT)
/* 0x3c : tx_err_count */
#define ISO11898_TX_ERR_CNT_SHIFT (0U)
#define ISO11898_TX_ERR_CNT_MASK (0xff<<ISO11898_TX_ERR_CNT_SHIFT)
/* 0x40 : frame_information */
#define ISO11898_FRAME_INFORMATION_DLC_SHIFT (0U)
#define ISO11898_FRAME_INFORMATION_DLC_MASK (0xf<<ISO11898_FRAME_INFORMATION_DLC_SHIFT)
#define ISO11898_FRAME_INFORMATION_RTR (1<<6U)
#define ISO11898_FRAME_INFORMATION_FF (1<<7U)
/* 0x40 : acceptance_code_0 */
#define ISO11898_ACCEPTANCE_CODE_0_SHIFT (0U)
#define ISO11898_ACCEPTANCE_CODE_0_MASK (0xff<<ISO11898_ACCEPTANCE_CODE_0_SHIFT)
/* 0x44 : sff_id1 */
#define ISO11898_SFF_ID1_BIT28_21_SHIFT (0U)
#define ISO11898_SFF_ID1_BIT28_21_MASK (0xff<<ISO11898_SFF_ID1_BIT28_21_SHIFT)
/* 0x44 : eff_id1 */
#define ISO11898_EFF_ID1_BIT28_21_SHIFT (0U)
#define ISO11898_EFF_ID1_BIT28_21_MASK (0xff<<ISO11898_EFF_ID1_BIT28_21_SHIFT)
/* 0x44 : acceptance_code_1 */
#define ISO11898_ACCEPTANCE_CODE_1_SHIFT (0U)
#define ISO11898_ACCEPTANCE_CODE_1_MASK (0xff<<ISO11898_ACCEPTANCE_CODE_1_SHIFT)
/* 0x48 : sff_id2 */
#define ISO11898_SFF_ID2_BIT20_18_SHIFT (5U)
#define ISO11898_SFF_ID2_BIT20_18_MASK (0x7<<ISO11898_SFF_ID2_BIT20_18_SHIFT)
/* 0x48 : eff_id2 */
#define ISO11898_EFF_ID2_BIT20_13_SHIFT (0U)
#define ISO11898_EFF_ID2_BIT20_13_MASK (0xff<<ISO11898_EFF_ID2_BIT20_13_SHIFT)
/* 0x48 : acceptance_code_2 */
#define ISO11898_ACCEPTANCE_CODE_2_SHIFT (0U)
#define ISO11898_ACCEPTANCE_CODE_2_MASK (0xff<<ISO11898_ACCEPTANCE_CODE_2_SHIFT)
/* 0x4c : sff_data1 */
#define ISO11898_SFF_DATA1_SHIFT (0U)
#define ISO11898_SFF_DATA1_MASK (0xff<<ISO11898_SFF_DATA1_SHIFT)
/* 0x4c : eff_id3 */
#define ISO11898_EFF_ID3_BIT12_5_SHIFT (0U)
#define ISO11898_EFF_ID3_BIT12_5_MASK (0xff<<ISO11898_EFF_ID3_BIT12_5_SHIFT)
/* 0x4c : acceptance_code_3 */
#define ISO11898_ACCEPTANCE_CODE_3_SHIFT (0U)
#define ISO11898_ACCEPTANCE_CODE_3_MASK (0xff<<ISO11898_ACCEPTANCE_CODE_3_SHIFT)
/* 0x50 : sff_data2 */
#define ISO11898_SFF_DATA2_SHIFT (0U)
#define ISO11898_SFF_DATA2_MASK (0xff<<ISO11898_SFF_DATA2_SHIFT)
/* 0x50 : eff_id4 */
#define ISO11898_EFF_ID4_BIT4_0_SHIFT (3U)
#define ISO11898_EFF_ID4_BIT4_0_MASK (0x1f<<ISO11898_EFF_ID4_BIT4_0_SHIFT)
/* 0x50 : acceptance_mask_0 */
#define ISO11898_ACCEPTANCE_MASK_0_SHIFT (3U)
#define ISO11898_ACCEPTANCE_MASK_0_MASK (0x1f<<ISO11898_ACCEPTANCE_MASK_0_SHIFT)
/* 0x54 : sff_data3 */
#define ISO11898_SFF_DATA3_SHIFT (0U)
#define ISO11898_SFF_DATA3_MASK (0xff<<ISO11898_SFF_DATA3_SHIFT)
/* 0x54 : eff_data1 */
#define ISO11898_EFF_DATA1_SHIFT (0U)
#define ISO11898_EFF_DATA1_MASK (0xff<<ISO11898_EFF_DATA1_SHIFT)
/* 0x54 : acceptance_mask_1 */
#define ISO11898_ACCEPTANCE_MASK_1_SHIFT (0U)
#define ISO11898_ACCEPTANCE_MASK_1_MASK (0xff<<ISO11898_ACCEPTANCE_MASK_1_SHIFT)
/* 0x58 : sff_data4 */
#define ISO11898_SFF_DATA4_SHIFT (0U)
#define ISO11898_SFF_DATA4_MASK (0xff<<ISO11898_SFF_DATA4_SHIFT)
/* 0x58 : eff_data2 */
#define ISO11898_EFF_DATA2_SHIFT (0U)
#define ISO11898_EFF_DATA2_MASK (0xff<<ISO11898_EFF_DATA2_SHIFT)
/* 0x58 : acceptance_mask_2 */
#define ISO11898_ACCEPTANCE_MASK_2_SHIFT (0U)
#define ISO11898_ACCEPTANCE_MASK_2_MASK (0xff<<ISO11898_ACCEPTANCE_MASK_2_SHIFT)
/* 0x5c : sff_data5 */
#define ISO11898_SFF_DATA5_SHIFT (0U)
#define ISO11898_SFF_DATA5_MASK (0xff<<ISO11898_SFF_DATA5_SHIFT)
/* 0x5c : eff_data3 */
#define ISO11898_EFF_DATA3_SHIFT (0U)
#define ISO11898_EFF_DATA3_MASK (0xff<<ISO11898_EFF_DATA3_SHIFT)
/* 0x5c : acceptance_mask_3 */
#define ISO11898_ACCEPTANCE_MASK_3_SHIFT (0U)
#define ISO11898_ACCEPTANCE_MASK_3_MASK (0xff<<ISO11898_ACCEPTANCE_MASK_3_SHIFT)
/* 0x60 : sff_data6 */
#define ISO11898_SFF_DATA6_SHIFT (0U)
#define ISO11898_SFF_DATA6_MASK (0xff<<ISO11898_SFF_DATA6_SHIFT)
/* 0x60 : eff_data4 */
#define ISO11898_ESFF_DATA4_SHIFT (0U)
#define ISO11898_ESFF_DATA4_MASK (0xff<<ISO11898_ESFF_DATA4_SHIFT)
/* 0x64 : sff_data7 */
#define ISO11898_SFF_DATA7_SHIFT (0U)
#define ISO11898_SFF_DATA7_MASK (0xff<<ISO11898_SFF_DATA7_SHIFT)
/* 0x64 : eff_data5 */
#define ISO11898_EFF_DATA5_SHIFT (0U)
#define ISO11898_EFF_DATA5_MASK (0xff<<ISO11898_EFF_DATA5_SHIFT)
/* 0x68 : sff_data8 */
#define ISO11898_SFF_DATA8_SHIFT (0U)
#define ISO11898_SFF_DATA8_MASK (0xff<<ISO11898_SFF_DATA8_SHIFT)
/* 0x68 : eff_data6 */
#define ISO11898_EFF_DATA6_SHIFT (0U)
#define ISO11898_EFF_DATA6_MASK (0xff<<ISO11898_EFF_DATA6_SHIFT)
/* 0x6c : eff_data7 */
#define ISO11898_EFF_DATA7_SHIFT (0U)
#define ISO11898_EFF_DATA7_MASK (0xff<<ISO11898_EFF_DATA7_SHIFT)
/* 0x70 : eff_data8 */
#define ISO11898_EFF_DATA8_SHIFT (0U)
#define ISO11898_EFF_DATA8_MASK (0xff<<ISO11898_EFF_DATA8_SHIFT)
/* 0x74 : rx_message_count */
#define ISO11898_RX_MESSAGE_CNT_SHIFT (0U)
#define ISO11898_RX_MESSAGE_CNT_MASK (0xff<<ISO11898_RX_MESSAGE_CNT_SHIFT)
/* 0x7c : clock_divider */
#define ISO11898_CD_SHIFT (0U)
#define ISO11898_CD_MASK (0x7<<ISO11898_CD_SHIFT)
#define ISO11898_CLOCKOFF (1<<3U)
#define ISO11898_READONLY (1<<4U)
#define ISO11898_RXINTEN (1<<5U)
#define ISO11898_CBP (1<<6U)
#define ISO11898_CAN_MODE (1<<7U)
#endif /* __ISO11898_REG_H__ */

4
drivers/lhal/src/bflb_adc.c
View File

@ -137,8 +137,8 @@ void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *co
regval |= AON_GPADC_POS_SATUR_MASK;
putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
//coe = bflb_efuse_get_adc_trim(); /* read from efuse */
//tsen_offset = bflb_efuse_get_adc_tsen_trim(); /* read from efuse */
coe = bflb_efuse_get_adc_trim(); /* read from efuse */
tsen_offset = bflb_efuse_get_adc_tsen_trim(); /* read from efuse */
}
void bflb_adc_deinit(struct bflb_device_s *dev)

631
drivers/lhal/src/bflb_cam.c Normal file
View File

@ -0,0 +1,631 @@
#include "bflb_cam.h"
#include "hardware/cam_reg.h"
#if !defined(BL702)
#include "hardware/cam_front_reg.h"
#include "bflb_clock.h"
#endif
#if defined(BL616)
#define CAM_FRONT_BASE 0x20050000
#endif
#if defined(BL808)
#define CAM_FRONT_BASE 0x30010000
#endif
void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config)
{
uint32_t reg_base;
uint32_t regval;
uint8_t data_mode = 0;
uint16_t resolution_x, resolution_y;
uint32_t frame_size;
#if !defined(BL702)
uint32_t threshold;
#endif
#if defined(BL808)
uint32_t tmpval;
if (config->input_source) {
tmpval = 0x15;
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
regval |= CAM_FRONT_REG_ISP_DTSRC_SRC;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_ADJA_CTRL_2_OFFSET);
regval |= 1;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_ADJA_CTRL_2_OFFSET);
} else {
tmpval = 0x24;
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
regval &= ~CAM_FRONT_REG_ISP_DTSRC_SRC;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
}
#endif
reg_base = dev->reg_base;
putreg32(config->output_bufaddr, reg_base + CAM_DVP2AXI_ADDR_START_OFFSET);
putreg32(config->resolution_y << 16 | config->resolution_x, reg_base + CAM_DVP2AXI_FRAM_EXM_OFFSET);
putreg32(data_mode, reg_base + CAM_DVP_DEBUG_OFFSET);
regval = getreg32(reg_base + CAM_DVP2AXI_HSYNC_CROP_OFFSET);
#if defined(BL702)
if ((regval & 0xffff) > 2 * config->resolution_x) {
resolution_x = config->resolution_x;
} else {
resolution_x = ((regval & 0xffff) - (regval >> 16 & 0xffff)) / 2;
}
#else
if ((regval & 0xffff) > config->resolution_x) {
resolution_x = config->resolution_x;
} else {
resolution_x = (regval & 0xffff) - (regval >> 16 & 0xffff);
}
#endif
regval = getreg32(reg_base + CAM_DVP2AXI_VSYNC_CROP_OFFSET);
if ((regval & 0xffff) > config->resolution_y) {
resolution_y = config->resolution_y;
} else {
resolution_y = (regval & 0xffff) - (regval >> 16 & 0xffff);
}
#if defined(BL616)
putreg32(0, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
#endif
#if !defined(BL702)
#if defined(BL808)
if (config->input_source != CAM_INPUT_SOURCE_CSI) {
#endif
regval = bflb_clk_get_system_clock(BFLB_SYSTEM_PBCLK);
if (regval == 0) {
regval = 80;
}
threshold = (config->h_blank + 4 * config->resolution_x - 2 * config->resolution_x * (config->pixel_clock / 1000000) / regval) / 4;
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval &= ~CAM_FRONT_RG_DVPAS_FIFO_TH_MASK;
regval |= threshold << CAM_FRONT_RG_DVPAS_FIFO_TH_SHIFT;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
#if defined(BL808)
}
#endif
#endif
/* Set output format */
frame_size = resolution_x * resolution_y * 2;
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
if (config->with_mjpeg) {
regval &= ~CAM_REG_SW_MODE;
} else {
regval |= CAM_REG_SW_MODE;
}
#if defined(BL702)
regval |= CAM_REG_INTERLV_MODE;
regval &= ~(CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN | CAM_REG_SUBSAMPLE_EVEN);
#else
regval &= ~(CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_DVP_DATA_MODE_MASK | CAM_REG_DVP_DATA_BSEL | CAM_REG_V_SUBSAMPLE_EN | CAM_REG_V_SUBSAMPLE_POL);
#endif
switch (config->input_format) {
case CAM_INPUT_FORMAT_YUV422_YUYV:
#if defined(BL808)
if (config->output_format >= CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 && config->output_format <= CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
tmpval = 0x23;
if (config->input_source) {
putreg32(0x18000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
} else {
putreg32(0xa8000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
}
putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_1_OFFSET);
putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_2_OFFSET);
putreg32(0x200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_3_OFFSET);
putreg32(0x20002ce, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_4_OFFSET);
putreg32(0xfe92ff50, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_5_OFFSET);
putreg32(0x38b0200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_6_OFFSET);
putreg32(0, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_7_OFFSET);
if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
data_mode = 1;
frame_size = resolution_x * resolution_y * 3;
break;
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
data_mode = 2;
frame_size = resolution_x * resolution_y * 2;
putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
break;
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
data_mode = 2;
frame_size = resolution_x * resolution_y * 2;
putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
break;
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
data_mode = 3;
frame_size = resolution_x * resolution_y * 4;
break;
}
}
#endif
case CAM_INPUT_FORMAT_YUV422_YVYU:
if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_YUV422) {
data_mode = 0;
frame_size = resolution_x * resolution_y * 2;
} else if (config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
#if defined(BL702)
regval |= CAM_REG_DROP_EN;
#endif
data_mode = 4;
frame_size = resolution_x * resolution_y;
} else if (config->output_format == CAM_OUTPUT_FORMAT_YUV422_UV) {
#if defined(BL702)
regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN;
#else
regval |= CAM_REG_DVP_DATA_BSEL;
#endif
data_mode = 4;
frame_size = resolution_x * resolution_y;
} else if (config->output_format == CAM_OUTPUT_FORMAT_YUV420_UV) {
#if defined(BL702)
regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN;
#else
regval |= CAM_REG_DVP_DATA_BSEL | CAM_REG_V_SUBSAMPLE_EN | CAM_REG_V_SUBSAMPLE_POL;
#endif
data_mode = 4;
frame_size = resolution_x * resolution_y / 2;
#if defined(BL616)
putreg32(1, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
#endif
}
break;
case CAM_INPUT_FORMAT_YUV422_UYVY:
#if defined(BL808)
if (config->output_format >= CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 && config->output_format <= CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
bflb_cam_swap_input_yu_order(dev, true);
tmpval = 0x23;
if (config->input_source) {
putreg32(0x18000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
} else {
putreg32(0xa8000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
}
putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_1_OFFSET);
putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_2_OFFSET);
putreg32(0x200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_3_OFFSET);
putreg32(0x20002ce, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_4_OFFSET);
putreg32(0xfe92ff50, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_5_OFFSET);
putreg32(0x38b0200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_6_OFFSET);
putreg32(0, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_7_OFFSET);
if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
data_mode = 1;
frame_size = resolution_x * resolution_y * 3;
break;
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
data_mode = 2;
frame_size = resolution_x * resolution_y * 2;
putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
break;
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
data_mode = 2;
frame_size = resolution_x * resolution_y * 2;
putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
break;
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
data_mode = 3;
frame_size = resolution_x * resolution_y * 4;
break;
}
}
#endif
case CAM_INPUT_FORMAT_YUV422_VYUY:
if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_YUV422) {
data_mode = 0;
frame_size = resolution_x * resolution_y * 2;
} else if (config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
#if defined(BL702)
regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN;
#else
regval |= CAM_REG_DVP_DATA_BSEL;
#endif
data_mode = 4;
frame_size = resolution_x * resolution_y;
} else if (config->output_format == CAM_OUTPUT_FORMAT_YUV422_UV) {
#if defined(BL702)
regval |= CAM_REG_DROP_EN;
#endif
data_mode = 4;
frame_size = resolution_x * resolution_y;
} else if (config->output_format == CAM_OUTPUT_FORMAT_YUV420_UV) {
#if defined(BL702)
regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN | CAM_REG_SUBSAMPLE_EVEN;
#else
regval |= CAM_REG_V_SUBSAMPLE_EN;
#endif
data_mode = 4;
frame_size = resolution_x * resolution_y / 2;
#if defined(BL616)
putreg32(1, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
#endif
}
break;
case CAM_INPUT_FORMAT_GRAY:
if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
data_mode = 0;
frame_size = resolution_x * resolution_y;
}
break;
case CAM_INPUT_FORMAT_RGB565:
/* Same as CAM_INPUT_FORMAT_BGR565 */
case CAM_INPUT_FORMAT_BGR565:
if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_RGB565_OR_BGR565) {
data_mode = 0;
frame_size = resolution_x * resolution_y * 2;
}
break;
case CAM_INPUT_FORMAT_RGB888:
/* Same as CAM_INPUT_FORMAT_BGR888 */
case CAM_INPUT_FORMAT_BGR888:
if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
data_mode = 1;
frame_size = resolution_x * resolution_y * 3;
#if !defined(BL702)
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
data_mode = 2;
frame_size = resolution_x * resolution_y * 2;
putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
data_mode = 2;
frame_size = resolution_x * resolution_y * 2;
putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
} else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
/* Default A = 0 */
data_mode = 3;
frame_size = resolution_x * resolution_y * 4;
#endif
}
break;
default:
break;
}
#if !defined(BL702)
putreg32(frame_size, reg_base + CAM_DVP2AXI_FRAME_BCNT_OFFSET);
regval |= data_mode << CAM_REG_DVP_DATA_MODE_SHIFT;
#endif
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
/* Set output buffer burst count */
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
regval = (regval & CAM_REG_XLEN_MASK) >> CAM_REG_XLEN_SHIFT;
switch (regval) {
case CAM_BURST_INCR1:
#if defined(BL702)
regval = config->output_bufsize >> 2;
frame_size = frame_size >> 2;
#else
regval = config->output_bufsize >> 3;
#endif
break;
case CAM_BURST_INCR4:
#if defined(BL702)
regval = config->output_bufsize >> 4;
frame_size = frame_size >> 4;
#else
regval = config->output_bufsize >> 5;
#endif
break;
case CAM_BURST_INCR8:
#if defined(BL702)
regval = config->output_bufsize >> 5;
frame_size = frame_size >> 5;
#else
regval = config->output_bufsize >> 6;
#endif
break;
case CAM_BURST_INCR16:
#if defined(BL702)
regval = config->output_bufsize >> 6;
frame_size = frame_size >> 6;
#else
regval = config->output_bufsize >> 7;
#endif
break;
#if !defined(BL702)
case CAM_BURST_INCR32:
regval = config->output_bufsize >> 8;
break;
case CAM_BURST_INCR64:
regval = config->output_bufsize >> 9;
break;
#endif
default:
regval = config->output_bufsize >> 7;
frame_size = frame_size >> 6;
break;
}
putreg32(regval, reg_base + CAM_DVP2AXI_MEM_BCNT_OFFSET);
#if defined(BL702)
putreg32(frame_size, reg_base + CAM_DVP2AXI_FRAME_BCNT_0_OFFSET);
#endif
#if defined(BL808)
if (dev->idx < 4) {
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
regval &= ~(0x3f << (dev->idx * 8));
regval |= tmpval << (dev->idx * 8);
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
} else {
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET);
regval &= ~(0x3f << ((dev->idx - 4) * 8));
regval |= tmpval << ((dev->idx - 4) * 8);
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET);
}
#endif
}
void bflb_cam_start(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
regval |= CAM_REG_DVP_ENABLE;
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
#if !defined(BL702)
#if defined(BL808)
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
if (regval & CAM_FRONT_REG_ISP_DTSRC_SRC) {
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval |= CAM_FRONT_RG_DVPAS_ENABLE;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
}
#else
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval |= CAM_FRONT_RG_DVPAS_ENABLE;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
#endif
#endif
}
void bflb_cam_stop(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
regval &= ~CAM_REG_DVP_ENABLE;
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
#if !defined(BL702)
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval &= ~CAM_FRONT_RG_DVPAS_ENABLE;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
#endif
}
void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
#if defined(BL702)
regval = getreg32(reg_base + CAM_INT_CONTROL_OFFSET);
#else
regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
#endif
if (mask) {
regval &= ~int_type;
} else {
regval |= int_type;
}
#if defined(BL702)
putreg32(regval, reg_base + CAM_INT_CONTROL_OFFSET);
#else
putreg32(regval, reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
#endif
}
void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type)
{
putreg32(int_type, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
}
void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line)
{
/* Get start_line ~ (end_line - 1), not include end_line */
putreg32(start_line << 16 | end_line, dev->reg_base + CAM_DVP2AXI_VSYNC_CROP_OFFSET);
}
void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel)
{
#if defined(BL702)
start_pixel = start_pixel * 2;
end_pixel = end_pixel * 2;
#endif
/* Get start_pixel ~ (end_pixel - 1), not include end_pixel */
putreg32(start_pixel << 16 | end_pixel, dev->reg_base + CAM_DVP2AXI_HSYNC_CROP_OFFSET);
}
void bflb_cam_pop_one_frame(struct bflb_device_s *dev)
{
#if defined(BL702)
putreg32(3, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
#else
putreg32(1, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
#endif
}
#if !defined(BL702)
void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable)
{
uint32_t regval;
/* If image sensor output format is YUYV, it will be changed to UYVY */
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
if (enable) {
regval |= CAM_FRONT_RG_DVPAS_DA_ORDER;
} else {
regval &= ~CAM_FRONT_RG_DVPAS_DA_ORDER;
}
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
}
void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid)
{
/* For example: frame_count is 4, frame_valid is 0x14 (10100b). Third/fifth frame will be retained,
First/second/fourth frame will be dropped in every (4 + 1) frames */
putreg32(frame_count, dev->reg_base + CAM_DVP2AXI_FRAME_PERIOD_OFFSET);
putreg32(frame_valid, dev->reg_base + CAM_DVP2AXI_FRAME_VLD_OFFSET);
}
#endif
uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
regval &= CAM_FRAME_VALID_CNT_MASK;
return (regval >> CAM_FRAME_VALID_CNT_SHIFT);
}
uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic)
{
uint32_t reg_base;
reg_base = dev->reg_base;
*pic = (uint8_t *)getreg32(reg_base + CAM_FRAME_START_ADDR0_OFFSET);
#if defined(BL702)
return (getreg32(reg_base + CAM_FRAME_BYTE_CNT0_0_OFFSET));
#else
return (getreg32(reg_base + CAM_DVP2AXI_FRAME_BCNT_OFFSET));
#endif
}
uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev)
{
return (getreg32(dev->reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET));
}
int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
{
int ret = 0;
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
switch (cmd) {
case CAM_CMD_SET_VSYNC_POLARITY:
/* Set vsync polarity, arg use @ref CAM_POLARITY */
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
if (arg) {
regval |= CAM_REG_FRAM_VLD_POL;
} else {
regval &= ~CAM_REG_FRAM_VLD_POL;
}
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
break;
case CAM_CMD_SET_HSYNC_POLARITY:
/* Set hsync polarity, arg use @ref CAM_POLARITY */
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
if (arg) {
regval |= CAM_REG_LINE_VLD_POL;
} else {
regval &= ~CAM_REG_LINE_VLD_POL;
}
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
break;
case CAM_CMD_SET_BURST:
/* Set burst length, arg use @ref CAM_BURST */
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
regval &= ~CAM_REG_XLEN_MASK;
regval |= (arg << CAM_REG_XLEN_SHIFT) & CAM_REG_XLEN_MASK;
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
break;
#if !defined(BL702)
case CAM_CMD_SET_RGBA8888_ALPHA:
/* Set alpha value of RGBA8888 output, arg is alpha */
regval = getreg32(reg_base + CAM_DVP2AXI_MISC_OFFSET);
regval &= ~CAM_REG_ALPHA_MASK;
regval |= arg & CAM_REG_ALPHA_MASK;
putreg32(regval, reg_base + CAM_DVP2AXI_MISC_OFFSET);
break;
case CAM_CMD_GET_FRAME_ID:
/* Get frame id */
*(uint16_t *)arg = getreg32(reg_base + CAM_FRAME_ID_STS01_OFFSET) & 0xffff;
break;
#endif
case CAM_CMD_WRAP_MODE:
/* Wrap to output buffer start address, only effective in mjpeg mode, arg use ENABLE or DISABLE */
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
if (arg) {
regval |= CAM_REG_HW_MODE_FWRAP;
} else {
regval &= ~CAM_REG_HW_MODE_FWRAP;
}
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
break;
case CAM_CMD_COUNT_TRIGGER_NORMAL_INT:
/* Set frame count to trigger normal interrupt, arg is frame count */
#if defined(BL702)
regval = getreg32(reg_base + CAM_INT_CONTROL_OFFSET);
regval &= ~CAM_REG_FRAME_CNT_TRGR_INT_MASK;
regval |= arg << CAM_REG_FRAME_CNT_TRGR_INT_SHIFT;
putreg32(regval, reg_base + CAM_INT_CONTROL_OFFSET);
#else
regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
regval &= ~CAM_REG_FRAME_CNT_TRGR_INT_MASK;
regval |= arg & CAM_REG_FRAME_CNT_TRGR_INT_MASK;
putreg32(regval, reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
#endif
break;
#if !defined(BL702)
case CAM_CMD_FRAME_ID_RESET:
/* Reset frame id */
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_ISP_ID_YUV_OFFSET);
regval |= CAM_FRONT_REG_YUV_IDGEN_RST;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_ISP_ID_YUV_OFFSET);
break;
case CAM_CMD_INVERSE_VSYNC_POLARITY:
/* Inverse vsync polarity */
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval |= CAM_FRONT_RG_DVPAS_VS_INV;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
break;
case CAM_CMD_INVERSE_HSYNC_POLARITY:
/* Inverse hsync polarity */
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval |= CAM_FRONT_RG_DVPAS_HS_INV;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
break;
#endif
default:
ret = -EPERM;
break;
}
return ret;
}

4
drivers/lhal/src/bflb_dac.c
View File

@ -7,7 +7,7 @@
#define DAC_GPIP_BASE ((uint32_t)0x20002000)
#endif
void bflb_dac_init(struct bflb_device_s *dev, uint8_t frequence)
void bflb_dac_init(struct bflb_device_s *dev, uint8_t clk_div)
{
uint32_t regval;
uint32_t reg_base;
@ -46,7 +46,7 @@ void bflb_dac_init(struct bflb_device_s *dev, uint8_t frequence)
#ifdef GPIP_GPDAC_EN2
regval |= GPIP_GPDAC_EN2;
#endif
regval |= (frequence << GPIP_GPDAC_MODE_SHIFT);
regval |= (clk_div << GPIP_GPDAC_MODE_SHIFT);
putreg32(regval, DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET);
regval = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);

8
drivers/lhal/src/bflb_dma.c
View File

@ -290,7 +290,7 @@ void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
#endif
}
int bflb_dma_channel_start(struct bflb_device_s *dev)
void bflb_dma_channel_start(struct bflb_device_s *dev)
{
uint32_t regval;
uint32_t channel_base;
@ -301,11 +301,9 @@ int bflb_dma_channel_start(struct bflb_device_s *dev)
regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
regval |= DMA_E;
putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
return 0;
}
int bflb_dma_channel_stop(struct bflb_device_s *dev)
void bflb_dma_channel_stop(struct bflb_device_s *dev)
{
uint32_t regval;
uint32_t channel_base;
@ -316,8 +314,6 @@ int bflb_dma_channel_stop(struct bflb_device_s *dev)
regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
regval &= ~DMA_E;
putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
return 0;
}
bool bflb_dma_channel_isbusy(struct bflb_device_s *dev)

131
drivers/lhal/src/bflb_ef_ctrl.c
View File

@ -1,6 +1,14 @@
#include "bflb_ef_ctrl.h"
#include "hardware/ef_ctrl_reg.h"
#if defined(BL602) || defined(BL702) || defined(BL702L)
#define BFLB_EF_CTRL_BASE ((uint32_t)0x40007000)
#elif defined(BL616) || defined(BL808) || defined(BL606P)
#define BFLB_EF_CTRL_BASE ((uint32_t)0x20056000)
#elif defined(BL628)
#define BFLB_EF_CTRL_BASE ((uint32_t)0x2000C000)
#endif
#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24)
#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8)
#define EF_CTRL_OP_MODE_AUTO 0
@ -71,7 +79,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_switch_ahb_clk_r0(struct bflb_device_s
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
/* Add delay for CLK to be stable */
arch_delay_us(4);
@ -109,7 +117,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_switch_ahb_clk_r1(struct bflb_device_s
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
@ -118,7 +126,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_switch_ahb_clk_r1(struct bflb_device_s
(0 << EF_CTRL_EF_IF_1_RW_POS) |
(0 << EF_CTRL_EF_IF_1_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
/* Add delay for CLK to be stable */
arch_delay_us(4);
@ -150,7 +158,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r0(struct bflb_device_s
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
/* Program */
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
@ -165,7 +173,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r0(struct bflb_device_s
(1 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
/* Add delay for POR to be stable */
arch_delay_us(4);
@ -183,7 +191,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r0(struct bflb_device_s
(1 << EF_CTRL_EF_IF_0_RW_POS) |
(1 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
}
/****************************************************************************/ /**
@ -211,7 +219,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
@ -220,7 +228,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s
(0 << EF_CTRL_EF_IF_1_RW_POS) |
(0 << EF_CTRL_EF_IF_1_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
/* Program */
/* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
@ -234,7 +242,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
/* Add delay for POR to be stable */
arch_delay_us(4);
@ -246,7 +254,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s
(1 << EF_CTRL_EF_IF_1_RW_POS) |
(0 << EF_CTRL_EF_IF_1_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
@ -255,7 +263,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s
(1 << EF_CTRL_EF_IF_1_RW_POS) |
(1 << EF_CTRL_EF_IF_1_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
}
#endif
@ -269,7 +277,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s
*******************************************************************************/
static void ATTR_TCM_SECTION bflb_ef_ctrl_clear_data_reg0(struct bflb_device_s *dev)
{
uint32_t *pefuse_start = (uint32_t *)(dev->reg_base + 0x00);
uint32_t *pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + 0x00);
uint32_t i = 0;
/* Switch to AHB clock */
@ -292,7 +300,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_clear_data_reg0(struct bflb_device_s *
#ifdef EF_CTRL_EFUSE_R1_SIZE
static void ATTR_TCM_SECTION bflb_ef_ctrl_clear_data_reg1(struct bflb_device_s *dev)
{
uint32_t *pefuse_start = (uint32_t *)(dev->reg_base + EF_CTRL_EFUSE_R0_SIZE);
uint32_t *pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + EF_CTRL_EFUSE_R0_SIZE);
uint32_t i = 0;
/* Switch to AHB clock */
@ -333,7 +341,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r0(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
@ -347,13 +355,13 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r0(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(1 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
arch_delay_us(10);
/* Wait for efuse control idle */
do {
reg_val = getreg32(dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
timeout--;
if (timeout == 0) {
@ -374,7 +382,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r0(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
}
/****************************************************************************/ /**
@ -404,7 +412,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r1(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
@ -413,7 +421,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r1(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_1_RW_POS) |
(0 << EF_CTRL_EF_IF_1_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
@ -422,17 +430,17 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r1(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_1_RW_POS) |
(1 << EF_CTRL_EF_IF_1_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
arch_delay_us(10);
/* Wait for efuse control idle */
do {
reg_val = getreg32(dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
} while (reg_val & EF_CTRL_EF_IF_1_BUSY_MASK);
do {
reg_val = getreg32(dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
} while (!(reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK));
/* Switch to AHB clock since often read efuse data after load */
@ -447,7 +455,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r1(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_0_RW_POS) |
(0 << EF_CTRL_EF_IF_0_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
(EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
@ -456,7 +464,7 @@ static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r1(struct bflb_device_s *de
(0 << EF_CTRL_EF_IF_1_RW_POS) |
(0 << EF_CTRL_EF_IF_1_TRIG_POS);
putreg32(reg_val, dev->reg_base + EF_CTRL_EF_IF_CTRL_1_OFFSET);
putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
}
#endif
@ -472,7 +480,7 @@ static int ATTR_TCM_SECTION bflb_ef_ctrl_busy(struct bflb_device_s *dev)
{
uint32_t reg_val;
reg_val = getreg32(dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
if (reg_val & EF_CTRL_EF_IF_0_BUSY_MASK) {
return 1;
@ -493,14 +501,14 @@ int ATTR_TCM_SECTION bflb_ef_ctrl_autoload_done(struct bflb_device_s *dev)
{
uint32_t reg_val;
if (dev == NULL) {
dev = bflb_device_get_by_name("ef_ctrl");
}
// if (dev == NULL) {
// dev = bflb_device_get_by_name("ef_ctrl");
// }
/* Switch to AHB clock */
bflb_ef_ctrl_switch_ahb_clk_r0(dev);
reg_val = getreg32(dev->reg_base + EF_CTRL_EF_IF_CTRL_0_OFFSET);
reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
if (reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK) {
return 1;
@ -549,14 +557,13 @@ void ATTR_TCM_SECTION bflb_ef_ctrl_write_direct(struct bflb_device_s *dev, uint3
region1_count = count;
}
if (dev == NULL) {
dev = bflb_device_get_by_name("ef_ctrl");
}
pefuse_start = (uint32_t *)(dev->reg_base + offset);
// if (dev == NULL) {
// dev = bflb_device_get_by_name("ef_ctrl");
// }
pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + offset);
irq_stat = bflb_irq_save();
#if defined(BL702) || defined(BL602) || defined(BL702L)
extern void bflb_efuse_switch_cpu_clock_save(void);
bflb_efuse_switch_cpu_clock_save();
#endif
if (region0_count > 0) {
@ -635,10 +642,10 @@ void ATTR_TCM_SECTION bflb_ef_ctrl_read_direct(struct bflb_device_s *dev, uint32
region1_count = count;
}
if (dev == NULL) {
dev = bflb_device_get_by_name("ef_ctrl");
}
pefuse_start = (uint32_t *)(dev->reg_base + offset);
// if (dev == NULL) {
// dev = bflb_device_get_by_name("ef_ctrl");
// }
pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + offset);
irq_stat = bflb_irq_save();
#if defined(BL702) || defined(BL602) || defined(BL702L)
@ -682,17 +689,17 @@ void ATTR_TCM_SECTION bflb_ef_ctrl_read_direct(struct bflb_device_s *dev, uint32
* @return None
*
*******************************************************************************/
void ATTR_TCM_SECTION bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_type *trim, uint8_t reload)
void ATTR_TCM_SECTION bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_t *trim, uint8_t reload)
{
uint32_t reg_val;
uint32_t i = 0;
const bflb_ef_ctrl_com_trim_cfg *trim_list = NULL;
const bflb_ef_ctrl_com_trim_cfg_t *trim_list = NULL;
uint32_t trim_list_len;
uintptr_t irq_stat;
if (dev == NULL) {
dev = bflb_device_get_by_name("ef_ctrl");
}
// if (dev == NULL) {
// dev = bflb_device_get_by_name("ef_ctrl");
// }
irq_stat = bflb_irq_save();
#if defined(BL702) || defined(BL602) || defined(BL702L)
@ -727,22 +734,22 @@ void ATTR_TCM_SECTION bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, c
}
#endif
trim->len = trim_list[i].value_len;
reg_val = getreg32(dev->reg_base + (trim_list[i].en_addr / 32) * 4);
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4);
if (reg_val & (1 << (trim_list[i].en_addr % 32))) {
trim->en = 1;
}
reg_val = getreg32(dev->reg_base + (trim_list[i].parity_addr / 32) * 4);
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4);
if (reg_val & (1 << (trim_list[i].parity_addr % 32))) {
trim->parity = 1;
}
if (((trim_list[i].value_addr % 32) + trim_list[i].value_len) > 32) {
uint64_t tmpval64 = (uint64_t)getreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4);
tmpval64 |= (((uint64_t)getreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4 + 4)) << 32);
uint64_t tmpval64 = (uint64_t)getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
tmpval64 |= (((uint64_t)getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4 + 4)) << 32);
tmpval64 = tmpval64 >> (trim_list[i].value_addr % 32);
trim->value = (uint32_t)(tmpval64 & (((uint64_t)1 << trim_list[i].value_len) - 1));
} else {
reg_val = getreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4);
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
reg_val = reg_val >> (trim_list[i].value_addr % 32);
trim->value = reg_val & ((1 << trim_list[i].value_len) - 1);
}
@ -778,13 +785,13 @@ void ATTR_TCM_SECTION bflb_ef_ctrl_write_common_trim(struct bflb_device_s *dev,
uint32_t reg_val;
uint32_t i = 0;
uint8_t parity = 0;
const bflb_ef_ctrl_com_trim_cfg *trim_list = NULL;
const bflb_ef_ctrl_com_trim_cfg_t *trim_list = NULL;
uint32_t trim_list_len;
uintptr_t irq_stat;
if (dev == NULL) {
dev = bflb_device_get_by_name("ef_ctrl");
}
// if (dev == NULL) {
// dev = bflb_device_get_by_name("ef_ctrl");
// }
trim_list_len = bflb_ef_ctrl_get_common_trim_list(&trim_list);
@ -805,29 +812,29 @@ void ATTR_TCM_SECTION bflb_ef_ctrl_write_common_trim(struct bflb_device_s *dev,
bflb_ef_ctrl_switch_ahb_clk_r1(dev);
}
#endif
reg_val = getreg32(dev->reg_base + (trim_list[i].en_addr / 32) * 4);
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4);
reg_val |= (1 << (trim_list[i].en_addr % 32));
putreg32(dev->reg_base + (trim_list[i].en_addr / 32) * 4, reg_val);
putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4, reg_val);
parity = bflb_ef_ctrl_get_trim_parity(value, trim_list[i].value_len);
if (parity) {
reg_val = getreg32(dev->reg_base + (trim_list[i].parity_addr / 32) * 4);
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4);
reg_val |= (1 << (trim_list[i].parity_addr % 32));
putreg32(dev->reg_base + (trim_list[i].parity_addr / 32) * 4, reg_val);
putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4, reg_val);
}
if (((trim_list[i].value_addr % 32) + trim_list[i].value_len) > 32) {
reg_val = getreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4);
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
reg_val |= (value << (trim_list[i].value_addr % 32));
putreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4, reg_val);
putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4, reg_val);
reg_val = getreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4) + 4;
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4) + 4;
reg_val |= (value >> (32 - (trim_list[i].value_addr % 32)));
putreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4 + 4, reg_val);
putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4 + 4, reg_val);
} else {
reg_val = getreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4);
reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
reg_val |= (value << (trim_list[i].value_addr % 32));
putreg32(dev->reg_base + (trim_list[i].value_addr / 32) * 4, reg_val);
putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4, reg_val);
}
if (program) {

50
drivers/lhal/src/bflb_emac.c
View File

@ -33,7 +33,6 @@
*
******************************************************************************
*/
#include "bflb_core.h"
#include "bflb_emac.h"
#include "bflb_clock.h"
#include "bflb_l1c.h"
@ -44,8 +43,41 @@
#define EMAC_TX_COMMON_FLAGS (EMAC_BD_TX_RD_MASK | EMAC_BD_TX_IRQ_MASK | EMAC_BD_TX_PAD_MASK | EMAC_BD_TX_CRC_MASK | EMAC_BD_TX_EOF_MASK)
#define EMAC_RX_COMMON_FLAGS ((ETH_MAX_PACKET_SIZE << 16) | EMAC_BD_RX_IRQ_MASK)
static struct emac_handle_s ethHandle;
static struct emac_handle_s *thiz = NULL;
/**
* @brief Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern.
*/
struct bflb_emac_bd_desc_s {
uint32_t C_S_L; /*!< Buffer Descriptors(BD) control,status,length */
uint32_t Buffer; /*!< BD buffer address */
};
/**
* @brief emac handle type definition
* @param bd Tx descriptor header pointer
* @param tx_index_emac TX index: EMAC
* @param tx_index_cpu TX index: CPU/SW
* @param tx_buff_limit TX index max
* @param rsv0 rsv0
* @param rx_index_emac RX index: EMAC
* @param rx_index_cpu RX index: CPU/SW
* @param rx_buff_limit RX index max
* @param rsv1 rsv1
*
*/
struct bflb_emac_handle_s {
struct bflb_emac_bd_desc_s *bd;
uint8_t tx_index_emac;
uint8_t tx_index_cpu;
uint8_t tx_buff_limit;
uint8_t rsv0;
uint8_t rx_index_emac;
uint8_t rx_index_cpu;
uint8_t rx_buff_limit;
uint8_t rsv1;
};
static struct bflb_emac_handle_s eth_handle;
static struct bflb_emac_handle_s *thiz = NULL;
/**
*
@ -132,7 +164,7 @@ void bflb_emac_bd_rx_on_err(uint32_t index)
*/
void bflb_emac_bd_tx_dequeue(uint32_t index)
{
struct emac_bd_desc_s *DMADesc;
struct bflb_emac_bd_desc_s *DMADesc;
thiz->tx_index_emac = index;
DMADesc = &thiz->bd[thiz->tx_index_emac];
@ -202,7 +234,7 @@ int emac_bd_fragment_support(void)
int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
{
uint32_t err = 0;
struct emac_bd_desc_s *DMADesc;
struct bflb_emac_bd_desc_s *DMADesc;
uint32_t tx_flags = EMAC_TX_COMMON_FLAGS;
DMADesc = &thiz->bd[thiz->tx_index_cpu];
@ -257,7 +289,7 @@ int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in
int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out)
{
uint32_t err = 0;
struct emac_bd_desc_s *DMADesc;
struct bflb_emac_bd_desc_s *DMADesc;
DMADesc = &thiz->bd[thiz->rx_index_cpu];
@ -488,12 +520,12 @@ uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev)
* @param rx_buff_cnt
*
*/
static void emac_dma_desc_list_init(uint32_t reg_base, struct emac_handle_s *handle, uint8_t *tx_buff, uint32_t tx_buff_cnt, uint8_t *rx_buff, uint32_t rx_buff_cnt)
static void emac_dma_desc_list_init(uint32_t reg_base, struct bflb_emac_handle_s *handle, uint8_t *tx_buff, uint32_t tx_buff_cnt, uint8_t *rx_buff, uint32_t rx_buff_cnt)
{
uint32_t i = 0;
/* Set the Ethernet handler env */
handle->bd = (struct emac_bd_desc_s *)(uintptr_t)(reg_base + EMAC_DMA_DESC_OFFSET);
handle->bd = (struct bflb_emac_bd_desc_s *)(uintptr_t)(reg_base + EMAC_DMA_DESC_OFFSET);
handle->tx_index_emac = 0;
handle->tx_index_cpu = 0;
handle->tx_buff_limit = tx_buff_cnt - 1;
@ -536,7 +568,7 @@ static void emac_dma_desc_list_init(uint32_t reg_base, struct emac_handle_s *han
*/
void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count)
{
thiz = &ethHandle;
thiz = &eth_handle;
uint32_t reg_base;
reg_base = dev->reg_base;
/* init the BDs in emac with buffer address */

37
drivers/lhal/src/bflb_ir.c
View File

@ -215,23 +215,23 @@ void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length)
length = length < 4 ? length : 4;
}
while(i < length){
if (bflb_ir_txfifo_cnt(dev) > 0) {
if (bflb_ir_get_txfifo_cnt(dev) > 0) {
putreg32(data[i], reg_base + IR_FIFO_WDATA_OFFSET);
i++;
}
}
if ((getreg32(reg_base + IRTX_CONFIG_OFFSET) & IR_CR_IRTX_FRM_EN) == 0) {
while((bflb_ir_txint_status(dev) & IR_TX_INT_END) == 0){
while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
/* Waiting for sending */
}
} else {
while(bflb_ir_txfifo_cnt(dev) < 4){
while(bflb_ir_get_txfifo_cnt(dev) < 4){
/* Waiting for sending */
}
}
#else
while((bflb_ir_txint_status(dev) & IR_TX_INT_END) == 0){
while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
/* Waiting for sending */
}
#endif
@ -326,12 +326,12 @@ void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
}
/* Write to tx fifo */
while(bflb_ir_txfifo_cnt(dev) == 0){}
while(bflb_ir_get_txfifo_cnt(dev) == 0){}
putreg32(pwval, reg_base + IR_FIFO_WDATA_OFFSET);
}
#endif
while((bflb_ir_txint_status(dev) & IR_TX_INT_END) == 0){
while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
/* Waiting for sending */
}
@ -383,7 +383,7 @@ void bflb_ir_txint_clear(struct bflb_device_s *dev)
putreg32(regval, reg_base + IRTX_INT_STS_OFFSET);
}
uint32_t bflb_ir_txint_status(struct bflb_device_s *dev)
uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev)
{
uint32_t reg_base;
@ -407,7 +407,7 @@ void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable)
putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
}
uint8_t bflb_ir_txfifo_cnt(struct bflb_device_s *dev)
uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev)
{
uint32_t reg_base;
@ -494,7 +494,7 @@ uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data)
regval |= IR_CR_IRRX_EN;
putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
while((bflb_ir_rxint_status(dev) & IR_RX_INT_END) == 0){
while((bflb_ir_get_rxint_status(dev) & IR_RX_INTSTS_END) == 0){
/* Waiting for receiving */
}
@ -526,8 +526,8 @@ uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t l
regval |= IR_CR_IRRX_EN;
putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
while((bflb_ir_rxint_status(dev) & IR_RX_INT_END) == 0){
if (bflb_ir_rxfifo_cnt(dev) != 0 && i < length) {
while((bflb_ir_get_rxint_status(dev) & IR_RX_INTSTS_END) == 0){
if (bflb_ir_get_rxfifo_cnt(dev) != 0 && i < length) {
#if defined(BL602) || defined(BL702)
data[i] = getreg32(reg_base + IRRX_SWM_FIFO_RDATA_OFFSET);
#else
@ -587,7 +587,7 @@ void bflb_ir_rxint_clear(struct bflb_device_s *dev)
putreg32(regval, reg_base + IRRX_INT_STS_OFFSET);
}
uint32_t bflb_ir_rxint_status(struct bflb_device_s *dev)
uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev)
{
uint32_t reg_base;
@ -595,7 +595,7 @@ uint32_t bflb_ir_rxint_status(struct bflb_device_s *dev)
return (getreg32(reg_base + IRRX_INT_STS_OFFSET) & 0x7);
}
uint8_t bflb_ir_rxfifo_cnt(struct bflb_device_s *dev)
uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev)
{
uint32_t reg_base;
@ -624,3 +624,14 @@ void bflb_ir_rxfifo_clear(struct bflb_device_s *dev)
#endif
}
#endif
int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
{
int ret = 0;
switch (cmd) {
default:
ret = -EPERM;
break;
}
return ret;
}

366
drivers/lhal/src/bflb_iso11898.c Normal file
View File

@ -0,0 +1,366 @@
#include "bflb_iso11898.h"
#include "hardware/iso11898_reg.h"
void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
/* first enter reset mode */
regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
regval |= ISO11898_RESET_REQUEST;
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
/* force using PeliISO11898 not BasicISO11898 */
regval = getreg32(reg_base + ISO11898_CLOCK_DIVIDER_OFFSET);
regval |= ISO11898_CAN_MODE;
putreg32(regval, reg_base + ISO11898_CLOCK_DIVIDER_OFFSET);
/* config prescale and synchronisation_jump_width */
regval = getreg32(reg_base + ISO11898_BUS_TIMING_0_OFFSET);
regval &= ~ISO11898_BAUD_RATE_PRESCALER_MASK;
regval |= (config->prescaler << ISO11898_BAUD_RATE_PRESCALER_SHIFT);
regval &= ~ISO11898_SYNC_JUMP_WIDTH_MASK;
regval |= (config->sjw << ISO11898_SYNC_JUMP_WIDTH_SHIFT);
putreg32(regval, reg_base + ISO11898_BUS_TIMING_0_OFFSET);
/* config samping and bit_segment_1/2 */
regval = getreg32(reg_base + ISO11898_BUS_TIMING_1_OFFSET);
if (config->sample == ISO11898_SAMPLE_SINGLE) {
regval &= ~ISO11898_SAMPLING;
} else {
regval |= ISO11898_SAMPLING;
}
regval &= ~ISO11898_TIME_SEGMENT_1_MASK;
regval |= (config->bs1 << ISO11898_TIME_SEGMENT_1_SHIFT);
regval &= ~ISO11898_TIME_SEGMENT_2_MASK;
regval |= (config->bs2 << ISO11898_TIME_SEGMENT_2_SHIFT);
putreg32(regval, reg_base + ISO11898_BUS_TIMING_1_OFFSET);
/* config mode */
regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
if (config->mode == ISO11898_MODE_NORMAL) {
regval &= ~ISO11898_LISTEN_ONLY;
regval &= ~ISO11898_SELF_TEST;
} else if (config->mode == ISO11898_MODE_LOOPBACK) {
regval &= ~ISO11898_LISTEN_ONLY;
regval |= ISO11898_SELF_TEST;
} else if (config->mode == ISO11898_MODE_SILENT) {
regval |= ISO11898_LISTEN_ONLY;
regval &= ~ISO11898_SELF_TEST;
} else if (config->mode == ISO11898_MODE_SILENT_LOOPBACK) {
regval |= ISO11898_LISTEN_ONLY;
regval |= ISO11898_SELF_TEST;
} else {
}
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
/* last leave reset mode */
regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
regval &= ~ISO11898_RESET_REQUEST;
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
}
void bflb_iso11898_deinit(struct bflb_device_s *dev)
{
}
void bflb_iso11898_abort_send(struct bflb_device_s *dev)
{
putreg32(ISO11898_ABORT_TRANSMISSION, dev->reg_base + ISO11898_COMMAND_OFFSET);
}
int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout)
{
uint32_t reg_base;
uint32_t regval;
uint32_t data_base_addr;
uint8_t mode;
uint64_t start_time;
reg_base = dev->reg_base;
start_time = bflb_mtimer_get_time_ms();
while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_TX_AVAILABLE)) {
if ((bflb_mtimer_get_time_ms() - start_time) > timeout) {
return -ETIMEDOUT;
}
}
/* config frame information register */
regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
regval &= ~ISO11898_FRAME_INFORMATION_DLC_MASK;
regval |= (msg->dlc << ISO11898_FRAME_INFORMATION_DLC_SHIFT);
if (msg->id_type == ISO11898_ID_STANDARD) {
regval &= ~ISO11898_FRAME_INFORMATION_FF;
} else {
regval |= ISO11898_FRAME_INFORMATION_FF;
}
if (msg->rtr == ISO11898_RTR_DATA) {
regval &= ~ISO11898_FRAME_INFORMATION_RTR;
} else {
regval |= ISO11898_FRAME_INFORMATION_RTR;
}
putreg32(regval, reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
/* config id */
if (msg->id_type == ISO11898_ID_STANDARD) {
putreg32(msg->std_id >> (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT), reg_base + ISO11898_SFF_ID1_OFFSET);
putreg32(msg->std_id << ISO11898_SFF_ID2_BIT20_18_SHIFT, reg_base + ISO11898_SFF_ID2_OFFSET);
data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET;
} else {
putreg32(msg->ext_id >> 21, reg_base + ISO11898_EFF_ID1_OFFSET);
putreg32(msg->ext_id >> 13, reg_base + ISO11898_EFF_ID2_OFFSET);
putreg32(msg->ext_id >> 5, reg_base + ISO11898_EFF_ID3_OFFSET);
putreg32(msg->ext_id << ISO11898_EFF_ID4_BIT4_0_SHIFT, reg_base + ISO11898_EFF_ID4_OFFSET);
data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET;
}
/* move data from user buff to registers */
for (uint32_t i = 0; i < msg->dlc; i++) {
*((uint32_t *)data_base_addr + i) = msg->data[i];
}
/* trig a request for transmit */
mode = bflb_iso11898_get_mode(dev);
if (mode == ISO11898_MODE_SILENT_LOOPBACK || mode == ISO11898_MODE_LOOPBACK) {
putreg32(ISO11898_SELF_REQUEST, reg_base + ISO11898_COMMAND_OFFSET);
} else if (mode == ISO11898_MODE_NORMAL) {
putreg32(ISO11898_TRANSMIT_REQUEST, reg_base + ISO11898_COMMAND_OFFSET);
} else {
return -2;
}
return 0;
}
int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout)
{
uint32_t reg_base;
uint32_t regval, regval2, regval3, regval4;
uint32_t data_base_addr;
uint64_t start_time;
reg_base = dev->reg_base;
start_time = bflb_mtimer_get_time_ms();
while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_RX_NOT_EMPTY)) {
if ((bflb_mtimer_get_time_ms() - start_time) > timeout) {
return -ETIMEDOUT;
}
}
/* read information register */
regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
msg->dlc = (uint8_t)((regval & ISO11898_FRAME_INFORMATION_DLC_MASK) >> ISO11898_FRAME_INFORMATION_DLC_SHIFT);
if (regval & ISO11898_FRAME_INFORMATION_FF) {
msg->id_type = ISO11898_ID_EXTENDED;
} else {
msg->id_type = ISO11898_ID_STANDARD;
}
if (regval & ISO11898_FRAME_INFORMATION_RTR) {
msg->rtr = ISO11898_RTR_REMOTE;
} else {
msg->rtr = ISO11898_RTR_DATA;
}
/* receive with 11 or 29 bits ID */
if (msg->id_type == ISO11898_ID_STANDARD) {
regval = getreg32(reg_base + ISO11898_SFF_ID1_OFFSET);
regval &= ISO11898_SFF_ID1_BIT28_21_MASK;
regval <<= (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT);
regval2 = getreg32(reg_base + ISO11898_SFF_ID2_OFFSET);
regval2 &= ISO11898_SFF_ID2_BIT20_18_MASK;
regval2 >>= ISO11898_SFF_ID2_BIT20_18_SHIFT;
msg->std_id = regval | regval2;
data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET;
} else {
regval = getreg32(reg_base + ISO11898_EFF_ID1_OFFSET);
regval &= ISO11898_EFF_ID1_BIT28_21_MASK;
regval <<= 21;
regval2 = getreg32(reg_base + ISO11898_EFF_ID2_OFFSET);
regval2 &= ISO11898_EFF_ID2_BIT20_13_MASK;
regval2 <<= 13;
regval3 = getreg32(reg_base + ISO11898_EFF_ID3_OFFSET);
regval3 &= ISO11898_EFF_ID3_BIT12_5_MASK;
regval3 <<= 5;
regval4 = getreg32(reg_base + ISO11898_EFF_ID4_OFFSET);
regval4 &= ISO11898_EFF_ID4_BIT4_0_MASK;
regval4 >>= ISO11898_EFF_ID4_BIT4_0_SHIFT;
msg->ext_id = regval | regval2 | regval3 | regval4;
data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET;
}
/* move data from registers to user buff */
for (uint32_t i = 0; i < msg->dlc; i++) {
msg->data[i] = (uint8_t)(*((uint32_t *)data_base_addr + i));
}
putreg32(ISO11898_RELEASE_RECEIVE_BUFFER, reg_base + ISO11898_COMMAND_OFFSET);
return 0;
}
uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev)
{
return getreg32(dev->reg_base + ISO11898_STATUS_OFFSET) & 0xff;
}
void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
/* first enter reset mode */
regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
regval |= ISO11898_RESET_REQUEST;
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
/* config mode */
regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
if (mode == ISO11898_MODE_NORMAL) {
regval &= ~ISO11898_LISTEN_ONLY;
regval &= ~ISO11898_SELF_TEST;
} else if (mode == ISO11898_MODE_LOOPBACK) {
regval &= ~ISO11898_LISTEN_ONLY;
regval |= ISO11898_SELF_TEST;
} else if (mode == ISO11898_MODE_SILENT) {
regval |= ISO11898_LISTEN_ONLY;
regval &= ~ISO11898_SELF_TEST;
} else if (mode == ISO11898_MODE_SILENT_LOOPBACK) {
regval |= ISO11898_LISTEN_ONLY;
regval |= ISO11898_SELF_TEST;
} else {
}
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
/* last leave reset mode */
regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
regval &= ~ISO11898_RESET_REQUEST;
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
}
uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev)
{
uint32_t regval;
uint8_t silent, loopback;
regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET);
if (regval & ISO11898_SELF_TEST) {
loopback = 1;
} else {
loopback = 0;
}
if (regval & ISO11898_LISTEN_ONLY) {
silent = 1;
} else {
silent = 0;
}
if (loopback && silent) {
return ISO11898_MODE_SILENT_LOOPBACK;
} else if (!loopback && silent) {
return ISO11898_MODE_SILENT;
} else if (loopback && !silent) {
return ISO11898_MODE_LOOPBACK;
} else {
return ISO11898_MODE_NORMAL;
}
}
void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter)
{
uint32_t reg_base;
uint32_t regval;
uint8_t mode;
reg_base = dev->reg_base;
/* first save mode */
mode = bflb_iso11898_get_mode(dev);
/* enter reset mode */
regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
regval |= ISO11898_RESET_REQUEST;
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
/* config filter type */
regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET);
if (filter->filter_type == ISO11898_FILTER_TYPE_SINGLE) {
regval |= ISO11898_FILTER_TYPE;
} else {
regval &= ~ISO11898_FILTER_TYPE;
}
putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
/* config filter code and mask */
putreg32(filter->code0, reg_base + ISO11898_ACCEPTANCE_CODE_0_OFFSET);
putreg32(filter->code1, reg_base + ISO11898_ACCEPTANCE_CODE_1_OFFSET);
putreg32(filter->code2, reg_base + ISO11898_ACCEPTANCE_CODE_2_OFFSET);
putreg32(filter->code3, reg_base + ISO11898_ACCEPTANCE_CODE_3_OFFSET);
putreg32(filter->mask0, reg_base + ISO11898_ACCEPTANCE_MASK_0_OFFSET);
putreg32(filter->mask1, reg_base + ISO11898_ACCEPTANCE_MASK_1_OFFSET);
putreg32(filter->mask2, reg_base + ISO11898_ACCEPTANCE_MASK_2_OFFSET);
putreg32(filter->mask3, reg_base + ISO11898_ACCEPTANCE_MASK_3_OFFSET);
/* restore saved mode */
bflb_iso11898_set_mode(dev, mode);
}
void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
if (mask) {
regval &= ~ISO11898_TRANSMIT_INT_EN;
} else {
regval |= ISO11898_TRANSMIT_INT_EN;
}
putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
}
void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
if (mask) {
regval &= ~ISO11898_RECEIVE_INT_EN;
} else {
regval |= ISO11898_RECEIVE_INT_EN;
}
putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
}
void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
if (mask) {
regval &= ~ISO11898_ERROR_INT_EN;
regval &= ~ISO11898_DATA_OVERRUN_INT_EN;
regval &= ~ISO11898_ERROR_PASSIVE_INT_EN;
regval &= ~ISO11898_ARB_LOST_INT_EN;
regval &= ~ISO11898_BUS_ERROR_INT_EN;
} else {
regval |= ISO11898_ERROR_INT_EN;
regval |= ISO11898_DATA_OVERRUN_INT_EN;
regval |= ISO11898_ERROR_PASSIVE_INT_EN;
regval |= ISO11898_ARB_LOST_INT_EN;
regval |= ISO11898_BUS_ERROR_INT_EN;
}
putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
}
uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev)
{
return getreg32(dev->reg_base + ISO11898_INTERRUPT_OFFSET);
}

38
drivers/lhal/src/bflb_mjpeg.c
View File

@ -189,6 +189,44 @@ void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s
/* Clear interrupt */
putreg32(0x3F00, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
static uint16_t q_table_50_y[64] = {
16, 11, 10, 16, 24, 40, 51, 61,
12, 12, 14, 19, 26, 58, 60, 55,
14, 13, 16, 24, 40, 57, 69, 56,
14, 17, 22, 29, 51, 87, 80, 62,
18, 22, 37, 56, 68, 109, 103, 77,
24, 35, 55, 64, 81, 104, 113, 92,
49, 64, 78, 87, 103, 121, 120, 101,
72, 92, 95, 98, 112, 100, 103, 99
};
static uint16_t q_table_50_uv[64] = {
17, 18, 24, 47, 99, 99, 99, 99,
18, 21, 26, 66, 99, 99, 99, 99,
24, 26, 56, 99, 99, 99, 99, 99,
47, 66, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99,
99, 99, 99, 99, 99, 99, 99, 99
};
uint16_t tmp_table_y[64] = { 0 };
uint16_t tmp_table_uv[64] = { 0 };
if (config->input_yy_table) {
bflb_mjpeg_calculate_quantize_table(config->quality, config->input_yy_table, tmp_table_y);
} else {
bflb_mjpeg_calculate_quantize_table(config->quality, q_table_50_y, tmp_table_y);
}
if (config->input_uv_table) {
bflb_mjpeg_calculate_quantize_table(config->quality, config->input_uv_table, tmp_table_uv);
} else {
bflb_mjpeg_calculate_quantize_table(config->quality, q_table_50_uv, tmp_table_uv);
}
bflb_mjpeg_fill_quantize_table(dev, tmp_table_y, tmp_table_uv);
}
void bflb_mjpeg_start(struct bflb_device_s *dev)

1
drivers/lhal/src/bflb_pwm_v1.c
View File

@ -1,4 +1,5 @@
#include "bflb_pwm_v1.h"
#include "bflb_clock.h"
#include "hardware/pwm_v1_reg.h"
void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struct bflb_pwm_v1_channel_config_s *config)

1
drivers/lhal/src/bflb_pwm_v2.c
View File

@ -1,4 +1,5 @@
#include "bflb_pwm_v2.h"
#include "bflb_clock.h"
#include "hardware/pwm_v2_reg.h"
void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config_s *config)

12
drivers/lhal/src/bflb_rtc.c
View File

@ -1,13 +1,21 @@
#include "bflb_rtc.h"
#include "hardware/rtc_reg.h"
#if defined(BL602) || defined(BL702) || defined(BL702L)
#define BFLB_RTC_BASE 0x4000F000
#elif defined(BL808) || defined(BL606P) || defined(BL616)
#define BFLB_RTC_BASE 0x2000F000
#elif defined(BL628)
#define BFLB_RTC_BASE 0x2008F000
#endif
void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time)
{
uint32_t reg_base;
uint32_t regval;
uint32_t comp_l, comp_h;
reg_base = dev->reg_base;
reg_base = BFLB_RTC_BASE;
/* Clear & Disable RTC counter */
regval = getreg32(reg_base + HBN_CTL_OFFSET);
@ -51,7 +59,7 @@ uint64_t bflb_rtc_get_time(struct bflb_device_s *dev)
uint64_t time_l;
uint64_t time_h;
reg_base = dev->reg_base;
reg_base = BFLB_RTC_BASE;
/* Tigger RTC val read */
regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET);

90
drivers/lhal/src/bflb_sec_aes.c
View File

@ -150,7 +150,11 @@ int bflb_aes_encrypt(struct bflb_device_s *dev,
regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
if (temp_iv) {
regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
} else {
regval |= SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select last iv */
}
regval &= ~SEC_ENG_SE_AES_0_DEC_EN; /* Set AES encryption */
regval &= ~SEC_ENG_SE_AES_0_MSG_LEN_MASK;
regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
@ -159,24 +163,26 @@ int bflb_aes_encrypt(struct bflb_device_s *dev,
mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
if (mode == AES_MODE_XTS) {
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
} else {
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
if (temp_iv) {
if (mode == AES_MODE_XTS) {
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
} else {
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
}
}
/* Set input and output address */
@ -216,8 +222,12 @@ int bflb_aes_decrypt(struct bflb_device_s *dev,
regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
regval |= SEC_ENG_SE_AES_0_DEC_EN; /* Set AES decryption */
if (temp_iv) {
regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
} else {
regval |= SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select last iv */
}
regval |= SEC_ENG_SE_AES_0_DEC_EN; /* Set AES decryption */
regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
regval &= ~SEC_ENG_SE_AES_0_MSG_LEN_MASK;
regval |= ((len / 16) << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT);
@ -225,24 +235,26 @@ int bflb_aes_decrypt(struct bflb_device_s *dev,
mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
if (mode == AES_MODE_XTS) {
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
} else {
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
if (temp_iv) {
if (mode == AES_MODE_XTS) {
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
} else {
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
temp_iv += 4;
putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
temp_iv += 4;
}
}
/* Set input and output address */

12
drivers/lhal/src/bflb_spi.c
View File

@ -566,6 +566,18 @@ int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
break;
case SPI_CMD_RX_IGNORE:
/* set rx ignore, start: arg[20:16], stop: arg[4:0] */
regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
if (arg) {
regval |= SPI_CR_SPI_RXD_IGNR_EN;
putreg32(arg, reg_base + SPI_RXD_IGNR_OFFSET);
} else {
regval &= ~SPI_CR_SPI_RXD_IGNR_EN;
}
putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
break;
default:
ret = -EPERM;
break;