CloudEdge/bl_mcu_sdk
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* use nuttx libc, disable system libc
* use tlsf as default
* update lhal flash driver
* add example readme
* add flash ini for new flash tool
* add fw header for new flash tool
This commit is contained in:
jzlv 2023-01-17 20:54:15 +08:00
parent 89592fc9a3
commit 356f258e83
554 changed files with 79150 additions and 46596 deletions
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3
bsp/board/bl602dk/CMakeLists.txt
View File

@ -1,5 +1,8 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl602_flash.ld)
# sdk_add_link_options(-ufw_header)

10
bsp/board/bl602dk/bl602_flash.ld
View File

@ -22,6 +22,7 @@ HeapSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 16K
dtcm_memory (rx) : ORIGIN = 0x42014000, LENGTH = 48K
@ -32,6 +33,11 @@ SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);
@ -189,6 +195,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory

69
bsp/board/bl602dk/board.c
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@ -3,27 +3,16 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "board.h"
#include "bl602_glb.h"
#include "bl602_sflash.h"
#include "mem.h"
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if defined(CONFIG_BFLOG)
@ -72,7 +61,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -83,17 +72,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -124,40 +113,38 @@ static void console_init()
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
#if defined(CONFIG_BFLOG)
rtc = bflb_device_get_by_name("rtc");
#endif
bflb_irq_restore(flag);
}
void board_uartx_gpio_init()

118
bsp/board/bl602dk/fw_header.c Normal file
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@ -0,0 +1,118 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x04, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M,1:XTAL,2:PLL 48M,3:PLL 120M,4:PLL 160M,5:PLL 192M */
.clk_cfg.cfg.hclk_div = 0x00,
.clk_cfg.cfg.bclk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x03, /*!< 0:120M,1:XCLK(RC32M or XTAL),2:48M,3:80M,4:BCLK,5:96M */
.clk_cfg.cfg.flash_clk_div = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* boot cfg */
.boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/
.boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */
.boot_cfg.bval.key_sel = 0x0, /* [5: 4] for key sel in boot interface*/
.boot_cfg.bval.rsvd6_7 = 0x0, /* [7: 6] for encrypt*/
.boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */
.boot_cfg.bval.cache_select = 0x1, /* [9] for cache */
.boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */
.boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */
.boot_cfg.bval.cache_way_disable = 0x3, /* [15: 12] cache way disable info*/
.boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */
.boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */
.boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */
.boot_cfg.bval.rsvd19_31 = 0x0, /* [31:19] rsvd */
.img_segment_info.img_len = 0x00010000, /* image length or segment count */
.rsvd0 = 0x00000000,
.img_start.flashoffset = 0x00001000, /* flash controller offset */
.hash = { 0xdeadbeef }, /* hash of the image */
.crc32 = 0xdeadbeef /* 4 */
};

165
bsp/board/bl602dk/fw_header.h Normal file
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@ -0,0 +1,165 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 8 + 4 */
union __attribute__((packed, aligned(1))) {
struct __attribute__((packed, aligned(1))) {
uint32_t sign : 2; /* [1: 0] for sign*/
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/
uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_select : 1; /* [9] for cache */
uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash crc */
uint32_t halt_ap : 1; /* [18] halt ap */
uint32_t rsvd19_31 : 13; /* [31:19] rsvd */
} bval;
uint32_t wval;
} boot_cfg; /* 4 */
union __attribute__((packed, aligned(1))) {
uint32_t segment_cnt;
uint32_t img_len;
} img_segment_info; /* 4 */
uint32_t rsvd0; /* rsvd */
union __attribute__((packed, aligned(1))) {
uint32_t ramaddr;
uint32_t flashoffset;
} img_start; /* 4 */
uint32_t hash[32 / 4]; /*hash of the image*/
uint32_t rsv1;
uint32_t rsv2;
uint32_t crc32;
};
#endif

3
bsp/board/bl616dk/CMakeLists.txt
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@ -1,9 +1,12 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl616_flash.ld)
if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)
endif()
# sdk_add_link_options(-ufw_header)

83
bsp/board/bl616dk/bl616_flash.ld
View File

@ -17,29 +17,59 @@ INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x1000; /* 1KB */
StackSize = 0x1000; /* 4KB */
HeapMinSize = 0x1000; /* 4KB */
__EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K;
__RFTLV_SIZE_OFFSET = 1K;
__RFTLV_SIZE_HOLE = 2K;
__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */
__RFTLV_HEAD1_L = (0x41524150); /* PAPA */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0xA0000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0xA0000000, LENGTH = 4M
ram_code (wxa) : ORIGIN = 0xA8000000, LENGTH = 4M
itcm_memory (rx) : ORIGIN = 0x62FC0000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62FC5000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K
ram_memory (!rx) : ORIGIN = 0x62FE0000 , LENGTH = 320K+160K-20K-4K-44K-60K
ram_memory (!rx) : ORIGIN = 0x62FE0000, LENGTH = 320K-20K-4K-44K-60K
ram_wifi (wxa) : ORIGIN = 0x23010000, LENGTH = 160K - __EM_SIZE
}
SECTIONS
{
BOOT2_PT_ADDR = 0x63027c00;
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.init :
{
*(.text.entry)
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
} > xip_memory
.rftlv.tool :
{
. = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET;
PROVIDE( _ld_symbol_rftlv_address = . );
LONG(__RFTLV_HEAD1_H);
LONG(__RFTLV_HEAD1_L);
. = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE;
} > xip_memory
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
*(.text)
*(.text.*)
@ -139,7 +169,9 @@ SECTIONS
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region : AT (__nocache_ram_load_addr)
@ -192,6 +224,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory
@ -250,5 +286,42 @@ SECTIONS
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
.psmram_data (NOLOAD):
{
. = ALIGN(4);
__psram_data_start__ = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.psram_data*))
. = ALIGN(4);
__psram_data_end__ = .;
} > ram_code
.wifibss (NOLOAD) :
{
PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
_sshram = . ;
*(SHAREDRAMIPC)
*(SHAREDRAM)
_eshram = . ;
*ipc_shared.o(COMMON)
*sdu_shared.o(COMMON)
*hal_desc.o(COMMON)
*txl_buffer_shared.o(COMMON)
*txl_frame_shared.o(COMMON)
*scan_shared.o(COMMON)
*scanu_shared.o(COMMON)
*mfp_bip.o(COMMON)
*me_mic.o(COMMON)
*(.wifi_ram*)
. = ALIGN(16);
} > ram_wifi
PROVIDE( _heap_wifi_start = . );
PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
}

101
bsp/board/bl616dk/board.c
View File

@ -3,16 +3,12 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "board.h"
#include "bl616_tzc_sec.h"
#include "bl616_psram.h"
#include "bl616_glb.h"
#include "bl616_sflash.h"
#include "mem.h"
#define WB_4MB_PSRAM (1)
@ -20,18 +16,11 @@
#include "sdh_sdcard.h"
#endif
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
@ -40,10 +29,18 @@ static struct bflb_device_s *rtc;
static void system_clock_init(void)
{
#if 1
/* wifipll/audiopll */
GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL);
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M);
CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_CLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK) / 1000000 - 1);
#else
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL);
GLB_Config_AUDIO_PLL_To_384M();
GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1);
GLB_Set_MCU_System_CLK_Div(0, 3);
#endif
CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1);
}
static void peripheral_clock_init(void)
@ -110,7 +107,7 @@ static void psram_winbond_default_init(void)
.PASR = PSRAM_PARTIAL_REFRESH_FULL,
.disDeepPowerDownMode = ENABLE,
.fixedLatency = DISABLE,
.brustLen = PSRAM_WINBOND_BURST_LENGTH_32_BYTES,
.brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES,
.brustType = PSRAM_WRAPPED_BURST,
.latency = PSRAM_WINBOND_6_CLOCKS_LATENCY,
.driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M,
@ -152,7 +149,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -163,17 +160,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -204,31 +201,26 @@ static void console_init()
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
@ -237,6 +229,8 @@ void board_init(void)
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
rtc = bflb_device_get_by_name("rtc");
#endif
@ -245,6 +239,8 @@ void board_init(void)
board_psram_x8_init();
Tzc_Sec_PSRAMB_Access_Release();
#endif
bflb_irq_restore(flag);
}
void board_uartx_gpio_init()
@ -438,6 +434,17 @@ void board_dvp_gpio_init(void)
#endif
}
void board_i2s_gpio_init()
{
struct bflb_device_s *gpio;
gpio = bflb_device_get_by_name("gpio");
bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
}
void board_iso11898_gpio_init()
{
// struct bflb_device_s *gpio;
@ -495,3 +502,13 @@ __attribute__((weak)) uint32_t get_fattime(void)
| ((uint32_t)tm.sec >> 1); /* Sec 0 */
}
#endif
#ifdef CONFIG_SHELL
#include "shell.h"
static void reboot_cmd(int argc, char **argv)
{
GLB_SW_POR_Reset();
}
SHELL_CMD_EXPORT_ALIAS(reboot_cmd, reboot, reboot);
#endif

1
bsp/board/bl616dk/board.h
View File

@ -13,6 +13,7 @@ void board_emac_gpio_init();
void board_sdh_gpio_init();
void board_ir_gpio_init();
void board_dvp_gpio_init();
void board_i2s_gpio_init();
void board_iso11898_gpio_init();
#define DEFAULT_TEST_UART "uart1"

165
bsp/board/bl616dk/fw_header.c Normal file
View File

@ -0,0 +1,165 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x05, /*!< mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M */
.clk_cfg.cfg.mcu_clk_div = 0x00, /*!< mcu_clk divider */
.clk_cfg.cfg.mcu_bclk_div = 0x00, /*!< mcu_bclk divider */
.clk_cfg.cfg.mcu_pbclk_div = 0x03, /*!< mcu_pclk divider */
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01, /*!< emi clock divider */
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x00,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg.config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg.halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg.cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg.cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg.rsvd = 0x0,
/* image_address_offset */
.cpu_cfg.image_address_offset = 0x0,
.cpu_cfg.rsvd1 = 0xA0000000, /* rsvd */
.cpu_cfg.msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef
};

197
bsp/board/bl616dk/fw_header.h Normal file
View File

@ -0,0 +1,197 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t rsvd0;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd1; /* rsvd */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 12 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg; /* 16 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd; /* 4 */
uint32_t crc32; /* 4 */
};
#endif

3
bsp/board/bl702dk/CMakeLists.txt
View File

@ -1,9 +1,12 @@
sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c)
sdk_set_linker_script(bl702_flash.ld)
if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)
endif()
# sdk_add_link_options(-ufw_header)

10
bsp/board/bl702dk/bl702_flash.ld
View File

@ -21,6 +21,7 @@ StackSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 12K
dtcm_memory (rx) : ORIGIN = 0x42017000, LENGTH = 4K
@ -32,6 +33,11 @@ SECTIONS
{
PROVIDE(__metal_chicken_bit = 0);
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);
@ -183,6 +189,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory

154
bsp/board/bl702dk/board.c
View File

@ -3,28 +3,17 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "board.h"
#include "bflb_spi_psram.h"
#include "bl702_glb.h"
#include "bl702_sflash.h"
#include "bl702_psram.h"
#include "board.h"
#include "mem.h"
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if defined(CONFIG_BFLOG)
@ -51,7 +40,7 @@ static void peripheral_clock_init(void)
PERIPHERAL_CLOCK_IR_ENABLE();
PERIPHERAL_CLOCK_I2S_ENABLE();
PERIPHERAL_CLOCK_USB_ENABLE();
GLB_AHB_Slave1_Clock_Gate(DISABLE,BL_AHB_SLAVE1_CAM);
GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM);
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0);
GLB_Set_SPI_CLK(ENABLE, 0);
@ -66,45 +55,46 @@ static void peripheral_clock_init(void)
/* bsp sf psram private variables */
SPI_Psram_Cfg_Type apMemory1604 = {
.readIdCmd = 0x9F,
.readIdDmyClk = 0,
.burstToggleCmd = 0xC0,
.resetEnableCmd = 0x66,
.resetCmd = 0x99,
.enterQuadModeCmd = 0x35,
.exitQuadModeCmd = 0xF5,
.readRegCmd = 0xB5,
.readRegDmyClk = 1,
.writeRegCmd = 0xB1,
.readCmd = 0x03,
.readDmyClk = 0,
.fReadCmd = 0x0B,
.fReadDmyClk = 1,
.fReadQuadCmd = 0xEB,
.fReadQuadDmyClk = 3,
.writeCmd = 0x02,
.quadWriteCmd = 0x38,
.pageSize = 512,
.ctrlMode = PSRAM_SPI_CTRL_MODE,
.driveStrength = PSRAM_DRIVE_STRENGTH_50_OHMS,
.burstLength = PSRAM_BURST_LENGTH_512_BYTES,
struct spi_psram_cfg_type ap_memory1604 = {
.read_id_cmd = 0x9F,
.read_id_dmy_clk = 0,
.burst_toggle_cmd = 0xC0,
.reset_enable_cmd = 0x66,
.reset_cmd = 0x99,
.enter_quad_mode_cmd = 0x35,
.exit_quad_mode_cmd = 0xF5,
.read_reg_cmd = 0xB5,
.read_reg_dmy_clk = 1,
.write_reg_cmd = 0xB1,
.read_cmd = 0x03,
.read_dmy_clk = 0,
.f_read_cmd = 0x0B,
.f_read_dmy_clk = 1,
.f_read_quad_cmd = 0xEB,
.f_read_quad_dmy_clk = 3,
.write_cmd = 0x02,
.quad_write_cmd = 0x38,
.page_size = 512,
.ctrl_mode = PSRAM_SPI_CTRL_MODE,
.drive_strength = PSRAM_DRIVE_STRENGTH_50_OHMS,
.burst_length = PSRAM_BURST_LENGTH_512_BYTES,
};
SF_Ctrl_Cmds_Cfg cmdsCfg = {
.cmdsEn = ENABLE,
.burstToggleEn = ENABLE,
.wrapModeEn = DISABLE,
.wrapLen = SF_CTRL_WRAP_LEN_512,
struct sf_ctrl_cmds_cfg cmds_cfg = {
.cmds_core_en = 1,
.cmds_en = 1,
.burst_toggle_en = 1,
.cmds_wrap_mode = 0,
.cmds_wrap_len = SF_CTRL_WRAP_LEN_512,
};
SF_Ctrl_Psram_Cfg sfCtrlPsramCfg = {
struct sf_ctrl_psram_cfg psram_cfg = {
.owner = SF_CTRL_OWNER_SAHB,
.padSel = SF_CTRL_PAD_SEL_DUAL_CS_SF2,
.bankSel = SF_CTRL_SEL_PSRAM,
.psramRxClkInvertSrc = ENABLE,
.psramRxClkInvertSel = DISABLE,
.psramDelaySrc = ENABLE,
.psramClkDelay = 1,
.pad_sel = SF_CTRL_SEL_DUAL_CS_SF2,
.bank_sel = SF_CTRL_SEL_PSRAM,
.psram_rx_clk_invert_src = 1,
.psram_rx_clk_invert_sel = 0,
.psram_delay_src = 1,
.psram_clk_delay = 1,
};
#define BFLB_EXTFLASH_CS_GPIO GLB_GPIO_PIN_25
@ -156,12 +146,12 @@ void ATTR_TCM_SECTION board_psram_init(void)
{
psram_gpio_init();
Psram_Init(&apMemory1604, &cmdsCfg, &sfCtrlPsramCfg);
bflb_psram_init(&ap_memory1604, &cmds_cfg, &psram_cfg);
Psram_SoftwareReset(&apMemory1604, apMemory1604.ctrlMode);
bflb_psram_softwarereset(&ap_memory1604, ap_memory1604.ctrl_mode);
Psram_ReadId(&apMemory1604, psramId);
Psram_Cache_Write_Set(&apMemory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE);
bflb_psram_readid(&ap_memory1604, psramId);
bflb_psram_cache_write_set(&ap_memory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE);
L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE);
}
@ -181,7 +171,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -192,17 +182,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -233,43 +223,41 @@ static void console_init()
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
#if defined(CONFIG_BFLOG)
rtc = bflb_device_get_by_name("rtc");
#endif
#ifdef CONFIG_PSRAM
board_psram_init();
#endif
bflb_irq_restore(flag);
}
void board_uartx_gpio_init()

122
bsp/board/bl702dk/fw_header.c Normal file
View File

@ -0,0 +1,122 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x01, /*!< 0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M */
.clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M */
.clk_cfg.cfg.hclk_div = 0x00,
.clk_cfg.cfg.bclk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.crc32 = 0xdeadbeef,
/* boot cfg */
.boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/
.boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */
.boot_cfg.bval.key_sel = 0x01, /* [5: 4] for key sel in boot interface*/
.boot_cfg.bval.rsvd_7_6 = 0x0, /* [7: 6] for encrypt*/
.boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */
.boot_cfg.bval.cache_select = 0x1, /* [9] for cache */
.boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */
.boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */
.boot_cfg.bval.cache_way_disable = 0x0, /* [15: 12] cache way disable info*/
.boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */
.boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */
.boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */
.boot_cfg.bval.boot2_enable = 0x00, /* [19] boot2 enable */
.boot_cfg.bval.boot2_rollback = 0x00, /* [20] boot2 rollback */
.boot_cfg.bval.rsvd_31_21 = 0x0, /* [31:21] rsvd */
.img_segment_info.img_len = 0x00010000, /* image length or segment count */
.rsvd0 = 0x00000000,
.img_start.flashoffset = 0x00001000, /* flash controller offset */
.hash = { 0xdeadbeef }, /* hash of the image */
.boot2_pt_table_0 = 0x1000, /* address of partition table 0 */
.boot2_pt_table_1 = 0x2000, /* address of partition table 1 */
.crc32 = 0xdeadbeef /* 4 */
};

167
bsp/board/bl702dk/fw_header.h Normal file
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@ -0,0 +1,167 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t pll_clk;
uint8_t hclk_div;
uint8_t bclk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t rsvd[2];
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /*'BFXP'*/
uint32_t rivison;
struct boot_flash_cfg_t flash_cfg;
struct boot_clk_cfg_t clk_cfg;
union __attribute__((packed, aligned(1))) {
struct __attribute__((packed, aligned(1))) {
uint32_t sign : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface */
uint32_t rsvd_7_6 : 2; /* [7: 6] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t cache_select : 1; /* [9] cache enable */
uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */
uint32_t aes_region_lock : 1; /* [11] aes region lock */
uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] ignore hash */
uint32_t halt_ap : 1; /* [18] halt ap */
uint32_t boot2_enable : 1; /* [19] boot2 enable */
uint32_t boot2_rollback : 1; /* [20] boot2 rollback */
uint32_t rsvd_31_21 : 11; /* [31: 21] rsvd */
} bval;
uint32_t wval;
} boot_cfg;
union __attribute__((packed, aligned(1))) {
uint32_t segment_cnt;
uint32_t img_len;
} img_segment_info;
uint32_t rsvd0; /* rsvd */
union __attribute__((packed, aligned(1))) {
uint32_t ramaddr;
uint32_t flashoffset;
} img_start;
uint32_t hash[32 / 4]; /*hash of the image*/
uint32_t boot2_pt_table_0; /* address of partition table 0 */
uint32_t boot2_pt_table_1; /* address of partition table 1 */
uint32_t crc32;
};
#endif

11
bsp/board/bl808dk/CMakeLists.txt
View File

@ -2,7 +2,16 @@ sdk_add_include_directories(.)
target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c)
sdk_set_linker_script(bl808_flash_${CPU_ID}.ld)
if(CONFIG_IOT)
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/iot/fw_header.c)
sdk_set_linker_script(iot/bl808_flash_${CPU_ID}.ld)
# sdk_add_link_options(-ufw_header)
else()
# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/mcu/fw_header.c)
sdk_set_linker_script(mcu/bl808_flash_${CPU_ID}.ld)
# sdk_add_link_options(-ufw_header0)
# sdk_add_link_options(-ufw_header1)
endif()
if(CONFIG_PSRAM)
sdk_add_compile_definitions(-DCONFIG_PSRAM)

158
bsp/board/bl808dk/board.c
View File

@ -3,35 +3,24 @@
#include "bflb_clock.h"
#include "bflb_rtc.h"
#include "bflb_flash.h"
#ifdef CONFIG_TLSF
#include "bflb_tlsf.h"
#else
#include "bflb_mmheap.h"
#endif
#include "bl808_glb.h"
#include "bl808_sflash.h"
#include "bl808_psram_uhs.h"
#include "bl808_tzc_sec.h"
#include "bl808_ef_cfg.h"
#include "bl808_uhs_phy.h"
#include "board.h"
#include "mem.h"
#ifdef CONFIG_BSP_SDH_SDCARD
#include "sdh_sdcard.h"
#endif
extern void log_start(void);
extern uint32_t __HeapBase;
extern uint32_t __HeapLimit;
#ifndef CONFIG_TLSF
struct heap_info mmheap_root;
static struct heap_region system_mmheap[] = {
{ NULL, 0 },
{ NULL, 0 }, /* Terminates the array. */
};
#endif
static struct bflb_device_s *uart0;
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
@ -94,13 +83,12 @@ static void peripheral_clock_init(void)
BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val);
GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH);
#endif
GLB_Set_USB_CLK_From_WIFIPLL(1);
#ifdef CONFIG_BSP_CSI
GLB_CSI_Config_MIPIPLL(2, 0x21000);
GLB_CSI_Power_Up_MIPIPLL();
GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1);
#endif
GLB_Set_USB_CLK_From_WIFIPLL(1);
}
#ifdef CONFIG_PSRAM
@ -175,7 +163,7 @@ void bl_show_log(void)
void bl_show_flashinfo(void)
{
SPI_Flash_Cfg_Type flashCfg;
spi_flash_cfg_type flashCfg;
uint8_t *pFlashCfg = NULL;
uint32_t flashCfgLen = 0;
uint32_t flashJedecId = 0;
@ -186,17 +174,17 @@ void bl_show_flashinfo(void)
printf("=========== flash cfg ==============\r\n");
printf("jedec id 0x%06X\r\n", flashJedecId);
printf("mid 0x%02X\r\n", flashCfg.mid);
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
printf("iomode 0x%02X\r\n", flashCfg.io_mode);
printf("clk delay 0x%02X\r\n", flashCfg.clk_delay);
printf("clk invert 0x%02X\r\n", flashCfg.clk_invert);
printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]);
printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]);
printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]);
printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]);
printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len);
printf("cread support 0x%02X\r\n", flashCfg.c_read_support);
printf("cread code 0x%02X\r\n", flashCfg.c_read_mode);
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd);
printf("=====================================\r\n");
}
@ -211,8 +199,9 @@ static void console_init()
bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX);
bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX);
#elif defined(CPU_D0)
bflb_gpio_init(gpio, GPIO_PIN_8, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
//bflb_gpio_init(gpio, GPIO_PIN_9, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* sipeed m1s dock */
bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
#endif
struct bflb_uart_config_s cfg;
cfg.baudrate = 2000000;
@ -234,50 +223,37 @@ static void console_init()
#if defined(CPU_M0)
void board_init(void)
{
int ret = -1;
uintptr_t flag;
flag = bflb_irq_save();
bflb_flash_init();
ret = bflb_flash_init();
GLB_Halt_CPU(GLB_CORE_ID_D0);
GLB_Halt_CPU(GLB_CORE_ID_LP);
system_clock_init();
peripheral_clock_init();
bflb_irq_initialize();
GLB_Release_CPU(GLB_CORE_ID_D0);
GLB_Release_CPU(GLB_CORE_ID_LP);
bflb_irq_restore(flag);
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
console_init();
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
bl_show_log();
if (ret != 0) {
printf("flash init fail!!!\r\n");
}
bl_show_flashinfo();
#ifdef CONFIG_TLSF
bflb_tlsf_size_container_t *tlsf_size = bflb_tlsf_stats();
printf("TLSF Dynamic Memory Init Success: Heap Size = %d Kbyte, Used Size = %d Kbyte, Free Size = %d Kbyte\r\n",
tlsf_size->free + tlsf_size->used / 1024, tlsf_size->used / 1024, tlsf_size->free / 1024);
#else
printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024);
#endif
printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024);
printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
log_start();
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
rtc = bflb_device_get_by_name("rtc");
#endif
@ -288,6 +264,18 @@ void board_init(void)
}
}
#endif
/* set CPU D0 boot XIP address and flash address */
// Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
// /* D0 boot from 0x58000000 */
// GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
// /* D0 image offset on flash is 0x100000+0x1000(header) */
// bflb_sf_ctrl_set_flash_image_offset(0x101000, 1, SF_CTRL_FLASH_BANK0);
bflb_irq_restore(flag);
/* we do not check header at 0x10000, just boot */
GLB_Release_CPU(GLB_CORE_ID_D0);
/* release d0 and then do can run */
BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
@ -300,16 +288,8 @@ void board_init(void)
bflb_irq_initialize();
#ifdef CONFIG_TLSF
bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase));
#else
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
if (system_mmheap[0].mem_size > 0) {
bflb_mmheap_init(&mmheap_root, system_mmheap);
}
#endif
size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
kmem_init((void *)&__HeapBase, heap_len);
console_init();
@ -320,6 +300,8 @@ void board_init(void)
printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE));
log_start();
}
#endif
@ -502,25 +484,43 @@ void board_csi_gpio_init(void)
gpio = bflb_device_get_by_name("gpio");
GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V);
#if 1 /* sipeed m1s dock */
/* I2C GPIO */
bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* Power down GPIO */
bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_set(gpio, GPIO_PIN_22);
/* Reset GPIO */
bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_set(gpio, GPIO_PIN_21);
bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* MCLK GPIO */
bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V);
/* Power down GPIO */
bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_reset(gpio, GPIO_PIN_40);
/* Reset GPIO */
bflb_gpio_init(gpio, GPIO_PIN_41, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_mtimer_delay_us(20);
bflb_gpio_set(gpio, GPIO_PIN_41);
#else
/* I2C GPIO */
bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* MCLK GPIO */
bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
/* Power down GPIO */
bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_gpio_reset(gpio, GPIO_PIN_6);
/* Reset GPIO */
bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
bflb_mtimer_delay_us(20);
bflb_gpio_set(gpio, GPIO_PIN_23);
#endif
}
void board_iso11898_gpio_init(void)
void board_iso11898_gpio_init()
{
// struct bflb_device_s *gpio;

266
bsp/board/bl808dk/iot/bl808_flash_d0.ld Normal file
View File

@ -0,0 +1,266 @@
/****************************************************************************************
* @file flash.ld
*
* @brief This file is the link script file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x0400; /* 1KB */
HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K
dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K
ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 32K + 32K
xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
}
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
*(.text)
*(.text.*)
/* section information for shell */
. = ALIGN(8);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/*put .rodata**/
*(EXCLUDE_FILE( *bl808_glb*.o* \
*bl808_glb_gpio*.o* \
*bl808_pds*.o* \
*bl808_aon*.o* \
*bl808_hbn*.o* \
*bl808_l1c*.o* \
*bl808_common*.o* \
*bl808_clock*.o* \
*bl808_ef_ctrl*.o* \
*bl808_sf_cfg*.o* \
*bl808_sf_ctrl*.o* \
*bl808_sflash*.o* \
*bl808_xip_sflash*.o* \
*bl808_romapi_patch*.o* ) .rodata*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl808_glb*.o*(.rodata*)
*bl808_glb_gpio*.o*(.rodata*)
*bl808_pds*.o*(.rodata*)
*bl808_aon*.o*(.rodata*)
*bl808_hbn*.o*(.rodata*)
*bl808_l1c*.o*(.rodata*)
*bl808_common*.o*(.rodata*)
*bl808_clock*.o*(.rodata*)
*bl808_ef_ctrl*.o*(.rodata*)
*bl808_sf_cfg*.o*(.rodata*)
*bl808_sf_ctrl*.o*(.rodata*)
*bl808_sflash*.o*(.rodata*)
*bl808_xip_sflash*.o*(.rodata*)
*bl808_romapi_patch*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_noinit_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
}

9
bsp/board/bl808dk/bl808_flash_m0.ld → bsp/board/bl808dk/iot/bl808_flash_m0.ld
View File

@ -22,6 +22,7 @@ HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K
@ -32,6 +33,10 @@ MEMORY
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header))
} > fw_header_memory
.text :
{
@ -202,6 +207,10 @@ SECTIONS
*(.sdata2.*)
. = ALIGN(4);
__bflog_tags_start__ = .;
*(.bflog_tags_array)
. = ALIGN(4);
__bflog_tags_end__ = .;
__ram_data_end__ = .;
} > ram_memory

199
bsp/board/bl808dk/iot/fw_header.c Normal file
View File

@ -0,0 +1,199 @@
#include "fw_header.h"
__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef /* 4 */
};

210
bsp/board/bl808dk/iot/fw_header.h Normal file
View File

@ -0,0 +1,210 @@
#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t lp_div;
uint8_t dsp_clk;
uint8_t dsp_clk_div;
uint8_t dsp_bclk_div;
uint8_t dsp_pbclk;
uint8_t dsp_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t cpupll_pu;
uint8_t mipipll_pu;
uint8_t uhspll_pu;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t cache_range_h; /* cache range high */
uint32_t cache_range_l; /* cache range low */
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd0; /* rsvd0 */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd3[5]; /* 4 */
uint32_t crc32; /* 4 */
};
#endif

5
bsp/board/bl808dk/bl808_flash_d0.ld → bsp/board/bl808dk/mcu/bl808_flash_d0.ld
View File

@ -22,6 +22,7 @@ HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K
dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K
@ -32,6 +33,10 @@ MEMORY
SECTIONS
{
.fw_header :
{
KEEP(*(.fw_header0))
} > fw_header_memory
.text :
{

314
bsp/board/bl808dk/mcu/bl808_flash_m0.ld Normal file
View File

@ -0,0 +1,314 @@
/****************************************************************************************
* @file flash.ld
*
* @brief This file is the link script file (gnuarm or armgcc).
*
* Copyright (C) BouffaloLab 2021
*
****************************************************************************************
*/
/* configure the CPU type */
OUTPUT_ARCH( "riscv" )
/* link with the standard c library */
INPUT(-lc)
/* link with the standard GCC library */
INPUT(-lgcc)
/* configure the entry point */
ENTRY(__start)
StackSize = 0x0400; /* 1KB */
HeapMinSize = 0x1000; /* 4KB */
MEMORY
{
fw_header_memory0 (rx) : ORIGIN = 0x58000000 - 0x2000, LENGTH = 4K
fw_header_memory1 (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K
dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K
nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K
ram_memory (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K
xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
}
SECTIONS
{
.fw_header0 :
{
KEEP(*(.fw_header0))
} > fw_header_memory0
.fw_header1 :
{
KEEP(*(.fw_header1))
} > fw_header_memory1
.text :
{
. = ALIGN(4);
__text_code_start__ = .;
KEEP (*(SORT_NONE(.init)))
KEEP (*(SORT_NONE(.vector)))
*(.text)
*(.text.*)
/* section information for shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
/* section information for usb usbh_class_info */
. = ALIGN(4);
__usbh_class_info_start__ = .;
KEEP(*(.usbh_class_info))
. = ALIGN(4);
__usbh_class_info_end__ = .;
/*put .rodata**/
*(EXCLUDE_FILE( *bl808_glb*.o* \
*bl808_glb_gpio*.o* \
*bl808_pds*.o* \
*bl808_aon*.o* \
*bl808_hbn*.o* \
*bl808_l1c*.o* \
*bl808_common*.o* \
*bl808_clock*.o* \
*bl808_ef_ctrl*.o* \
*bl808_sf_cfg*.o* \
*bl808_sf_ctrl*.o* \
*bl808_sflash*.o* \
*bl808_xip_sflash*.o* \
*bl808_romapi_patch*.o* ) .rodata*)
*(.srodata)
*(.srodata.*)
. = ALIGN(4);
__text_code_end__ = .;
} > xip_memory
. = ALIGN(4);
__itcm_load_addr = .;
.itcm_region : AT (__itcm_load_addr)
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl808_glb*.o*(.rodata*)
*bl808_glb_gpio*.o*(.rodata*)
*bl808_pds*.o*(.rodata*)
*bl808_aon*.o*(.rodata*)
*bl808_hbn*.o*(.rodata*)
*bl808_l1c*.o*(.rodata*)
*bl808_common*.o*(.rodata*)
*bl808_clock*.o*(.rodata*)
*bl808_ef_ctrl*.o*(.rodata*)
*bl808_sf_cfg*.o*(.rodata*)
*bl808_sf_ctrl*.o*(.rodata*)
*bl808_sflash*.o*(.rodata*)
*bl808_xip_sflash*.o*(.rodata*)
*bl808_romapi_patch*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
} > itcm_memory
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
.dtcm_region : AT (__dtcm_load_addr)
{
. = ALIGN(4);
__tcm_data_start__ = .;
*(.tcm_data)
/* *finger_print.o(.data*) */
. = ALIGN(4);
__tcm_data_end__ = .;
} > dtcm_memory
/*************************************************************************/
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (NOLOAD):
{
. = ALIGN(0x4);
. = . + StackSize;
. = ALIGN(0x4);
} > dtcm_memory
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
PROVIDE( __freertos_irq_stack_top = __StackTop);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
/*************************************************************************/
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
.nocache_ram_region : AT (__nocache_ram_load_addr)
{
. = ALIGN(4);
__nocache_ram_data_start__ = .;
*(.nocache_ram)
. = ALIGN(4);
__nocache_ram_data_end__ = .;
} > nocache_ram_memory
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
.system_ram_data_region : AT (__system_ram_load_addr)
{
. = ALIGN(4);
__system_ram_data_start__ = .;
*(.system_ram)
. = ALIGN(4);
__system_ram_data_end__ = .;
} > ram_memory
.system_ram_noinit_data_region (NOLOAD) :
{
. = ALIGN(4);
*(.system_ram_noinit)
. = ALIGN(4);
} > ram_memory
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
/* Data section */
RAM_DATA : AT (__ram_load_addr)
{
. = ALIGN(4);
__ram_data_start__ = .;
PROVIDE( __global_pointer$ = . + 0x800 );
*(.data)
*(.data.*)
*(.sdata)
*(.sdata.*)
*(.sdata2)
*(.sdata2.*)
. = ALIGN(4);
__ram_data_end__ = .;
} > ram_memory
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
.bss (NOLOAD) :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(.sbss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > ram_memory
.noinit_data (NOLOAD) :
{
. = ALIGN(4);
__noinit_data_start__ = .;
*(.noinit_data*)
. = ALIGN(4);
__noinit_data_end__ = .;
} > ram_memory
.nocache_noinit_ram_region (NOLOAD) :
{
. = ALIGN(4);
__nocache_noinit_ram_data_start__ = .;
*(.nocache_noinit_ram)
*(.noncacheable)
. = ALIGN(4);
__nocache_noinit_ram_data_end__ = .;
} > nocache_ram_memory
.heap (NOLOAD):
{
. = ALIGN(4);
__HeapBase = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.heap*))
. = ALIGN(4);
__HeapLimit = .;
} > ram_memory
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
.psmram_data (NOLOAD):
{
. = ALIGN(4);
__psram_data_start__ = .;
/*__end__ = .;*/
/*end = __end__;*/
KEEP(*(.psram_data*))
. = ALIGN(4);
__psram_data_end__ = .;
} > ram_code
.wifibss (NOLOAD) :
{
PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
_sshram = . ;
*(SHAREDRAMIPC)
*(SHAREDRAM)
_eshram = . ;
*ipc_shared.o(COMMON)
*sdu_shared.o(COMMON)
*hal_desc.o(COMMON)
*txl_buffer_shared.o(COMMON)
*txl_frame_shared.o(COMMON)
*scan_shared.o(COMMON)
*scanu_shared.o(COMMON)
*mfp_bip.o(COMMON)
*me_mic.o(COMMON)
*(.wifi_ram*)
. = ALIGN(16);
} > ram_wifi
PROVIDE( _heap_wifi_start = . );
PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
}

403
bsp/board/bl808dk/mcu/fw_header.c Normal file
View File

@ -0,0 +1,403 @@
#include "fw_header.h"
__attribute__((section(".fw_header0"))) struct bootheader_t fw_header0 = {
.magiccode = 0x504e4642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x00, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.rsvd1[0] = 0x20000320,
.rsvd1[1] = 0x00000000,
.rsvd1[2] = 0x2000F038,
.rsvd1[3] = 0x18000000,
.crc32 = 0xdeadbeef /* 4 */
};
__attribute__((section(".fw_header1"))) struct bootheader_t fw_header1 = {
.magiccode = 0x50414642,
.rivison = 0x00000001,
/*flash config */
.flash_cfg.magiccode = 0x47464346,
.flash_cfg.cfg.ioMode = 0x10, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
.flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
.flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
.flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
.flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */
.flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */
.flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */
.flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */
.flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */
.flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */
.flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */
.flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */
.flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */
.flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */
.flash_cfg.cfg.pageSize = 0x100, /*!< Page size */
.flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */
.flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */
.flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */
.flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */
.flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */
.flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */
.flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */
.flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */
.flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */
.flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */
.flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */
.flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */
.flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */
.flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */
.flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */
.flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */
.flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */
.flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */
.flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */
.flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */
.flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */
.flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */
.flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */
.flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */
.flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */
.flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */
.flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */
.flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */
.flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */
.flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */
.flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */
.flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */
.flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */
.flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */
.flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */
.flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */
.flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */
.flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */
.flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */
.flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */
.flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */
.flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */
.flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */
.flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */
.flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */
.flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */
.flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
.flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */
.flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */
.flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */
.flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */
.flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */
.flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */
.flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */
.flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */
.flash_cfg.cfg.qeData = 0, /*!< QE set data */
.flash_cfg.crc32 = 0xdeadbeef,
/* clock cfg */
.clk_cfg.magiccode = 0x47464350,
.clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */
.clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
.clk_cfg.cfg.mcu_clk_div = 0x00,
.clk_cfg.cfg.mcu_bclk_div = 0x00,
.clk_cfg.cfg.mcu_pbclk_div = 0x03,
.clk_cfg.cfg.lp_div = 0x01,
.clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
.clk_cfg.cfg.dsp_clk_div = 0x00,
.clk_cfg.cfg.dsp_bclk_div = 0x01,
.clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
.clk_cfg.cfg.dsp_pbclk_div = 0x00,
.clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
.clk_cfg.cfg.emi_clk_div = 0x01,
.clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
.clk_cfg.cfg.flash_clk_div = 0x00,
.clk_cfg.cfg.wifipll_pu = 0x01,
.clk_cfg.cfg.aupll_pu = 0x01,
.clk_cfg.cfg.cpupll_pu = 0x01,
.clk_cfg.cfg.mipipll_pu = 0x01,
.clk_cfg.cfg.uhspll_pu = 0x01,
.clk_cfg.crc32 = 0xdeadbeef,
/* basic cfg */
.basic_cfg.sign_type = 0x0, /* [1: 0] for sign */
.basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */
.basic_cfg.key_sel = 0x0, /* [5: 4] key slot */
.basic_cfg.xts_mode = 0x0, /* [6] for xts mode */
.basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */
.basic_cfg.no_segment = 0x1, /* [8] no segment info */
.basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */
.basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */
.basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */
.basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */
.basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */
.basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */
.basic_cfg.power_on_mm = 0x1, /* [18] power on mm */
.basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */
.basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */
#if 0
# 0 : cmds bypass wrap commands to macro, original mode;
# 1 : cmds handle wrap commands, original mode;
# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
#endif
.basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
#if 0
# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
#endif
.basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */
.basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
.basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
.basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */
.basic_cfg.group_image_offset = 0x00011000, /* flash controller offset */
.basic_cfg.aes_region_len = 0x00000000, /* aes region length */
.basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */
.basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */
/* cpu cfg */
.cpu_cfg[0].config_enable = 0x00, /* coinfig this cpu */
.cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[0].rsvd = 0x0,
.cpu_cfg[0].cache_range_h = 0x00000000,
.cpu_cfg[0].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[0].image_address_offset = 0x0,
.cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[0].msp_val = 0x00000000, /* msp value */
/* cpu cfg */
.cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */
.cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */
.cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */
.cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
.cpu_cfg[1].rsvd = 0x0,
.cpu_cfg[1].cache_range_h = 0x00000000,
.cpu_cfg[1].cache_range_l = 0x00000000,
/* image_address_offset */
.cpu_cfg[1].image_address_offset = 0x0,
.cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */
.cpu_cfg[1].msp_val = 0x00000000, /* msp value */
/* address of partition table 0 */ /* 4 */
.boot2_pt_table_0_rsvd = 0x00000000,
/* address of partition table 1 */ /* 4 */
.boot2_pt_table_1_rsvd = 0x00000000,
/* address of flashcfg table list */ /* 4 */
.flash_cfg_table_addr = 0x00000000,
/* flashcfg table list len */ /* 4 */
.flash_cfg_table_len = 0x00000000,
.crc32 = 0xdeadbeef /* 4 */
};

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bsp/board/bl808dk/mcu/fw_header.h Normal file
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#ifndef __FW_HEADER_H__
#define __FW_HEADER_H__
#include "stdint.h"
#include "stdio.h"
struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */
uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
};
struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
uint32_t magiccode;
struct spi_flash_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
uint8_t xtal_type;
uint8_t mcu_clk;
uint8_t mcu_clk_div;
uint8_t mcu_bclk_div;
uint8_t mcu_pbclk_div;
uint8_t lp_div;
uint8_t dsp_clk;
uint8_t dsp_clk_div;
uint8_t dsp_bclk_div;
uint8_t dsp_pbclk;
uint8_t dsp_pbclk_div;
uint8_t emi_clk;
uint8_t emi_clk_div;
uint8_t flash_clk_type;
uint8_t flash_clk_div;
uint8_t wifipll_pu;
uint8_t aupll_pu;
uint8_t cpupll_pu;
uint8_t mipipll_pu;
uint8_t uhspll_pu;
};
struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
uint32_t magiccode;
struct sys_clk_cfg_t cfg;
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
uint32_t sign_type : 2; /* [1: 0] for sign */
uint32_t encrypt_type : 2; /* [3: 2] for encrypt */
uint32_t key_sel : 2; /* [5: 4] key slot */
uint32_t xts_mode : 1; /* [6] for xts mode */
uint32_t aes_region_lock : 1; /* [7] rsvd */
uint32_t no_segment : 1; /* [8] no segment info */
uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */
uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */
uint32_t cpu_master_id : 4; /* [14: 11] master id */
uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */
uint32_t crc_ignore : 1; /* [16] ignore crc */
uint32_t hash_ignore : 1; /* [17] hash ignore */
uint32_t power_on_mm : 1; /* [18] power on mm */
uint32_t em_sel : 3; /* [21: 19] em_sel */
uint32_t cmds_en : 1; /* [22] command spliter enable */
uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */
uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */
uint32_t icache_invalid : 1; /* [29] icache invalid */
uint32_t dcache_invalid : 1; /* [30] dcache invalid */
uint32_t rsvd_3 : 1; /* [31] rsvd_3 */
uint32_t group_image_offset; /* flash controller offset */
uint32_t aes_region_len; /* aes region length */
uint32_t img_len_cnt; /* image length or segment count */
uint32_t hash[32 / 4]; /* hash of the image */
};
struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
uint8_t config_enable; /* coinfig this cpu */
uint8_t halt_cpu; /* halt this cpu */
uint8_t cache_enable : 1; /* cache setting */
uint8_t cache_wa : 1; /* cache setting */
uint8_t cache_wb : 1; /* cache setting */
uint8_t cache_wt : 1; /* cache setting */
uint8_t cache_way_dis : 4; /* cache setting */
uint8_t rsvd;
uint32_t cache_range_h; /* cache range high */
uint32_t cache_range_l; /* cache range low */
uint32_t image_address_offset; /* image_address_offset */
uint32_t rsvd0; /* rsvd0 */
uint32_t msp_val; /* msp value */
};
struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
uint8_t aesiv[16];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) pkey_cfg_t {
uint8_t eckeyx[32]; /* ec key in boot header */
uint8_t eckeyy[32]; /* ec key in boot header */
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) sign_cfg_t {
uint32_t sig_len;
uint8_t signature[32];
uint32_t crc32;
};
struct __attribute__((packed, aligned(4))) bootheader_t {
uint32_t magiccode; /* 4 */
uint32_t rivison; /* 4 */
struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */
struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */
uint32_t rsvd0[6]; /* rsvd */
uint32_t rsvd1[6]; /* rsvd */
uint32_t rsvd3[5]; /* 4 */
uint32_t crc32; /* 4 */
};
#endif

12
bsp/common/CMakeLists.txt
View File

@ -23,6 +23,7 @@ endif()
if(CONFIG_BSP_LCD)
target_sources(app PRIVATE lcd/lcd.c)
target_sources(app PRIVATE lcd/font.c)
target_sources(app PRIVATE lcd/spi/ili9341_spi.c)
target_sources(app PRIVATE lcd/spi/ili9488_spi.c)
target_sources(app PRIVATE lcd/spi/st7796_spi.c)
@ -30,8 +31,19 @@ target_sources(app PRIVATE lcd/spi/st7789v_spi.c)
sdk_add_include_directories(lcd)
endif()
# touch sensor driver
if(CONFIG_BSP_TOUCH)
target_sources(app PRIVATE touch/touch.c)
target_sources(app PRIVATE touch/ft6x36_i2c.c)
target_sources(app PRIVATE touch/gt911_i2c.c)
sdk_add_include_directories(touch)
endif()
# image sensor driver
if(CONFIG_BSP_IMAGE_SENSOR)
target_sources(app PRIVATE image_sensor/image_sensor.c)
sdk_add_include_directories(image_sensor)
if(CONFIG_BSP_CSI)
sdk_add_compile_definitions(-DCONFIG_BSP_CSI)
endif()
endif()

166
bsp/common/image_sensor/gc2053.h
View File

@ -26,6 +26,165 @@
#include "image_sensor.h"
static struct image_sensor_command_s gc2053_init_list[] = {
#ifdef CONFIG_BSP_CSI
{ 0xfe, 0x80 },
{ 0xfe, 0x80 },
{ 0xfe, 0x80 },
{ 0xfe, 0x00 },
{ 0xf2, 0x00 },
{ 0xf3, 0x00 },
{ 0xf4, 0x36 },
{ 0xf5, 0xc0 },
{ 0xf6, 0x84 },
{ 0xf7, 0x11 },
{ 0xf8, 0x37 },
{ 0xf9, 0x82 },
{ 0xfc, 0x8e },
{ 0xfe, 0x00 },//mirror and flip
{ 0x17, 0x83 },
{ 0xfe, 0x00 },
{ 0x87, 0x18 },
{ 0xee, 0x30 },
{ 0xd0, 0xb7 },
{ 0x03, 0x04 },
{ 0x04, 0x60 },
{ 0x05, 0x04 },
{ 0x06, 0x4c },
{ 0x07, 0x00 },
{ 0x08, 0x64 },
{ 0x09, 0x00 },
{ 0x0a, 0x02 },
{ 0x0b, 0x00 },
{ 0x0c, 0x02 },
{ 0x0d, 0x04 },
{ 0x0e, 0x40 },
{ 0x12, 0xe2 },
{ 0x13, 0x16 },
{ 0x19, 0x0a },
{ 0x21, 0x1c },
{ 0x28, 0x0a },
{ 0x29, 0x24 },
{ 0x2b, 0x04 },
{ 0x32, 0xf8 },
{ 0x37, 0x03 },
{ 0x39, 0x15 },
{ 0x43, 0x07 },
{ 0x44, 0x40 },
{ 0x46, 0x0b },
{ 0x4b, 0x20 },
{ 0x4e, 0x08 },
{ 0x55, 0x20 },
{ 0x66, 0x05 },
{ 0x67, 0x05 },
{ 0x77, 0x01 },
{ 0x78, 0x00 },
{ 0x7c, 0x93 },
{ 0x8c, 0x12 },
{ 0x8d, 0x92 },
{ 0x90, 0x00 },
{ 0x41, 0x04 },
{ 0x42, 0xb0 },
{ 0x9d, 0x10 },
{ 0xce, 0x7c },
{ 0xd2, 0x41 },
{ 0xd3, 0xdc },
{ 0xe6, 0x50 },
{ 0xb6, 0xc0 },
{ 0xb0, 0x70 },
{ 0xb1, 0x01 },
{ 0xb2, 0x00 },
{ 0xb3, 0x00 },
{ 0xb4, 0x00 },
{ 0xb8, 0x01 },
{ 0xb9, 0x00 },
{ 0x26, 0x30 },
{ 0xfe, 0x01 },
{ 0x40, 0x23 },
{ 0x55, 0x07 },
{ 0x60, 0x40 },
{ 0xfe, 0x04 },
{ 0x14, 0x78 },
{ 0x15, 0x78 },
{ 0x16, 0x78 },
{ 0x17, 0x78 },
{ 0xfe, 0x01 },
{ 0x92, 0x01 },
{ 0x94, 0x04 },
{ 0x95, 0x04 },
{ 0x96, 0x38 },
{ 0x97, 0x07 },
{ 0x98, 0x80 },
/*skip frame*/
{ 0xfe, 0x01 },
{ 0x83, 0x01 },
{ 0x87, 0x50 },//0x50, skip 0, default:0x53,skip 3
{ 0xfe, 0x00 },
{ 0xfe, 0x01 },
{ 0x01, 0x05 },
{ 0x02, 0x89 },
{ 0x04, 0x00 },//DD_en
{ 0x07, 0xa6 },
{ 0x08, 0xa9 },
{ 0x09, 0xa8 },
{ 0x0a, 0xa7 },
{ 0x0b, 0xff },
{ 0x0c, 0xff },
{ 0x0f, 0x00 },
{ 0x50, 0x1c },
{ 0x89, 0x03 },
{ 0xfe, 0x04 },
{ 0x28, 0x86 },
{ 0x29, 0x86 },
{ 0x2a, 0x86 },
{ 0x2b, 0x68 },
{ 0x2c, 0x68 },
{ 0x2d, 0x68 },
{ 0x2e, 0x68 },
{ 0x2f, 0x68 },
{ 0x30, 0x4f },
{ 0x31, 0x68 },
{ 0x32, 0x67 },
{ 0x33, 0x66 },
{ 0x34, 0x66 },
{ 0x35, 0x66 },
{ 0x36, 0x66 },
{ 0x37, 0x66 },
{ 0x38, 0x62 },
{ 0x39, 0x62 },
{ 0x3a, 0x62 },
{ 0x3b, 0x62 },
{ 0x3c, 0x62 },
{ 0x3d, 0x62 },
{ 0x3e, 0x62 },
{ 0x3f, 0x62 },
{ 0xfe, 0x01 },
//{ 0x8c, 0x01 }, // test mode
{ 0x9a, 0x06 },
{ 0xfe, 0x00 },
{ 0x7b, 0x2a },
//{ 0x22, 0x0a }, // jz tmp
{ 0x23, 0x2d },
{ 0xfe, 0x03 },
{ 0x01, 0x27 },
{ 0x02, 0x56 },
//{ 0x03, 0xb6 }, // default is 0xb6
{ 0x03, 0x8e },
{ 0x12, 0x80 },
{ 0x13, 0x07 },
{ 0x15, 0x12 },
{ 0xfe, 0x01 },
{ 0x8c, 0x10 },
{ 0xfe, 0x00 },
{ 0x3e, 0x91 },
#else
{ 0xfe, 0x80 }, // page select
{ 0xfe, 0x80 },
{ 0xfe, 0x80 },
@ -155,7 +314,7 @@ static struct image_sensor_command_s gc2053_init_list[] = {
{ 0x3f, 0x62 },
/****DVP & MIPI****/
{ 0xfe, 0x01 },
// {0x8c,0x01}, // test mode
//{0x8c,0x01}, // test mode
//{0x9a,0x06}, /* VSYNC low pulse */
{ 0x9a, 0x02 }, /* VSYNC high pulse */
{ 0xfe, 0x00 },
@ -170,6 +329,7 @@ static struct image_sensor_command_s gc2053_init_list[] = {
{ 0xfe, 0x00 },
{ 0x3e, 0x40 },
#endif
};
static struct image_sensor_config_s gc2053_config = {
@ -183,7 +343,11 @@ static struct image_sensor_config_s gc2053_config = {
.resolution_y = 1080,
.id_addr = 0xf0f1,
.id_value = 0x2053,
#ifdef CONFIG_BSP_CSI
.pixel_clock = 66000000,
#else
.pixel_clock = 24000000,
#endif
.init_list_len = sizeof(gc2053_init_list)/sizeof(gc2053_init_list[0]),
.init_list = gc2053_init_list,
};

23
bsp/common/image_sensor/image_sensor.c
View File

@ -25,16 +25,18 @@
#include "gc0308.h"
#include "gc0328.h"
#include "gc2053.h"
#include "ov2685.h"
#include "bflb_i2c.h"
static struct image_sensor_config_s *sensor_list[] = {
NULL, &bf2013_config, &gc0308_config, &gc0328_config, &gc2053_config
NULL, &bf2013_config, &gc0308_config, &gc0328_config, &gc2053_config, &ov2685_config
};
void image_sensor_read(struct bflb_device_s *i2c, uint32_t sensor_index, struct image_sensor_command_s *read_list, uint32_t list_len)
{
uint32_t i;
struct bflb_i2c_msg_s msgs[2];
uint8_t buffer[2];
msgs[0].addr = sensor_list[sensor_index]->slave_addr;
msgs[0].flags = I2C_M_NOSTOP;
@ -47,7 +49,14 @@ void image_sensor_read(struct bflb_device_s *i2c, uint32_t sensor_index, struct
msgs[1].length = 1;
for(i=0;i<list_len;i++){
msgs[0].buffer = (uint8_t *)&read_list[i].address;
if (sensor_list[sensor_index]->reg_size == 1) {
buffer[0] = read_list[i].address & 0xff;
} else {
buffer[0] = read_list[i].address >> 8;
buffer[1] = read_list[i].address & 0xff;
}
msgs[0].buffer = buffer;
msgs[1].buffer = &read_list[i].paramete;
bflb_i2c_transfer(i2c, msgs, 2);
}
@ -57,6 +66,7 @@ void image_sensor_write(struct bflb_device_s *i2c, uint32_t sensor_index, struct
{
uint32_t i;
struct bflb_i2c_msg_s msgs[2];
uint8_t buffer[2];
msgs[0].addr = sensor_list[sensor_index]->slave_addr;
msgs[0].flags = I2C_M_NOSTOP;
@ -69,7 +79,14 @@ void image_sensor_write(struct bflb_device_s *i2c, uint32_t sensor_index, struct
msgs[1].length = 1;
for(i=0;i<list_len;i++){
msgs[0].buffer = (uint8_t *)&read_list[i].address;
if (sensor_list[sensor_index]->reg_size == 1) {
buffer[0] = read_list[i].address & 0xff;
} else {
buffer[0] = read_list[i].address >> 8;
buffer[1] = read_list[i].address & 0xff;
}
msgs[0].buffer = buffer;
msgs[1].buffer = &read_list[i].paramete;
bflb_i2c_transfer(i2c, msgs, 2);
}

296
bsp/common/image_sensor/ov2685.h Normal file
View File

@ -0,0 +1,296 @@
/**
* @file image_sensor.h
* @brief
*
* Copyright (c) 2022 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __OV2685_H__
#define __OV2685_H__
#include "image_sensor.h"
static struct image_sensor_command_s ov2685_init_list[] = {
{0x0103, 0x0001},
{0xffff, 0x0005},
{0x3002, 0x0000},
{0x3016, 0x001c},
{0x3018, 0x0084},
{0x301d, 0x00f0},
{0x3020, 0x0000},
{0x3082, 0x002c},
{0x3083, 0x0003},
{0x3084, 0x0007},
{0x3085, 0x0003},
{0x3086, 0x0000},
{0x3087, 0x0000},
{0x3501, 0x004e},
{0x3502, 0x00e0},
{0x3503, 0x0003},
{0x350b, 0x0036},
{0x3600, 0x00b4},
{0x3603, 0x0035},
{0x3604, 0x0024},
{0x3605, 0x0000},
{0x3620, 0x0024},
{0x3621, 0x0034},
{0x3622, 0x0003},
{0x3628, 0x0010},
{0x3705, 0x003c},
{0x370a, 0x0021},
{0x370c, 0x0050},
{0x370d, 0x00c0},
{0x3717, 0x0058},
{0x3718, 0x0080},
{0x3720, 0x0000},
{0x3721, 0x0009},
{0x3722, 0x0006},
{0x3723, 0x0059},
{0x3738, 0x0099},
{0x3781, 0x0080},
{0x3784, 0x000c},
{0x3789, 0x0060},
{0x3800, 0x0000},
{0x3801, 0x0000},
{0x3802, 0x0000},
{0x3803, 0x0000},
{0x3804, 0x0006},
{0x3805, 0x004f},
{0x3806, 0x0004},
{0x3807, 0x00bf},
{0x3808, 0x0006},
{0x3809, 0x0040},
{0x380a, 0x0004},
{0x380b, 0x00b0},
{0x380c, 0x0006},
{0x380d, 0x00a4},
{0x380e, 0x0005},
{0x380f, 0x000e},
{0x3810, 0x0000},
{0x3811, 0x0008},
{0x3812, 0x0000},
{0x3813, 0x0008},
{0x3814, 0x0011},
{0x3815, 0x0011},
{0x3819, 0x0004},
{0x3820, 0x00c0},
{0x3821, 0x0000},
{0x3a06, 0x0001},
{0x3a07, 0x0084},
{0x3a08, 0x0001},
{0x3a09, 0x0043},
{0x3a0a, 0x0024},
{0x3a0b, 0x0060},
{0x3a0c, 0x0028},
{0x3a0d, 0x0060},
{0x3a0e, 0x0004},
{0x3a0f, 0x008c},
{0x3a10, 0x0005},
{0x3a11, 0x000c},
{0x4000, 0x0081},
{0x4001, 0x0040},
{0x4008, 0x0002},
{0x4009, 0x0009},
{0x4300, 0x0032},//output format
{0x430e, 0x0000},
{0x4602, 0x0002},
{0x4837, 0x001e},
{0x5000, 0x00ff},
{0x5001, 0x0005},
{0x5002, 0x0032},
{0x5003, 0x0004},
{0x5004, 0x00ff},
{0x5005, 0x0012},
//{0x5080, 0x0092},//test pattern
{0x0100, 0x0001},
{0x0101, 0x0001},
{0x1000, 0x0003},
{0x0129, 0x0010},
{0x5180, 0x00f4},
{0x5181, 0x0011},
{0x5182, 0x0041},
{0x5183, 0x0042},
{0x5184, 0x0078},
{0x5185, 0x0058},
{0x5186, 0x00b5},
{0x5187, 0x00b2},
{0x5188, 0x0008},
{0x5189, 0x000e},
{0x518a, 0x000c},
{0x518b, 0x004c},
{0x518c, 0x0038},
{0x518d, 0x00f8},
{0x518e, 0x0004},
{0x518f, 0x007f},
{0x5190, 0x0040},
{0x5191, 0x005f},
{0x5192, 0x0040},
{0x5193, 0x00ff},
{0x5194, 0x0040},
{0x5195, 0x0007},
{0x5196, 0x0004},
{0x5197, 0x0004},
{0x5198, 0x0000},
{0x5199, 0x0005},
{0x519a, 0x00d2},
{0x519b, 0x0010},
{0x5200, 0x0009},
{0x5201, 0x0000},
{0x5202, 0x0006},
{0x5203, 0x0020},
{0x5204, 0x0041},
{0x5205, 0x0016},
{0x5206, 0x0000},
{0x5207, 0x0005},
{0x520b, 0x0030},
{0x520c, 0x0075},
{0x520d, 0x0000},
{0x520e, 0x0030},
{0x520f, 0x0075},
{0x5210, 0x0000},
{0x5280, 0x0014},
{0x5281, 0x0002},
{0x5282, 0x0002},
{0x5283, 0x0004},
{0x5284, 0x0006},
{0x5285, 0x0008},
{0x5286, 0x000c},
{0x5287, 0x0010},
{0x5300, 0x00c5},
{0x5301, 0x00a0},
{0x5302, 0x0006},
{0x5303, 0x000a},
{0x5304, 0x0030},
{0x5305, 0x0060},
{0x5306, 0x0090},
{0x5307, 0x00c0},
{0x5308, 0x0082},
{0x5309, 0x0000},
{0x530a, 0x0026},
{0x530b, 0x0002},
{0x530c, 0x0002},
{0x530d, 0x0000},
{0x530e, 0x000c},
{0x530f, 0x0014},
{0x5310, 0x001a},
{0x5311, 0x0020},
{0x5312, 0x0080},
{0x5313, 0x004b},
{0x5380, 0x0001},
{0x5381, 0x0052},
{0x5382, 0x0000},
{0x5383, 0x004a},
{0x5384, 0x0000},
{0x5385, 0x00b6},
{0x5386, 0x0000},
{0x5387, 0x008d},
{0x5388, 0x0000},
{0x5389, 0x003a},
{0x538a, 0x0000},
{0x538b, 0x00a6},
{0x538c, 0x0000},
{0x5400, 0x000d},
{0x5401, 0x0018},
{0x5402, 0x0031},
{0x5403, 0x005a},
{0x5404, 0x0065},
{0x5405, 0x006f},
{0x5406, 0x0077},
{0x5407, 0x0080},
{0x5408, 0x0087},
{0x5409, 0x008f},
{0x540a, 0x00a2},
{0x540b, 0x00b2},
{0x540c, 0x00cc},
{0x540d, 0x00e4},
{0x540e, 0x00f0},
{0x540f, 0x00a0},
{0x5410, 0x006e},
{0x5411, 0x0006},
{0x5480, 0x0019},
{0x5481, 0x0000},
{0x5482, 0x0009},
{0x5483, 0x0012},
{0x5484, 0x0004},
{0x5485, 0x0006},
{0x5486, 0x0008},
{0x5487, 0x000c},
{0x5488, 0x0010},
{0x5489, 0x0018},
{0x5500, 0x0002},
{0x5501, 0x0003},
{0x5502, 0x0004},
{0x5503, 0x0005},
{0x5504, 0x0006},
{0x5505, 0x0008},
{0x5506, 0x0000},
{0x5600, 0x0002},
{0x5603, 0x0040},
{0x5604, 0x0028},
{0x5609, 0x0020},
{0x560a, 0x0060},
{0x5800, 0x0003},
{0x5801, 0x0024},
{0x5802, 0x0002},
{0x5803, 0x0040},
{0x5804, 0x0034},
{0x5805, 0x0005},
{0x5806, 0x0012},
{0x5807, 0x0005},
{0x5808, 0x0003},
{0x5809, 0x003c},
{0x580a, 0x0002},
{0x580b, 0x0040},
{0x580c, 0x0026},
{0x580d, 0x0005},
{0x580e, 0x0052},
{0x580f, 0x0006},
{0x5810, 0x0003},
{0x5811, 0x0028},
{0x5812, 0x0002},
{0x5813, 0x0040},
{0x5814, 0x0024},
{0x5815, 0x0005},
{0x5816, 0x0042},
{0x5817, 0x0006},
{0x5818, 0x000d},
{0x5819, 0x0040},
{0x581a, 0x0004},
{0x581b, 0x000c},
{0x3a03, 0x004c},
{0x3a04, 0x0040},
{0x3503, 0x0000},
};
static struct image_sensor_config_s ov2685_config = {
.name = "OV2685",
.output_format = IMAGE_SENSOR_FORMAT_YUV422_YUYV,
.slave_addr = 0x3c,
.id_size = 2,
.reg_size = 2,
.h_blank = 0xde,
.resolution_x = 1600,
.resolution_y = 1200,
.id_addr = 0x300a300b,
.id_value = 0x2685,
.pixel_clock = 66000000,
.init_list_len = sizeof(ov2685_init_list)/sizeof(ov2685_init_list[0]),
.init_list = ov2685_init_list,
};
#endif /* __OV2685_H__ */

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/**
* @file ft6x36_i2c.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "touch.h"
#ifdef TOUCH_I2C_FT6X36
#include "bflb_mtimer.h"
#include "bflb_gpio.h"
#include "bflb_i2c.h"
#include "ft6x36_i2c.h"
static struct bflb_device_s *touch_ft6x36_i2c = NULL;
static void ft6x36_i2c_gpio_init(void)
{
struct bflb_device_s *ft63x6_i2c_gpio = NULL;
ft63x6_i2c_gpio = bflb_device_get_by_name("gpio");
/* I2C0_SCL */
bflb_gpio_init(ft63x6_i2c_gpio, GPIO_PIN_10, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
/* I2C0_SDA */
bflb_gpio_init(ft63x6_i2c_gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
}
static int ft6x36_i2c_peripheral_init(void)
{
touch_ft6x36_i2c = bflb_device_get_by_name("i2c0");
if (touch_ft6x36_i2c) {
// printf("ft6x36 i2c gpio init\r\n");
/* init i2c gpio */
ft6x36_i2c_gpio_init();
/* init i2c 200k */
bflb_i2c_init(touch_ft6x36_i2c, 200000);
} else {
printf("i2c device get fail\r\n");
return -1;
}
return 0;
}
static int ft6x36_i2c_read_byte(uint8_t register_addr, uint8_t *data_buf, uint16_t len)
{
static struct bflb_i2c_msg_s msg[2];
msg[0].addr = FT6236_I2C_SLAVE_ADDR;
msg[0].flags = I2C_M_NOSTOP;
msg[0].buffer = &register_addr;
msg[0].length = 1;
msg[1].flags = I2C_M_READ;
msg[1].buffer = data_buf;
msg[1].length = len;
bflb_i2c_transfer(touch_ft6x36_i2c, msg, 2);
return 0;
}
int ft6x36_get_gesture_id()
{
uint8_t data_buf = FT6X36_GEST_ID_NO_GESTURE;
if (ft6x36_i2c_read_byte(FT6X36_GEST_ID_REG, &data_buf, 1)) {
return -1;
}
return data_buf;
}
int ft6x36_i2c_init(touch_coord_t *max_value)
{
uint8_t data_buf;
printf("ft6x36 i2c init\r\n");
ft6x36_i2c_peripheral_init();
if (ft6x36_i2c_read_byte(FT6X36_PANEL_ID_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Device ID: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_CHIPSELECT_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Chip ID: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_DEV_MODE_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Device mode: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_FIRMWARE_ID_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Firmware ID: 0x%02x\r\n", data_buf);
if (ft6x36_i2c_read_byte(FT6X36_RELEASECODE_REG, &data_buf, 1)) {
return -1;
}
printf("Touch Release code: 0x%02x\r\n", data_buf);
return 0;
}
int ft6x36_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num)
{
uint8_t data_buf[5];
*point_num = 0;
if (point_num == NULL || touch_coord == NULL || max_num == 0) {
return -1;
}
if (ft6x36_i2c_read_byte(FT6X36_TD_STAT_REG, &data_buf[0], 1)) {
return -1;
}
data_buf[0] &= FT6X36_TD_STAT_MASK;
/* no touch or err */
if (data_buf[0] == 0 || data_buf[0] > 2) {
if (data_buf[0] > 2) {
return -2;
} else {
return 0;
}
}
/* Get the first point */
ft6x36_i2c_read_byte(FT6X36_P1_XH_REG, &data_buf[1], 4);
touch_coord[0].coord_x = (data_buf[1] & FT6X36_MSB_MASK) << 8 | (data_buf[2] & FT6X36_LSB_MASK);
touch_coord[0].coord_y = (data_buf[3] & FT6X36_MSB_MASK) << 8 | (data_buf[4] & FT6X36_LSB_MASK);
*point_num = 1;
/* Get the second point */
if (data_buf[0] > 1 && max_num > 1) {
ft6x36_i2c_read_byte(FT6X36_P2_XH_REG, &data_buf[1], 4);
touch_coord[1].coord_x = (data_buf[1] & FT6X36_MSB_MASK) << 8 | (data_buf[2] & FT6X36_LSB_MASK);
touch_coord[1].coord_y = (data_buf[3] & FT6X36_MSB_MASK) << 8 | (data_buf[4] & FT6X36_LSB_MASK);
*point_num = 2;
}
return 0;
}
#endif

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/**
* @file ft6x36_i2c.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _FT6X36_I2C_H
#define _FT6X36_I2C_H
#include "bflb_core.h"
#include "touch.h"
#define FT6236_I2C_SLAVE_ADDR 0x38
/* Maximum border values of the touchscreen pad that the chip can handle */
#define FT6X36_MAX_WIDTH ((uint16_t)800)
#define FT6X36_MAX_HEIGHT ((uint16_t)480)
/* Max detectable simultaneous touch points */
#define FT6X36_I2C_MAX_POINT 2
/* Register of the current mode */
#define FT6X36_DEV_MODE_REG 0x00
/* Possible modes as of FT6X36_DEV_MODE_REG */
#define FT6X36_DEV_MODE_WORKING 0x00
#define FT6X36_DEV_MODE_FACTORY 0x04
#define FT6X36_DEV_MODE_MASK 0x70
#define FT6X36_DEV_MODE_SHIFT 4
/* Gesture ID register */
#define FT6X36_GEST_ID_REG 0x01
/* Possible values returned by FT6X36_GEST_ID_REG */
#define FT6X36_GEST_ID_NO_GESTURE 0x00
#define FT6X36_GEST_ID_MOVE_UP 0x10
#define FT6X36_GEST_ID_MOVE_RIGHT 0x14
#define FT6X36_GEST_ID_MOVE_DOWN 0x18
#define FT6X36_GEST_ID_MOVE_LEFT 0x1C
#define FT6X36_GEST_ID_ZOOM_IN 0x48
#define FT6X36_GEST_ID_ZOOM_OUT 0x49
/* Status register: stores number of active touch points (0, 1, 2) */
#define FT6X36_TD_STAT_REG 0x02
#define FT6X36_TD_STAT_MASK 0x0F
#define FT6X36_TD_STAT_SHIFT 0x00
/* Touch events */
#define FT6X36_TOUCH_EVT_FLAG_PRESS_DOWN 0x00
#define FT6X36_TOUCH_EVT_FLAG_LIFT_UP 0x01
#define FT6X36_TOUCH_EVT_FLAG_CONTACT 0x02
#define FT6X36_TOUCH_EVT_FLAG_NO_EVENT 0x03
#define FT6X36_TOUCH_EVT_FLAG_SHIFT 6
#define FT6X36_TOUCH_EVT_FLAG_MASK (3 << FT6X36_TOUCH_EVT_FLAG_SHIFT)
#define FT6X36_MSB_MASK 0x0F
#define FT6X36_MSB_SHIFT 0
#define FT6X36_LSB_MASK 0xFF
#define FT6X36_LSB_SHIFT 0
#define FT6X36_P1_XH_REG 0x03
#define FT6X36_P1_XL_REG 0x04
#define FT6X36_P1_YH_REG 0x05
#define FT6X36_P1_YL_REG 0x06
#define FT6X36_P1_WEIGHT_REG 0x07 /* Register reporting touch pressure - read only */
#define FT6X36_TOUCH_WEIGHT_MASK 0xFF
#define FT6X36_TOUCH_WEIGHT_SHIFT 0
#define FT6X36_P1_MISC_REG 0x08 /* Touch area register */
#define FT6X36_TOUCH_AREA_MASK (0x04 << 4) /* Values related to FT6X36_Pn_MISC_REG */
#define FT6X36_TOUCH_AREA_SHIFT 0x04
#define FT6X36_P2_XH_REG 0x09
#define FT6X36_P2_XL_REG 0x0A
#define FT6X36_P2_YH_REG 0x0B
#define FT6X36_P2_YL_REG 0x0C
#define FT6X36_P2_WEIGHT_REG 0x0D
#define FT6X36_P2_MISC_REG 0x0E
/* Threshold for touch detection */
#define FT6X36_TH_GROUP_REG 0x80
#define FT6X36_THRESHOLD_MASK 0xFF /* Values FT6X36_TH_GROUP_REG : threshold related */
#define FT6X36_THRESHOLD_SHIFT 0
#define FT6X36_TH_DIFF_REG 0x85 /* Filter function coefficients */
#define FT6X36_CTRL_REG 0x86 /* Control register */
#define FT6X36_CTRL_KEEP_ACTIVE_MODE 0x00 /* Will keep the Active mode when there is no touching */
#define FT6X36_CTRL_KEEP_AUTO_SWITCH_MONITOR_MODE 0x01 /* Switching from Active mode to Monitor mode automatically when there is no touching */
#define FT6X36_TIME_ENTER_MONITOR_REG 0x87 /* The time period of switching from Active mode to Monitor mode when there is no touching */
#define FT6X36_PERIOD_ACTIVE_REG 0x88 /* Report rate in Active mode */
#define FT6X36_PERIOD_MONITOR_REG 0x89 /* Report rate in Monitor mode */
#define FT6X36_RADIAN_VALUE_REG 0x91 /* The value of the minimum allowed angle while Rotating gesture mode */
#define FT6X36_OFFSET_LEFT_RIGHT_REG 0x92 /* Maximum offset while Moving Left and Moving Right gesture */
#define FT6X36_OFFSET_UP_DOWN_REG 0x93 /* Maximum offset while Moving Up and Moving Down gesture */
#define FT6X36_DISTANCE_LEFT_RIGHT_REG 0x94 /* Minimum distance while Moving Left and Moving Right gesture */
#define FT6X36_DISTANCE_UP_DOWN_REG 0x95 /* Minimum distance while Moving Up and Moving Down gesture */
#define FT6X36_LIB_VER_H_REG 0xA1 /* High 8-bit of LIB Version info */
#define FT6X36_LIB_VER_L_REG 0xA2 /* Low 8-bit of LIB Version info */
#define FT6X36_CHIPSELECT_REG 0xA3 /* 0x36 for ft6236; 0x06 for ft6206 */
#define FT6X36_POWER_MODE_REG 0xA5
#define FT6X36_FIRMWARE_ID_REG 0xA6
#define FT6X36_RELEASECODE_REG 0xAF
#define FT6X36_PANEL_ID_REG 0xA8
#define FT6X36_OPMODE_REG 0xBC
int ft6x36_i2c_init(touch_coord_t *max_value);
int ft6x36_i2c_get_gesture_id();
int ft6x36_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num);
#endif /* __FT6X36_H */

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/**
* @file gt911_i2c.c
* @brief
*
* Copyright (c) 2022 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "touch.h"
#ifdef TOUCH_I2C_GT911
#include "bflb_mtimer.h"
#include "bflb_gpio.h"
#include "bflb_i2c.h"
#include "gt911_i2c.h"
#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
static struct bflb_device_s *touch_gt911_i2c = NULL;
static void gt911_i2c_gpio_init(void)
{
struct bflb_device_s *gt911_i2c_gpio = NULL;
gt911_i2c_gpio = bflb_device_get_by_name("gpio");
/* I2C0_SCL */
bflb_gpio_init(gt911_i2c_gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
/* I2C0_SDA */
bflb_gpio_init(gt911_i2c_gpio, GPIO_PIN_9, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
}
static int gt911_i2c_peripheral_init(void)
{
touch_gt911_i2c = bflb_device_get_by_name("i2c0");
if (touch_gt911_i2c) {
// printf("gt911 i2c gpio init\r\n");
/* init i2c gpio */
gt911_i2c_gpio_init();
/* init i2c 200k */
bflb_i2c_init(touch_gt911_i2c, 200000);
} else {
printf("i2c device get fail\r\n");
return -1;
}
return 0;
}
static int gt911_i2c_read_byte(uint16_t register_addr, uint8_t *data_buf, uint16_t len)
{
static struct bflb_i2c_msg_s msg[2];
msg[0].addr = GT911_I2C_SLAVE_ADDR;
msg[0].flags = I2C_M_NOSTOP;
msg[0].buffer = (uint8_t *)(&register_addr);
msg[0].length = 2;
msg[1].addr = GT911_I2C_SLAVE_ADDR;
msg[1].flags = I2C_M_READ;
msg[1].buffer = data_buf;
msg[1].length = len;
bflb_i2c_transfer(touch_gt911_i2c, msg, 2);
return 0;
}
static int gt911_i2c_write_byte(uint16_t register_addr, uint8_t *data_buf, uint16_t len)
{
static struct bflb_i2c_msg_s msg[2];
msg[0].addr = GT911_I2C_SLAVE_ADDR;
msg[0].flags = I2C_M_NOSTOP;
msg[0].buffer = (uint8_t *)(&register_addr);
msg[0].length = 2;
msg[1].addr = GT911_I2C_SLAVE_ADDR;
msg[1].flags = 0;
msg[1].buffer = data_buf;
msg[1].length = len;
bflb_i2c_transfer(touch_gt911_i2c, msg, 2);
return 0;
}
int gt911_i2c_get_gesture_id()
{
uint8_t data_buf = 0;
if (gt911_i2c_read_byte(GT911_READ_XY_REG, &data_buf, 1)) {
return -1;
}
return data_buf;
}
int gt911_i2c_init(touch_coord_t *max_value)
{
uint8_t data_buf[5] = { 0 };
uint32_t product_id = 0;
uint16_t x_max = 0, y_max = 0;
gt911_i2c_peripheral_init();
if (gt911_i2c_read_byte(GT911_PRODUCT_ID_REG, data_buf, 4)) {
printf("touch i2c read error\r\n");
return -1;
}
product_id = BL_RDWD_FRM_BYTEP(data_buf);
printf("Touch Product ID: 0x%08x\r\n", product_id);
if (product_id == GT911_PRODUCT_ID) {
#if 0
data_buf[0] = 0;
data_buf[1] = (uint8_t)(max_value->coord_x << 8);
data_buf[2] = (uint8_t)(max_value->coord_x);
data_buf[3] = (uint8_t)(max_value->coord_y << 8);
data_buf[4] = (uint8_t)(max_value->coord_y);
if (gt911_i2c_write_byte(GT911_CONFIG_REG, data_buf, 5)) {
return -1;
}
if (gt911_i2c_write_byte(GT911_CONFIG_REG + (0x0005 << 8), (void *)g_gt911_cfg_params + 5, (sizeof(g_gt911_cfg_params) / sizeof(g_gt911_cfg_params[0]) - 5))) {
return -1;
}
#else
if (gt911_i2c_write_byte(GT911_CONFIG_REG, (void *)g_gt911_cfg_params, (sizeof(g_gt911_cfg_params) / sizeof(g_gt911_cfg_params[0])))) {
return -1;
}
#endif
} else {
printf("Touch Product ID read fail!\r\n");
return -1;
}
if (gt911_i2c_read_byte(GT911_FIRMWARE_VERSION_REG, data_buf, 2)) {
return -1;
}
printf("Touch Firmware Version: 0x%04x\r\n", data_buf);
if (gt911_i2c_read_byte(GT911_X_RESOLUTION, data_buf, 4)) {
return -1;
}
x_max = (((uint16_t)data_buf[1] << 8) | data_buf[0]);
y_max = (((uint16_t)data_buf[3] << 8) | data_buf[2]);
printf("Touch Resolution %dx%d \r\n", x_max, y_max);
return 0;
}
int gt911_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num)
{
uint8_t data_buf[8 * GT911_I2C_MAX_POINT] = { 0 };
uint8_t read_num;
*point_num = 0;
if (point_num == NULL || touch_coord == NULL || max_num == 0) {
return -1;
}
if (gt911_i2c_read_byte(GT911_READ_XY_REG, data_buf, 1)) {
return -1;
}
/* no touch */
if (data_buf[0] == 0) {
return 0;
}
if (data_buf[0] > GT911_I2C_MAX_POINT) {
data_buf[0] = GT911_I2C_MAX_POINT;
}
read_num = (data_buf[0] > max_num) ? max_num : data_buf[0];
/* read gt911 reg */
gt911_i2c_read_byte(GT911_READ_XY_REG, data_buf, (8 * read_num));
/* get point coordinates */
for (uint8_t i = 0; i < read_num; i++) {
uint8_t *p_data = &data_buf[i * 8];
touch_coord[i].coord_x = (uint16_t)p_data[3] << 8 | p_data[2];
touch_coord[i].coord_y = (uint16_t)p_data[5] << 8 | p_data[4];
}
*point_num = read_num;
data_buf[0] = 0;
gt911_i2c_write_byte(GT911_READ_XY_REG, data_buf, 1);
return 0;
}
#endif

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/**
* @file gt911_i2c.h
* @brief
*
* Copyright (c) 2022 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _GT911_I2C_H
#define _GT911_I2C_H
#include "bflb_core.h"
#include "touch.h"
#define GT911_CUSTOM_CFG (1)
#define GT911_I2C_SLAVE_ADDR (0xBA >> 1) // #define GT911_ADDR (0xBA) //(0x28) /* slave addr */
#define GT911_READ_XY_REG (0x4E81) //(0x814E) /* 坐标寄存器 */
#define GT911_CLEARBUF_REG (0x4E81) //(0x814E) /* 清除坐标寄存器 */
#define GT911_POINT1_REG (0x4F81) //(0x814f) /* point 1 reg */
#define GT911_POINT2_REG (0x5781) //(0x8157) /* point 2 reg */
#define GT911_POINT3_REG (0x5F81) //(0x815f) /* point 3 reg */
#define GT911_POINT4_REG (0x6781) //(0x8167) /* point 4 reg */
#define GT911_POINT5_REG (0x6F81) //(0x816f) /* point 5 reg */
#define GT911_CONFIG_REG (0x4780) //(0x8047) /* 配置参数寄存器 */
#define GT911_COMMAND_REG (0x4080) //(0x8040) /* 实时命令 */
#define GT911_PRODUCT_ID_REG (0x4081) //(0x8140) /* 芯片ID */
#define GT911_VENDOR_ID_REG (0x4A81) //(0x814A) /* 当前模组选项信息 */
#define GT911_CONFIG_VERSION_REG (0x4780) //(0x8047) /* 配置文件版本号 */
#define GT911_CONFIG_CHECKSUM_REG (0xFF80) //(0x80FF) /* 配置文件校验码 */
#define GT911_FIRMWARE_VERSION_REG (0x4481) //(0x8144) /* 固件版本号 */
#define GT911_X_RESOLUTION (0x4681) //(0x8146) /* x 坐标分辨率 */
#define GT911_Y_RESOLUTION (0x4881) //(0x8148) /* y 坐标分辨率 */
#define GT911_PRODUCT_ID (0x00313139)
/* Maximum border values of the touchscreen pad that the chip can handle */
#if GT911_CUSTOM_CFG
#define GT911_MAX_WIDTH ((uint16_t)320)
#define GT911_MAX_HEIGHT ((uint16_t)480)
#define GT911_INT_TRIGGER (0)
#else
#define GT911_MAX_WIDTH ((uint16_t)4096)
#define GT911_MAX_HEIGHT ((uint16_t)4096)
#define GT911_INT_TRIGGER (1)
#endif
/* Max detectable simultaneous touch points */
#define GT911_I2C_MAX_POINT 5
/* GT911 配置参数，一次性写入 */
static const uint8_t g_gt911_cfg_params[] = {
#if 1
/*KDC CFG*/
0x00, 0x40, 0x01, 0xE0, 0x01, 0x0A, 0x05, 0x00,
0x01, 0x08, 0x28, 0x05, 0x50, 0x32, 0x03, 0x05,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x86, 0x26, 0x07, 0x17, 0x15,
0x31, 0x0D, 0x00, 0x00, 0x01, 0xBA, 0x03, 0x1D,
0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x64, 0x32,
0x00, 0x00, 0x00, 0x0F, 0x4B, 0x94, 0xC5, 0x02,
0x07, 0x00, 0x00, 0x04, 0x9B, 0x11, 0x00, 0x72,
0x18, 0x00, 0x57, 0x21, 0x00, 0x42, 0x2E, 0x00,
0x35, 0x40, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x12, 0x10, 0x0E, 0x0C, 0x0A, 0x08, 0x06, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x21,
0x20, 0x1F, 0x1E, 0x1D, 0x00, 0x02, 0x04, 0x06,
0x08, 0x0A, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0xDC, 0x01
#else
0x00, //0x8047 版本号 发送 0x00 初始化为 A
0x40, 0x01, //0x8048/8049 X坐标输出最大值 320
0xE0, 0x01, //0x804a/804b Y坐标输出最大值 480
0x0A, //0x804c 输出触点个数上限
0x05, //0x804d x2y 坐标交换，软件降噪，下降沿触发
0x00, //0x804e reserved
0x01, //0x804f 手指按下去抖动次数
0x08, //0x8050 原始坐标窗口滤波值
0x28, //0x8051 大面积触点个数
0x05, //0x8052 噪声消除值
0x50, //0x8053 屏上触摸点从无到有的阈值
0x32, //0x8054 屏上触摸点从有到无的阈值
0x03, //0x8055 进低功耗时间 s
0x05, //0x8056 坐标上报率
0x00, //0x8057 X坐标输出门上限
0x00, //0x8058 Y坐标输出门上限
0x00, 0X00, //0x8059-0x805a reserved
0x00, //0x805b reserved
0x00, //0x805c reserved
0x00, //0x805d 划线过程中小filter设置
0x00, //0x805e 拉伸区间 1 系数
0x00, //0x805f 拉伸区间 2 系数
0x00, //0x8060 拉伸区间 3 系数
0x00, //0x8061 各拉伸区间基数
0x00, //0x8062 Driver Group A number
0x00, //0x8063 Driver Group B number
0x00, //0x8064 Sensor Group B | A number
0x00, //0x8065 驱动组A的驱动频率倍频系数
0x00, //0x8066 驱动组B的驱动频率倍频系数
0x00, //0x8067 驱动组A、B的基频
0x04, //0x8068
0x00, //0x8069 相邻两次驱动信号输出时间间隔
0x00, //0x806a
0x00, //0x806b 、、
0x02, //0x806c 、、
0x03, //0x806d 原始值放大系数
0x1D, //0x806e 、、
0x00, //0x806f reserved
0x01, //0x8070 、、
0x00, 0x00, //reserved
0x00, //0x8073 、、
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x8071 - 0x8079 reserved
0x50, //0x807a 跳频范围的起点频率
0xA0, //0x807b 跳频范围的终点频率
0x94, //0x807c 多次噪声检测后确定噪声量，1-63有效
0xD5, //0x807d 噪声检测超时时间
0x02, //0x807e 、、
0x07, //0x807f 判别有干扰的门限
0x00, 0x00, //0x8081 reserved
0x04, //0x8082 跳频检测区间频段1中心点基频（适用于驱动A、B）
0xA4, //0x8083
0x55, //0x8084 跳频检测区间频段1中心点倍频系数
0x00, //0x8085 跳频检测区间频段2中心点基频(驱动A、B在此基础上换算)
0x91, //0x8086
0x62, //0x8087 跳频检测区间频段2中心点倍频系数
0x00, //0x8088 跳频检测区间频段3中心点基频（适用于驱动A、B）
0x80, //0x8089
0x71, //0x808a 跳频检测区间频段3中心点倍频系数
0x00, //0x808b 跳频检测区间频段4中心点基频（适用于驱动A、B）
0x71, //0x808c
0x82, //0x808d 跳频检测区间频段4中心点倍频系数
0x00, //0x808e 跳频检测区间频段5中心点基频（适用于驱动A、B）
0x65, //0x808f
0x95, //0x8090 跳频检测区间频段5中心点倍频系数
0x00, 0x65, //reserved
0x00, //0x8093 key1位置 0：无按键
0x00, //0x8094 key2位置 0：无按键
0x00, //0x8095 key3位置 0：无按键
0x00, //0x8096 key4位置 0：无按键
0x00, //0x8097 reserved
0x00, //0x8098 reserved
0x00, //0x8099 reserved
0x00, //0x809a reserved
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x809b-0x80b2 reserved
0x00, //0x80b3 合框距离
0x00, //0x80b4
0x00, 0x00, //0x80b6 reserved
0x06, //0x80b7
0x08, //0x80b8
0x0A, //0x80b9
0x0C, //0x80ba
0x0E, //0x80bb
0x10, //0x80bc
0x12, //0x80bd
0x14, //0x80be
0x16, //0x80bf
0x18, //0x80c0
0x1A, //0x80c1
0x1C, //0x80c2
0xFF, //0x80c3
0xFF, //0x80c4
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80c5-0x80d4 reserved
0x00, //0x80d5
0x02, //0x80d6
0x04, //0x80d7
0x06, //0x80d8
0x08, //0x80d9
0x0A, //0x80da
0x0C, //0x80db
0x0F, //0x80dc
0x10, //0x80dd
0x12, //0x80de
0x13, //0x80df
0x14, //0x80e0
0x16, //0x80e1
0x18, //0x80e2
0x1C, //0x80e3
0x1D, //0x80e4
0x1E, //0x80e5
0x1F, //0x80e6
0x20, //0x80e7
0x21, //0x80e8
0xFF, //0x80e9
0xFF, //0x80ea
0xFF, //0x80eb
0xFF, //0x80ec
0xFF, //0x80ed
0xFF, //0x80ee
0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80ef-0x80fe reserved
0x0B, //0x80ff 配置信息校验
0x01 //0x8100 配置以更新标记
#endif
};
typedef struct
{
uint8_t touch_point_flag;
uint8_t touch_key_sts;
uint16_t x0;
uint16_t y0;
uint16_t p0;
uint16_t x1;
uint16_t y1;
uint16_t p1;
uint16_t x2;
uint16_t y2;
uint16_t p2;
uint16_t x3;
uint16_t y3;
uint16_t p3;
uint16_t x4;
uint16_t y4;
uint16_t p4;
} gt911_point_t;
int gt911_i2c_init(touch_coord_t *max_value);
int gt911_i2c_get_gesture_id();
int gt911_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num);
#endif /* __gt911_H */

33
bsp/common/touch/touch.c Normal file
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@ -0,0 +1,33 @@
/**
* @file touch.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "touch.h"
int touch_init(touch_coord_t *max_value)
{
return _TOUCH_FUNC_DEFINE(init, max_value);
}
int touch_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num)
{
return _TOUCH_FUNC_DEFINE(read, point_num, touch_coord, max_num);
}

78
bsp/common/touch/touch.h Normal file
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@ -0,0 +1,78 @@
/**
* @file touch.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef _TOUCH_H_
#define _TOUCH_H_
#include "bflb_core.h"
/* spi interface
TOUCH_SPI_XPT2046 // Not currently supported
*/
/* i2c interface
TOUCH_I2C_FT6X36
TOUCH_I2C_GT911
*/
/* Select Touch Type */
#define TOUCH_I2C_FT6X36
#define TOUCH_INTERFACE_SPI 1
#define TOUCH_INTERFACE_I2C 2
typedef struct
{
uint16_t coord_x;
uint16_t coord_y;
} touch_coord_t;
#if defined TOUCH_SPI_XPT2046
#include "xpt2046_spi.h"
#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_SPI
#define TOUCH_MAX_POINT XPT2046_MAX_POINT
#define _TOUCH_FUNC_DEFINE(_func, ...) xpt2046_spi_##_func(__VA_ARGS__)
#elif defined TOUCH_I2C_FT6X36
#include "ft6x36_i2c.h"
#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_I2C
#define TOUCH_MAX_POINT FT6X36_I2C_MAX_POINT
#define _TOUCH_FUNC_DEFINE(_func, ...) ft6x36_i2c_##_func(__VA_ARGS__)
#elif defined TOUCH_I2C_GT911
#include "gt911_i2c.h"
#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_I2C
#define TOUCH_MAX_POINT GT911_I2C_MAX_POINT
#define _TOUCH_FUNC_DEFINE(_func, ...) gt911_i2c_##_func(__VA_ARGS__)
#elif
#error "Please select a touch type"
#endif
int touch_init(touch_coord_t *max_value);
int touch_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num);
#endif

36
cmake/bflb_flash.cmake Normal file
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@ -0,0 +1,36 @@
if(MINGW OR CYGWIN OR WIN32)
set(TOOL_SUFFIX ".exe")
elseif(UNIX OR APPLE)
set(TOOL_SUFFIX "")
endif()
set(BL_FW_POST_PROC ${BL_SDK_BASE}/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc${TOOL_SUFFIX})
set(BL_FW_POST_PROC_CONFIG --chipname=${CHIP} --imgfile=${BIN_FILE})
if(BOARD_DIR)
list(APPEND BL_FW_POST_PROC_CONFIG --brdcfgdir=${BOARD_DIR}/${BOARD}/config)
else()
list(APPEND BL_FW_POST_PROC_CONFIG --brdcfgdir=${BL_SDK_BASE}/bsp/board/${BOARD}/config)
endif()
if(CONFIG_AES_KEY)
list(APPEND BL_FW_POST_PROC_CONFIG --key=${CONFIG_AES_KEY})
endif()
if(CONFIG_AES_IV)
list(APPEND BL_FW_POST_PROC_CONFIG --iv=${CONFIG_AES_IV})
endif()
if(CONFIG_PUBLIC_KEY)
list(APPEND BL_FW_POST_PROC_CONFIG --publickey=${CONFIG_PUBLIC_KEY})
endif()
if(CONFIG_PRIVATE_KEY)
list(APPEND BL_FW_POST_PROC_CONFIG --privatekey=${CONFIG_PRIVATE_KEY})
endif()
add_custom_target(combine
WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
COMMAND ${BL_FW_POST_PROC} ${BL_FW_POST_PROC_CONFIG})

97
cmake/extension.cmake
View File

@ -1,8 +1,6 @@
macro(sdk_generate_library)
if(${ARGC})
foreach(var ${ARGN})
set(library_name ${var})
endforeach()
set(library_name ${ARGV0})
else()
get_filename_component(library_name ${CMAKE_CURRENT_LIST_DIR} NAME)
endif()
@ -47,42 +45,89 @@ function(sdk_add_include_directories)
endforeach()
endfunction()
function(sdk_add_private_include_directories)
foreach(arg ${ARGV})
if(IS_ABSOLUTE ${arg})
set(path ${arg})
else()
set(path ${CMAKE_CURRENT_SOURCE_DIR}/${arg})
endif()
target_include_directories(${CURRENT_STATIC_LIBRARY} PRIVATE ${path})
endforeach()
endfunction()
function(sdk_add_include_directories_ifdef feature)
if(${${feature}})
sdk_add_include_directories(${ARGN})
endif()
endfunction()
function(sdk_add_private_include_directories_ifdef feature)
if(${${feature}})
sdk_add_private_include_directories(${ARGN})
endif()
endfunction()
function(sdk_add_compile_definitions)
target_compile_definitions(sdk_intf_lib INTERFACE ${ARGV})
endfunction()
function(sdk_add_private_compile_definitions)
target_compile_definitions(${CURRENT_STATIC_LIBRARY} PRIVATE ${ARGV})
endfunction()
function(sdk_add_compile_definitions_ifdef feature)
if(${${feature}})
sdk_add_compile_definitions(${ARGN})
endif()
endfunction()
function(sdk_add_private_compile_definitions_ifdef feature)
if(${${feature}})
sdk_add_private_compile_definitions(${ARGN})
endif()
endfunction()
function(sdk_add_compile_options)
target_compile_options(sdk_intf_lib INTERFACE ${ARGV})
endfunction()
function(sdk_add_private_compile_options)
target_compile_options(${CURRENT_STATIC_LIBRARY} PRIVATE ${ARGV})
endfunction()
function(sdk_add_compile_options_ifdef feature)
if(${${feature}})
sdk_add_compile_options(${ARGN})
endif()
endfunction()
function(sdk_add_private_compile_options_ifdef feature)
if(${${feature}})
sdk_add_private_compile_options(${ARGN})
endif()
endfunction()
function(sdk_add_link_options)
target_link_options(sdk_intf_lib INTERFACE ${ARGV})
endfunction()
function(sdk_add_private_link_options)
target_link_options(${CURRENT_STATIC_LIBRARY} PRIVATE ${ARGV})
endfunction()
function(sdk_add_link_options_ifdef feature)
if(${${feature}})
sdk_add_link_options(${ARGN})
endif()
endfunction()
function(sdk_add_private_link_options_ifdef feature)
if(${${feature}})
sdk_add_private_link_options(${ARGN})
endif()
endfunction()
function(sdk_add_link_libraries)
target_link_libraries(sdk_intf_lib INTERFACE ${ARGV})
endfunction()
@ -99,21 +144,6 @@ function(sdk_add_subdirectory_ifdef feature dir)
endif()
endfunction()
macro(sdk_ifndef define val)
if(NOT DEFINED ${define})
set(${define} ${val})
endif()
endmacro()
function(sdk_set_linker_script ld)
if(IS_ABSOLUTE ${ld})
set(path ${ld})
else()
set(path ${CMAKE_CURRENT_SOURCE_DIR}/${ld})
endif()
set_property(GLOBAL PROPERTY LINKER_SCRIPT ${path})
endfunction()
function(sdk_add_static_library)
foreach(arg ${ARGV})
if(IS_DIRECTORY ${arg})
@ -131,6 +161,35 @@ function(sdk_add_static_library)
endforeach()
endfunction()
function(sdk_add_static_library_ifdef feature)
if(${${feature}})
sdk_add_static_library(${ARGN})
endif()
endfunction()
macro(sdk_ifndef define val)
if(NOT DEFINED ${define})
set(${define} ${val})
endif()
endmacro()
function(sdk_set_linker_script ld)
if(IS_ABSOLUTE ${ld})
set(path ${ld})
else()
set(path ${CMAKE_CURRENT_SOURCE_DIR}/${ld})
endif()
set_property(GLOBAL PROPERTY LINKER_SCRIPT ${path})
endfunction()
macro(sdk_set_vscode_dir dir)
if(IS_ABSOLUTE ${dir})
set(VSCODE_DIR ${dir})
else()
set(VSCODE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/${dir})
endif()
endmacro()
macro(sdk_set_main_file)
if(IS_ABSOLUTE ${ARGV0})
set(path ${ARGV0})
@ -190,4 +249,6 @@ macro(project name)
)
endif()
# include(${BL_SDK_BASE}/cmake/bflb_flash.cmake)
# include(${BL_SDK_BASE}/cmake/gen_c_cpp_properties_json.cmake)
endmacro()

28
cmake/gen_c_cpp_properties_json.cmake Normal file
View File

@ -0,0 +1,28 @@
cmake_minimum_required(VERSION 3.19.3)
get_target_property(C_CPP_PROPERTIES_INCLUDE sdk_intf_lib INTERFACE_INCLUDE_DIRECTORIES)
get_target_property(C_CPP_PROPERTIES_DEFINES sdk_intf_lib INTERFACE_COMPILE_DEFINITIONS)
list(SORT C_CPP_PROPERTIES_INCLUDE)
list(SORT C_CPP_PROPERTIES_DEFINES)
foreach(item ${C_CPP_PROPERTIES_INCLUDE})
string(APPEND C_CPP_PROPERTIES_INCLUDE_IN "\n \"${item}\",")
endforeach()
foreach(item ${C_CPP_PROPERTIES_DEFINES})
string(APPEND C_CPP_PROPERTIES_DEFINES_IN "\n \"${item}\",")
endforeach()
get_filename_component(SYS_INCLUDE_PATH ${CMAKE_C_COMPILER} DIRECTORY)
string(APPEND C_CPP_PROPERTIES_INCLUDE_IN "\n \"${SYS_INCLUDE_PATH}/../riscv64-unknown-elf/include\",")
get_filename_component(BL_SDK_CMAKE_DIR ${BL_SDK_BASE}/cmake/extension.cmake ABSOLUTE)
get_filename_component(BL_SDK_CMAKE_DIR ${BL_SDK_CMAKE_DIR} DIRECTORY)
if(VSCODE_DIR)
set(VSCODE_DIR_ ${VSCODE_DIR}/.vscode)
else()
set(VSCODE_DIR_ ${BL_SDK_CMAKE_DIR}/../.vscode)
endif()
configure_file(${BL_SDK_BASE}/tools/vscode/c_cpp_properties.json ${VSCODE_DIR_}/c_cpp_properties.json)

17
drivers/lhal/CMakeLists.txt
View File

@ -23,6 +23,11 @@ src/bflb_spi.c
src/bflb_timer.c
src/bflb_uart.c
src/bflb_wdg.c
src/bflb_flash.c
src/flash/bflb_sf_cfg.c
src/flash/bflb_xip_sflash.c
src/flash/bflb_sflash.c
src/flash/bflb_sf_ctrl.c
)
if("${CHIP}" STREQUAL "bl602")
@ -38,12 +43,13 @@ src/bflb_emac.c
src/bflb_ir.c
src/bflb_pwm_v1.c
src/bflb_cam.c
src/bflb_spi_psram.c
)
elseif("${CHIP}" STREQUAL "bl702l")
sdk_library_add_sources(
src/bflb_kys.c
src/bflb_pwm_v1.c
src/bflb_pwm_v2.c
src/bflb_spi_psram.c
)
elseif("${CHIP}" STREQUAL "bl616")
sdk_library_add_sources(
@ -54,6 +60,7 @@ src/bflb_mjpeg.c
src/bflb_pwm_v2.c
src/bflb_cam.c
src/bflb_iso11898.c
src/bflb_i2s.c
)
elseif("${CHIP}" STREQUAL "bl628")
sdk_library_add_sources(
@ -72,6 +79,8 @@ src/bflb_mjpeg.c
src/bflb_pwm_v2.c
src/bflb_cam.c
src/bflb_iso11898.c
src/bflb_csi.c
src/bflb_i2s.c
)
endif()
@ -96,6 +105,7 @@ sdk_add_include_directories(include/arch)
sdk_add_include_directories(include/arch/risc-v/t-head)
sdk_add_include_directories(include/arch/risc-v/t-head/Core/Include)
sdk_add_include_directories(config/${CHIP})
sdk_add_include_directories(src/flash)
if((NOT ("${CHIP}" STREQUAL "bl702")) AND (NOT ("${CHIP}" STREQUAL "bl602")) AND (NOT ("${CHIP}" STREQUAL "bl702l")))
sdk_library_add_sources(include/arch/risc-v/t-head/rv_hart.c)
@ -113,4 +123,7 @@ sdk_add_compile_definitions(-DCPU_${CPU_ID_NAME})
endif()
sdk_add_static_library(src/pka/libpka.a)
#add_subdirectory(src/pka)
# add_subdirectory(src/pka)
if(("${CHIP}" STREQUAL "bl616") OR ("${CHIP}" STREQUAL "bl628"))
# keep
endif()

41
drivers/lhal/bouffalo.mk
View File

@ -1,41 +0,0 @@
# Component Makefile
#
## These include paths would be exported to project level
COMPONENT_ADD_INCLUDEDIRS += include
COMPONENT_ADD_INCLUDEDIRS += include/arch
COMPONENT_ADD_INCLUDEDIRS += include/arch/risc-v/t-head
COMPONENT_ADD_INCLUDEDIRS += include/arch/risc-v/t-head/Core/Include
## not be exported to project level
COMPONENT_PRIV_INCLUDEDIRS :=
## This component's src
COMPONENT_SRCS := src/bflb_gpio.c \
src/bflb_irq.c \
src/bflb_l1c.c \
src/bflb_mtimer.c \
src/bflb_sec_aes.c \
src/bflb_uart.c \
CHIP_NAME = $(shell echo $(CONFIG_CHIP_NAME) | tr A-Z a-z)
COMPONENT_SRCS += config/$(CHIP_NAME)/device_table.c
COMPONENT_ADD_INCLUDEDIRS += config/$(CHIP_NAME)
CFLAGS += -D$(CONFIG_CHIP_NAME)
CFLAGS += -DCONFIG_IRQ_NUM=80
CFLAGS += -DBL_IOT_SDK
ifeq ($(CONFIG_CHIP_NAME),BL616)
COMPONENT_SRCS += include/arch/risc-v/t-head/rv_hart.c
COMPONENT_SRCS += include/arch/risc-v/t-head/rv_pmp.c
ifeq ($(CONFIG_CHERRYUSB),1)
COMPONENT_SRCS += src/bflb_usb_v2.c
endif
endif
COMPONENT_OBJS := $(patsubst %.c,%.o, $(COMPONENT_SRCS))
COMPONENT_SRCDIRS := src include/arch/risc-v/t-head config/$(CHIP_NAME)

2
drivers/lhal/config/bl616/bl616_irq.h
View File

@ -62,7 +62,7 @@
#define BL616_IRQ_TIMER1 (BL616_IRQ_NUM_BASE + 37)
#define BL616_IRQ_WDG (BL616_IRQ_NUM_BASE + 38)
#define BL616_IRQ_I2C1 (BL616_IRQ_NUM_BASE + 39)
#define BL616_IRQ_I2CS (BL616_IRQ_NUM_BASE + 40)
#define BL616_IRQ_I2S (BL616_IRQ_NUM_BASE + 40)
#define BL616_IRQ_ANA_OCP_OUT_TO_CPU_0 (BL616_IRQ_NUM_BASE + 41)
#define BL616_IRQ_ANA_OCP_OUT_TO_CPU_1 (BL616_IRQ_NUM_BASE + 42)
#define BL616_IRQ_XTAL_RDY_SCAN (BL616_IRQ_NUM_BASE + 43)

7
drivers/lhal/config/bl616/device_table.c
View File

@ -121,6 +121,13 @@ struct bflb_device_s bl616_device_table[] = {
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_I2C,
.user_data = NULL },
{ .name = "i2s0",
.reg_base = I2S_BASE,
.irq_num = BL616_IRQ_I2S,
.idx = 0,
.sub_idx = 0,
.dev_type = BFLB_DEVICE_TYPE_I2S,
.user_data = NULL },
{ .name = "timer0",
.reg_base = TIMER_BASE,
.irq_num = BL616_IRQ_TIMER0,

92
drivers/lhal/include/bflb_cam.h
View File

@ -193,120 +193,120 @@ extern "C" {
#endif
/**
* @brief
* @brief Initialize cam.
*
* @param [in] dev
* @param [in] config
* @param [in] dev device handle
* @param [in] config pointer to cam configure structure
*/
void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config);
/**
* @brief
* @brief Enable cam.
*
* @param [in] dev
* @param [in] dev device handle
*/
void bflb_cam_start(struct bflb_device_s *dev);
/**
* @brief
* @brief Disable cam.
*
* @param [in] dev
* @param [in] dev device handle
*/
void bflb_cam_stop(struct bflb_device_s *dev);
/**
* @brief
* @brief Mask or unmask cam interrupt.
*
* @param [in] dev
* @param [in] int_type
* @param [in] mask
* @param [in] dev device handle
* @param [in] int_type cam interrupt mask type, use @ref CAM_INTMASK
* @param [in] mask mask or unmask
*/
void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
/**
* @brief
* @brief Clear cam interrupt.
*
* @param [in] dev
* @param [in] int_type
* @param [in] dev device handle
* @param [in] int_type int_type cam interrupt clear type, use @ref CAM_INTCLR
*/
void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type);
/**
* @brief
* @brief Crop vsync.
*
* @param [in] dev
* @param [in] start_line
* @param [in] end_line
* @param [in] dev device handle
* @param [in] start_line start line of window
* @param [in] end_line end line of window, not include
*/
void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line);
/**
* @brief
* @brief Crop hsync.
*
* @param [in] dev
* @param [in] start_pixel
* @param [in] end_pixel
* @param [in] dev device handle
* @param [in] start_pixel start pixel of each line
* @param [in] end_pixel end pixel of each line, not include
*/
void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel);
/**
* @brief
* @brief Pop one frame.
*
* @param [in] dev
* @param [in] dev device handle
*/
void bflb_cam_pop_one_frame(struct bflb_device_s *dev);
#if !defined(BL702)
/**
* @brief
* @brief Swap input order of y and uv.
*
* @param [in] dev
* @param [in] enable
* @param [in] dev device handle
* @param [in] enable enable or disable
*/
void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable);
/**
* @brief
* @brief Set frame filter, if frame_count = 3, frame_valid = 101b, second frame will be dropped every 3 frames.
*
* @param [in] dev
* @param [in] frame_count
* @param [in] frame_valid
* @param [in] dev device handle
* @param [in] frame_count frame filter period
* @param [in] frame_valid frame valid
*/
void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid);
#endif
/**
* @brief
* @brief Get frame count.
*
* @param [in] dev
* @return uint8_t
* @param [in] dev device handle
* @return Frame count
*/
uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev);
/**
* @brief
* @brief Get frame information.
*
* @param [in] dev
* @param [in] pic
* @return uint32_t
* @param [in] dev device handle
* @param [out] pic pointer to frame start address
* @return Size of frame
*/
uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
/**
* @brief
* @brief Get interrupt status.
*
* @param [in] dev
* @return uint32_t
* @param [in] dev device handle
* @return Interrupt status
*/
uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev);
/**
* @brief
* @brief Control cam feature.
*
* @param [in] dev
* @param [in] cmd
* @param [in] arg
* @return int
* @param [in] dev device handle
* @param [in] cmd feature command
* @param [in] arg user data
* @return A negated errno value on failure
*/
int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);

158
drivers/lhal/include/bflb_csi.h Normal file
View File

@ -0,0 +1,158 @@
#ifndef _BFLB_CSI_H
#define _BFLB_CSI_H
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup CSI
* @{
*/
/** @defgroup CSI_LANE_NUMBER CSI lane number definition
* @{
*/
#define CSI_LANE_NUMBER_1 0
#define CSI_LANE_NUMBER_2 1
/**
* @}
*/
/** @defgroup CSI_INTSTS CSI interrupt status definition
* @{
*/
#define CSI_INTSTS_GENERIC_PACKET (1 << 0)
#define CSI_INTSTS_LANE_MERGE_ERROR (1 << 1)
#define CSI_INTSTS_ECC_ERROR (1 << 2)
#define CSI_INTSTS_CRC_ERROR (1 << 3)
#define CSI_INTSTS_PHY_HS_SOT_ERROR (1 << 4)
#define CSI_INTSTS_PHY_HS_SOT_SYNC_ERROR (1 << 5)
/**
* @}
*/
/** @defgroup CSI_INTMASK CSI interrupt mask definition
* @{
*/
#define CSI_INTMASK_GENERIC_PACKET (1 << 0)
#define CSI_INTMASK_LANE_MERGE_ERROR (1 << 1)
#define CSI_INTMASK_ECC_ERROR (1 << 2)
#define CSI_INTMASK_CRC_ERROR (1 << 3)
#define CSI_INTMASK_PHY_HS_SOT_ERROR (1 << 4)
#define CSI_INTMASK_PHY_HS_SOT_SYNC_ERROR (1 << 5)
/**
* @}
*/
/** @defgroup CSI_INTCLR CSI interrupt clear definition
* @{
*/
#define CSI_INTCLR_GENERIC_PACKET (1 << 0)
#define CSI_INTCLR_LANE_MERGE_ERROR (1 << 1)
#define CSI_INTCLR_ECC_ERROR (1 << 2)
#define CSI_INTCLR_CRC_ERROR (1 << 3)
#define CSI_INTCLR_PHY_HS_SOT_ERROR (1 << 4)
#define CSI_INTCLR_PHY_HS_SOT_SYNC_ERROR (1 << 5)
/**
* @}
*/
/**
* @brief CSI configuration structure
*
* @param lane_number CSI lane number, use @ref CSI_LANE_NUMBER
* @param tx_clk_escape CSI tx clock in escape mode
* @param data_rate CSI data rate
*/
struct bflb_csi_config_s {
uint8_t lane_number;
uint32_t tx_clk_escape;
uint32_t data_rate;
};
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize csi.
*
* @param [in] dev device handle
* @param [in] config pointer to csi configure structure
*/
void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config);
/**
* @brief Enable csi.
*
* @param [in] dev device handle
*/
void bflb_csi_start(struct bflb_device_s *dev);
/**
* @brief Disable csi.
*
* @param [in] dev device handle
*/
void bflb_csi_stop(struct bflb_device_s *dev);
/**
* @brief Set threshold of line buffer, data will be sent to following module when threshold reached.
*
* @param [in] dev device handle
* @param [in] resolution_x number of columns
* @param [in] pixel_clock pixel clock
* @param [in] dsp_clock dsp clock
*/
void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock);
/**
* @brief Mask or unmask csi interrupt.
*
* @param [in] dev device handle
* @param [in] int_type csi interrupt mask type, use @ref CSI_INTMASK
* @param [in] mask mask or unmask
*/
void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
/**
* @brief Clear csi interrupt.
*
* @param [in] dev device handle
* @param [in] int_type csi interrupt clear type, use @ref CSI_INTCLR
*/
void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type);
/**
* @brief Get csi interrupt status.
*
* @param [in] dev device handle
* @return Interrupt status
*/
uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Control csi feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command
* @param [in] arg user data
* @return A negated errno value on failure
*/
int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

3
drivers/lhal/include/bflb_dma.h
View File

@ -144,7 +144,8 @@
#define DMA_REQUEST_I2C0_TX 0x00000007
#define DMA_REQUEST_SPI0_RX 0x0000000A
#define DMA_REQUEST_SPI0_TX 0x0000000B
#define DMA_REQUEST_AUDIO_TX 0x0000000D
#define DMA_REQUEST_AUADC_RX 0x00000015
#define DMA_REQUEST_AUDAC_TX 0x0000000D
#define DMA_REQUEST_I2S_RX 0x00000010
#define DMA_REQUEST_I2S_TX 0x00000011
#define DMA_REQUEST_ADC 0x00000016

1
drivers/lhal/include/bflb_flash.h
View File

@ -2,6 +2,7 @@
#define _BFLB_FLASH_H
#include "bflb_core.h"
#include "bflb_sflash.h"
/** @addtogroup LHAL
* @{

34
drivers/lhal/include/bflb_gpio.h
View File

@ -119,6 +119,7 @@
#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_AUDAC_PWM (25 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
#elif defined(BL606P) || defined(BL808)
#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT)
@ -156,6 +157,7 @@
#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT)
#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
#endif
@ -282,6 +284,38 @@ void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin);
*/
bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin);
/**
* @brief Write gpio pin 0~31.
*
* @param [in] dev device handle
* @param [in] val gpio pin 0~31 value
*/
void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val);
/**
* @brief Write gpio pin 32~63.
*
* @param [in] dev device handle
* @param [in] val gpio pin 32~63 value
*/
void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val);
/**
* @brief Read level from gpio pin 0~31.
*
* @param [in] dev device handle
* @return level of gpio pin 0~31
*/
uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev);
/**
* @brief Read level from gpio pin 32~63.
*
* @param [in] dev device handle
* @return level of gpio pin32~63
*/
uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev);
/**
* @brief Config gpio pin interrupt.
*

204
drivers/lhal/include/bflb_i2s.h Normal file
View File

@ -0,0 +1,204 @@
#ifndef _BFLB_I2S_H
#define _BFLB_I2S_H
#include "bflb_core.h"
/** @addtogroup LHAL
* @{
*/
/** @addtogroup I2S
* @{
*/
/** @defgroup I2S_ROLE i2s role definition
* @{
*/
#define I2S_ROLE_MASTER 0
#define I2S_ROLE_SLAVE 1
/**
* @}
*/
/** @defgroup I2S_FORMAT_MODE i2s mode definition
* @{
*/
#define I2S_MODE_LEFT_JUSTIFIED 0 /* left-justified or Phillips standard */
#define I2S_MODE_RIGHT_JUSTIFIED 1 /* right-justified */
#define I2S_MODE_DSP_SHORT_FRAME_SYNC 2 /* dsp modeA/B short frame sync */
#define I2S_MODE_DSP_LONG_FRAME_SYNC 3 /* dsp modeA/B long frame sync */
/**
* @}
*/
/** @defgroup I2S_CHANNEL_MODE i2s mode definition
* @{
*/
#define I2S_CHANNEL_MODE_NUM_1 0
#define I2S_CHANNEL_MODE_NUM_2 1
#define I2S_CHANNEL_MODE_NUM_3 2 /* only DSP mode, frame_size must equal data_size */
#define I2S_CHANNEL_MODE_NUM_4 3 /* only DSP mode, frame_size must equal data_size */
#define I2S_CHANNEL_MODE_NUM_6 4 /* only DSP mode, frame_size must equal data_size */
/**
* @}
*/
/** @defgroup I2S_SLOT_WIDTH i2s slot width definition
* @{
*/
#define I2S_SLOT_WIDTH_8 0
#define I2S_SLOT_WIDTH_16 1
#define I2S_SLOT_WIDTH_24 2
#define I2S_SLOT_WIDTH_32 3
/**
* @}
*/
/** @defgroup I2S_INTSTS i2s interrupt status definition
* @{
*/
#define I2S_INTSTS_TX_FIFO (1 << 1)
#define I2S_INTSTS_RX_FIFO (1 << 2)
#define I2S_INTSTS_FIFO_ERR (1 << 3)
/**
* @}
*/
/** @defgroup I2S_CMD i2s feature control cmd definition
* @{
*/
#define I2S_CMD_CLEAR_TX_FIFO (0x01)
#define I2S_CMD_CLEAR_RX_FIFO (0x02)
#define I2S_CMD_RX_DEGLITCH (0x03)
#define I2S_CMD_DATA_ENABLE (0x04)
#define I2S_CMD_CHANNEL_LR_MERGE (0x05)
#define I2S_CMD_CHANNEL_LR_EXCHG (0x06)
#define I2S_CMD_MUTE (0x07)
#define I2S_CMD_BIT_REVERSE (0x08)
/** @defgroup I2S_CMD_DATA_ENABLE_TYPE i2s data enable type
* @{
*/
#define I2S_CMD_DATA_ENABLE_TX (1 << 1)
#define I2S_CMD_DATA_ENABLE_RX (1 << 2)
/**
* @}
*/
/**
* @brief I2S configuration structure
*
* @param bclk_freq_hz I2S bit frequence, Sampling_rate = bclk_freq_hz / frame_width / channel_num.
* @param role I2S role, use @ref I2S_ROLE
* @param format_mode I2S mode, use @ref I2S_FORMAT_MODE
* @param channel_mode I2S channel num, Only DSP mode supports more than 2 channels, use @ref I2S_CHANNEL_MODE
* @param frame_width I2S frame width, use @ref I2S_SLOT_WIDTH
* @param data_width I2S data order, frame_size must equal data_size in 3/4/6-channel mode, use @ref I2S_SLOT_WIDTH
* @param fs_offset_cycle I2S first bit offset of the data
* @param tx_fifo_threshold I2S tx fifo threshold, should be less than 16
* @param rx_fifo_threshold I2S rx fifo threshold, should be less than 16
*/
struct bflb_i2s_config_s {
uint32_t bclk_freq_hz;
uint8_t role;
uint8_t format_mode;
uint8_t channel_mode;
uint8_t frame_width;
uint8_t data_width;
uint8_t fs_offset_cycle;
uint8_t tx_fifo_threshold;
uint8_t rx_fifo_threshold;
};
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Initialize i2s.
*
* @param [in] dev device handle
* @param [in] config pointer to save i2s config
*/
void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config);
/**
* @brief Deinitialize i2s.
*
* @param [in] dev device handle
*/
void bflb_i2s_deinit(struct bflb_device_s *dev);
/**
* @brief Enable i2s tx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Enable i2s rx dma.
*
* @param [in] dev device handle
* @param [in] enable true means enable, otherwise disable.
*/
void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable);
/**
* @brief Enable or disable i2s rx fifo threhold interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable i2s rx fifo threhold interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Enable or disable i2s error interrupt.
*
* @param [in] dev device handle
* @param [in] mask true means disable, false means enable
*/
void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask);
/**
* @brief Get i2s interrupt status.
*
* @param [in] dev device handle
* @return interrupt status, use @ref I2S_INTSTS
*/
uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev);
/**
* @brief Control i2s feature.
*
* @param [in] dev device handle
* @param [in] cmd feature command, use @ref I2S_CMD
* @param [in] arg user data
* @return A negated errno value on failure.
*/
int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
/**
* @}
*/
#endif

136
drivers/lhal/include/bflb_ir.h
View File

@ -102,7 +102,7 @@
/**
* @brief IR TX configuration structure
*
* @param tx_mode TX mode select,NEC protocol/RC-5 protocol/software mode/customize
* @param tx_mode TX mode select, use @ref IR_TX_MODE
* @param data_bits Bit count of data phase (don't care if tx freerun mode is enabled)
* @param tail_inverse Enable or disable signal of tail pulse inverse (don't care if SWM is enabled)
* @param tail_enable Enable or disable signal of tail pulse (don't care if SWM is enabled)
@ -116,7 +116,7 @@
* @param output_inverse Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high
* @param freerun_enable Enable or disable tx freerun mode (don't care if SWM is enabled)
* @param continue_enable Disable:idle time between frames = (tailPulseWidth_0+tailPulseWidth_1)*pulseWidthUnit,Enable:no idle time between frames
* @param fifo_width IR frame size(also the valid width for each fifo entry)
* @param fifo_width IR frame size(also the valid width for each fifo entry), use @ref IR_TX_FIFO_WIDTH
* @param fifo_threshold TX FIFO threshold
* @param logic0_pulse_width_1 Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled)
* @param logic0_pulse_width_0 Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled)
@ -165,7 +165,7 @@ struct bflb_ir_tx_config_s {
/**
* @brief IR RX configuration structure
*
* @param rx_mode RX mode select,NEC protocol/RC-5 protocol/software mode
* @param rx_mode RX mode select, use @ref IR_RX_MODE
* @param input_inverse Enable or disable signal of input inverse
* @param deglitch_enable Enable or disable signal of rx input de-glitch function
* @param deglitch_cnt De-glitch function cycle count
@ -190,84 +190,84 @@ extern "C" {
#if !defined(BL616)
/**
* @brief
* @brief Initialize ir tx.
*
* @param [in] dev
* @param [in] config
* @param [in] dev device handle
* @param [in] config pointer to ir tx configure structure
*/
void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config);
/**
* @brief
* @brief Send data in NEC/RC5/customize mode.
*
* @param [in] dev
* @param [in] data
* @param [in] length
* @param [in] dev device handle
* @param [in] data data buffer to send
* @param [in] length length of data buffer
*/
void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length);
/**
* @brief
* @brief Send data in software mode.
*
* @param [in] dev
* @param [in] data
* @param [in] length
* @param [in] dev device handle
* @param [in] data data data buffer to send
* @param [in] length length of data buffer
*/
void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
/**
* @brief
* @brief Enable or disable ir tx.
*
* @param [in] dev
* @param [in] enable
* @param [in] dev device handle
* @param [in] enable enable or disable
*/
void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable);
/**
* @brief
* @brief Mask or unmask ir tx interrupt.
*
* @param [in] dev
* @param [in] int_type
* @param [in] mask
* @param [in] dev device handle
* @param [in] int_type ir tx interrupt type, use @ref IR_TX_INTEN
* @param [in] mask mask or unmask
*/
void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
/**
* @brief
* @brief Get ir tx interrupt status.
*
* @param [in] dev
* @return uint32_t
* @param [in] dev device handle
* @return Ir tx interrupt status
*/
uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev);
/**
* @brief
* @brief Clear ir tx interrupt.
*
* @param [in] dev
* @param [in] dev device handle
*/
void bflb_ir_txint_clear(struct bflb_device_s *dev);
#if !defined(BL602) && !defined(BL702)
/**
* @brief
* @brief Enable or disable ir tx dma mode.
*
* @param [in] dev
* @param [in] enable
* @param [in] dev device handle
* @param [in] enable enable or disable
*/
void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable);
/**
* @brief
* @brief Get ir tx fifo available count.
*
* @param [in] dev
* @return uint8_t
* @param [in] dev device handle
* @return Ir tx fifo available count
*/
uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev);
/**
* @brief
* @brief Clear ir tx fifo.
*
* @param [in] dev
* @param [in] dev device handle
*/
void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
#endif
@ -275,88 +275,88 @@ void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
#if !defined(BL702L)
/**
* @brief
* @brief Initialize ir rx.
*
* @param [in] dev
* @param [in] config
* @param [in] dev device handle
* @param [in] config config pointer to ir rx configure structure
*/
void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config);
/**
* @brief
* @brief Receive data in NEC/RC5/customize mode.
*
* @param [in] dev
* @param [in] data
* @return uint8_t
* @param [in] dev device handle
* @param [out] data data received
* @return Bit count of data received
*/
uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data);
/**
* @brief
* @brief Receive data in software mode.
*
* @param [in] dev
* @param [in] data
* @param [in] length
* @return uint8_t
* @param [in] dev device handle
* @param [out] data data buffer to receive
* @param [in] length of data buffer
* @return Length of data received
*/
uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
/**
* @brief
* @brief Enable or disable ir rx.
*
* @param [in] dev
* @param [in] enable
* @param [in] dev device handle
* @param [in] enable enable or disable
*/
void bflb_ir_rx_enable(struct bflb_device_s *dev, bool enable);
/**
* @brief
* @brief Get ir rx fifo available count.
*
* @param [in] dev
* @return uint8_t
* @param [in] dev device handle
* @return Ir rx fifo available count
*/
uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev);
/**
* @brief
* @brief Clear ir rx fifo.
*
* @param [in] dev
* @param [in] dev device handle
*/
void bflb_ir_rxfifo_clear(struct bflb_device_s *dev);
/**
* @brief
* @brief Mask ir rx interrupt.
*
* @param [in] dev
* @param [in] int_type
* @param [in] mask
* @param [in] dev device handle
* @param [in] int_type ir rx interrupt type, use @ref IR_RX_INTEN
* @param [in] mask mask or unmask
*/
void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
/**
* @brief
* @brief Get ir rx interrupt status.
*
* @param [in] dev
* @return uint32_t
* @param [in] dev device handle
* @return Ir rx interrupt status
*/
uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev);
/**
* @brief
* @brief Clear ir rx interrupt.
*
* @param [in] dev
* @param [in] dev device handle
*/
void bflb_ir_rxint_clear(struct bflb_device_s *dev);
#endif
/**
* @brief
* @brief Control ir feature.
*
* @param [in] dev
* @param [in] cmd
* @param [in] arg
* @return int
* @param [in] dev device handle
* @param [in] cmd feature command
* @param [in] arg user data
* @return A negated errno value on failure
*/
int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);

4
drivers/lhal/include/bflb_l1c.h
View File

@ -83,6 +83,10 @@ void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size);
*/
void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size);
void bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high);
uint32_t bflb_l1c_miss_count_get(void);
void bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en);
/**
* @}
*/

152
drivers/lhal/include/bflb_spi_psram.h Normal file
View File

@ -0,0 +1,152 @@
/**
******************************************************************************
* @file bflb_spi_psram.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BFLB_SPI_PSRAM_H__
#define __BFLB_SPI_PSRAM_H__
#include "sf_ctrl_reg.h"
#include "bflb_common.h"
#include "bflb_sf_ctrl.h"
/** @addtogroup BFLB_Peripheral_Driver
* @{
*/
/** @addtogroup PSRAM
* @{
*/
/** @defgroup PSRAM_Public_Types
* @{
*/
/**
* @brief Psram drive strength type definition
*/
#define PSRAM_DRIVE_STRENGTH_50_OHMS 0 /*!< Drive strength 50 ohms(default) */
#define PSRAM_DRIVE_STRENGTH_100_OHMS 1 /*!< Drive strength 100 ohms */
#define PSRAM_DRIVE_STRENGTH_200_OHMS 2 /*!< Drive strength 200 ohms */
/**
* @brief Psram burst length size type definition
*/
#define PSRAM_BURST_LENGTH_16_BYTES 0 /*!< Burst Length 16 bytes */
#define PSRAM_BURST_LENGTH_32_BYTES 1 /*!< Burst Length 32 bytes */
#define PSRAM_BURST_LENGTH_64_BYTES 2 /*!< Burst Length 64 bytes */
#define PSRAM_BURST_LENGTH_512_BYTES 3 /*!< Burst Length 512 bytes(default) */
/**
* @brief Psram ctrl mode type definition
*/
#define PSRAM_SPI_CTRL_MODE 0 /*!< Psram SPI ctrl mode */
#define PSRAM_QPI_CTRL_MODE 1 /*!< Psram QPI ctrl mode */
/**
* @brief Psram ctrl configuration structure type definition
*/
struct spi_psram_cfg_type {
uint8_t read_id_cmd; /*!< Read ID command */
uint8_t read_id_dmy_clk; /*!< Read ID command dummy clock */
uint8_t burst_toggle_cmd; /*!< Burst toggle length command */
uint8_t reset_enable_cmd; /*!< Psram reset enable command */
uint8_t reset_cmd; /*!< Psram reset command */
uint8_t enter_quad_mode_cmd; /*!< Psram enter quad mode command */
uint8_t exit_quad_mode_cmd; /*!< Psram exit quad mode command */
uint8_t read_reg_cmd; /*!< Read register command */
uint8_t read_reg_dmy_clk; /*!< Read register command dummy clock */
uint8_t write_reg_cmd; /*!< Write register command */
uint8_t read_cmd; /*!< Psram read command */
uint8_t read_dmy_clk; /*!< Psram read command dummy clock */
uint8_t f_read_cmd; /*!< Psram fast read command */
uint8_t f_read_dmy_clk; /*!< Psram fast read command dummy clock */
uint8_t f_read_quad_cmd; /*!< Psram fast read quad command */
uint8_t f_read_quad_dmy_clk; /*!< Psram fast read quad command dummy clock */
uint8_t write_cmd; /*!< Psram write command */
uint8_t quad_write_cmd; /*!< Psram quad write command */
uint16_t page_size; /*!< Psram page size */
#if defined(BL702L)
uint8_t burst_toggle_en; /*!< Psram burst toggle mode enable */
#endif
uint8_t ctrl_mode; /*!< Psram ctrl mode */
uint8_t drive_strength; /*!< Psram drive strength */
uint8_t burst_length; /*!< Psram burst length size */
};
/*@} end of group PSRAM_Public_Types */
/** @defgroup PSRAM_Public_Constants
* @{
*/
/*@} end of group PSRAM_Public_Constants */
/** @defgroup PSRAM_Public_Macros
* @{
*/
/*@} end of group PSRAM_Public_Macros */
/** @defgroup PSRAM_Public_Functions
* @{
*/
/**
* @brief PSRAM Functions
*/
void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg,
struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg);
void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
int bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg);
int bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg);
void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data);
int bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg);
int bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg);
int bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
int bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
int bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint32_t len);
int bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint8_t wt_en,
uint8_t wb_en, uint8_t wa_en);
int bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
int bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
/*@} end of group PSRAM_Public_Functions */
/*@} end of group PSRAM */
/*@} end of group BFLB_Peripheral_Driver */
#endif /* __BFLB_SPI_PSRAM_H__ */

5
drivers/lhal/include/bflb_timer.h
View File

@ -184,6 +184,11 @@ bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no);
*/
void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no);
#if !defined(BL702) || !defined(BL602)
void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config);
uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev);
#endif
#ifdef __cplusplus
}
#endif

165
drivers/lhal/include/hardware/csi_reg.h Normal file
View File

@ -0,0 +1,165 @@
/**
******************************************************************************
* @file csi_reg.h
* @version V1.0
* @date 2022-12-13
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_CSI_H__
#define __HARDWARE_CSI_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define CSI_MIPI_CONFIG_OFFSET (0x0)/* mipi_config */
#define CSI_INT_STATUS_OFFSET (0x10)/* csi_int_status */
#define CSI_INT_MASK_OFFSET (0x14)/* csi_int_mask */
#define CSI_INT_CLEAR_OFFSET (0x18)/* csi_int_clear */
#define CSI_INT_ENABLE_OFFSET (0x1C)/* csi_int_enable */
#define CSI_GNR_BUF_STATUS_OFFSET (0x20)/* gnr_buf_status */
#define CSI_GNR_BUF_RDATA_OFFSET (0x24)/* gnr_buf_rdata */
#define CSI_DPHY_CONFIG_0_OFFSET (0x80)/* dphy_config_0 */
#define CSI_DPHY_CONFIG_1_OFFSET (0x84)/* dphy_config_1 */
#define CSI_DPHY_CONFIG_2_OFFSET (0x88)/* dphy_config_2 */
#define CSI_DPHY_CONFIG_3_OFFSET (0x8C)/* dphy_config_3 */
#define CSI_DPHY_CONFIG_4_OFFSET (0x90)/* dphy_config_4 */
#define CSI_DPHY_CONFIG_5_OFFSET (0x94)/* dphy_config_5 */
#define CSI_DUMMY_REG_OFFSET (0xFC)/* dummy_reg */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : mipi_config */
#define CSI_CR_CSI_EN (1<<0U)
#define CSI_CR_LANE_NUM (1<<1U)
#define CSI_CR_LANE_INV (1<<3U)
#define CSI_CR_DATA_BIT_INV (1<<4U)
#define CSI_CR_SYNC_SP_EN (1<<5U)
#define CSI_CR_UNPACK_EN (1<<6U)
#define CSI_CR_VC_DVP0_SHIFT (12U)
#define CSI_CR_VC_DVP0_MASK (0x3<<CSI_CR_VC_DVP0_SHIFT)
#define CSI_CR_VC_DVP1_SHIFT (14U)
#define CSI_CR_VC_DVP1_MASK (0x3<<CSI_CR_VC_DVP1_SHIFT)
/* 0x10 : csi_int_status */
#define CSI_INT_STATUS_SHIFT (0U)
#define CSI_INT_STATUS_MASK (0x3f<<CSI_INT_STATUS_SHIFT)
/* 0x14 : csi_int_mask */
#define CSI_INT_MASK_SHIFT (0U)
#define CSI_INT_MASK_MASK (0x3f<<CSI_INT_MASK_SHIFT)
/* 0x18 : csi_int_clear */
#define CSI_INT_CLEAR_SHIFT (0U)
#define CSI_INT_CLEAR_MASK (0x3f<<CSI_INT_CLEAR_SHIFT)
/* 0x1C : csi_int_enable */
#define CSI_INT_ENABLE_SHIFT (0U)
#define CSI_INT_ENABLE_MASK (0x3f<<CSI_INT_ENABLE_SHIFT)
/* 0x20 : gnr_buf_status */
#define CSI_ST_GNR_FIFO_CNT_SHIFT (0U)
#define CSI_ST_GNR_FIFO_CNT_MASK (0xf<<CSI_ST_GNR_FIFO_CNT_SHIFT)
/* 0x24 : gnr_buf_rdata */
#define CSI_GNR_BUF_RDATA_SHIFT (0U)
#define CSI_GNR_BUF_RDATA_MASK (0xffffffff<<CSI_GNR_BUF_RDATA_SHIFT)
/* 0x80 : dphy_config_0 */
#define CSI_DL0_ENABLE (1<<0U)
#define CSI_DL1_ENABLE (1<<1U)
#define CSI_CL_ENABLE (1<<2U)
#define CSI_DL0_STOPSTATE (1<<4U)
#define CSI_DL1_STOPSTATE (1<<5U)
#define CSI_CL_STOPSTATE (1<<6U)
#define CSI_DL0_ULPSACTIVENOT (1<<8U)
#define CSI_DL1_ULPSACTIVENOT (1<<9U)
#define CSI_CL_ULPSACTIVENOT (1<<10U)
#define CSI_DL0_FORCERXMODE (1<<12U)
#define CSI_DL1_FORCERXMODE (1<<13U)
#define CSI_CL_RXCLKACTIVEHS (1<<14U)
#define CSI_CL_RXULPSCLKNOT (1<<15U)
#define CSI_RESET_N (1<<31U)
/* 0x84 : dphy_config_1 */
#define CSI_REG_TIME_CK_SETTLE_SHIFT (0U)
#define CSI_REG_TIME_CK_SETTLE_MASK (0xff<<CSI_REG_TIME_CK_SETTLE_SHIFT)
#define CSI_REG_TIME_CK_TERM_EN_SHIFT (8U)
#define CSI_REG_TIME_CK_TERM_EN_MASK (0xff<<CSI_REG_TIME_CK_TERM_EN_SHIFT)
#define CSI_REG_TIME_HS_SETTLE_SHIFT (16U)
#define CSI_REG_TIME_HS_SETTLE_MASK (0xff<<CSI_REG_TIME_HS_SETTLE_SHIFT)
#define CSI_REG_TIME_HS_TERM_EN_SHIFT (24U)
#define CSI_REG_TIME_HS_TERM_EN_MASK (0xff<<CSI_REG_TIME_HS_TERM_EN_SHIFT)
/* 0x88 : dphy_config_2 */
#define CSI_REG_ANA_LPRXEN_CLK (1<<0U)
#define CSI_REG_ANA_HSRXEN_CLK (1<<1U)
#define CSI_REG_ANA_HSRX_STOP_STATE_SHIFT (2U)
#define CSI_REG_ANA_HSRX_STOP_STATE_MASK (0x3<<CSI_REG_ANA_HSRX_STOP_STATE_SHIFT)
#define CSI_REG_ANA_HSRX_SYNC_EN_SHIFT (4U)
#define CSI_REG_ANA_HSRX_SYNC_EN_MASK (0x3<<CSI_REG_ANA_HSRX_SYNC_EN_SHIFT)
#define CSI_REG_ANA_LPRXEN_SHIFT (6U)
#define CSI_REG_ANA_LPRXEN_MASK (0x3<<CSI_REG_ANA_LPRXEN_SHIFT)
#define CSI_REG_ANA_HSRXEN_SHIFT (8U)
#define CSI_REG_ANA_HSRXEN_MASK (0x3<<CSI_REG_ANA_HSRXEN_SHIFT)
#define CSI_REG_ANA_TERM_EN_SHIFT (10U)
#define CSI_REG_ANA_TERM_EN_MASK (0x1f<<CSI_REG_ANA_TERM_EN_SHIFT)
#define CSI_REG_ANA_TEST_EN (1<<15U)
#define CSI_REG_PT_LOCK_COUNTER_SHIFT (16U)
#define CSI_REG_PT_LOCK_COUNTER_MASK (0xf<<CSI_REG_PT_LOCK_COUNTER_SHIFT)
#define CSI_REG_PT_PRBS_OR_JITT (1<<20U)
#define CSI_REG_PT_LP_MODE (1<<21U)
#define CSI_REG_PT_EN (1<<22U)
#define CSI_REG_PT_LOCK (1<<23U)
#define CSI_REG_PT_PASS (1<<24U)
/* 0x8C : dphy_config_3 */
#define CSI_REG_CSI_ANA_1_SHIFT (0U)
#define CSI_REG_CSI_ANA_1_MASK (0xffff<<CSI_REG_CSI_ANA_1_SHIFT)
#define CSI_REG_CSI_ANA_0_SHIFT (16U)
#define CSI_REG_CSI_ANA_0_MASK (0xffff<<CSI_REG_CSI_ANA_0_SHIFT)
/* 0x90 : dphy_config_4 */
#define CSI_REG_CSI_DC_TP_OUT_EN (1<<0U)
#define CSI_REG_CSI_PW_AVDD1815 (1<<4U)
/* 0x94 : dphy_config_5 */
#define CSI_REG_CSI_BYTE_CLK_INV (1<<0U)
#define CSI_REG_CSI_DDR_CLK_INV (1<<1U)
/* 0xFC : dummy_reg */
#define CSI_DUMMY_REG_SHIFT (0U)
#define CSI_DUMMY_REG_MASK (0xffffffff<<CSI_DUMMY_REG_SHIFT)
#endif /* __HARDWARE_CSI_H__ */

168
drivers/lhal/include/hardware/dtsrc_reg.h Normal file
View File

@ -0,0 +1,168 @@
/**
******************************************************************************
* @file dtsrc_reg.h
* @version V1.0
* @date 2022-12-15
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_DTSRC_H__
#define __HARDWARE_DTSRC_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define DTSRC_CONFIG_OFFSET (0x0)/* config */
#define DTSRC_FRAME_SIZE_H_OFFSET (0x4)/* frame_size_h */
#define DTSRC_FRAME_SIZE_V_OFFSET (0x8)/* frame_size_v */
#define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC)/* frame_size_cea_861 */
#define DTSRC_PIX_DATA_RANGE_OFFSET (0x10)/* pix_data_range */
#define DTSRC_PIX_DATA_STEP_OFFSET (0x14)/* pix_data_step */
#define DTSRC_AXI2DVP_SETTING_OFFSET (0x20)/* axi2dvp_setting */
#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24)/* axi2dvp_start_addr_by */
#define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28)/* axi2dvp_burst_cnt */
#define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C)/* axi2dvp_status */
#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30)/* axi2dvp_swap_addr_by */
#define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34)/* axi2dvp_prefetch */
#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38)/* snsr2dvp_wait_pos */
#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40)/* axi2dvp_start_addr_uv */
#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44)/* axi2dvp_swap_addr_uv */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : config */
#define DTSRC_CR_ENABLE (1<<0U)
#define DTSRC_CR_AXI_EN (1<<1U)
#define DTSRC_CR_MODE_CEA_861 (1<<2U)
#define DTSRC_CR_SNSR_EN (1<<3U)
#define DTSRC_CR_SNSR_HSYNC_INV (1<<4U)
#define DTSRC_CR_SNSR_VSYNC_INV (1<<5U)
#define DTSRC_CR_AXI_SWAP_MODE (1<<7U)
#define DTSRC_CR_AXI_SWAP_IDX_SEL_SHIFT (8U)
#define DTSRC_CR_AXI_SWAP_IDX_SEL_MASK (0xf<<DTSRC_CR_AXI_SWAP_IDX_SEL_SHIFT)
#define DTSRC_CR_AXI_SWAP_IDX_SWM (1<<12U)
#define DTSRC_CR_AXI_SWAP_IDX_SWV (1<<13U)
#define DTSRC_CR_AXI_DVP_DATA_MODE_SHIFT (16U)
#define DTSRC_CR_AXI_DVP_DATA_MODE_MASK (0x7<<DTSRC_CR_AXI_DVP_DATA_MODE_SHIFT)
#define DTSRC_CR_AXI_B0_SEL_SHIFT (20U)
#define DTSRC_CR_AXI_B0_SEL_MASK (0x3<<DTSRC_CR_AXI_B0_SEL_SHIFT)
#define DTSRC_CR_AXI_B1_SEL_SHIFT (22U)
#define DTSRC_CR_AXI_B1_SEL_MASK (0x3<<DTSRC_CR_AXI_B1_SEL_SHIFT)
#define DTSRC_CR_AXI_B2_SEL_SHIFT (24U)
#define DTSRC_CR_AXI_B2_SEL_MASK (0x3<<DTSRC_CR_AXI_B2_SEL_SHIFT)
/* 0x4 : frame_size_h */
#define DTSRC_CR_TOTAL_H_SHIFT (0U)
#define DTSRC_CR_TOTAL_H_MASK (0xfff<<DTSRC_CR_TOTAL_H_SHIFT)
#define DTSRC_CR_BLANK_H_SHIFT (16U)
#define DTSRC_CR_BLANK_H_MASK (0xfff<<DTSRC_CR_BLANK_H_SHIFT)
/* 0x8 : frame_size_v */
#define DTSRC_CR_TOTAL_V_SHIFT (0U)
#define DTSRC_CR_TOTAL_V_MASK (0xfff<<DTSRC_CR_TOTAL_V_SHIFT)
#define DTSRC_CR_BLANK_V_SHIFT (16U)
#define DTSRC_CR_BLANK_V_MASK (0xfff<<DTSRC_CR_BLANK_V_SHIFT)
/* 0xC : frame_size_cea_861 */
#define DTSRC_CR_H_DURATION_SHIFT (0U)
#define DTSRC_CR_H_DURATION_MASK (0xff<<DTSRC_CR_H_DURATION_SHIFT)
#define DTSRC_CR_H_PLACEMENT_SHIFT (8U)
#define DTSRC_CR_H_PLACEMENT_MASK (0xff<<DTSRC_CR_H_PLACEMENT_SHIFT)
#define DTSRC_CR_V_DURATION_SHIFT (16U)
#define DTSRC_CR_V_DURATION_MASK (0xff<<DTSRC_CR_V_DURATION_SHIFT)
#define DTSRC_CR_V_PLACEMENT_SHIFT (24U)
#define DTSRC_CR_V_PLACEMENT_MASK (0xff<<DTSRC_CR_V_PLACEMENT_SHIFT)
/* 0x10 : pix_data_range */
#define DTSRC_CR_DATA_MIN_SHIFT (0U)
#define DTSRC_CR_DATA_MIN_MASK (0xffff<<DTSRC_CR_DATA_MIN_SHIFT)
#define DTSRC_CR_DATA_MAX_SHIFT (16U)
#define DTSRC_CR_DATA_MAX_MASK (0xffff<<DTSRC_CR_DATA_MAX_SHIFT)
/* 0x14 : pix_data_step */
#define DTSRC_CR_DATA_STEP_SHIFT (0U)
#define DTSRC_CR_DATA_STEP_MASK (0xff<<DTSRC_CR_DATA_STEP_SHIFT)
/* 0x20 : axi2dvp_setting */
#define DTSRC_CR_AXI_XLEN_SHIFT (0U)
#define DTSRC_CR_AXI_XLEN_MASK (0x7<<DTSRC_CR_AXI_XLEN_SHIFT)
#define DTSRC_CR_AXI_DRAIN_ERR_CLR (1<<4U)
#define DTSRC_CR_AXI_420_MODE (1<<8U)
#define DTSRC_CR_AXI_420_UD_SEL (1<<9U)
#define DTSRC_CR_QOS_SW_MODE (1<<10U)
#define DTSRC_CR_QOS_SW (1<<11U)
/* 0x24 : axi2dvp_start_addr_by */
#define DTSRC_CR_AXI_ADDR_START_BY_SHIFT (0U)
#define DTSRC_CR_AXI_ADDR_START_BY_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_START_BY_SHIFT)
/* 0x28 : axi2dvp_burst_cnt */
#define DTSRC_CR_AXI_FRAME_BC_SHIFT (0U)
#define DTSRC_CR_AXI_FRAME_BC_MASK (0xffffffff<<DTSRC_CR_AXI_FRAME_BC_SHIFT)
/* 0x2C : axi2dvp_status */
#define DTSRC_ST_AXI_FIFO_CNT_BY_SHIFT (0U)
#define DTSRC_ST_AXI_FIFO_CNT_BY_MASK (0x7f<<DTSRC_ST_AXI_FIFO_CNT_BY_SHIFT)
#define DTSRC_ST_AXI_DRAIN_ERROR_BY (1<<7U)
#define DTSRC_ST_AXI_STATE_IDLE_BY (1<<8U)
#define DTSRC_ST_AXI_STATE_FUNC_BY (1<<9U)
#define DTSRC_ST_AXI_STATE_FLSH_BY (1<<10U)
#define DTSRC_ST_AXI_FIFO_CNT_UV_SHIFT (16U)
#define DTSRC_ST_AXI_FIFO_CNT_UV_MASK (0x7f<<DTSRC_ST_AXI_FIFO_CNT_UV_SHIFT)
#define DTSRC_ST_AXI_DRAIN_ERROR_UV (1<<23U)
#define DTSRC_ST_AXI_STATE_IDLE_UV (1<<24U)
#define DTSRC_ST_AXI_STATE_FUNC_UV (1<<25U)
#define DTSRC_ST_AXI_STATE_FLSH_UV (1<<26U)
/* 0x30 : axi2dvp_swap_addr_by */
#define DTSRC_CR_AXI_ADDR_SWAP_BY_SHIFT (0U)
#define DTSRC_CR_AXI_ADDR_SWAP_BY_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_SWAP_BY_SHIFT)
/* 0x34 : axi2dvp_prefetch */
#define DTSRC_CR_PREFETCH_V_SHIFT (0U)
#define DTSRC_CR_PREFETCH_V_MASK (0xfff<<DTSRC_CR_PREFETCH_V_SHIFT)
/* 0x38 : snsr2dvp_wait_pos */
#define DTSRC_CR_SNSR_FIFO_TH_SHIFT (0U)
#define DTSRC_CR_SNSR_FIFO_TH_MASK (0x7ff<<DTSRC_CR_SNSR_FIFO_TH_SHIFT)
/* 0x40 : axi2dvp_start_addr_uv */
#define DTSRC_CR_AXI_ADDR_START_UV_SHIFT (0U)
#define DTSRC_CR_AXI_ADDR_START_UV_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_START_UV_SHIFT)
/* 0x44 : axi2dvp_swap_addr_uv */
#define DTSRC_CR_AXI_ADDR_SWAP_UV_SHIFT (0U)
#define DTSRC_CR_AXI_ADDR_SWAP_UV_MASK (0xffffffff<<DTSRC_CR_AXI_ADDR_SWAP_UV_SHIFT)
#endif /* __HARDWARE_DTSRC_H__ */

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/**
******************************************************************************
* @file i2s_reg.h
* @version V1.0
* @date 2023-01-03
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __I2S_REG_H__
#define __I2S_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define I2S_CONFIG_OFFSET (0x0) /* i2s_config */
#define I2S_INT_STS_OFFSET (0x4) /* i2s_int_sts */
#define I2S_BCLK_CONFIG_OFFSET (0x10) /* i2s_bclk_config */
#define I2S_FIFO_CONFIG_0_OFFSET (0x80) /* i2s_fifo_config_0 */
#define I2S_FIFO_CONFIG_1_OFFSET (0x84) /* i2s_fifo_config_1 */
#define I2S_FIFO_WDATA_OFFSET (0x88) /* i2s_fifo_wdata */
#define I2S_FIFO_RDATA_OFFSET (0x8C) /* i2s_fifo_rdata */
#define I2S_IO_CONFIG_OFFSET (0xFC) /* i2s_io_config */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : i2s_config */
#define I2S_CR_I2S_M_EN (1 << 0U)
#define I2S_CR_I2S_S_EN (1 << 1U)
#define I2S_CR_I2S_TXD_EN (1 << 2U)
#define I2S_CR_I2S_RXD_EN (1 << 3U)
#define I2S_CR_MONO_MODE (1 << 4U)
#define I2S_CR_MUTE_MODE (1 << 5U)
#define I2S_CR_FS_1T_MODE (1 << 6U)
#define I2S_CR_FS_CH_CNT_SHIFT (7U)
#define I2S_CR_FS_CH_CNT_MASK (0x3 << I2S_CR_FS_CH_CNT_SHIFT)
#define I2S_CR_FRAME_SIZE_SHIFT (12U)
#define I2S_CR_FRAME_SIZE_MASK (0x3 << I2S_CR_FRAME_SIZE_SHIFT)
#define I2S_CR_DATA_SIZE_SHIFT (14U)
#define I2S_CR_DATA_SIZE_MASK (0x3 << I2S_CR_DATA_SIZE_SHIFT)
#define I2S_CR_I2S_MODE_SHIFT (16U)
#define I2S_CR_I2S_MODE_MASK (0x3 << I2S_CR_I2S_MODE_SHIFT)
#define I2S_CR_ENDIAN (1 << 18U)
#define I2S_CR_MONO_RX_CH (1 << 19U)
#define I2S_CR_OFS_CNT_SHIFT (20U)
#define I2S_CR_OFS_CNT_MASK (0x1f << I2S_CR_OFS_CNT_SHIFT)
#define I2S_CR_OFS_EN (1 << 25U)
/* 0x4 : i2s_int_sts */
#define I2S_TXF_INT (1 << 0U)
#define I2S_RXF_INT (1 << 1U)
#define I2S_FER_INT (1 << 2U)
#define I2S_CR_I2S_TXF_MASK (1 << 8U)
#define I2S_CR_I2S_RXF_MASK (1 << 9U)
#define I2S_CR_I2S_FER_MASK (1 << 10U)
#define I2S_CR_I2S_TXF_EN (1 << 24U)
#define I2S_CR_I2S_RXF_EN (1 << 25U)
#define I2S_CR_I2S_FER_EN (1 << 26U)
/* 0x10 : i2s_bclk_config */
#define I2S_CR_BCLK_DIV_L_SHIFT (0U)
#define I2S_CR_BCLK_DIV_L_MASK (0xfff << I2S_CR_BCLK_DIV_L_SHIFT)
#define I2S_CR_BCLK_DIV_H_SHIFT (16U)
#define I2S_CR_BCLK_DIV_H_MASK (0xfff << I2S_CR_BCLK_DIV_H_SHIFT)
/* 0x80 : i2s_fifo_config_0 */
#define I2S_DMA_TX_EN (1 << 0U)
#define I2S_DMA_RX_EN (1 << 1U)
#define I2S_TX_FIFO_CLR (1 << 2U)
#define I2S_RX_FIFO_CLR (1 << 3U)
#define I2S_TX_FIFO_OVERFLOW (1 << 4U)
#define I2S_TX_FIFO_UNDERFLOW (1 << 5U)
#define I2S_RX_FIFO_OVERFLOW (1 << 6U)
#define I2S_RX_FIFO_UNDERFLOW (1 << 7U)
#define I2S_CR_FIFO_LR_MERGE (1 << 8U)
#define I2S_CR_FIFO_LR_EXCHG (1 << 9U)
#define I2S_CR_FIFO_24B_LJ (1 << 10U)
/* 0x84 : i2s_fifo_config_1 */
#define I2S_TX_FIFO_CNT_SHIFT (0U)
#define I2S_TX_FIFO_CNT_MASK (0x1f << I2S_TX_FIFO_CNT_SHIFT)
#define I2S_RX_FIFO_CNT_SHIFT (8U)
#define I2S_RX_FIFO_CNT_MASK (0x1f << I2S_RX_FIFO_CNT_SHIFT)
#define I2S_TX_FIFO_TH_SHIFT (16U)
#define I2S_TX_FIFO_TH_MASK (0xf << I2S_TX_FIFO_TH_SHIFT)
#define I2S_RX_FIFO_TH_SHIFT (24U)
#define I2S_RX_FIFO_TH_MASK (0xf << I2S_RX_FIFO_TH_SHIFT)
/* 0x88 : i2s_fifo_wdata */
#define I2S_FIFO_WDATA_SHIFT (0U)
#define I2S_FIFO_WDATA_MASK (0xffffffff << I2S_FIFO_WDATA_SHIFT)
/* 0x8C : i2s_fifo_rdata */
#define I2S_FIFO_RDATA_SHIFT (0U)
#define I2S_FIFO_RDATA_MASK (0xffffffff << I2S_FIFO_RDATA_SHIFT)
/* 0xFC : i2s_io_config */
#define I2S_CR_I2S_TXD_INV (1 << 0U)
#define I2S_CR_I2S_RXD_INV (1 << 1U)
#define I2S_CR_I2S_FS_INV (1 << 2U)
#define I2S_CR_I2S_BCLK_INV (1 << 3U)
#define I2S_CR_DEG_CNT_SHIFT (4U)
#define I2S_CR_DEG_CNT_MASK (0x7 << I2S_CR_DEG_CNT_SHIFT)
#define I2S_CR_DEG_EN (1 << 7U)
#endif /* __I2S_REG_H__ */

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/**
******************************************************************************
* @file kys_reg.h
* @version V1.0
* @date 2022-11-17
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without
*modification, are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
*notice, this list of conditions and the following disclaimer in the
*documentation and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
*ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
*LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
*CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
*SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
*INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
*CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
*ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
*POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_KYS_H__
#define __HARDWARE_KYS_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define KYS_KS_CTRL_OFFSET (0x0)
#define KYS_KS_INT_EN_OFFSET (0x10)
#define KYS_KS_INT_STS_OFFSET (0x14)
#define KYS_KEYCODE_CLR_OFFSET (0x18)
#if defined(bl702)
#define KYS_KEYFIFO_VALUE_OFFSET (0x1C)
#else
#define KYS_KEYFIFO_IDX_OFFSET (0x30)
#define KYS_KEYFIFO_VALUE_OFFSET (0x34)
#endif
/* 0x0 : ks_ctrl */
#define KYS_KS_EN_SHIFT (0U)
#define KYS_KS_EN_MASK (0x1 << KYS_KS_EN_SHIFT)
#define KYS_GHOST_EN_SHIFT (2U)
#define KYS_GHOST_EN_MASK (0x1 << KYS_GHOST_EN_SHIFT)
#define KYS_DEG_EN_SHIFT (3U)
#define KYS_DEG_EN_MASK (0x1 << KYS_DEG_EN_SHIFT)
#define KYS_DEG_CNT_SHIFT (4U)
#define KYS_DEG_CNT_MASK (0xf << KYS_DEG_CNT_SHIFT)
#define KYS_RC_EXT_SHIFT (8U)
#define KYS_RC_EXT_MASK (0x3 << KYS_RC_EXT_SHIFT)
#define KYS_ROW_NUM_SHIFT (16U)
#define KYS_ROW_NUM_MASK (0x7 << KYS_ROW_NUM_SHIFT)
#if defined(bl702)
#define KYS_COL_NUM_SHIFT (20U)
#define KYS_COL_NUM_MASK (0x7 << KYS_COL_NUM_SHIFT)
#else
#define KYS_FIFO_MODE_SHIFT (1U)
#define KYS_FIFO_MODE_MASK (0x1 << KYS_FIFO_MODE_SHIFT)
#define KYS_COL_NUM_SHIFT (20U)
#define KYS_COL_NUM_MASK (0x1f << KYS_COL_NUM_SHIFT)
#endif
/* 0x10 : ks_int_en */
#if defined(bl702)
#define KYS_KS_INT_EN_SHIFT (0U)
#define KYS_KS_INT_EN_MASK (0x1 << KYS_KS_INT_EN_SHIFT)
#else
#define KYS_KS_DONE_INT_EN_SHIFT (7U)
#define KYS_KS_DONE_INT_EN_MASK (0x1 << KYS_KS_DONE_INT_EN_SHIFT)
#define KYS_KEYFIFO_FULL_INT_EN_SHIFT (8U)
#define KYS_KEYFIFO_FULL_INT_EN_MASK (0x1 << KYS_KEYFIFO_FULL_INT_EN_SHIFT)
#define KYS_KEYFIFO_HALF_INT_EN_SHIFT (9U)
#define KYS_KEYFIFO_HALF_INT_EN_MASK (0x1 << KYS_KEYFIFO_HALF_INT_EN_SHIFT)
#define KYS_KEYFIFO_QUARTER_INT_EN_SHIFT (10U)
#define KYS_KEYFIFO_QUARTER_INT_EN_MASK (0x1 << KYS_KEYFIFO_QUARTER_INT_EN_SHIFT)
#define KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT (11U)
#define KYS_KEYFIFO_NONEMPTY_INT_EN_MASK (0x1 << KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT)
#define KYS_GHOST_INT_EN_SHIFT (12U)
#define KYS_GHOST_INT_EN_MASK (0x1 << KYS_GHOST_INT_EN_SHIFT)
#endif
/* 0x14 : ks_int_sts */
#if defined(bl702)
#define KYS_KEYCODE_VALID_SHIFT (0U)
#define KYS_KEYCODE_VALID_MASK (0xf << KYS_KEYCODE_VALID_SHIFT)
#else
#define KYS_KEYCODE_DONE_SHIFT (7U)
#define KYS_KEYCODE_DONE_MASK (0x1 << KYS_KEYCODE_DONE_SHIFT)
#define KYS_KEYFIFO_FULL_SHIFT (8U)
#define KYS_KEYFIFO_FULL_MASK (0x1 << KYS_KEYFIFO_FULL_SHIFT)
#define KYS_KEYFIFO_HALF_SHIFT (9U)
#define KYS_KEYFIFO_HALF_MSK (0x1 << KYS_KEYFIFO_HALF_SHIFT)
#define KYS_KEYFIFO_QUARTER_SHIFT (10U)
#define KYS_KEYFIFO_QUARTER_MSK (0x1 << KYS_KEYFIFO_QUARTER_SHIFT)
#define KYS_KEYFIFO_NONEMPTY_SHIFT (11U)
#define KYS_KEYFIFO_NONEMPTY_MSK (0x1 << KYS_KEYFIFO_NONEMPTY_SHIFT)
#define KYS_GHOST_DET_SHIFT (12U)
#define KYS_GHOST_DET_MASK (0x1 << KYS_GHOST_DET_SHIFT)
#endif
/* 0x18 : keycode_clr */
#if defined(bl702)
#define KYS_KEYCODE_CLR_SHIFT (0U)
#define KYS_KEYCODE_CLR_MASK (0xf << KYS_KEYCODE_CLR_SHIFT)
#else
#define KYS_KS_DONE_CLR_SHIFT (7U)
#define KYS_KS_DONE_CLR_MASK (0x1 << KYS_KS_DONE_CLR_SHIFT)
#define KYS_KEYFIFO_FULL_CLR_SHIFT (8U)
#define KYS_KEYFIFO_FULL_CLR_MASK (0x1 << KYS_KEYFIFO_FULL_CLR_SHIFT)
#define KYS_GHOST_CLR_SHIFT (12U)
#define KYS_GHOST_CLR_MASK (0x1 << KYS_GHOST_CLR_SHIFT)
#endif
#if defined(bl702)
/* 0x1c : keycode value */
#define KYS_KEYCODE0_SHIFT (0U)
#define KYS_KEYCODE0_MASK (0xff << KYS_KEYCODE0_SHIFT)
#define KYS_KEYCODE1_SHIFT (8U)
#define KYS_KEYCODE1_MASK (0xff << KYS_KEYCODE1_SHIFT)
#define KYS_KEYCODE2_SHIFT (16U)
#define KYS_KEYCODE2_MASK (0xff << KYS_KEYCODE2_SHIFT)
#define KYS_KEYCODE3_SHIFT (24U)
#define KYS_KEYCODE3_MASK (0xff << KYS_KEYCODE3_SHIFT)
#endif
#if defined(bl702l)
/* 0x30 : keyfifo_idx */
#define KYS_KEYFIFO_HEAD_SHIFT (0U)
#define KYS_KEYFIFO_HEAD_MASK (0x7 << KYS_KEYFIFO_HEAD_SHIFT)
#define KYS_KEYFIFO_TAIL_SHIFT (8U)
#define KYS_KEYFIFO_TAIL_MASK (0x7 << KYS_KEYFIFO_TAIL_SHIFT)
/* 0x34 : keyfifo_value */
#define KYS_KEYFIFO_VALUE_SHIFT (0U)
#define KYS_KEYFIFO_VALUE_MASK (0xff << KYS_KEYFIFO_VALUE_SHIFT)
#endif
#endif /* __HARDWARE_KYS_H__ */

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/**
******************************************************************************
* @file sdio2.h
* @version V1.0
* @date 2022-08-03
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HARDWARE_SDIO2_H__
#define __HARDWARE_SDIO2_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define SDIO2_IO_ENABLE_OFFSET (0x0002) /* SDIO I/O Enable */
#define SDIO2_FN1_BLK_SIZE_0_OFFSET (0x0028) /* SDIO block size infor */
#define SDIO2_FN1_BLK_SIZE_1_OFFSET (0x0029) /* SDIO block size infor */
#define SDIO2_DEV_SLEEP_OFFSET (0x0092) /* SDIO Device Sleep */
#define SDIO2_CCR_FUNC_OFFSET (0x0100) /* Address offset of CCR between two functions */
#define SDIO2_HOST_TO_CARD_EVENT_OFFSET (0x0100)
#define SDIO2_HOST_INT_CAUSE_OFFSET (0x0101)
#define SDIO2_HOST_INT_MASK_OFFSET (0x0102)
#define SDIO2_HOST_INT_STATUS_OFFSET (0x0103)
#define SDIO2_RD_BIT_MAP_OFFSET (0x0104)
#define SDIO2_WR_BIT_MAP_OFFSET (0x0106)
#define SDIO2_RD_LEN_OFFSET (0x0108)
#define SDIO2_HOST_TRANS_STATUS_OFFSET (0x0128)
#define SDIO2_CARD_TO_HOST_EVENT_OFFSET (0x0130)
#define SDIO2_CARD_INT_MASK_OFFSET (0x0134)
#define SDIO2_CARD_INT_STATUS_OFFSET (0x0138)
#define SDIO2_CARD_INT_MODE_OFFSET (0x013C)
#define SDIO2_SQ_READ_BASE_OFFSET (0x0140)
#define SDIO2_SQ_WRITE_BASE_OFFSET (0x0144)
#define SDIO2_READ_INDEX_OFFSET (0x0148)
#define SDIO2_WRITE_INDEX_OFFSET (0x0149)
#define SDIO2_DNLD_QUEUE_WRPTR_OFFSET (0x014A)
#define SDIO2_UPLD_QUEUE_WRPTR_OFFSET (0x014B)
#define SDIO2_DNLD_QUEUE_OFFSET (0x014C)
#define SDIO2_UPLD_QUEUE_OFFSET (0x0154)
#define SDIO2_CHIP_VERSION_OFFSET (0x015C)
#define SDIO2_IP_VERSION0_OFFSET (0x015E)
#define SDIO2_IP_VERSION1_OFFSET (0x015F)
#define SDIO2_SCRATCH2_OFFSET (0x0164)
#define SDIO2_SCRATCH1_OFFSET (0x0166)
#define SDIO2_OCR0_OFFSET (0x0168)
#define SDIO2_OCR1_OFFSET (0x0169)
#define SDIO2_OCR2_OFFSET (0x016A)
#define SDIO2_CONFIG_OFFSET (0x016B)
#define SDIO2_CONFIG2_OFFSET (0x016C)
#define SDIO2_DEBUG_OFFSET (0x0170)
#define SDIO2_DMA_ADDR_OFFSET (0x0174)
#define SDIO2_IO_PORT_OFFSET (0x0178)
// Bit Def. Scratch register 0
#define SDIO2_SCRATCH_OFFSET (0x0160)
// Bit Def. Block size 1 mask (Offset 0x29)
#define SDIO2_FN1_BLK_SIZE_1_MASK 0x01
// Bit Def. Host To Card Interrupt Event (Offset 0x100/200)
#define SDIO2_HCR_CONFIG_HostPwrUp (1 << 1)
// Bit Def. Host Transfer Status (Offset 0x128/228)
#define SDIO2_CCR_HOST_INT_DnLdReStart (1 << 0)
#define SDIO2_CCR_HOST_INT_UpLdReStart (1 << 1)
#define SDIO2_CCR_HOST_INT_DnLdCRC_err (1 << 2)
// Bit Def. Card To Host Interrupt Event (Offset 0x130/230)
#define SDIO2_CCR_CS_DnLdRdy (1 << 0)
#define SDIO2_CCR_CS_UpLdRdy (1 << 1)
#define SDIO2_CCR_CS_ReadCISRdy (1 << 2)
#define SDIO2_CCR_CS_IORdy (1 << 3)
// Bit Def. Card Interrupt Mask (Offset 0x134/234)
#define SDIO2_CCR_CIM_DnLdOvr (1 << 0)
#define SDIO2_CCR_CIM_UpLdOvr (1 << 1)
#define SDIO2_CCR_CIM_Abort (1 << 2)
#define SDIO2_CCR_CIM_PwrDn (1 << 3)
#define SDIO2_CCR_CIM_PwrUp (1 << 4)
#define SDIO2_CCR_CIM_MASK 0x0007
// Bit Def. Card Interrupt Status (Offset 0x138/238)
#define SDIO2_CCR_CIC_DnLdOvr (1 << 0)
#define SDIO2_CCR_CIC_UpLdOvr (1 << 1)
#define SDIO2_CCR_CIC_Abort (1 << 2)
#define SDIO2_CCR_CIC_PwrDn (1 << 3)
#define SDIO2_CCR_CIC_PwrUp (1 << 4)
#define SDIO2_CCR_CIC_MASK 0x001F
// Bit Def. Card Interrupt RSR (Offset 0x13C/23C)
#define SDIO2_CCR_CIO_DnLdOvr (1 << 0)
#define SDIO2_CCR_CIO_UpLdOvr (1 << 1)
#define SDIO2_CCR_CIO_Abort (1 << 2)
#define SDIO2_CCR_CIO_PwrDn (1 << 3)
#define SDIO2_CCR_CIO_PwrUp (1 << 4)
#define SDIO2_CCR_CIO_MASK 0x001F
//Config2 register mask
#define SDIO2_CONFIG2_MSK 0x00000C00
//CardIntMode register mask
#define SDIO2_CARD_INT_MODE_MSK 0x00000003
#define SDIO2_HOST_INT_MSK 0x00000002
#endif /* __HARDWARE_SDIO2_H__ */

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drivers/lhal/include/hardware/sf_ctrl_reg.h Normal file
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/**
******************************************************************************
* @file sf_ctrl_reg.h
* @version V1.0
* @date 2022-10-20
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __SF_CTRL_REG_H__
#define __SF_CTRL_REG_H__
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define SF_CTRL_0_OFFSET (0x0)/* sf_ctrl_0 */
#define SF_CTRL_1_OFFSET (0x4)/* sf_ctrl_1 */
#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8)/* sf_if_sahb_0 */
#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC)/* sf_if_sahb_1 */
#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10)/* sf_if_sahb_2 */
#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14)/* sf_if_iahb_0 */
#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18)/* sf_if_iahb_1 */
#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C)/* sf_if_iahb_2 */
#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)/* sf_if_status_0 */
#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)/* sf_if_status_1 */
#define SF_CTRL_SF_AES_OFFSET (0x28)/* sf_aes */
#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)/* sf_ahb2sif_status */
#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30)/* sf_if_io_dly_0 */
#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34)/* sf_if_io_dly_1 */
#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38)/* sf_if_io_dly_2 */
#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C)/* sf_if_io_dly_3 */
#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40)/* sf_if_io_dly_4 */
#define SF_CTRL_SF_RESERVED_OFFSET (0x44)/* sf_reserved */
#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48)/* sf2_if_io_dly_0 */
#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C)/* sf2_if_io_dly_1 */
#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50)/* sf2_if_io_dly_2 */
#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54)/* sf2_if_io_dly_3 */
#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58)/* sf2_if_io_dly_4 */
#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C)/* sf3_if_io_dly_0 */
#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60)/* sf3_if_io_dly_1 */
#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64)/* sf3_if_io_dly_2 */
#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68)/* sf3_if_io_dly_3 */
#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C)/* sf3_if_io_dly_4 */
#define SF_CTRL_2_OFFSET (0x70)/* sf_ctrl_2 */
#define SF_CTRL_3_OFFSET (0x74)/* sf_ctrl_3 */
#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78)/* sf_if_iahb_3 */
#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C)/* sf_if_iahb_4 */
#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80)/* sf_if_iahb_5 */
#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84)/* sf_if_iahb_6 */
#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88)/* sf_if_iahb_7 */
#define SF_CTRL_SF_IF_IAHB_8_OFFSET (0x8C)/* sf_if_iahb_8 */
#define SF_CTRL_SF_IF_IAHB_9_OFFSET (0x90)/* sf_if_iahb_9 */
#define SF_CTRL_SF_IF_IAHB_10_OFFSET (0x94)/* sf_if_iahb_10 */
#define SF_CTRL_SF_IF_IAHB_11_OFFSET (0x98)/* sf_if_iahb_11 */
#define SF_CTRL_SF_IF_IAHB_12_OFFSET (0x9C)/* sf_if_iahb_12 */
#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0xA0)/* sf_id0_offset */
#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0xA4)/* sf_id1_offset */
#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0xA8)/* sf_bk2_id0_offset */
#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0xAC)/* sf_bk2_id1_offset */
#define SF_CTRL_SF_DBG_OFFSET (0xB0)/* sf_dbg */
#define SF_CTRL_SF_IF2_CTRL_0_OFFSET (0xC0)/* sf_if2_ctrl_0 */
#define SF_CTRL_SF_IF2_CTRL_1_OFFSET (0xC4)/* sf_if2_ctrl_1 */
#define SF_CTRL_SF_IF2_SAHB_0_OFFSET (0xC8)/* sf_if2_sahb_0 */
#define SF_CTRL_SF_IF2_SAHB_1_OFFSET (0xCC)/* sf_if2_sahb_1 */
#define SF_CTRL_SF_IF2_SAHB_2_OFFSET (0xD0)/* sf_if2_sahb_2 */
#define SF_CTRL_PROT_EN_RD_OFFSET (0x100)/* sf_ctrl_prot_en_rd */
#define SF_CTRL_PROT_EN_OFFSET (0x104)/* sf_ctrl_prot_en */
#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)/* sf_aes_key_r0_0 */
#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)/* sf_aes_key_r0_1 */
#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)/* sf_aes_key_r0_2 */
#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)/* sf_aes_key_r0_3 */
#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)/* sf_aes_key_r0_4 */
#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)/* sf_aes_key_r0_5 */
#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)/* sf_aes_key_r0_6 */
#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)/* sf_aes_key_r0_7 */
#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)/* sf_aes_iv_r0_w0 */
#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)/* sf_aes_iv_r0_w1 */
#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)/* sf_aes_iv_r0_w2 */
#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)/* sf_aes_iv_r0_w3 */
#define SF_CTRL_SF_AES_R0_START_OFFSET (0x230)/* sf_aes_r0_start */
#define SF_CTRL_SF_AES_R0_END_OFFSET (0x234)/* sf_aes_r0_end */
#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x280)/* sf_aes_key_r1_0 */
#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x284)/* sf_aes_key_r1_1 */
#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x288)/* sf_aes_key_r1_2 */
#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x28C)/* sf_aes_key_r1_3 */
#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x290)/* sf_aes_key_r1_4 */
#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x294)/* sf_aes_key_r1_5 */
#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x298)/* sf_aes_key_r1_6 */
#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x29C)/* sf_aes_key_r1_7 */
#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x2A0)/* sf_aes_iv_r1_w0 */
#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x2A4)/* sf_aes_iv_r1_w1 */
#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x2A8)/* sf_aes_iv_r1_w2 */
#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x2AC)/* sf_aes_iv_r1_w3 */
#define SF_CTRL_SF_AES_R1_START_OFFSET (0x2B0)/* sf_aes_r1_start */
#define SF_CTRL_SF_AES_R1_END_OFFSET (0x2B4)/* sf_aes_r1_end */
#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x300)/* sf_aes_key_r2_0 */
#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x304)/* sf_aes_key_r2_1 */
#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x308)/* sf_aes_key_r2_2 */
#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x30C)/* sf_aes_key_r2_3 */
#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x310)/* sf_aes_key_r2_4 */
#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x314)/* sf_aes_key_r2_5 */
#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x318)/* sf_aes_key_r2_6 */
#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x31C)/* sf_aes_key_r2_7 */
#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x320)/* sf_aes_iv_r2_w0 */
#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x324)/* sf_aes_iv_r2_w1 */
#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x328)/* sf_aes_iv_r2_w2 */
#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x32C)/* sf_aes_iv_r2_w3 */
#define SF_CTRL_SF_AES_R2_START_OFFSET (0x330)/* sf_aes_r2_start */
#define SF_CTRL_SF_AES_R2_END_OFFSET (0x334)/* sf_aes_r2_end */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : sf_ctrl_0 */
#define SF_CTRL_SF_CLK_SF_RX_INV_SEL (1<<2U)
#define SF_CTRL_SF_CLK_OUT_GATE_EN (1<<3U)
#define SF_CTRL_SF_CLK_OUT_INV_SEL (1<<4U)
#define SF_CTRL_SF_IF_READ_DLY_N_SHIFT (8U)
#define SF_CTRL_SF_IF_READ_DLY_N_MASK (0x7<<SF_CTRL_SF_IF_READ_DLY_N_SHIFT)
#define SF_CTRL_SF_IF_READ_DLY_EN (1<<11U)
#define SF_CTRL_SF_IF_INT (1<<16U)
#define SF_CTRL_SF_IF_INT_CLR (1<<17U)
#define SF_CTRL_SF_IF_INT_SET (1<<18U)
#define SF_CTRL_SF_IF_32B_ADR_EN (1<<19U)
#define SF_CTRL_SF_AES_DOUT_ENDIAN (1<<20U)
#define SF_CTRL_SF_AES_DIN_ENDIAN (1<<21U)
#define SF_CTRL_SF_AES_KEY_ENDIAN (1<<22U)
#define SF_CTRL_SF_AES_IV_ENDIAN (1<<23U)
#define SF_CTRL_SF_ID_SHIFT (24U)
#define SF_CTRL_SF_ID_MASK (0xff<<SF_CTRL_SF_ID_SHIFT)
/* 0x4 : sf_ctrl_1 */
#define SF_CTRL_SF_IF_SR_PAT_MASK_SHIFT (0U)
#define SF_CTRL_SF_IF_SR_PAT_MASK_MASK (0xff<<SF_CTRL_SF_IF_SR_PAT_MASK_SHIFT)
#define SF_CTRL_SF_IF_SR_PAT_SHIFT (8U)
#define SF_CTRL_SF_IF_SR_PAT_MASK (0xff<<SF_CTRL_SF_IF_SR_PAT_SHIFT)
#define SF_CTRL_SF_IF_SR_INT (1<<16U)
#define SF_CTRL_SF_IF_SR_INT_EN (1<<17U)
#define SF_CTRL_SF_IF_SR_INT_SET (1<<18U)
#define SF_CTRL_SF_IF_0_ACK_LAT_SHIFT (20U)
#define SF_CTRL_SF_IF_0_ACK_LAT_MASK (0x7<<SF_CTRL_SF_IF_0_ACK_LAT_SHIFT)
#define SF_CTRL_SF_AHB2SIF_DISWRAP (1<<23U)
#define SF_CTRL_SF_IF_REG_HOLD (1<<24U)
#define SF_CTRL_SF_IF_REG_WP (1<<25U)
#define SF_CTRL_SF_AHB2SIF_STOPPED (1<<26U)
#define SF_CTRL_SF_AHB2SIF_STOP (1<<27U)
#define SF_CTRL_SF_IF_FN_SEL (1<<28U)
#define SF_CTRL_SF_IF_EN (1<<29U)
#define SF_CTRL_SF_AHB2SIF_EN (1<<30U)
#define SF_CTRL_SF_AHB2SRAM_EN (1<<31U)
/* 0x8 : sf_if_sahb_0 */
#define SF_CTRL_SF_IF_BUSY (1<<0U)
#define SF_CTRL_SF_IF_0_TRIG (1<<1U)
#define SF_CTRL_SF_IF_0_DAT_BYTE_SHIFT (2U)
#define SF_CTRL_SF_IF_0_DAT_BYTE_MASK (0x3ff<<SF_CTRL_SF_IF_0_DAT_BYTE_SHIFT)
#define SF_CTRL_SF_IF_0_DMY_BYTE_SHIFT (12U)
#define SF_CTRL_SF_IF_0_DMY_BYTE_MASK (0x1f<<SF_CTRL_SF_IF_0_DMY_BYTE_SHIFT)
#define SF_CTRL_SF_IF_0_ADR_BYTE_SHIFT (17U)
#define SF_CTRL_SF_IF_0_ADR_BYTE_MASK (0x7<<SF_CTRL_SF_IF_0_ADR_BYTE_SHIFT)
#define SF_CTRL_SF_IF_0_CMD_BYTE_SHIFT (20U)
#define SF_CTRL_SF_IF_0_CMD_BYTE_MASK (0x7<<SF_CTRL_SF_IF_0_CMD_BYTE_SHIFT)
#define SF_CTRL_SF_IF_0_DAT_RW (1<<23U)
#define SF_CTRL_SF_IF_0_DAT_EN (1<<24U)
#define SF_CTRL_SF_IF_0_DMY_EN (1<<25U)
#define SF_CTRL_SF_IF_0_ADR_EN (1<<26U)
#define SF_CTRL_SF_IF_0_CMD_EN (1<<27U)
#define SF_CTRL_SF_IF_0_SPI_MODE_SHIFT (28U)
#define SF_CTRL_SF_IF_0_SPI_MODE_MASK (0x7<<SF_CTRL_SF_IF_0_SPI_MODE_SHIFT)
#define SF_CTRL_SF_IF_0_QPI_MODE_EN (1<<31U)
/* 0xC : sf_if_sahb_1 */
#define SF_CTRL_SF_IF_0_CMD_BUF_0_SHIFT (0U)
#define SF_CTRL_SF_IF_0_CMD_BUF_0_MASK (0xffffffffL<<SF_CTRL_SF_IF_0_CMD_BUF_0_SHIFT)
/* 0x10 : sf_if_sahb_2 */
#define SF_CTRL_SF_IF_0_CMD_BUF_1_SHIFT (0U)
#define SF_CTRL_SF_IF_0_CMD_BUF_1_MASK (0xffffffffL<<SF_CTRL_SF_IF_0_CMD_BUF_1_SHIFT)
/* 0x14 : sf_if_iahb_0 */
#define SF_CTRL_SF_IF_1_DMY_BYTE_SHIFT (12U)
#define SF_CTRL_SF_IF_1_DMY_BYTE_MASK (0x1f<<SF_CTRL_SF_IF_1_DMY_BYTE_SHIFT)
#define SF_CTRL_SF_IF_1_ADR_BYTE_SHIFT (17U)
#define SF_CTRL_SF_IF_1_ADR_BYTE_MASK (0x7<<SF_CTRL_SF_IF_1_ADR_BYTE_SHIFT)
#define SF_CTRL_SF_IF_1_CMD_BYTE_SHIFT (20U)
#define SF_CTRL_SF_IF_1_CMD_BYTE_MASK (0x7<<SF_CTRL_SF_IF_1_CMD_BYTE_SHIFT)
#define SF_CTRL_SF_IF_1_DAT_RW (1<<23U)
#define SF_CTRL_SF_IF_1_DAT_EN (1<<24U)
#define SF_CTRL_SF_IF_1_DMY_EN (1<<25U)
#define SF_CTRL_SF_IF_1_ADR_EN (1<<26U)
#define SF_CTRL_SF_IF_1_CMD_EN (1<<27U)
#define SF_CTRL_SF_IF_1_SPI_MODE_SHIFT (28U)
#define SF_CTRL_SF_IF_1_SPI_MODE_MASK (0x7<<SF_CTRL_SF_IF_1_SPI_MODE_SHIFT)
#define SF_CTRL_SF_IF_1_QPI_MODE_EN (1<<31U)
/* 0x18 : sf_if_iahb_1 */
#define SF_CTRL_SF_IF_1_CMD_BUF_0_SHIFT (0U)
#define SF_CTRL_SF_IF_1_CMD_BUF_0_MASK (0xffffffffL<<SF_CTRL_SF_IF_1_CMD_BUF_0_SHIFT)
/* 0x1C : sf_if_iahb_2 */
#define SF_CTRL_SF_IF_1_CMD_BUF_1_SHIFT (0U)
#define SF_CTRL_SF_IF_1_CMD_BUF_1_MASK (0xffffffffL<<SF_CTRL_SF_IF_1_CMD_BUF_1_SHIFT)
/* 0x20 : sf_if_status_0 */
#define SF_CTRL_SF_IF_STATUS_0_SHIFT (0U)
#define SF_CTRL_SF_IF_STATUS_0_MASK (0xffffffffL<<SF_CTRL_SF_IF_STATUS_0_SHIFT)
/* 0x24 : sf_if_status_1 */
#define SF_CTRL_SF_IF_STATUS_1_SHIFT (0U)
#define SF_CTRL_SF_IF_STATUS_1_MASK (0xffffffffL<<SF_CTRL_SF_IF_STATUS_1_SHIFT)
/* 0x28 : sf_aes */
#define SF_CTRL_SF_AES_EN (1<<0U)
#define SF_CTRL_SF_AES_MODE_SHIFT (1U)
#define SF_CTRL_SF_AES_MODE_MASK (0x3<<SF_CTRL_SF_AES_MODE_SHIFT)
#define SF_CTRL_SF_AES_BLK_MODE (1<<3U)
#define SF_CTRL_SF_AES_XTS_KEY_OPT (1<<4U)
#define SF_CTRL_SF_AES_STATUS_SHIFT (5U)
#define SF_CTRL_SF_AES_STATUS_MASK (0x7ffffff<<SF_CTRL_SF_AES_STATUS_SHIFT)
/* 0x2C : sf_ahb2sif_status */
#define SF_CTRL_SF_AHB2SIF_STATUS_SHIFT (0U)
#define SF_CTRL_SF_AHB2SIF_STATUS_MASK (0xffffffffL<<SF_CTRL_SF_AHB2SIF_STATUS_SHIFT)
/* 0x30 : sf_if_io_dly_0 */
#define SF_CTRL_SF_CS_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF_CS_DLY_SEL_MASK (0x3<<SF_CTRL_SF_CS_DLY_SEL_SHIFT)
#define SF_CTRL_SF_CS2_DLY_SEL_SHIFT (2U)
#define SF_CTRL_SF_CS2_DLY_SEL_MASK (0x3<<SF_CTRL_SF_CS2_DLY_SEL_SHIFT)
#define SF_CTRL_SF_CLK_OUT_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MASK (0x3<<SF_CTRL_SF_CLK_OUT_DLY_SEL_SHIFT)
#define SF_CTRL_SF_DQS_OE_DLY_SEL_SHIFT (26U)
#define SF_CTRL_SF_DQS_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF_DQS_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF_DQS_DI_DLY_SEL_SHIFT (28U)
#define SF_CTRL_SF_DQS_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF_DQS_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF_DQS_DO_DLY_SEL_SHIFT (30U)
#define SF_CTRL_SF_DQS_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF_DQS_DO_DLY_SEL_SHIFT)
/* 0x34 : sf_if_io_dly_1 */
#define SF_CTRL_SF_IO_0_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_0_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_0_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_0_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_0_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_0_DO_DLY_SEL_SHIFT)
/* 0x38 : sf_if_io_dly_2 */
#define SF_CTRL_SF_IO_1_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_1_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_1_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_1_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_1_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_1_DO_DLY_SEL_SHIFT)
/* 0x3C : sf_if_io_dly_3 */
#define SF_CTRL_SF_IO_2_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_2_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_2_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_2_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_2_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_2_DO_DLY_SEL_SHIFT)
/* 0x40 : sf_if_io_dly_4 */
#define SF_CTRL_SF_IO_3_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_3_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_3_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_3_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF_IO_3_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF_IO_3_DO_DLY_SEL_SHIFT)
/* 0x44 : sf_reserved */
#define SF_CTRL_SF_RESERVED_SHIFT (0U)
#define SF_CTRL_SF_RESERVED_MASK (0xffffffffL<<SF_CTRL_SF_RESERVED_SHIFT)
/* 0x48 : sf2_if_io_dly_0 */
#define SF_CTRL_SF2_CS_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF2_CS_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_CS_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_CS2_DLY_SEL_SHIFT (2U)
#define SF_CTRL_SF2_CS2_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_CS2_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_CLK_OUT_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_DQS_OE_DLY_SEL_SHIFT (26U)
#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_DQS_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_DQS_DI_DLY_SEL_SHIFT (28U)
#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_DQS_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_DQS_DO_DLY_SEL_SHIFT (30U)
#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_DQS_DO_DLY_SEL_SHIFT)
/* 0x4C : sf2_if_io_dly_1 */
#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_0_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_0_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_0_DO_DLY_SEL_SHIFT)
/* 0x50 : sf2_if_io_dly_2 */
#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_1_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_1_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_1_DO_DLY_SEL_SHIFT)
/* 0x54 : sf2_if_io_dly_3 */
#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_2_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_2_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_2_DO_DLY_SEL_SHIFT)
/* 0x58 : sf2_if_io_dly_4 */
#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_3_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_3_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF2_IO_3_DO_DLY_SEL_SHIFT)
/* 0x5C : sf3_if_io_dly_0 */
#define SF_CTRL_SF3_CS_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF3_CS_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_CS_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_CS2_DLY_SEL_SHIFT (2U)
#define SF_CTRL_SF3_CS2_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_CS2_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_CLK_OUT_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_DQS_OE_DLY_SEL_SHIFT (26U)
#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_DQS_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_DQS_DI_DLY_SEL_SHIFT (28U)
#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_DQS_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_DQS_DO_DLY_SEL_SHIFT (30U)
#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_DQS_DO_DLY_SEL_SHIFT)
/* 0x60 : sf3_if_io_dly_1 */
#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_0_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_0_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_0_DO_DLY_SEL_SHIFT)
/* 0x64 : sf3_if_io_dly_2 */
#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_1_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_1_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_1_DO_DLY_SEL_SHIFT)
/* 0x68 : sf3_if_io_dly_3 */
#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_2_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_2_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_2_DO_DLY_SEL_SHIFT)
/* 0x6C : sf3_if_io_dly_4 */
#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_3_OE_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_3_DI_DLY_SEL_SHIFT)
#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MASK (0x3<<SF_CTRL_SF3_IO_3_DO_DLY_SEL_SHIFT)
/* 0x70 : sf_ctrl_2 */
#define SF_CTRL_SF_IF_PAD_SEL_SHIFT (0U)
#define SF_CTRL_SF_IF_PAD_SEL_MASK (0x3<<SF_CTRL_SF_IF_PAD_SEL_SHIFT)
#define SF_CTRL_SF_IF_PAD_SEL_LOCK (1<<3U)
#define SF_CTRL_SF_IF_DTR_EN (1<<4U)
#define SF_CTRL_SF_IF_DQS_EN (1<<5U)
#define SF_CTRL_SF_IF_TRIG_WR_PROT (1<<6U)
#define SF_CTRL_SF_ID_OFFSET_LOCK (1<<7U)
#define SF_CTRL_SF_AHB2SIF_REMAP_LOCK (1<<25U)
#define SF_CTRL_SF_AHB2SIF_REMAP_SHIFT (26U)
#define SF_CTRL_SF_AHB2SIF_REMAP_MASK (0x3<<SF_CTRL_SF_AHB2SIF_REMAP_SHIFT)
#define SF_CTRL_SF_IF_BK_SWAP (1<<28U)
#define SF_CTRL_SF_IF_BK2_MODE (1<<29U)
#define SF_CTRL_SF_IF_BK2_EN (1<<30U)
#define SF_CTRL_SF_IF_0_BK_SEL (1<<31U)
/* 0x74 : sf_ctrl_3 */
#define SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT (0U)
#define SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK (0xf<<SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT)
#define SF_CTRL_SF_CMDS_2_EN (1<<4U)
#define SF_CTRL_SF_CMDS_2_BT_DLY_SHIFT (5U)
#define SF_CTRL_SF_CMDS_2_BT_DLY_MASK (0x7<<SF_CTRL_SF_CMDS_2_BT_DLY_SHIFT)
#define SF_CTRL_SF_CMDS_2_BT_EN (1<<8U)
#define SF_CTRL_SF_CMDS_2_WRAP_Q_INI (1<<9U)
#define SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT (10U)
#define SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK (0x3<<SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT)
#define SF_CTRL_SF_CMDS_2_WRAP_Q (1<<12U)
#define SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT (13U)
#define SF_CTRL_SF_CMDS_1_WRAP_LEN_MASK (0xf<<SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT)
#define SF_CTRL_SF_CMDS_1_EN (1<<17U)
#define SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT (18U)
#define SF_CTRL_SF_CMDS_1_WRAP_MODE_MASK (0x3<<SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT)
#define SF_CTRL_SF_CMDS_CORE_EN (1<<20U)
#define SF_CTRL_SF_IF_1_ACK_LAT_SHIFT (29U)
#define SF_CTRL_SF_IF_1_ACK_LAT_MASK (0x7<<SF_CTRL_SF_IF_1_ACK_LAT_SHIFT)
/* 0x78 : sf_if_iahb_3 */
#define SF_CTRL_SF_IF_2_DMY_BYTE_SHIFT (12U)
#define SF_CTRL_SF_IF_2_DMY_BYTE_MASK (0x1f<<SF_CTRL_SF_IF_2_DMY_BYTE_SHIFT)
#define SF_CTRL_SF_IF_2_ADR_BYTE_SHIFT (17U)
#define SF_CTRL_SF_IF_2_ADR_BYTE_MASK (0x7<<SF_CTRL_SF_IF_2_ADR_BYTE_SHIFT)
#define SF_CTRL_SF_IF_2_CMD_BYTE_SHIFT (20U)
#define SF_CTRL_SF_IF_2_CMD_BYTE_MASK (0x7<<SF_CTRL_SF_IF_2_CMD_BYTE_SHIFT)
#define SF_CTRL_SF_IF_2_DAT_RW (1<<23U)
#define SF_CTRL_SF_IF_2_DAT_EN (1<<24U)
#define SF_CTRL_SF_IF_2_DMY_EN (1<<25U)
#define SF_CTRL_SF_IF_2_ADR_EN (1<<26U)
#define SF_CTRL_SF_IF_2_CMD_EN (1<<27U)
#define SF_CTRL_SF_IF_2_SPI_MODE_SHIFT (28U)
#define SF_CTRL_SF_IF_2_SPI_MODE_MASK (0x7<<SF_CTRL_SF_IF_2_SPI_MODE_SHIFT)
#define SF_CTRL_SF_IF_2_QPI_MODE_EN (1<<31U)
/* 0x7C : sf_if_iahb_4 */
#define SF_CTRL_SF_IF_2_CMD_BUF_0_SHIFT (0U)
#define SF_CTRL_SF_IF_2_CMD_BUF_0_MASK (0xffffffffL<<SF_CTRL_SF_IF_2_CMD_BUF_0_SHIFT)
/* 0x80 : sf_if_iahb_5 */
#define SF_CTRL_SF_IF_2_CMD_BUF_1_SHIFT (0U)
#define SF_CTRL_SF_IF_2_CMD_BUF_1_MASK (0xffffffffL<<SF_CTRL_SF_IF_2_CMD_BUF_1_SHIFT)
/* 0x84 : sf_if_iahb_6 */
#define SF_CTRL_SF_IF_3_ADR_BYTE_SHIFT (17U)
#define SF_CTRL_SF_IF_3_ADR_BYTE_MASK (0x7<<SF_CTRL_SF_IF_3_ADR_BYTE_SHIFT)
#define SF_CTRL_SF_IF_3_CMD_BYTE_SHIFT (20U)
#define SF_CTRL_SF_IF_3_CMD_BYTE_MASK (0x7<<SF_CTRL_SF_IF_3_CMD_BYTE_SHIFT)
#define SF_CTRL_SF_IF_3_ADR_EN (1<<26U)
#define SF_CTRL_SF_IF_3_CMD_EN (1<<27U)
#define SF_CTRL_SF_IF_3_SPI_MODE_SHIFT (28U)
#define SF_CTRL_SF_IF_3_SPI_MODE_MASK (0x7<<SF_CTRL_SF_IF_3_SPI_MODE_SHIFT)
#define SF_CTRL_SF_IF_3_QPI_MODE_EN (1<<31U)
/* 0x88 : sf_if_iahb_7 */
#define SF_CTRL_SF_IF_3_CMD_BUF_0_SHIFT (0U)
#define SF_CTRL_SF_IF_3_CMD_BUF_0_MASK (0xffffffffL<<SF_CTRL_SF_IF_3_CMD_BUF_0_SHIFT)
/* 0x8C : sf_if_iahb_8 */
#define SF_CTRL_SF_IF_3_CMD_BUF_1_SHIFT (0U)
#define SF_CTRL_SF_IF_3_CMD_BUF_1_MASK (0xffffffffL<<SF_CTRL_SF_IF_3_CMD_BUF_1_SHIFT)
/* 0x90 : sf_if_iahb_9 */
#define SF_CTRL_SF_IF_4_DMY_BYTE_SHIFT (12U)
#define SF_CTRL_SF_IF_4_DMY_BYTE_MASK (0x1f<<SF_CTRL_SF_IF_4_DMY_BYTE_SHIFT)
#define SF_CTRL_SF_IF_4_ADR_BYTE_SHIFT (17U)
#define SF_CTRL_SF_IF_4_ADR_BYTE_MASK (0x7<<SF_CTRL_SF_IF_4_ADR_BYTE_SHIFT)
#define SF_CTRL_SF_IF_4_CMD_BYTE_SHIFT (20U)
#define SF_CTRL_SF_IF_4_CMD_BYTE_MASK (0x7<<SF_CTRL_SF_IF_4_CMD_BYTE_SHIFT)
#define SF_CTRL_SF_IF_4_DAT_RW (1<<23U)
#define SF_CTRL_SF_IF_4_DAT_EN (1<<24U)
#define SF_CTRL_SF_IF_4_DMY_EN (1<<25U)
#define SF_CTRL_SF_IF_4_ADR_EN (1<<26U)
#define SF_CTRL_SF_IF_4_CMD_EN (1<<27U)
#define SF_CTRL_SF_IF_4_SPI_MODE_SHIFT (28U)
#define SF_CTRL_SF_IF_4_SPI_MODE_MASK (0x7<<SF_CTRL_SF_IF_4_SPI_MODE_SHIFT)
#define SF_CTRL_SF_IF_4_QPI_MODE_EN (1<<31U)
/* 0x94 : sf_if_iahb_10 */
#define SF_CTRL_SF_IF_4_CMD_BUF_0_SHIFT (0U)
#define SF_CTRL_SF_IF_4_CMD_BUF_0_MASK (0xffffffffL<<SF_CTRL_SF_IF_4_CMD_BUF_0_SHIFT)
/* 0x98 : sf_if_iahb_11 */
#define SF_CTRL_SF_IF_4_CMD_BUF_1_SHIFT (0U)
#define SF_CTRL_SF_IF_4_CMD_BUF_1_MASK (0xffffffffL<<SF_CTRL_SF_IF_4_CMD_BUF_1_SHIFT)
/* 0x9C : sf_if_iahb_12 */
#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL (1<<2U)
#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC (1<<3U)
#define SF_CTRL_SF2_CLK_OUT_INV_SEL (1<<4U)
#define SF_CTRL_SF3_CLK_OUT_INV_SEL (1<<5U)
#define SF_CTRL_SF2_IF_READ_DLY_N_SHIFT (8U)
#define SF_CTRL_SF2_IF_READ_DLY_N_MASK (0x7<<SF_CTRL_SF2_IF_READ_DLY_N_SHIFT)
#define SF_CTRL_SF2_IF_READ_DLY_EN (1<<11U)
#define SF_CTRL_SF2_IF_READ_DLY_SRC (1<<12U)
/* 0xA0 : sf_id0_offset */
#define SF_CTRL_SF_ID0_OFFSET_SHIFT (0U)
#define SF_CTRL_SF_ID0_OFFSET_MASK (0xfffffff<<SF_CTRL_SF_ID0_OFFSET_SHIFT)
/* 0xA4 : sf_id1_offset */
#define SF_CTRL_SF_ID1_OFFSET_SHIFT (0U)
#define SF_CTRL_SF_ID1_OFFSET_MASK (0xfffffff<<SF_CTRL_SF_ID1_OFFSET_SHIFT)
/* 0xA8 : sf_bk2_id0_offset */
#define SF_CTRL_SF_BK2_ID0_OFFSET_SHIFT (0U)
#define SF_CTRL_SF_BK2_ID0_OFFSET_MASK (0xfffffff<<SF_CTRL_SF_BK2_ID0_OFFSET_SHIFT)
/* 0xAC : sf_bk2_id1_offset */
#define SF_CTRL_SF_BK2_ID1_OFFSET_SHIFT (0U)
#define SF_CTRL_SF_BK2_ID1_OFFSET_MASK (0xfffffff<<SF_CTRL_SF_BK2_ID1_OFFSET_SHIFT)
/* 0xB0 : sf_dbg */
#define SF_CTRL_SF_AUTOLOAD_ST_SHIFT (0U)
#define SF_CTRL_SF_AUTOLOAD_ST_MASK (0x1f<<SF_CTRL_SF_AUTOLOAD_ST_SHIFT)
#define SF_CTRL_SF_AUTOLOAD_ST_DONE (1<<5U)
/* 0xC0 : sf_if2_ctrl_0 */
#define SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL (1<<2U)
#define SF_CTRL_SF_IF2_READ_DLY_N_SHIFT (8U)
#define SF_CTRL_SF_IF2_READ_DLY_N_MASK (0x7<<SF_CTRL_SF_IF2_READ_DLY_N_SHIFT)
#define SF_CTRL_SF_IF2_READ_DLY_EN (1<<11U)
#define SF_CTRL_SF_IF2_INT (1<<16U)
#define SF_CTRL_SF_IF2_INT_CLR (1<<17U)
#define SF_CTRL_SF_IF2_INT_SET (1<<18U)
#define SF_CTRL_SF_IF2_REPLACE_SF1 (1<<23U)
#define SF_CTRL_SF_IF2_REPLACE_SF2 (1<<24U)
#define SF_CTRL_SF_IF2_REPLACE_SF3 (1<<25U)
#define SF_CTRL_SF_IF2_PAD_SEL_SHIFT (26U)
#define SF_CTRL_SF_IF2_PAD_SEL_MASK (0x3<<SF_CTRL_SF_IF2_PAD_SEL_SHIFT)
#define SF_CTRL_SF_IF2_BK_SWAP (1<<28U)
#define SF_CTRL_SF_IF2_BK2_MODE (1<<29U)
#define SF_CTRL_SF_IF2_BK2_EN (1<<30U)
#define SF_CTRL_SF_IF2_BK_SEL (1<<31U)
/* 0xC4 : sf_if2_ctrl_1 */
#define SF_CTRL_SF_IF2_SR_PAT_MASK_SHIFT (0U)
#define SF_CTRL_SF_IF2_SR_PAT_MASK_MASK (0xff<<SF_CTRL_SF_IF2_SR_PAT_MASK_SHIFT)
#define SF_CTRL_SF_IF2_SR_PAT_SHIFT (8U)
#define SF_CTRL_SF_IF2_SR_PAT_MASK (0xff<<SF_CTRL_SF_IF2_SR_PAT_SHIFT)
#define SF_CTRL_SF_IF2_SR_INT (1<<16U)
#define SF_CTRL_SF_IF2_SR_INT_EN (1<<17U)
#define SF_CTRL_SF_IF2_SR_INT_SET (1<<18U)
#define SF_CTRL_SF_IF2_ACK_LAT_SHIFT (20U)
#define SF_CTRL_SF_IF2_ACK_LAT_MASK (0x7<<SF_CTRL_SF_IF2_ACK_LAT_SHIFT)
#define SF_CTRL_SF_IF2_REG_HOLD (1<<24U)
#define SF_CTRL_SF_IF2_REG_WP (1<<25U)
#define SF_CTRL_SF_IF2_FN_SEL (1<<28U)
#define SF_CTRL_SF_IF2_EN (1<<29U)
/* 0xC8 : sf_if2_sahb_0 */
#define SF_CTRL_SF_IF2_BUSY (1<<0U)
#define SF_CTRL_SF_IF2_0_TRIG (1<<1U)
#define SF_CTRL_SF_IF2_0_DAT_BYTE_SHIFT (2U)
#define SF_CTRL_SF_IF2_0_DAT_BYTE_MASK (0x3ff<<SF_CTRL_SF_IF2_0_DAT_BYTE_SHIFT)
#define SF_CTRL_SF_IF2_0_DMY_BYTE_SHIFT (12U)
#define SF_CTRL_SF_IF2_0_DMY_BYTE_MASK (0x1f<<SF_CTRL_SF_IF2_0_DMY_BYTE_SHIFT)
#define SF_CTRL_SF_IF2_0_ADR_BYTE_SHIFT (17U)
#define SF_CTRL_SF_IF2_0_ADR_BYTE_MASK (0x7<<SF_CTRL_SF_IF2_0_ADR_BYTE_SHIFT)
#define SF_CTRL_SF_IF2_0_CMD_BYTE_SHIFT (20U)
#define SF_CTRL_SF_IF2_0_CMD_BYTE_MASK (0x7<<SF_CTRL_SF_IF2_0_CMD_BYTE_SHIFT)
#define SF_CTRL_SF_IF2_0_DAT_RW (1<<23U)
#define SF_CTRL_SF_IF2_0_DAT_EN (1<<24U)
#define SF_CTRL_SF_IF2_0_DMY_EN (1<<25U)
#define SF_CTRL_SF_IF2_0_ADR_EN (1<<26U)
#define SF_CTRL_SF_IF2_0_CMD_EN (1<<27U)
#define SF_CTRL_SF_IF2_0_SPI_MODE_SHIFT (28U)
#define SF_CTRL_SF_IF2_0_SPI_MODE_MASK (0x7<<SF_CTRL_SF_IF2_0_SPI_MODE_SHIFT)
#define SF_CTRL_SF_IF2_0_QPI_MODE_EN (1<<31U)
/* 0xCC : sf_if2_sahb_1 */
#define SF_CTRL_SF_IF2_0_CMD_BUF_0_SHIFT (0U)
#define SF_CTRL_SF_IF2_0_CMD_BUF_0_MASK (0xffffffffL<<SF_CTRL_SF_IF2_0_CMD_BUF_0_SHIFT)
/* 0xD0 : sf_if2_sahb_2 */
#define SF_CTRL_SF_IF2_0_CMD_BUF_1_SHIFT (0U)
#define SF_CTRL_SF_IF2_0_CMD_BUF_1_MASK (0xffffffffL<<SF_CTRL_SF_IF2_0_CMD_BUF_1_SHIFT)
/* 0x100 : sf_ctrl_prot_en_rd */
#define SF_CTRL_ID0_EN_RD (1<<1U)
#define SF_CTRL_ID1_EN_RD (1<<2U)
#define SF_CTRL_SF_SEC_TZSID_LOCK (1<<28U)
#define SF_CTRL_SF_IF2_0_TRIG_WR_LOCK (1<<29U)
#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK (1<<30U)
#define SF_CTRL_SF_DBG_DIS (1<<31U)
/* 0x104 : sf_ctrl_prot_en */
#define SF_CTRL_ID0_EN (1<<1U)
#define SF_CTRL_ID1_EN (1<<2U)
/* 0x200 : sf_aes_key_r0_0 */
#define SF_CTRL_SF_AES_KEY_R0_0_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_0_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_0_SHIFT)
/* 0x204 : sf_aes_key_r0_1 */
#define SF_CTRL_SF_AES_KEY_R0_1_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_1_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_1_SHIFT)
/* 0x208 : sf_aes_key_r0_2 */
#define SF_CTRL_SF_AES_KEY_R0_2_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_2_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_2_SHIFT)
/* 0x20C : sf_aes_key_r0_3 */
#define SF_CTRL_SF_AES_KEY_R0_3_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_3_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_3_SHIFT)
/* 0x210 : sf_aes_key_r0_4 */
#define SF_CTRL_SF_AES_KEY_R0_4_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_4_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_4_SHIFT)
/* 0x214 : sf_aes_key_r0_5 */
#define SF_CTRL_SF_AES_KEY_R0_5_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_5_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_5_SHIFT)
/* 0x218 : sf_aes_key_r0_6 */
#define SF_CTRL_SF_AES_KEY_R0_6_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_6_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_6_SHIFT)
/* 0x21C : sf_aes_key_r0_7 */
#define SF_CTRL_SF_AES_KEY_R0_7_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R0_7_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R0_7_SHIFT)
/* 0x220 : sf_aes_iv_r0_w0 */
#define SF_CTRL_SF_AES_IV_R0_W0_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R0_W0_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R0_W0_SHIFT)
/* 0x224 : sf_aes_iv_r0_w1 */
#define SF_CTRL_SF_AES_IV_R0_W1_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R0_W1_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R0_W1_SHIFT)
/* 0x228 : sf_aes_iv_r0_w2 */
#define SF_CTRL_SF_AES_IV_R0_W2_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R0_W2_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R0_W2_SHIFT)
/* 0x22C : sf_aes_iv_r0_w3 */
#define SF_CTRL_SF_AES_IV_R0_W3_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R0_W3_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R0_W3_SHIFT)
/* 0x230 : sf_aes_r0_start */
#define SF_CTRL_SF_AES_REGION_R0_START_SHIFT (0U)
#define SF_CTRL_SF_AES_REGION_R0_START_MASK (0x7ffff<<SF_CTRL_SF_AES_REGION_R0_START_SHIFT)
#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN (1<<29U)
#define SF_CTRL_SF_AES_REGION_R0_EN (1<<30U)
#define SF_CTRL_SF_AES_REGION_R0_LOCK (1<<31U)
/* 0x234 : sf_aes_r0_end */
#define SF_CTRL_SF_AES_REGION_R0_END_SHIFT (0U)
#define SF_CTRL_SF_AES_REGION_R0_END_MASK (0x7ffff<<SF_CTRL_SF_AES_REGION_R0_END_SHIFT)
/* 0x280 : sf_aes_key_r1_0 */
#define SF_CTRL_SF_AES_KEY_R1_0_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_0_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_0_SHIFT)
/* 0x284 : sf_aes_key_r1_1 */
#define SF_CTRL_SF_AES_KEY_R1_1_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_1_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_1_SHIFT)
/* 0x288 : sf_aes_key_r1_2 */
#define SF_CTRL_SF_AES_KEY_R1_2_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_2_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_2_SHIFT)
/* 0x28C : sf_aes_key_r1_3 */
#define SF_CTRL_SF_AES_KEY_R1_3_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_3_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_3_SHIFT)
/* 0x290 : sf_aes_key_r1_4 */
#define SF_CTRL_SF_AES_KEY_R1_4_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_4_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_4_SHIFT)
/* 0x294 : sf_aes_key_r1_5 */
#define SF_CTRL_SF_AES_KEY_R1_5_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_5_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_5_SHIFT)
/* 0x298 : sf_aes_key_r1_6 */
#define SF_CTRL_SF_AES_KEY_R1_6_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_6_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_6_SHIFT)
/* 0x29C : sf_aes_key_r1_7 */
#define SF_CTRL_SF_AES_KEY_R1_7_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R1_7_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R1_7_SHIFT)
/* 0x2A0 : sf_aes_iv_r1_w0 */
#define SF_CTRL_SF_AES_IV_R1_W0_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R1_W0_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R1_W0_SHIFT)
/* 0x2A4 : sf_aes_iv_r1_w1 */
#define SF_CTRL_SF_AES_IV_R1_W1_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R1_W1_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R1_W1_SHIFT)
/* 0x2A8 : sf_aes_iv_r1_w2 */
#define SF_CTRL_SF_AES_IV_R1_W2_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R1_W2_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R1_W2_SHIFT)
/* 0x2AC : sf_aes_iv_r1_w3 */
#define SF_CTRL_SF_AES_IV_R1_W3_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R1_W3_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R1_W3_SHIFT)
/* 0x2B0 : sf_aes_r1_start */
#define SF_CTRL_SF_AES_R1_START_SHIFT (0U)
#define SF_CTRL_SF_AES_R1_START_MASK (0x7ffff<<SF_CTRL_SF_AES_R1_START_SHIFT)
#define SF_CTRL_SF_AES_R1_HW_KEY_EN (1<<29U)
#define SF_CTRL_SF_AES_R1_EN (1<<30U)
#define SF_CTRL_SF_AES_R1_LOCK (1<<31U)
/* 0x2B4 : sf_aes_r1_end */
#define SF_CTRL_SF_AES_R1_END_SHIFT (0U)
#define SF_CTRL_SF_AES_R1_END_MASK (0x7ffff<<SF_CTRL_SF_AES_R1_END_SHIFT)
/* 0x300 : sf_aes_key_r2_0 */
#define SF_CTRL_SF_AES_KEY_R2_0_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_0_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_0_SHIFT)
/* 0x304 : sf_aes_key_r2_1 */
#define SF_CTRL_SF_AES_KEY_R2_1_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_1_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_1_SHIFT)
/* 0x308 : sf_aes_key_r2_2 */
#define SF_CTRL_SF_AES_KEY_R2_2_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_2_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_2_SHIFT)
/* 0x30C : sf_aes_key_r2_3 */
#define SF_CTRL_SF_AES_KEY_R2_3_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_3_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_3_SHIFT)
/* 0x310 : sf_aes_key_r2_4 */
#define SF_CTRL_SF_AES_KEY_R2_4_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_4_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_4_SHIFT)
/* 0x314 : sf_aes_key_r2_5 */
#define SF_CTRL_SF_AES_KEY_R2_5_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_5_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_5_SHIFT)
/* 0x318 : sf_aes_key_r2_6 */
#define SF_CTRL_SF_AES_KEY_R2_6_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_6_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_6_SHIFT)
/* 0x31C : sf_aes_key_r2_7 */
#define SF_CTRL_SF_AES_KEY_R2_7_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_R2_7_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_R2_7_SHIFT)
/* 0x320 : sf_aes_iv_r2_w0 */
#define SF_CTRL_SF_AES_IV_R2_W0_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R2_W0_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R2_W0_SHIFT)
/* 0x324 : sf_aes_iv_r2_w1 */
#define SF_CTRL_SF_AES_IV_R2_W1_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R2_W1_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R2_W1_SHIFT)
/* 0x328 : sf_aes_iv_r2_w2 */
#define SF_CTRL_SF_AES_IV_R2_W2_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R2_W2_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R2_W2_SHIFT)
/* 0x32C : sf_aes_iv_r2_w3 */
#define SF_CTRL_SF_AES_IV_R2_W3_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_R2_W3_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_R2_W3_SHIFT)
/* 0x330 : sf_aes_r2_start */
#define SF_CTRL_SF_AES_R2_START_SHIFT (0U)
#define SF_CTRL_SF_AES_R2_START_MASK (0x7ffff<<SF_CTRL_SF_AES_R2_START_SHIFT)
#define SF_CTRL_SF_AES_R2_HW_KEY_EN (1<<29U)
#define SF_CTRL_SF_AES_R2_EN (1<<30U)
#define SF_CTRL_SF_AES_R2_LOCK (1<<31U)
/* 0x334 : sf_aes_r2_end */
#define SF_CTRL_SF_AES_R2_END_SHIFT (0U)
#define SF_CTRL_SF_AES_R2_END_MASK (0x7ffff<<SF_CTRL_SF_AES_R2_END_SHIFT)
/*Following is reg patch*/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define SF_CTRL_IF_SAHB_0_OFFSET (0x0)/* sf_if_sahb_0 */
#define SF_CTRL_IF_SAHB_1_OFFSET (0x4)/* sf_if_sahb_1 */
#define SF_CTRL_IF_SAHB_2_OFFSET (0x8)/* sf_if_sahb_2 */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : sf_if_sahb_0 */
#define SF_CTRL_IF_BUSY (1<<0U)
#define SF_CTRL_IF_0_TRIG (1<<1U)
#define SF_CTRL_IF_0_DAT_BYTE_SHIFT (2U)
#define SF_CTRL_IF_0_DAT_BYTE_MASK (0x3ff<<SF_CTRL_IF_0_DAT_BYTE_SHIFT)
#define SF_CTRL_IF_0_DMY_BYTE_SHIFT (12U)
#define SF_CTRL_IF_0_DMY_BYTE_MASK (0x1f<<SF_CTRL_IF_0_DMY_BYTE_SHIFT)
#define SF_CTRL_IF_0_ADR_BYTE_SHIFT (17U)
#define SF_CTRL_IF_0_ADR_BYTE_MASK (0x7<<SF_CTRL_IF_0_ADR_BYTE_SHIFT)
#define SF_CTRL_IF_0_CMD_BYTE_SHIFT (20U)
#define SF_CTRL_IF_0_CMD_BYTE_MASK (0x7<<SF_CTRL_IF_0_CMD_BYTE_SHIFT)
#define SF_CTRL_IF_0_DAT_RW (1<<23U)
#define SF_CTRL_IF_0_DAT_EN (1<<24U)
#define SF_CTRL_IF_0_DMY_EN (1<<25U)
#define SF_CTRL_IF_0_ADR_EN (1<<26U)
#define SF_CTRL_IF_0_CMD_EN (1<<27U)
#define SF_CTRL_IF_0_SPI_MODE_SHIFT (28U)
#define SF_CTRL_IF_0_SPI_MODE_MASK (0x7<<SF_CTRL_IF_0_SPI_MODE_SHIFT)
#define SF_CTRL_IF_0_QPI_MODE_EN (1<<31U)
/* 0x4 : sf_if_sahb_1 */
#define SF_CTRL_IF_0_CMD_BUF_0_SHIFT (0U)
#define SF_CTRL_IF_0_CMD_BUF_0_MASK (0xffffffffL<<SF_CTRL_IF_0_CMD_BUF_0_SHIFT)
/* 0x8 : sf_if_sahb_2 */
#define SF_CTRL_IF_0_CMD_BUF_1_SHIFT (0U)
#define SF_CTRL_IF_0_CMD_BUF_1_MASK (0xffffffffL<<SF_CTRL_IF_0_CMD_BUF_1_SHIFT)
#define SF_CTRL_IF1_SAHB_OFFSET 0x8
#define SF_CTRL_IF2_SAHB_OFFSET 0xC8
/*Following is reg patch*/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define SF_CTRL_IO_DLY_0_OFFSET (0x0)/* if_io_dly_0 */
#define SF_CTRL_IO_DLY_1_OFFSET (0x4)/* if_io_dly_1 */
#define SF_CTRL_IO_DLY_2_OFFSET (0x8)/* if_io_dly_2 */
#define SF_CTRL_IO_DLY_3_OFFSET (0xc)/* if_io_dly_3 */
#define SF_CTRL_IO_DLY_4_OFFSET (0x10)/* if_io_dly_4 */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : if_io_dly_0 */
#define SF_CTRL_CS_DLY_SEL_SHIFT (0U)
#define SF_CTRL_CS_DLY_SEL_MASK (0x3<<SF_CTRL_CS_DLY_SEL_SHIFT)
#define SF_CTRL_CS2_DLY_SEL_SHIFT (2U)
#define SF_CTRL_CS2_DLY_SEL_MASK (0x3<<SF_CTRL_CS2_DLY_SEL_SHIFT)
#define SF_CTRL_CLK_OUT_DLY_SEL_SHIFT (8U)
#define SF_CTRL_CLK_OUT_DLY_SEL_MASK (0x3<<SF_CTRL_CLK_OUT_DLY_SEL_SHIFT)
#define SF_CTRL_DQS_OE_DLY_SEL_SHIFT (26U)
#define SF_CTRL_DQS_OE_DLY_SEL_MASK (0x3<<SF_CTRL_DQS_OE_DLY_SEL_SHIFT)
#define SF_CTRL_DQS_DI_DLY_SEL_SHIFT (28U)
#define SF_CTRL_DQS_DI_DLY_SEL_MASK (0x3<<SF_CTRL_DQS_DI_DLY_SEL_SHIFT)
#define SF_CTRL_DQS_DO_DLY_SEL_SHIFT (30U)
#define SF_CTRL_DQS_DO_DLY_SEL_MASK (0x3<<SF_CTRL_DQS_DO_DLY_SEL_SHIFT)
/* 0x4 : if_io_dly_1 */
#define SF_CTRL_IO_0_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_IO_0_OE_DLY_SEL_MASK (0x3<<SF_CTRL_IO_0_OE_DLY_SEL_SHIFT)
#define SF_CTRL_IO_0_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_IO_0_DI_DLY_SEL_MASK (0x3<<SF_CTRL_IO_0_DI_DLY_SEL_SHIFT)
#define SF_CTRL_IO_0_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_IO_0_DO_DLY_SEL_MASK (0x3<<SF_CTRL_IO_0_DO_DLY_SEL_SHIFT)
/* 0x8 : if_io_dly_2 */
#define SF_CTRL_IO_1_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_IO_1_OE_DLY_SEL_MASK (0x3<<SF_CTRL_IO_1_OE_DLY_SEL_SHIFT)
#define SF_CTRL_IO_1_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_IO_1_DI_DLY_SEL_MASK (0x3<<SF_CTRL_IO_1_DI_DLY_SEL_SHIFT)
#define SF_CTRL_IO_1_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_IO_1_DO_DLY_SEL_MASK (0x3<<SF_CTRL_IO_1_DO_DLY_SEL_SHIFT)
/* 0xc : if_io_dly_3 */
#define SF_CTRL_IO_2_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_IO_2_OE_DLY_SEL_MASK (0x3<<SF_CTRL_IO_2_OE_DLY_SEL_SHIFT)
#define SF_CTRL_IO_2_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_IO_2_DI_DLY_SEL_MASK (0x3<<SF_CTRL_IO_2_DI_DLY_SEL_SHIFT)
#define SF_CTRL_IO_2_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_IO_2_DO_DLY_SEL_MASK (0x3<<SF_CTRL_IO_2_DO_DLY_SEL_SHIFT)
/* 0x10 : if_io_dly_4 */
#define SF_CTRL_IO_3_OE_DLY_SEL_SHIFT (0U)
#define SF_CTRL_IO_3_OE_DLY_SEL_MASK (0x3<<SF_CTRL_IO_3_OE_DLY_SEL_SHIFT)
#define SF_CTRL_IO_3_DI_DLY_SEL_SHIFT (8U)
#define SF_CTRL_IO_3_DI_DLY_SEL_MASK (0x3<<SF_CTRL_IO_3_DI_DLY_SEL_SHIFT)
#define SF_CTRL_IO_3_DO_DLY_SEL_SHIFT (16U)
#define SF_CTRL_IO_3_DO_DLY_SEL_MASK (0x3<<SF_CTRL_IO_3_DO_DLY_SEL_SHIFT)
#define SF_CTRL_IF_IO_DLY_1_OFFSET 0x30
#define SF_CTRL_IF_IO_DLY_2_OFFSET 0x48
#define SF_CTRL_IF_IO_DLY_3_OFFSET 0x5C
/*Following is reg patch*/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0)/* sf_aes_key_0 */
#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4)/* sf_aes_key_1 */
#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8)/* sf_aes_key_2 */
#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc)/* sf_aes_key_3 */
#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10)/* sf_aes_key_4 */
#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14)/* sf_aes_key_5 */
#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18)/* sf_aes_key_6 */
#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c)/* sf_aes_key_7 */
#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20)/* sf_aes_iv_w0 */
#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24)/* sf_aes_iv_w1 */
#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28)/* sf_aes_iv_w2 */
#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c)/* sf_aes_iv_w3 */
#define SF_CTRL_SF_AES_START_OFFSET (0x30)/* sf_aes_start */
#define SF_CTRL_SF_AES_END_OFFSET (0x34)/* sf_aes_end */
/* Register Bitfield definitions *****************************************************/
/* 0x0 : sf_aes_key_0 */
#define SF_CTRL_SF_AES_KEY_0_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_0_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_0_SHIFT)
/* 0x4 : sf_aes_key_1 */
#define SF_CTRL_SF_AES_KEY_1_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_1_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_1_SHIFT)
/* 0x8 : sf_aes_key_2 */
#define SF_CTRL_SF_AES_KEY_2_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_2_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_2_SHIFT)
/* 0xc : sf_aes_key_3 */
#define SF_CTRL_SF_AES_KEY_3_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_3_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_3_SHIFT)
/* 0x10 : sf_aes_key_4 */
#define SF_CTRL_SF_AES_KEY_4_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_4_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_4_SHIFT)
/* 0x14 : sf_aes_key_5 */
#define SF_CTRL_SF_AES_KEY_5_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_5_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_5_SHIFT)
/* 0x18 : sf_aes_key_6 */
#define SF_CTRL_SF_AES_KEY_6_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_6_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_6_SHIFT)
/* 0x1c : sf_aes_key_7 */
#define SF_CTRL_SF_AES_KEY_7_SHIFT (0U)
#define SF_CTRL_SF_AES_KEY_7_MASK (0xffffffffL<<SF_CTRL_SF_AES_KEY_7_SHIFT)
/* 0x20 : sf_aes_iv_w0 */
#define SF_CTRL_SF_AES_IV_W0_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_W0_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_W0_SHIFT)
/* 0x24 : sf_aes_iv_w1 */
#define SF_CTRL_SF_AES_IV_W1_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_W1_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_W1_SHIFT)
/* 0x28 : sf_aes_iv_w2 */
#define SF_CTRL_SF_AES_IV_W2_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_W2_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_W2_SHIFT)
/* 0x2c : sf_aes_iv_w3 */
#define SF_CTRL_SF_AES_IV_W3_SHIFT (0U)
#define SF_CTRL_SF_AES_IV_W3_MASK (0xffffffffL<<SF_CTRL_SF_AES_IV_W3_SHIFT)
/* 0x30 : sf_aes_start */
#define SF_CTRL_SF_AES_REGION_START_SHIFT (0U)
#define SF_CTRL_SF_AES_REGION_START_MASK (0x7ffff<<SF_CTRL_SF_AES_REGION_START_SHIFT)
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN (1<<29U)
#define SF_CTRL_SF_AES_REGION_EN (1<<30U)
#define SF_CTRL_SF_AES_REGION_LOCK (1<<31U)
/* 0x34 : sf_aes_end */
#define SF_CTRL_SF_AES_REGION_END_SHIFT (0U)
#define SF_CTRL_SF_AES_REGION_END_MASK (0x7ffff<<SF_CTRL_SF_AES_REGION_END_SHIFT)
#define SF_CTRL_AES_REGION_OFFSET 0x200
#endif /* __SF_CTRL_REG_H__ */

31
drivers/lhal/src/bflb_cam.c
View File

@ -369,22 +369,10 @@ void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *co
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET);
}
#endif
}
void bflb_cam_start(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
regval |= CAM_REG_DVP_ENABLE;
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
#if !defined(BL702)
#if defined(BL808)
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
if (regval & CAM_FRONT_REG_ISP_DTSRC_SRC) {
if (config->input_source == 0) {
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval |= CAM_FRONT_RG_DVPAS_ENABLE;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
@ -397,6 +385,17 @@ void bflb_cam_start(struct bflb_device_s *dev)
#endif
}
void bflb_cam_start(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
regval |= CAM_REG_DVP_ENABLE;
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
}
void bflb_cam_stop(struct bflb_device_s *dev)
{
uint32_t reg_base;
@ -406,12 +405,6 @@ void bflb_cam_stop(struct bflb_device_s *dev)
regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
regval &= ~CAM_REG_DVP_ENABLE;
putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
#if !defined(BL702)
regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
regval &= ~CAM_FRONT_RG_DVPAS_ENABLE;
putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
#endif
}
void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)

93
drivers/lhal/src/bflb_clock.c Normal file
View File

@ -0,0 +1,93 @@
#include "bflb_clock.h"
#if defined(BL702)
#include "bl702_clock.h"
#elif defined(BL702L)
#include "bl702l_clock.h"
#elif defined(BL606P)
#include "bl606p_clock.h"
#elif defined(BL808)
#include "bl808_clock.h"
#elif defined(BL616)
#include "bl616_clock.h"
#elif defined(WB03)
#include "wb03_clock.h"
#elif defined(BL628)
#include "bl628_clock.h"
#endif
/****************************************************************************/ /**
* @brief get system clock
*
* @param type: BFLB_SYSTEM_XXX
*
* @return NONE
*
*******************************************************************************/
uint32_t ATTR_CLOCK_SECTION bflb_clk_get_system_clock(uint8_t type)
{
switch (type) {
case BFLB_SYSTEM_ROOT_CLOCK:
return bflb_clock_get_root();
case BFLB_SYSTEM_CPU_CLK:
return bflb_clock_get_fclk();
case BFLB_SYSTEM_PBCLK:
return bflb_clock_get_bclk();
case BFLB_SYSTEM_XCLK:
return bflb_clock_get_xclk();
case BFLB_SYSTEM_32K_CLK:
return bflb_clock_get_f32k();
default:
return 0;
}
return 0;
}
/****************************************************************************/ /**
* @brief get peripheral clock
*
* @param type: BFLB_DEVICE_TYPE_XXX
* @param idx: peripheral index
*
* @return NONE
*
*******************************************************************************/
uint32_t ATTR_CLOCK_SECTION bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
{
switch (type) {
case BFLB_DEVICE_TYPE_ADC:
return bflb_clock_get_adc();
case BFLB_DEVICE_TYPE_DAC:
return bflb_clock_get_dac();
case BFLB_DEVICE_TYPE_UART:
return bflb_clock_get_uart();
case BFLB_DEVICE_TYPE_SPI:
return bflb_clock_get_spi();
case BFLB_DEVICE_TYPE_I2C:
return bflb_clock_get_i2c();
case BFLB_DEVICE_TYPE_PWM:
return bflb_clock_get_pwm();
case BFLB_DEVICE_TYPE_TIMER:
return bflb_clock_get_timer(idx);
case BFLB_DEVICE_TYPE_WDT:
return bflb_clock_get_wdt();
case BFLB_DEVICE_TYPE_FLASH:
return bflb_clock_get_flash();
case BFLB_DEVICE_TYPE_IR:
return bflb_clock_get_ir();
case BFLB_DEVICE_TYPE_PKA:
return bflb_clock_get_pka();
case BFLB_DEVICE_TYPE_SDH:
return bflb_clock_get_sdh();
case BFLB_DEVICE_TYPE_CAMERA:
return bflb_clock_get_cam();
case BFLB_DEVICE_TYPE_DBI:
return bflb_clock_get_dbi();
case BFLB_DEVICE_TYPE_PEC:
return bflb_clock_get_pec();
case BFLB_DEVICE_TYPE_I2S:
return bflb_clock_get_i2s();
default:
return 0;
}
return 0;
}

143
drivers/lhal/src/bflb_csi.c Normal file
View File

@ -0,0 +1,143 @@
#include "bflb_csi.h"
#include "hardware/csi_reg.h"
#include "hardware/dtsrc_reg.h"
#define DTSRC_BASE 0x30012800
static void bflb_csi_phy_config(struct bflb_device_s *dev, uint32_t tx_clk_escape, uint32_t data_rate)
{
uint32_t reg_base;
uint32_t regval;
/* Unit: ns */
float TD_TERM_EN_MAX = 35 + 4 * (1e3) / data_rate;
uint32_t TD_TERM_EN = (TD_TERM_EN_MAX * data_rate / 2 / (1e3)) - 1;
float THS_SETTLE_MAX = 145 + 10 * (1e3) / data_rate;
/* THS_SETTLE = reg_time_hs_settle + reg_time_hs_term_en */
uint32_t THS_SETTLE = ((THS_SETTLE_MAX - TD_TERM_EN * 2 * (1e3) / data_rate) * data_rate / 2 / (1e3)) - 1;
uint32_t TCLK_TERM_EN_MAX = 38;
uint32_t TCLK_TERM_EN = (tx_clk_escape * TCLK_TERM_EN_MAX) / (1e3);
uint32_t TCLK_SETTLE_MAX = 300;
/* TCLK_SETTLE = reg_time_ck_settle + reg_time_ck_term_en */
uint32_t TCLK_SETTLE = ((TCLK_SETTLE_MAX - TCLK_TERM_EN * (1e3) / tx_clk_escape) * tx_clk_escape / (1e3)) - 1;
uint32_t ANA_TERM_EN = 0x8;
reg_base = dev->reg_base;
regval = TD_TERM_EN << CSI_REG_TIME_HS_TERM_EN_SHIFT & CSI_REG_TIME_HS_TERM_EN_MASK;
regval |= THS_SETTLE << CSI_REG_TIME_HS_SETTLE_SHIFT & CSI_REG_TIME_HS_SETTLE_MASK;
regval |= TCLK_TERM_EN << CSI_REG_TIME_CK_TERM_EN_SHIFT & CSI_REG_TIME_CK_TERM_EN_MASK;
regval |= TCLK_SETTLE << CSI_REG_TIME_CK_SETTLE_SHIFT & CSI_REG_TIME_CK_SETTLE_MASK;
putreg32(regval, reg_base + CSI_DPHY_CONFIG_1_OFFSET);
regval = getreg32(DTSRC_BASE + CSI_DPHY_CONFIG_2_OFFSET);
regval &= ~CSI_REG_ANA_TERM_EN_MASK;
regval |= ANA_TERM_EN << CSI_REG_ANA_TERM_EN_SHIFT & CSI_REG_ANA_TERM_EN_MASK;
putreg32(regval, reg_base + CSI_DPHY_CONFIG_2_OFFSET);
}
void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET);
regval |= DTSRC_CR_SNSR_EN;
putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET);
regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET);
regval &= ~(CSI_DL0_ENABLE | CSI_DL1_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE | CSI_DL1_FORCERXMODE | CSI_RESET_N);
putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
regval |= CSI_RESET_N;
putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
if (config->lane_number) {
regval |= CSI_CR_LANE_NUM;
} else {
regval &= ~CSI_CR_LANE_NUM;
}
regval |= CSI_CR_UNPACK_EN | CSI_CR_SYNC_SP_EN;
putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
bflb_csi_phy_config(dev, config->tx_clk_escape / 1000000, config->data_rate / 1000000);
regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET);
regval |= CSI_DL0_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE;
if (config->lane_number) {
regval |= CSI_DL1_ENABLE | CSI_DL1_FORCERXMODE;
}
putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET);
regval |= DTSRC_CR_ENABLE;
putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET);
}
void bflb_csi_start(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
regval |= CSI_CR_CSI_EN;
putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
}
void bflb_csi_stop(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
regval &= ~CSI_CR_CSI_EN;
putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
}
void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock)
{
uint32_t threshold;
threshold = (dsp_clock - pixel_clock) / 1000 * resolution_x / (dsp_clock / 1000) + 10;
putreg32(threshold, DTSRC_BASE + DTSRC_SNSR2DVP_WAIT_POS_OFFSET);
}
void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + CSI_INT_MASK_OFFSET);
if (mask) {
regval |= int_type;
} else {
regval &= ~int_type;
}
putreg32(regval, reg_base + CSI_INT_MASK_OFFSET);
}
void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type)
{
putreg32(int_type, dev->reg_base + CSI_INT_CLEAR_OFFSET);
}
uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev)
{
return(getreg32(dev->reg_base + CSI_INT_STATUS_OFFSET));
}
int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
{
int ret = 0;
switch (cmd) {
default:
ret = -EPERM;
break;
}
return ret;
}

2
drivers/lhal/src/bflb_dma.c
View File

@ -112,7 +112,7 @@ void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_chan
regval |= (config->direction << DMA_FLOWCNTRL_SHIFT);
putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
/* disable dma error and tc interrupt */
/* enable dma error and tc interrupt */
regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
regval |= (DMA_ITC | DMA_IE);
putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);

789
drivers/lhal/src/bflb_flash.c Normal file
View File

@ -0,0 +1,789 @@
#if defined(BL616)
#include "bl616_memorymap.h"
#include "bl616_glb.h"
#include "bl616_ef_cfg.h"
#elif defined(BL606P)
#include "bl606p_memorymap.h"
#include "bl606p_glb.h"
#elif defined(BL808)
#include "bl808_memorymap.h"
#include "bl808_glb.h"
#elif defined(BL602)
#include "bl602_glb.h"
#include "bl602_sflash_ext.h"
#include "bl602_xip_sflash_ext.h"
#include "bl602_sf_cfg_ext.h"
#elif defined(BL702)
#include "bl702_glb.h"
#include "bl702_xip_sflash_ext.h"
#include "bl702_sf_cfg_ext.h"
#endif
#include "bflb_xip_sflash.h"
#include "bflb_sf_cfg.h"
#include "bflb_flash.h"
#include "hardware/sf_ctrl_reg.h"
#if defined(BL616)
static uint32_t flash1_size = 4 * 1024 * 1024;
static uint32_t flash2_size = 2 * 1024 * 1024;
static uint32_t g_jedec_id2 = 0;
#endif
static uint32_t g_jedec_id = 0;
static spi_flash_cfg_type g_flash_cfg = {
.reset_c_read_cmd = 0xff,
.reset_c_read_cmd_size = 3,
.mid = 0xc8,
.de_burst_wrap_cmd = 0x77,
.de_burst_wrap_cmd_dmy_clk = 0x3,
.de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
.de_burst_wrap_data = 0xF0,
/*reg*/
.write_enable_cmd = 0x06,
.wr_enable_index = 0x00,
.wr_enable_bit = 0x01,
.wr_enable_read_reg_len = 0x01,
.qe_index = 1,
.qe_bit = 0x01,
.qe_write_reg_len = 0x01,
.qe_read_reg_len = 0x1,
.busy_index = 0,
.busy_bit = 0x00,
.busy_read_reg_len = 0x1,
.release_powerdown = 0xab,
.read_reg_cmd[0] = 0x05,
.read_reg_cmd[1] = 0x35,
.write_reg_cmd[0] = 0x01,
.write_reg_cmd[1] = 0x31,
.fast_read_qio_cmd = 0xeb,
.fr_qio_dmy_clk = 16 / 8,
.c_read_support = 0,
.c_read_mode = 0x20,
.burst_wrap_cmd = 0x77,
.burst_wrap_cmd_dmy_clk = 0x3,
.burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
.burst_wrap_data = 0x40,
/*erase*/
.chip_erase_cmd = 0xc7,
.sector_erase_cmd = 0x20,
.blk32_erase_cmd = 0x52,
.blk64_erase_cmd = 0xd8,
/*write*/
.page_program_cmd = 0x02,
.qpage_program_cmd = 0x32,
.qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
.io_mode = 0x11,
.clk_delay = 0,
.clk_invert = 0x03,
.reset_en_cmd = 0x66,
.reset_cmd = 0x99,
.c_rexit = 0xff,
.wr_enable_write_reg_len = 0x00,
/*id*/
.jedec_id_cmd = 0x9f,
.jedec_id_cmd_dmy_clk = 0,
#if defined(BL702L) || defined(BL702) || defined(BL602)
.qpi_jedec_id_cmd = 0x9f,
.qpi_jedec_id_cmd_dmy_clk = 0x00,
#else
.enter_32bits_addr_cmd = 0xb7,
.exit_32bits_addr_cmd = 0xe9,
#endif
.sector_size = 4,
.page_size = 256,
/*read*/
.fast_read_cmd = 0x0b,
.fr_dmy_clk = 8 / 8,
.qpi_fast_read_cmd = 0x0b,
.qpi_fr_dmy_clk = 8 / 8,
.fast_read_do_cmd = 0x3b,
.fr_do_dmy_clk = 8 / 8,
.fast_read_dio_cmd = 0xbb,
.fr_dio_dmy_clk = 0,
.fast_read_qo_cmd = 0x6b,
.fr_qo_dmy_clk = 8 / 8,
.qpi_fast_read_qio_cmd = 0xeb,
.qpi_fr_qio_dmy_clk = 16 / 8,
.qpi_page_program_cmd = 0x02,
.write_vreg_enable_cmd = 0x50,
/* qpi mode */
.enter_qpi = 0x38,
.exit_qpi = 0xff,
/*AC*/
.time_e_sector = 300,
.time_e_32k = 1200,
.time_e_64k = 1200,
.time_page_pgm = 5,
.time_ce = 33 * 1000,
.pd_delay = 20,
.qe_data = 0,
};
#if defined(BL616)
static spi_flash_cfg_type g_flash2_cfg = {
.reset_c_read_cmd = 0xff,
.reset_c_read_cmd_size = 3,
.mid = 0xc8,
.de_burst_wrap_cmd = 0x77,
.de_burst_wrap_cmd_dmy_clk = 0x3,
.de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
.de_burst_wrap_data = 0xF0,
/*reg*/
.write_enable_cmd = 0x06,
.wr_enable_index = 0x00,
.wr_enable_bit = 0x01,
.wr_enable_read_reg_len = 0x01,
.qe_index = 1,
.qe_bit = 0x01,
.qe_write_reg_len = 0x01,
.qe_read_reg_len = 0x1,
.busy_index = 0,
.busy_bit = 0x00,
.busy_read_reg_len = 0x1,
.release_powerdown = 0xab,
.read_reg_cmd[0] = 0x05,
.read_reg_cmd[1] = 0x35,
.write_reg_cmd[0] = 0x01,
.write_reg_cmd[1] = 0x31,
.fast_read_qio_cmd = 0xeb,
.fr_qio_dmy_clk = 16 / 8,
.c_read_support = 0,
.c_read_mode = 0x20,
.burst_wrap_cmd = 0x77,
.burst_wrap_cmd_dmy_clk = 0x3,
.burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
.burst_wrap_data = 0x40,
/*erase*/
.chip_erase_cmd = 0xc7,
.sector_erase_cmd = 0x20,
.blk32_erase_cmd = 0x52,
.blk64_erase_cmd = 0xd8,
/*write*/
.page_program_cmd = 0x02,
.qpage_program_cmd = 0x32,
.qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
.io_mode = 0x10,
.clk_delay = 0,
.clk_invert = 0x03,
.reset_en_cmd = 0x66,
.reset_cmd = 0x99,
.c_rexit = 0xff,
.wr_enable_write_reg_len = 0x00,
/*id*/
.jedec_id_cmd = 0x9f,
.jedec_id_cmd_dmy_clk = 0,
.enter_32bits_addr_cmd = 0xb7,
.exit_32bits_addr_cmd = 0xe9,
.sector_size = 4,
.page_size = 256,
/*read*/
.fast_read_cmd = 0x0b,
.fr_dmy_clk = 8 / 8,
.qpi_fast_read_cmd = 0x0b,
.qpi_fr_dmy_clk = 8 / 8,
.fast_read_do_cmd = 0x3b,
.fr_do_dmy_clk = 8 / 8,
.fast_read_dio_cmd = 0xbb,
.fr_dio_dmy_clk = 0,
.fast_read_qo_cmd = 0x6b,
.fr_qo_dmy_clk = 8 / 8,
.qpi_fast_read_qio_cmd = 0xeb,
.qpi_fr_qio_dmy_clk = 16 / 8,
.qpi_page_program_cmd = 0x02,
.write_vreg_enable_cmd = 0x50,
/* qpi mode */
.enter_qpi = 0x38,
.exit_qpi = 0xff,
/*AC*/
.time_e_sector = 300,
.time_e_32k = 1200,
.time_e_64k = 1200,
.time_page_pgm = 5,
.time_ce = 33 * 1000,
.pd_delay = 20,
.qe_data = 0,
};
static bflb_efuse_device_info_type deviceInfo;
#endif
#if defined(BL616)
uint32_t bflb_flash2_get_jedec_id(void)
{
uint32_t jid = 0;
jid = ((g_jedec_id2 & 0xff) << 16) + (g_jedec_id2 & 0xff00) + ((g_jedec_id2 & 0xff0000) >> 16);
return jid;
}
#endif
#if defined(BL616) || defined(BL606P) || defined(BL808)
static int flash_get_clock_delay(spi_flash_cfg_type *cfg)
{
uint32_t reg_base = 0;
uint32_t regval = 0;
reg_base = BFLB_SF_CTRL_BASE;
regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
/* bit0-3 for clk delay */
if (regval & SF_CTRL_SF_IF_READ_DLY_EN) {
cfg->clk_delay = ((regval & SF_CTRL_SF_IF_READ_DLY_N_MASK) >> SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1;
} else {
cfg->clk_delay = 0;
}
cfg->clk_invert = 0;
/* bit0 for clk invert */
cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_OUT_INV_SEL) ? 1 : 0) << 0);
/* bit1 for rx clk invert */
cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_SF_RX_INV_SEL) ? 1 : 0) << 1);
regval = getreg32(reg_base + SF_CTRL_SF_IF_IO_DLY_1_OFFSET);
/* bit4-6 for do delay */
cfg->clk_delay |= (((regval & SF_CTRL_SF_IO_0_DO_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DO_DLY_SEL_SHIFT) << 4);
/* bit2-4 for di delay */
cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_DI_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DI_DLY_SEL_SHIFT) << 2);
/* bit5-7 for oe delay */
cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_OE_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_OE_DLY_SEL_SHIFT) << 5);
return 0;
}
static void ATTR_TCM_SECTION flash_set_cmds(spi_flash_cfg_type *p_flash_cfg)
{
struct sf_ctrl_cmds_cfg cmds_cfg;
cmds_cfg.ack_latency = 1;
cmds_cfg.cmds_core_en = 1;
cmds_cfg.cmds_en = 1;
cmds_cfg.cmds_wrap_mode = 1;
cmds_cfg.cmds_wrap_len = 9;
if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
cmds_cfg.cmds_wrap_mode = 2;
cmds_cfg.cmds_wrap_len = 2;
}
bflb_sf_ctrl_cmds_set(&cmds_cfg, 0);
}
#endif
static void ATTR_TCM_SECTION flash_set_qspi_enable(spi_flash_cfg_type *p_flash_cfg)
{
if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
bflb_sflash_qspi_enable(p_flash_cfg);
}
}
static void ATTR_TCM_SECTION flash_set_l1c_wrap(spi_flash_cfg_type *p_flash_cfg)
{
if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
L1C_Set_Wrap(ENABLE);
bflb_sflash_set_burst_wrap(p_flash_cfg);
} else {
L1C_Set_Wrap(DISABLE);
bflb_sflash_disable_burst_wrap(p_flash_cfg);
}
}
/**
* @brief flash_config_init
*
* @return int
*/
static int ATTR_TCM_SECTION flash_config_init(spi_flash_cfg_type *p_flash_cfg, uint8_t *jedec_id)
{
int ret = -1;
uint8_t is_aes_enable = 0;
uint32_t jid = 0;
uint32_t offset = 0;
uintptr_t flag;
flag = bflb_irq_save();
bflb_xip_sflash_opt_enter(&is_aes_enable);
bflb_xip_sflash_state_save(p_flash_cfg, &offset, 0, 0);
bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jid);
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
jid &= 0xFFFFFF;
g_jedec_id = jid;
ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jid, p_flash_cfg, 0, 0);
if (ret == 0) {
p_flash_cfg->mid = (jid & 0xff);
}
// p_flash_cfg->io_mode = 0x11;
// p_flash_cfg->c_read_support = 0x00;
/* Set flash controler from p_flash_cfg */
#if defined(BL616) || defined(BL606P) || defined(BL808)
flash_set_cmds(p_flash_cfg);
#endif
flash_set_qspi_enable(p_flash_cfg);
flash_set_l1c_wrap(p_flash_cfg);
#if defined(BL602)
bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, 0, 0);
#else
bflb_xip_sflash_state_restore(p_flash_cfg, offset, 0, 0);
#endif
bflb_xip_sflash_opt_exit(is_aes_enable);
bflb_irq_restore(flag);
return ret;
}
#if defined(BL616)
/**
* @brief flash2 init
*
* @return int
*/
static int ATTR_TCM_SECTION flash2_init(void)
{
int stat = -1;
uint32_t ret = 0;
uint32_t jid = 0;
struct sf_ctrl_bank2_cfg sf_bank2_cfg;
struct sf_ctrl_cmds_cfg cmds_cfg;
sf_bank2_cfg.sbus2_select = 1;
sf_bank2_cfg.bank2_rx_clk_invert_src = 0;
sf_bank2_cfg.bank2_rx_clk_invert_sel = 0;
sf_bank2_cfg.bank2_delay_src = 0;
sf_bank2_cfg.bank2_clk_delay = 1;
sf_bank2_cfg.do_delay = 0;
sf_bank2_cfg.di_delay = 0;
sf_bank2_cfg.oe_delay = 0;
sf_bank2_cfg.remap = SF_CTRL_REMAP_4MB;
sf_bank2_cfg.remap_lock = 1;
cmds_cfg.ack_latency = 1;
cmds_cfg.cmds_core_en = 1;
cmds_cfg.cmds_en = 1;
cmds_cfg.cmds_wrap_mode = 1;
cmds_cfg.cmds_wrap_len = SF_CTRL_WRAP_LEN_4096;
if (deviceInfo.memoryInfo == 0) {
/* memoryInfo==0, external flash */
flash1_size = 64 * 1024 * 1024;
flash2_size = 0;
} else if (deviceInfo.memoryInfo == 1) {
flash1_size = 2 * 1024 * 1024;
flash2_size = 0;
} else if (deviceInfo.memoryInfo == 2) {
flash1_size = 4 * 1024 * 1024;
flash2_size = 0;
} else if (deviceInfo.memoryInfo == 3) {
/* memoryInfo==3, embedded 4MB+2MB flash */
flash1_size = 4 * 1024 * 1024;
flash2_size = 2 * 1024 * 1024;
} else {
flash1_size = 8 * 1024 * 1024;
flash2_size = 0;
}
if (flash2_size > 0) {
bflb_sf_cfg_sbus2_flash_init(SF_IO_EMB_SWAP_IO3IO0_AND_SF2, &sf_bank2_cfg);
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
ret = bflb_sf_cfg_flash_identify_ext(0, SF_IO_EMB_SWAP_IO3IO0_AND_SF2, 0, &g_flash2_cfg, 0, SF_CTRL_FLASH_BANK1);
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) {
return -1;
}
g_flash2_cfg.io_mode = 0x11;
g_flash2_cfg.c_read_support = 0;
g_flash2_cfg.c_read_mode = 0xff;
bflb_sflash_get_jedecid(&g_flash2_cfg, (uint8_t *)&jid);
jid &= 0xFFFFFF;
g_jedec_id2 = jid;
bflb_sf_ctrl_cmds_set(&cmds_cfg, SF_CTRL_FLASH_BANK1);
stat = bflb_sflash_xip_read_enable(&g_flash2_cfg, (g_flash2_cfg.io_mode & 0xf), 0, SF_CTRL_FLASH_BANK1);
if (0 != stat) {
return -1;
}
bflb_sf_ctrl_sbus2_revoke_replace();
}
return 0;
}
#endif
/**
* @brief multi flash adapter
*
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_init(void)
{
int ret = -1;
uint32_t jedec_id = 0;
#if defined(BL602) || defined(BL702)
uint8_t clk_delay = 1;
uint8_t clk_invert = 1;
uintptr_t flag;
#endif
#if defined(BL616)
bflb_ef_ctrl_get_device_info(&deviceInfo);
#endif
#if defined(BL602) || defined(BL702)
flag = bflb_irq_save();
#if defined(BL602)
bflb_sflash_cache_flush();
#else
L1C_Cache_Flush();
#endif
bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
#if defined(BL602)
bflb_sflash_cache_flush();
#else
L1C_Cache_Flush();
#endif
bflb_irq_restore(flag);
if (g_flash_cfg.mid != 0xff) {
return 0;
}
clk_delay = g_flash_cfg.clk_delay;
clk_invert = g_flash_cfg.clk_invert;
g_flash_cfg.io_mode &= 0x0f;
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
g_flash_cfg.clk_delay = clk_delay;
g_flash_cfg.clk_invert = clk_invert;
#else
jedec_id = GLB_Get_Flash_Id_Value();
if (jedec_id != 0) {
ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
if (ret == 0) {
g_jedec_id = jedec_id;
g_flash_cfg.io_mode &= 0x0f;
flash_get_clock_delay(&g_flash_cfg);
#if defined(BL616)
flash2_init();
#endif
return 0;
}
}
g_flash_cfg.io_mode &= 0x0f;
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
g_flash_cfg.io_mode &= 0x0f;
flash_get_clock_delay(&g_flash_cfg);
GLB_Set_Flash_Id_Value(g_jedec_id);
#endif
#if defined(BL616)
flash2_init();
#endif
return ret;
}
uint32_t bflb_flash_get_jedec_id(void)
{
uint32_t jid = 0;
jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
return jid;
}
void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
{
*cfg_addr = (uint8_t *)&g_flash_cfg;
*len = sizeof(spi_flash_cfg_type);
}
void ATTR_TCM_SECTION bflb_flash_set_iomode(uint8_t iomode)
{
uintptr_t flag = 0;
uint8_t is_aes_enable = 0;
uint32_t offset = 0;
flag = bflb_irq_save();
bflb_xip_sflash_opt_enter(&is_aes_enable);
bflb_xip_sflash_state_save(&g_flash_cfg, &offset, 0, 0);
g_flash_cfg.io_mode &= ~0x1f;
if (iomode&4) {
g_flash_cfg.io_mode |= iomode;
} else {
g_flash_cfg.io_mode |= 0x10;
g_flash_cfg.io_mode |= iomode;
}
#if defined(BL616) || defined(BL606P) || defined(BL808)
flash_set_cmds(&g_flash_cfg);
#endif
flash_set_qspi_enable(&g_flash_cfg);
flash_set_l1c_wrap(&g_flash_cfg);
#if defined(BL602)
bflb_xip_sflash_state_restore_ext(&g_flash_cfg, offset, 0, 0);
#else
bflb_xip_sflash_state_restore(&g_flash_cfg, offset, 0, 0);
#endif
bflb_xip_sflash_opt_exit(is_aes_enable);
bflb_irq_restore(flag);
}
ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void)
{
return bflb_sf_ctrl_get_flash_image_offset(0, 0);
}
/**
* @brief erase flash via sbus
*
* @param flash absolute startaddr
* @param flash absolute endaddr
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len)
{
int stat = -1;
uintptr_t flag;
#if defined(BL616)
if ((startaddr + len) > (flash1_size + flash2_size)) {
return -ENOMEM;
} else if ((startaddr + len) <= flash1_size) {
flag = bflb_irq_save();
stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
bflb_irq_restore(flag);
} else if (startaddr >= flash1_size) {
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
stat = bflb_sflash_erase(&g_flash2_cfg, startaddr, startaddr + len - 1);
bflb_sf_ctrl_sbus2_revoke_replace();
} else {
flag = bflb_irq_save();
stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, flash1_size - startaddr, 0, 0);
bflb_irq_restore(flag);
if (stat != 0) {
return stat;
}
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
stat = bflb_sflash_erase(&g_flash2_cfg, flash1_size, startaddr + len - flash1_size - 1);
bflb_sf_ctrl_sbus2_revoke_replace();
}
#else
if (startaddr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
return -ENOMEM;
}
flag = bflb_irq_save();
#if defined(BL602)
stat = bflb_xip_sflash_erase_need_lock_ext(&g_flash_cfg, startaddr, startaddr+len-1, 0, 0);
#else
stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
#endif
bflb_irq_restore(flag);
#endif
return stat;
}
/**
* @brief write flash data via sbus
*
* @param flash absolute addr
* @param data
* @param len
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len)
{
int stat = -1;
uintptr_t flag;
#if defined(BL616)
if ((addr + len) > (flash1_size + flash2_size)) {
return -ENOMEM;
} else if ((addr + len) <= flash1_size) {
flag = bflb_irq_save();
stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
bflb_irq_restore(flag);
} else if (addr >= flash1_size) {
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, addr, data, len);
bflb_sf_ctrl_sbus2_revoke_replace();
} else {
flag = bflb_irq_save();
stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
bflb_irq_restore(flag);
if (stat != 0) {
return stat;
}
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
bflb_sf_ctrl_sbus2_revoke_replace();
}
#else
if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
return -ENOMEM;
}
flag = bflb_irq_save();
#if defined(BL602)
stat = bflb_xip_sflash_write_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
#else
stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
#endif
bflb_irq_restore(flag);
#endif
return stat;
}
/**
* @brief read flash data via sbus
*
* @param flash absolute addr
* @param data
* @param len
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
{
int stat = -1;
uintptr_t flag;
#if defined(BL616)
if ((addr + len) > (flash1_size + flash2_size)) {
return -ENOMEM;
} else if ((addr + len) <= flash1_size) {
flag = bflb_irq_save();
stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
bflb_irq_restore(flag);
} else if (addr >= flash1_size) {
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, addr, data, len);
bflb_sf_ctrl_sbus2_revoke_replace();
} else {
flag = bflb_irq_save();
stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
bflb_irq_restore(flag);
if (stat != 0) {
return stat;
}
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
bflb_sf_ctrl_sbus2_revoke_replace();
}
#else
if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
return -ENOMEM;
}
flag = bflb_irq_save();
#if defined(BL602)
stat = bflb_xip_sflash_read_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
#else
stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
#endif
bflb_irq_restore(flag);
#endif
return stat;
}
int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
{
uint8_t is_aes_enable = 0;
uint32_t tmp[1];
int stat;
bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
bflb_xip_sflash_opt_enter(&is_aes_enable);
/* To make it simple, exit cont read anyway */
bflb_sflash_reset_continue_read(&g_flash_cfg);
if (g_flash_cfg.c_read_support == 0) {
cont_read = 0;
}
if (cont_read == 1) {
stat = bflb_sflash_read(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
if (0 != stat) {
bflb_xip_sflash_opt_exit(is_aes_enable);
return -1;
}
}
#if defined(BL602) || defined(BL702)
#if defined(BL602)
bflb_sflash_cache_enable_set(0xf);
#else
L1C_Cache_Enable_Set(0xf);
#endif
if (cache_enable) {
bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
}
#if defined(BL602)
bflb_sflash_cache_enable_set(cache_way_disable);
#else
L1C_Cache_Enable_Set(cache_way_disable);
#endif
#else
bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
#endif
bflb_xip_sflash_opt_exit(is_aes_enable);
return 0;
}
void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
{
uint8_t hw_key_enable = 0;
if (config->key == NULL) {
hw_key_enable = 1;
}
bflb_sf_ctrl_aes_set_key_be(config->region, (uint8_t *)config->key, config->keybits);
bflb_sf_ctrl_aes_set_iv_be(config->region, (uint8_t *)config->iv, config->start_addr);
bflb_sf_ctrl_aes_set_region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable);
}
void bflb_flash_aes_enable(void)
{
bflb_sf_ctrl_aes_enable();
}
void bflb_flash_aes_disable(void)
{
bflb_sf_ctrl_aes_disable();
}

32
drivers/lhal/src/bflb_gpio.c
View File

@ -151,6 +151,38 @@ bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin)
#endif
}
void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val)
{
#if defined(BL702) || defined(BL602) || defined(BL702L)
putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
putreg32(val, dev->reg_base + GLB_GPIO_CFG136_OFFSET);
#endif
}
void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val)
{
#if defined(BL702) || defined(BL602) || defined(BL702L)
putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL33_OFFSET);
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
putreg32(val, dev->reg_base + GLB_GPIO_CFG137_OFFSET);
#endif
}
uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev)
{
#if defined(BL702) || defined(BL602) || defined(BL702L)
return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET));
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
return (getreg32(dev->reg_base + GLB_GPIO_CFG128_OFFSET));
#endif
}
uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev)
{
#if defined(BL702) || defined(BL602) || defined(BL702L)
return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL31_OFFSET));
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
return (getreg32(dev->reg_base + GLB_GPIO_CFG129_OFFSET));
#endif
}
void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode)
{
uint32_t reg_base;

341
drivers/lhal/src/bflb_i2s.c Normal file
View File

@ -0,0 +1,341 @@
#include "bflb_i2s.h"
#include "bflb_clock.h"
#include "hardware/i2s_reg.h"
void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config)
{
uint32_t reg_base;
uint32_t regval;
uint32_t div;
reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
/* disable I2S */
regval &= ~I2S_CR_I2S_M_EN;
regval &= ~I2S_CR_I2S_S_EN;
regval &= ~I2S_CR_I2S_TXD_EN;
regval &= ~I2S_CR_I2S_TXD_EN;
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
if (config->channel_mode == I2S_CHANNEL_MODE_NUM_1) {
/* Mono mode */
regval |= I2S_CR_MONO_MODE;
regval &= ~I2S_CR_FS_CH_CNT_MASK;
} else {
regval &= ~I2S_CR_MONO_MODE;
regval &= ~I2S_CR_FS_CH_CNT_MASK;
regval |= (config->channel_mode - 1) << I2S_CR_FS_CH_CNT_SHIFT;
}
/* disable mute */
regval &= ~I2S_CR_MUTE_MODE;
if (config->format_mode == I2S_MODE_DSP_SHORT_FRAME_SYNC) {
/* dsp modeA/B short frame sync, there is only one bclk cycle */
regval |= I2S_CR_FS_1T_MODE;
} else {
regval &= ~I2S_CR_FS_1T_MODE;
}
/* frame/data width */
regval &= ~I2S_CR_FRAME_SIZE_MASK;
regval &= ~I2S_CR_DATA_SIZE_MASK;
regval |= config->frame_width << I2S_CR_FRAME_SIZE_SHIFT;
regval |= config->data_width << I2S_CR_DATA_SIZE_SHIFT;
if (config->format_mode == I2S_MODE_LEFT_JUSTIFIED) {
/* left justified*/
regval &= ~I2S_CR_I2S_MODE_MASK;
} else if (config->format_mode == I2S_MODE_RIGHT_JUSTIFIED) {
/* right justified*/
regval &= ~I2S_CR_I2S_MODE_MASK;
regval |= 1 << I2S_CR_I2S_MODE_SHIFT;
} else {
/* dsp mode */
regval &= ~I2S_CR_I2S_MODE_MASK;
regval |= 2 << I2S_CR_I2S_MODE_SHIFT;
}
/* fs_offset_cycle */
if (config->fs_offset_cycle) {
regval |= I2S_CR_OFS_EN;
regval &= ~I2S_CR_OFS_CNT_MASK;
regval |= ((config->fs_offset_cycle - 1) << I2S_CR_OFS_CNT_SHIFT) & I2S_CR_OFS_CNT_MASK;
} else {
regval &= ~I2S_CR_OFS_EN;
}
/* rx mono mode L-channel */
regval &= ~I2S_CR_MONO_RX_CH;
/* MSB */
regval &= ~I2S_CR_ENDIAN;
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
/* integer frequency segmentation by rounding */
div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2S, dev->idx) / 2 * 10 / config->bclk_freq_hz + 5) / 10;
div = (div) ? (div - 1) : 0;
div = (div > 0xfff) ? 0xfff : div;
/* bclk timing config */
regval = getreg32(reg_base + I2S_BCLK_CONFIG_OFFSET);
regval &= ~I2S_CR_BCLK_DIV_L_MASK;
regval &= ~I2S_CR_BCLK_DIV_H_MASK;
regval |= div << I2S_CR_BCLK_DIV_L_SHIFT;
regval |= div << I2S_CR_BCLK_DIV_H_SHIFT;
putreg32(regval, reg_base + I2S_BCLK_CONFIG_OFFSET);
/* fifo threshold config */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_1_OFFSET);
regval &= ~I2S_TX_FIFO_TH_MASK;
regval &= ~I2S_RX_FIFO_TH_MASK;
regval |= (config->tx_fifo_threshold << I2S_TX_FIFO_TH_SHIFT) & I2S_TX_FIFO_TH_MASK;
regval |= (config->tx_fifo_threshold << I2S_RX_FIFO_TH_SHIFT) & I2S_RX_FIFO_TH_MASK;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_1_OFFSET);
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
/* 32bit to 24bit */
regval &= ~I2S_CR_FIFO_24B_LJ;
/* Exchange L/R channel data */
regval &= ~I2S_CR_FIFO_LR_EXCHG;
/* Each FIFO entry contains both L/R channel data */
regval &= ~I2S_CR_FIFO_LR_MERGE;
/* disable dma */
regval &= ~I2S_DMA_TX_EN;
regval &= ~I2S_DMA_RX_EN;
/* clean fifo */
regval |= I2S_TX_FIFO_CLR;
regval |= I2S_RX_FIFO_CLR;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
/* disable deglitch */
regval &= ~I2S_CR_DEG_EN;
/* disable inverse signal */
regval &= ~I2S_CR_I2S_BCLK_INV;
regval &= ~I2S_CR_I2S_FS_INV;
regval &= ~I2S_CR_I2S_RXD_INV;
regval &= ~I2S_CR_I2S_TXD_INV;
putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
/* enable I2S, but disable tx and rx */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
if (config->role == I2S_ROLE_MASTER) {
regval |= I2S_CR_I2S_M_EN;
} else {
regval |= I2S_CR_I2S_S_EN;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
}
void bflb_i2s_deinit(struct bflb_device_s *dev)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
/* disable I2S */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
regval &= ~I2S_CR_I2S_S_EN;
regval &= ~I2S_CR_I2S_M_EN;
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
}
void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (enable) {
regval |= I2S_DMA_TX_EN;
} else {
regval &= ~I2S_DMA_TX_EN;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
}
void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable)
{
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (enable) {
regval |= I2S_DMA_RX_EN;
} else {
regval &= ~I2S_DMA_RX_EN;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
}
void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
if (mask) {
regval |= I2S_CR_I2S_TXF_MASK;
} else {
regval &= ~I2S_CR_I2S_TXF_MASK;
}
putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
}
void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
if (mask) {
regval |= I2S_CR_I2S_RXF_MASK;
} else {
regval &= ~I2S_CR_I2S_RXF_MASK;
}
putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
}
void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask)
{
uint32_t regval;
uint32_t reg_base = dev->reg_base;
regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
if (mask) {
regval |= I2S_CR_I2S_FER_MASK;
} else {
regval &= ~I2S_CR_I2S_FER_MASK;
}
putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
}
uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t int_status;
uint32_t int_mask;
reg_base = dev->reg_base;
int_status = getreg32(reg_base + I2S_INT_STS_OFFSET) & 0x1f;
int_mask = (getreg32(reg_base + I2S_INT_STS_OFFSET) >> 8) & 0x1f;
return (int_status & ~int_mask);
}
int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
{
int ret = 0;
uint32_t reg_base;
uint32_t regval;
reg_base = dev->reg_base;
switch (cmd) {
case I2S_CMD_CLEAR_TX_FIFO:
/* clear tx fifo */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
regval |= I2S_TX_FIFO_CLR;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_CLEAR_RX_FIFO:
/* clear rx fifo */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
regval |= I2S_RX_FIFO_CLR;
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_RX_DEGLITCH:
/* set rx deglitch, arg: deglitch cycle count (unit: cycle of I2S kernel clock) */
regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
if (arg) {
regval |= I2S_CR_DEG_EN;
regval &= ~I2S_CR_DEG_CNT_MASK;
regval |= (arg << I2S_CR_DEG_CNT_SHIFT) & I2S_CR_DEG_CNT_MASK;
} else {
regval &= ~I2S_CR_DEG_EN;
}
putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
break;
case I2S_CMD_DATA_ENABLE:
/* data enable, arg: use @ref I2S_CMD_DATA_ENABLE_TYPE */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
/* enable tx data signal */
if (arg & I2S_CMD_DATA_ENABLE_TX) {
regval |= I2S_CR_I2S_TXD_EN;
} else {
regval &= ~I2S_CR_I2S_TXD_EN;
}
/* enable rx data signal */
if (arg & I2S_CMD_DATA_ENABLE_RX) {
regval |= I2S_CR_I2S_RXD_EN;
} else {
regval &= ~I2S_CR_I2S_RXD_EN;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
break;
case I2S_CMD_CHANNEL_LR_MERGE:
/* Each FIFO entry contains both L/R channel data ,
can only be enabled if data size is 8 or 16 bits,
arg use true or false */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (arg) {
regval |= I2S_CR_FIFO_LR_MERGE;
} else {
regval &= ~I2S_CR_FIFO_LR_MERGE;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_CHANNEL_LR_EXCHG:
/* The position of L/R channel data within each entry is exchanged,
can only be enabled if data size is 8 or 16 bits and I2S_CMD_CHANNEL_LR_MERGE is enabled,
arg use true or false */
regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
if (arg) {
regval |= I2S_CR_FIFO_LR_EXCHG;
} else {
regval &= ~I2S_CR_FIFO_LR_EXCHG;
}
putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
break;
case I2S_CMD_MUTE:
/* Enable mute, arg use true or false */
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
if (arg) {
regval |= I2S_CR_MUTE_MODE;
} else {
regval &= ~I2S_CR_MUTE_MODE;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
break;
case I2S_CMD_BIT_REVERSE:
/* Data endian (bit reverse), arg use true or false, true: MSB goes out first, false: LSB goes out first*/
regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
if (arg) {
regval |= I2S_CR_MUTE_MODE;
} else {
regval &= ~I2S_CR_MUTE_MODE;
}
putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
break;
default:
ret = -EPERM;
break;
}
return ret;
}

70
drivers/lhal/src/bflb_l1c.c
View File

@ -115,4 +115,74 @@ ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size
#endif
}
#if defined(BL702) || defined(BL702L)
/****************************************************************************/ /**
* @brief L1C cache write set
*
* @param wt_en: L1C write through enable
* @param wb_en: L1C write back enable
* @param wa_en: L1C write allocate enable
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
{
uint32_t regval = 0;
regval = getreg32(0x40009000 + 0x0);
if (wt_en) {
regval |= (1<<4);
} else {
regval &= ~(1<<4);
}
if (wb_en) {
regval |= (1<<5);
} else {
regval &= ~(1<<5);
}
if (wa_en) {
regval |= (1<<6);
} else {
regval &= ~(1<<6);
}
putreg32(regval, 0x40009000+0x0);
}
#endif
/****************************************************************************/ /**
* @brief Get hit count
*
* @param hit_count_low: hit count low 32 bits pointer
* @param hit_count_high: hit count high 32 bits pointer
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high)
{
*hit_count_low = getreg32(0x40009000 + 0x4);
*hit_count_high = getreg32(0x40009000 + 0x8);
}
/****************************************************************************/ /**
* @brief Get miss count
*
* @param None
*
* @return Miss count
*
*******************************************************************************/
__WEAK
uint32_t ATTR_TCM_SECTION bflb_l1c_miss_count_get(void)
{
return getreg32(0x40009000 + 0xC);
}
#endif

774
drivers/lhal/src/bflb_spi_psram.c Normal file
View File

@ -0,0 +1,774 @@
/**
******************************************************************************
* @file bflb_spi_psram.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bflb_spi_psram.h"
#include "bflb_l1c.h"
/** @addtogroup BFLB_Peripheral_Driver
* @{
*/
/** @addtogroup PSRAM
* @{
*/
/** @defgroup PSRAM_Private_Macros
* @{
*/
/*@} end of group PSRAM_Private_Macros */
/** @defgroup PSRAM_Private_Types
* @{
*/
/*@} end of group PSRAM_Private_Types */
/** @defgroup PSRAM_Private_Variables
* @{
*/
/*@} end of group PSRAM_Private_Variables */
/** @defgroup PSRAM_Global_Variables
* @{
*/
/*@} end of group PSRAM_Global_Variables */
/** @defgroup PSRAM_Private_Fun_Declaration
* @{
*/
/*@} end of group PSRAM_Private_Fun_Declaration */
/** @defgroup PSRAM_Private_Functions
* @{
*/
/*@} end of group PSRAM_Private_Functions */
/** @defgroup PSRAM_Public_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Init serial psram control interface
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param cmds_cfg: Serial Serial Flash controller configuration pointer
* @param sf_ctrl_psram_cfg: Serial psram controller configuration pointer
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg,
struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg)
{
bflb_sf_ctrl_psram_init(sf_ctrl_psram_cfg);
bflb_sf_ctrl_cmds_set(cmds_cfg, 0);
#if defined(BL702L)
bflb_sf_ctrl_burst_toggle_set(psram_cfg->burst_toggle_en, psram_cfg->ctrl_mode);
#endif
bflb_psram_setdrivestrength(psram_cfg);
bflb_psram_setburstwrap(psram_cfg);
}
/****************************************************************************/ /**
* @brief Read psram register
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param reg_value: Register value pointer to store data
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
{
uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
uint32_t timeout = 0;
struct sf_ctrl_cmd_cfg_type psram_cmd;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) {
psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
}
psram_cmd.cmd_buf[0] = (psram_cfg->read_reg_cmd) << 24;
psram_cmd.rw_flag = SF_CTRL_READ;
psram_cmd.addr_size = 3;
psram_cmd.dummy_clks = psram_cfg->read_reg_dmy_clk;
psram_cmd.nb_data = 1;
bflb_sf_ctrl_sendcmd(&psram_cmd);
timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return;
}
}
arch_memcpy(reg_value, psram_ctrl_buf, 1);
}
/****************************************************************************/ /**
* @brief Write psram register
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param reg_value: Register value pointer storing data
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
{
uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
struct sf_ctrl_cmd_cfg_type psram_cmd;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
arch_memcpy(psram_ctrl_buf, reg_value, 1);
if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) {
psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
}
psram_cmd.cmd_buf[0] = (psram_cfg->write_reg_cmd) << 24;
psram_cmd.rw_flag = SF_CTRL_WRITE;
psram_cmd.addr_size = 3;
psram_cmd.nb_data = 1;
bflb_sf_ctrl_sendcmd(&psram_cmd);
}
/****************************************************************************/ /**
* @brief Set psram driver strength
*
* @param psram_cfg: Serial psram parameter configuration pointer
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg)
{
uint32_t stat = 0;
bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
if ((stat & 0x3) == psram_cfg->drive_strength) {
return 0;
}
stat &= (~0x3);
stat |= psram_cfg->drive_strength;
bflb_psram_writereg(psram_cfg, (uint8_t *)&stat);
/* Wait for write done */
bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
if ((stat & 0x3) == psram_cfg->drive_strength) {
return 0;
}
return -1;
}
/****************************************************************************/ /**
* @brief Set psram burst wrap size
*
* @param psram_cfg: Serial psram parameter configuration pointer
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg)
{
uint32_t stat = 0;
bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
if (((stat >> 5) & 0x3) == psram_cfg->burst_length) {
return 0;
}
stat &= (~(0x3 << 5));
stat |= (psram_cfg->burst_length << 5);
bflb_psram_writereg(psram_cfg, (uint8_t *)&stat);
/* Wait for write done */
bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
if (((stat >> 5) & 0x3) == psram_cfg->burst_length) {
return 0;
}
return -1;
}
/****************************************************************************/ /**
* @brief Get psram ID
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param data: Data pointer to store read data
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data)
{
uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
uint32_t timeout = 0;
struct sf_ctrl_cmd_cfg_type psram_cmd;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
psram_cmd.cmd_buf[0] = (psram_cfg->read_id_cmd) << 24;
psram_cmd.rw_flag = SF_CTRL_READ;
psram_cmd.addr_size = 3;
psram_cmd.dummy_clks = psram_cfg->read_id_dmy_clk;
psram_cmd.nb_data = 8;
bflb_sf_ctrl_sendcmd(&psram_cmd);
timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return;
}
}
arch_memcpy(data, psram_ctrl_buf, 8);
}
/****************************************************************************/ /**
* @brief Psram enter quad mode
*
* @param psram_cfg: Serial psram parameter configuration pointer
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg)
{
struct sf_ctrl_cmd_cfg_type psram_cmd;
uint32_t timeout = 0;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
psram_cmd.cmd_buf[0] = (psram_cfg->enter_quad_mode_cmd) << 24;
psram_cmd.rw_flag = SF_CTRL_READ;
bflb_sf_ctrl_sendcmd(&psram_cmd);
timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return -2;
}
}
return 0;
}
/****************************************************************************/ /**
* @brief Psram exit quad mode
*
* @param psram_cfg: Serial psram parameter configuration pointer
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg)
{
struct sf_ctrl_cmd_cfg_type psram_cmd;
uint32_t timeout = 0;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
psram_cmd.cmd_buf[0] = (psram_cfg->exit_quad_mode_cmd) << 24;
psram_cmd.rw_flag = SF_CTRL_READ;
bflb_sf_ctrl_sendcmd(&psram_cmd);
timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return -2;
}
}
return 0;
}
/****************************************************************************/ /**
* @brief Psram toggle burst length
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param ctrl_mode: Psram ctrl mode type
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
{
struct sf_ctrl_cmd_cfg_type psram_cmd;
uint32_t timeout = 0;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
if (ctrl_mode == PSRAM_QPI_CTRL_MODE) {
psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
}
psram_cmd.cmd_buf[0] = (psram_cfg->burst_toggle_cmd) << 24;
psram_cmd.rw_flag = SF_CTRL_READ;
bflb_sf_ctrl_sendcmd(&psram_cmd);
timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return -2;
}
}
return 0;
}
/****************************************************************************/ /**
* @brief Psram software reset
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param ctrl_mode: Psram ctrl mode type
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
{
struct sf_ctrl_cmd_cfg_type psram_cmd;
uint32_t timeout = 0;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
if (ctrl_mode == PSRAM_QPI_CTRL_MODE) {
psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
}
/* Reset enable */
psram_cmd.cmd_buf[0] = (psram_cfg->reset_enable_cmd) << 24;
/* rw_flag don't care */
psram_cmd.rw_flag = SF_CTRL_READ;
/* Wait for write done */
bflb_sf_ctrl_sendcmd(&psram_cmd);
timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return -2;
}
}
/* Reset */
psram_cmd.cmd_buf[0] = (psram_cfg->reset_cmd) << 24;
/* rw_flag don't care */
psram_cmd.rw_flag = SF_CTRL_READ;
bflb_sf_ctrl_sendcmd(&psram_cmd);
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return -2;
}
}
arch_delay_us(50);
return 0;
}
/****************************************************************************/ /**
* @brief Psram set IDbus config
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param io_mode: Psram ctrl mode type
* @param addr: Address to read/write
* @param len: Data length to read/write
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg,
uint8_t io_mode, uint32_t addr, uint32_t len)
{
uint8_t cmd, dummy_clks;
struct sf_ctrl_cmd_cfg_type psram_cmd;
uint8_t cmd_valid = 1;
bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB);
/* read mode cache set */
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
if (SF_CTRL_NIO_MODE == io_mode) {
cmd = psram_cfg->f_read_cmd;
dummy_clks = psram_cfg->f_read_dmy_clk;
} else if (SF_CTRL_QIO_MODE == io_mode) {
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
cmd = psram_cfg->f_read_quad_cmd;
dummy_clks = psram_cfg->f_read_quad_dmy_clk;
} else {
return -1;
}
/* prepare command */
psram_cmd.rw_flag = SF_CTRL_READ;
psram_cmd.addr_size = 3;
psram_cmd.cmd_buf[0] = (cmd << 24) | addr;
psram_cmd.dummy_clks = dummy_clks;
psram_cmd.nb_data = len;
bflb_sf_ctrl_psram_read_set(&psram_cmd, cmd_valid);
/* write mode cache set */
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
if (SF_CTRL_NIO_MODE == io_mode) {
cmd = psram_cfg->write_cmd;
} else if (SF_CTRL_QIO_MODE == io_mode) {
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
cmd = psram_cfg->quad_write_cmd;
} else {
return -1;
}
dummy_clks = 0;
/* prepare command */
psram_cmd.rw_flag = SF_CTRL_WRITE;
psram_cmd.addr_size = 3;
psram_cmd.cmd_buf[0] = (cmd << 24) | addr;
psram_cmd.dummy_clks = dummy_clks;
psram_cmd.nb_data = len;
bflb_sf_ctrl_psram_write_set(&psram_cmd, cmd_valid);
return 0;
}
/****************************************************************************/ /**
* @brief Set cache write to psram with cache
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param io_mode: Psram controller interface mode
* @param wt_en: Psram cache write through enable
* @param wb_en: Psram cache write back enable
* @param wa_en: Psram cache write allocate enable
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
{
int stat = -1;
/* Cache now only support 32 bytes read */
stat = bflb_psram_set_idbus_cfg(psram_cfg, io_mode, 0, 32);
if (0 != stat) {
return stat;
}
bflb_l1c_cache_write_set(wt_en, wb_en, wa_en);
return 0;
}
/****************************************************************************/ /**
* @brief Write psram one region
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param io_mode: Write mode: SPI mode or QPI mode
* @param addr: Start address to be write
* @param data: Data pointer to be write
* @param len: Data length to be write
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
uint32_t addr, uint8_t *data, uint32_t len)
{
uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
uint32_t i = 0, cur_len = 0;
uint32_t burst_len = 512;
uint8_t cmd;
struct sf_ctrl_cmd_cfg_type psram_cmd;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
if (SF_CTRL_NIO_MODE == io_mode) {
cmd = psram_cfg->write_cmd;
} else if (SF_CTRL_QIO_MODE == io_mode) {
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
cmd = psram_cfg->quad_write_cmd;
} else {
return -1;
}
/* Prepare command */
psram_cmd.rw_flag = SF_CTRL_WRITE;
psram_cmd.addr_size = 3;
if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) {
burst_len = 16;
} else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) {
burst_len = 32;
} else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) {
burst_len = 64;
} else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) {
burst_len = 512;
}
for (i = 0; i < len;) {
/* Get current programmed length within page size */
cur_len = burst_len - addr % burst_len;
if (cur_len > len - i) {
cur_len = len - i;
}
/* Prepare command */
arch_memcpy_fast(psram_ctrl_buf, data, cur_len);
psram_cmd.cmd_buf[0] = (cmd << 24) | (addr);
psram_cmd.nb_data = cur_len;
bflb_sf_ctrl_sendcmd(&psram_cmd);
/* Adjust address and programmed length */
addr += cur_len;
i += cur_len;
data += cur_len;
/* Wait for write done */
}
return 0;
}
/****************************************************************************/ /**
* @brief Read data from psram
*
* @param psram_cfg: Serial psram parameter configuration pointer
* @param io_mode: IoMode: psram controller interface mode
* @param addr: Psram read start address
* @param data: Data pointer to store data read from psram
* @param len: Data length to read
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
uint32_t addr, uint8_t *data, uint32_t len)
{
uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
uint32_t cur_len, i;
uint32_t burst_len = 512;
uint32_t timeout = 0;
uint8_t cmd, dummy_clks;
struct sf_ctrl_cmd_cfg_type psram_cmd;
if (((uint32_t)&psram_cmd) % 4 == 0) {
arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
} else {
arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
}
if (SF_CTRL_NIO_MODE == io_mode) {
cmd = psram_cfg->f_read_cmd;
dummy_clks = psram_cfg->f_read_dmy_clk;
} else if (SF_CTRL_QIO_MODE == io_mode) {
psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
cmd = psram_cfg->f_read_quad_cmd;
dummy_clks = psram_cfg->f_read_quad_dmy_clk;
} else {
return -1;
}
/* Prepare command */
psram_cmd.rw_flag = SF_CTRL_READ;
psram_cmd.addr_size = 3;
psram_cmd.dummy_clks = dummy_clks;
if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) {
burst_len = 16;
} else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) {
burst_len = 32;
} else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) {
burst_len = 64;
} else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) {
burst_len = 512;
}
/* Read data */
for (i = 0; i < len;) {
/* Prepare command */
psram_cmd.cmd_buf[0] = (cmd << 24) | (addr);
cur_len = burst_len - addr % burst_len;
if (cur_len > len - i) {
cur_len = len - i;
}
if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
cur_len = NOR_FLASH_CTRL_BUF_SIZE;
psram_cmd.nb_data = cur_len;
} else {
/* Make sf_ctrl word read */
psram_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
}
bflb_sf_ctrl_sendcmd(&psram_cmd);
timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
while (bflb_sf_ctrl_get_busy_state()) {
timeout--;
if (timeout == 0) {
return -2;
}
}
arch_memcpy_fast(data, psram_ctrl_buf, cur_len);
addr += cur_len;
i += cur_len;
data += cur_len;
}
return 0;
}
/*@} end of group PSRAM_Public_Functions */
/*@} end of group PSRAM */
/*@} end of group BFLB_Peripheral_Driver */

90
drivers/lhal/src/bflb_timer.c
View File

@ -200,3 +200,93 @@ void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no)
regval |= (1 << cmp_no);
putreg32(regval, reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx);
}
#if !defined(BL702) && !defined(BL602)
void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config)
{
uint32_t regval;
uint32_t reg_base;
reg_base = dev->reg_base;
#if defined(BL702L)
regval = getreg32(0x20000000 + 0xc);
regval &= ~(0x3 << 14);
switch (config->pin & 0x03) {
case 0:
regval &= ~(1 << 10);
regval |= (0 << 14);
break;
case 1:
regval &= ~(1 << 11);
regval |= (1 << 14);
break;
case 2:
regval &= ~(1 << 12);
regval |= (2 << 14);
break;
case 3:
regval &= ~(1 << 13);
regval |= (3 << 14);
break;
default:
break;
}
putreg32(regval, 0x20000000 + 0xc);
struct bflb_device_s *gpio = bflb_device_get_by_name("gpio");
bflb_gpio_init(gpio, config->pin, (0 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1);
#else
regval = getreg32(0x20000000 + 0x258);
regval &= ~(3 << 12);
switch (config->pin & 0x03) {
case 0:
regval &= ~(1 << 8);
regval |= (0 << 12);
break;
case 1:
regval &= ~(1 << 9);
regval |= (1 << 12);
break;
case 2:
regval &= ~(1 << 10);
regval |= (2 << 12);
break;
case 3:
regval &= ~(1 << 11);
regval |= (3 << 12);
break;
default:
break;
}
putreg32(regval, 0x20000000 + 0x258);
struct bflb_device_s *gpio = bflb_device_get_by_name("gpio");
bflb_gpio_init(gpio, config->pin, (31 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1);
#endif
regval = getreg32(reg_base + TIMER_GPIO_OFFSET);
/* polarity: 1->neg, 0->pos */
if (config->polarity == TIMER_CAPTURE_POLARITY_NEGATIVE) {
regval |= (1 << (5 + dev->idx));
} else {
regval &= ~(1 << (5 + dev->idx));
}
regval |= TIMER0_GPIO_EN;
putreg32(regval, reg_base + TIMER_GPIO_OFFSET);
}
uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev)
{
uint32_t reg_base;
uint32_t lat1 = 0;
uint32_t lat2 = 0;
reg_base = dev->reg_base;
do {
lat1 = getreg32(reg_base + TIMER_GPIO_LAT1_OFFSET);
lat2 = getreg32(reg_base + TIMER_GPIO_LAT2_OFFSET);
} while (!(getreg32(reg_base + TIMER_GPIO_OFFSET) & TIMER_GPIO_LAT_OK) || (lat1 >= lat2));
return (lat2 - lat1);
}
#endif

3704
drivers/lhal/src/flash/bflb_sf_cfg.c Normal file
View File

File diff suppressed because it is too large Load Diff

215
drivers/lhal/src/flash/bflb_sf_cfg.h Normal file
View File

@ -0,0 +1,215 @@
/**
******************************************************************************
* @file bflb_sf_cfg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL628_SF_CFG_H__
#define __BL628_SF_CFG_H__
#include "bflb_gpio.h"
#include "bflb_sflash.h"
/** @addtogroup BL628_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CFG
* @{
*/
/** @defgroup SF_CFG_Public_Types
* @{
*/
/*@} end of group SF_CFG_Public_Types */
/** @defgroup SF_CFG_Public_Constants
* @{
*/
/*@} end of group SF_CFG_Public_Constants */
/** @defgroup SF_CFG_Public_Macros
* @{
*/
#define BFLB_GPIO_FUNC_SF 2
#if defined(BL628) || defined(BL616)
/* Flash option sf2 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_8
/* FLASH CS */
#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_4
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_7
#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_5
#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_6
#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_9
/* Flash option sf3 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_15
/* FLASH CS */
#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_20
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_16
#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_19
#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_18
#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_14
#elif defined(BL808) || defined(BL606P)
/* Flash option sf2 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_34
/* FLASH CS */
#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_35
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_36
#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_37
#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_38
#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_39
#elif defined(BL702L)
/* Flash option */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_27
/* FLASH CS */
#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_26
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_23
#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_25
#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_24
#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_28
#elif defined(BL702)
/* Flash option 0 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_21
/* FLASH CS */
#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_19
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_17
#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_18
#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_22
#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_20
/* Flash option 1 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_27
/* FLASH CS */
#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_25
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_28
#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_24
#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_23
#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_26
/* Flash option 2 */
/* Flash CLK */
#define BFLB_EXTFLASH_CLK2_GPIO GPIO_PIN_36
/* FLASH CS */
#define BFLB_EXTFLASH_CS2_GPIO GPIO_PIN_35
/* FLASH DATA */
#define BFLB_EXTFLASH_DATA02_GPIO GPIO_PIN_32
#define BFLB_EXTFLASH_DATA12_GPIO GPIO_PIN_34
#define BFLB_EXTFLASH_DATA22_GPIO GPIO_PIN_33
#define BFLB_EXTFLASH_DATA32_GPIO GPIO_PIN_37
#define BFLB_FLASH_CFG_SF2_EXT_23_28 0
#define BFLB_FLASH_CFG_SF2_INT_512K 1
#define BFLB_FLASH_CFG_SF2_INT_1M 2
#define BFLB_FLASH_CFG_SF1_EXT_17_22 3
#define BFLB_SF2_SWAP_NONE 0
#define BFLB_SF2_SWAP_CS_IO2 1
#define BFLB_SF2_SWAP_IO0_IO3 2
#define BFLB_SF2_SWAP_BOTH 3
#elif defined(BL602)
/*Flash option 0*/
/*Flash CLK*/
#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_22
/*FLASH CS*/
#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_21
/*FLASH DATA*/
#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_20
#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_19
#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_18
#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_17
/*Flash option 1*/
/*Flash CLK*/
#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_22
/*FLASH CS*/
#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_21
/*FLASH DATA*/
#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_20
#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_0
#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_1
#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_2
#define BFLB_FLASH_CFG_DESWAP 1
#define BFLB_FLASH_CFG_EXT0_17_22 2
#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3
#endif
#define BFLB_FLASH_ID_VALID_FLAG 0x80000000
#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF
/*@} end of group SF_CFG_Public_Macros */
/** @defgroup SF_CFG_Public_Functions
* @{
*/
int bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
uint8_t group, uint8_t bank);
int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
uint8_t group, uint8_t bank);
#if defined(BL702L) || defined(BL702)
void bflb_sf_cfg_init_internal_flash_gpio(void);
#endif
#if defined(BL602)
void bflb_sf_cfg_restore_gpio17_fun(uint8_t fun);
#endif
int bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default);
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
int bflb_sf_cfg_init_flash2_gpio(uint8_t swap);
#endif
int bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin);
int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin);
uint32_t bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t callfromflash, uint8_t flash_pin_cfg, uint8_t restore_default,
spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg,
const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
int bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
#else
int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg);
#endif
/*@} end of group SF_CFG_Public_Functions */
/*@} end of group SF_CFG */
/*@} end of group BL628_Peripheral_Driver */
#endif /* __BL628_SF_CFG_H__ */

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/**
******************************************************************************
* @file bflb_sf_ctrl.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL628_SF_CTRL_H__
#define __BL628_SF_CTRL_H__
#include "bflb_core.h"
/** @addtogroup BL628_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CTRL
* @{
*/
/** @defgroup SF_CTRL_Public_Types
* @{
*/
#if defined(BL602) || defined(BL702) || defined(BL702L)
#define BFLB_SF_CTRL_BASE ((uint32_t)0x4000B000)
#elif defined(BL606P) || defined(BL808) || defined(BL616)
#define BFLB_SF_CTRL_BASE ((uint32_t)0x2000b000)
#elif defined(BL628)
#define BFLB_SF_CTRL_BASE ((uint32_t)0x20082000)
#endif
#if defined(BL602) || defined(BL702) || defined(BL702L)
#define BFLB_FLASH_XIP_BASE (0x23000000)
#define BFLB_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024)
#elif defined(BL606P) || defined(BL808)
#define BFLB_FLASH_XIP_BASE (0x58000000)
#define BFLB_FLASH_XIP_END (0x58000000 + 64 * 1024 * 1024)
#elif defined(BL616)
#define BFLB_FLASH_XIP_BASE (0xA0000000)
#define BFLB_FLASH_XIP_END (0xA0000000 + 64 * 1024 * 1024)
#elif defined(BL628)
#define BFLB_FLASH_XIP_BASE (0x80000000)
#define BFLB_FLASH_XIP_END (0x80000000 + 64 * 1024 * 1024)
#endif
#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)
#define BFLB_SF_CTRL_SBUS2_ENABLE
#define BFLB_SF_CTRL_32BITS_ADDR_ENABLE
#define BFLB_SF_CTRL_AES_XTS_ENABLE
#endif
#if defined(BL702) || defined(BL702L)
#define BFLB_SF_CTRL_PSRAM_ENABLE
#endif
/**
* @brief Serial flash pad type definition
*/
#define SF_CTRL_PAD1 0 /*!< SF Ctrl pad 1 */
#define SF_CTRL_PAD2 1 /*!< SF Ctrl pad 2 */
#define SF_CTRL_PAD3 2 /*!< SF Ctrl pad 3 */
/**
* @brief Serial flash config pin select type definition
*/
#if defined(BL628) || defined(BL616)
#define SF_IO_EMB_SWAP_IO3IO0 0x0 /*!< SF select embedded flash swap io3 with io0 */
#define SF_IO_EMB_SWAP_IO3IO0_IO2CS 0x1 /*!< SF select embedded flash swap io3 with io0 and io2 with cs */
#define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */
#define SF_IO_EMB_SWAP_IO2CS 0x3 /*!< SF select embedded flash swap io2 with cs */
#define SF_IO_EXT_SF2_SWAP_IO3IO0 0x4 /*!< SF select external flash SF2 use gpio4-9 and SF2 swap io3 with io0 */
#define SF_IO_EXT_SF3 0x8 /*!< SF select external flash SF3 use gpio10-15 */
#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 0x14 /*!< SF select embedded flash swap io3 with io0 and SF2 swap io3 with io0*/
#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0 0x15 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 swap io3 with io0 */
#define SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0 0x16 /*!< SF select embedded flash no swap and SF2 swap io3 with io0 */
#define SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0 0x17 /*!< SF select embedded flash swap io2 with cs, and SF2 swap io3 with io0 */
#define SF_IO_EXT_SF2 0x24 /*!< SF select external flash SF2 use gpio4-9 */
#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2 0x34 /*!< SF select embedded flash swap io3 with io0 and SF2 use gpio4-9 */
#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2 0x35 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 use gpio4-9 */
#define SF_IO_EMB_SWAP_NONE_AND_SF2 0x36 /*!< SF select embedded flash no swap and SF2 use gpio4-9 */
#define SF_IO_EMB_SWAP_IO2CS_AND_SF2 0x37 /*!< SF select embedded flash swap io2 with cs and SF2 use gpio4-9 */
#elif defined(BL808) || defined(BL606P)
#define SF_IO_EMB_SWAP_IO0_IO3 0x0 /*!< SF select embedded flash swap io0 with io3 */
#define SF_IO_EMB_SWAP_DUAL_IO0_IO3 0x1 /*!< SF select embedded flash swap dual io0 with io3 */
#define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */
#define SF_IO_EMB_SWAP_NONE_DUAL_IO0 0x3 /*!< SF select embedded flash no swap and use dual io0 */
#define SF_IO_EXT_SF2 0x4 /*!< SF select external flash SF2 use gpio34-39 */
#define SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 0x14 /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */
#define SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 0x15 /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */
#define SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 0x16 /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */
#define SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 0x17 /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */
#elif defined(BL702L)
#define SF_CTRL_SEL_EXTERNAL_FLASH 0x0 /*!< SF select sf2, flash use GPIO 23-28, external flash */
#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE 0x1 /*!< SF select sf1, embedded flash do not swap */
#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2 0x2 /*!< SF select sf1, embedded flash swap cs/io2 */
#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3 0x3 /*!< SF select sf1, embedded flash swap io0/io3 */
#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH 0x4 /*!< SF select sf1, embedded flash swap cs/io2 and io0/io3 */
#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE 0x5 /*!< SF select sf1, embedded flash interface reverse and do not swap */
#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2 0x6 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 */
#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3 0x7 /*!< SF select sf1, embedded flash interface reverse and swap io0/io3 */
#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH 0x8 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 and io0/io3 */
#elif defined(BL702)
#define SF_CTRL_SEL_SF1 0x0 /*!< SF Ctrl select sf1, flash use GPIO 17-22, no psram */
#define SF_CTRL_SEL_SF2 0x1 /*!< SF Ctrl select sf2, flash use GPIO 23-28, no psram, embedded flash */
#define SF_CTRL_SEL_SF3 0x2 /*!< SF Ctrl select sf3, flash use GPIO 32-37, no psram */
#define SF_CTRL_SEL_DUAL_BANK_SF1_SF2 0x3 /*!< SF Ctrl select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */
#define SF_CTRL_SEL_DUAL_BANK_SF2_SF3 0x4 /*!< SF Ctrl select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */
#define SF_CTRL_SEL_DUAL_BANK_SF3_SF1 0x5 /*!< SF Ctrl select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */
#define SF_CTRL_SEL_DUAL_CS_SF2 0x6 /*!< SF Ctrl select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */
#define SF_CTRL_SEL_DUAL_CS_SF3 0x7 /*!< SF Ctrl select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */
#elif defined(BL602)
#define SF_CTRL_EMBEDDED_SEL 0x0 /*!< Embedded flash select */
#define SF_CTRL_EXTERNAL_17TO22_SEL 0x1 /*!< External flash select gpio 17-22 */
#define SF_CTRL_EXTERNAL_0TO2_20TO22_SEL 0x2 /*!< External flash select gpio 0-2 and 20-22 */
#endif
/**
* @brief Serial flash select bank control type definition
*/
#if defined(BL702) || defined(BL702L)
#define SF_CTRL_SEL_FLASH 0 /*!< SF Ctrl system bus control flash */
#define SF_CTRL_SEL_PSRAM 1 /*!< SF Ctrl system bus control psram */
#else
#define SF_CTRL_FLASH_BANK0 0 /*!< SF Ctrl select flash bank0 */
#define SF_CTRL_FLASH_BANK1 1 /*!< SF Ctrl select flash bank1 */
#endif
/**
* @brief Serial flash controller wrap mode type definition
*/
#define SF_CTRL_WRAP_MODE_0 0 /*!< Cmds bypass wrap commands to macro, original mode */
#define SF_CTRL_WRAP_MODE_1 1 /*!< Cmds handle wrap commands, original mode */
#define SF_CTRL_WRAP_MODE_2 2 /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */
#define SF_CTRL_WRAP_MODE_3 3 /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */
/**
* @brief Serail flash controller wrap mode len type definition
*/
#define SF_CTRL_WRAP_LEN_8 0 /*!< SF Ctrl wrap length: 8 */
#define SF_CTRL_WRAP_LEN_16 1 /*!< SF Ctrl wrap length: 16 */
#define SF_CTRL_WRAP_LEN_32 2 /*!< SF Ctrl wrap length: 32 */
#define SF_CTRL_WRAP_LEN_64 3 /*!< SF Ctrl wrap length: 64 */
#define SF_CTRL_WRAP_LEN_128 4 /*!< SF Ctrl wrap length: 128 */
#define SF_CTRL_WRAP_LEN_256 5 /*!< SF Ctrl wrap length: 256 */
#define SF_CTRL_WRAP_LEN_512 6 /*!< SF Ctrl wrap length: 512 */
#define SF_CTRL_WRAP_LEN_1024 7 /*!< SF Ctrl wrap length: 1024 */
#define SF_CTRL_WRAP_LEN_2048 8 /*!< SF Ctrl wrap length: 2048 */
#define SF_CTRL_WRAP_LEN_4096 9 /*!< SF Ctrl wrap length: 4096 */
/**
* @brief Serail flash controller memory remap type define
*/
#define SF_CTRL_ORIGINAL_MEMORY_MAP 0 /*!< Remap none, use two addr map when use dual flash */
#define SF_CTRL_REMAP_16MB 1 /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */
#define SF_CTRL_REMAP_8MB 2 /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */
#define SF_CTRL_REMAP_4MB 3 /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */
/**
* @brief Serial flash controller select clock type definition
*/
#define SF_CTRL_OWNER_SAHB 0 /*!< System AHB bus control serial flash controller */
#define SF_CTRL_OWNER_IAHB 1 /*!< I-Code AHB bus control serial flash controller */
/**
* @brief Serial flash controller select clock type definition
*/
#define SF_CTRL_SAHB_CLOCK 0 /*!< Serial flash controller select default sahb clock */
#define SF_CTRL_FLASH_CLOCK 1 /*!< Serial flash controller select flash clock */
/**
* @brief Read and write type definition
*/
#define SF_CTRL_READ 0 /*!< Serail flash read command flag */
#define SF_CTRL_WRITE 1 /*!< Serail flash write command flag */
/**
* @brief Serail flash interface IO type definition
*/
#define SF_CTRL_NIO_MODE 0 /*!< Normal IO mode define */
#define SF_CTRL_DO_MODE 1 /*!< Dual Output mode define */
#define SF_CTRL_QO_MODE 2 /*!< Quad Output mode define */
#define SF_CTRL_DIO_MODE 3 /*!< Dual IO mode define */
#define SF_CTRL_QIO_MODE 4 /*!< Quad IO mode define */
/**
* @brief Serail flash controller interface mode type definition
*/
#define SF_CTRL_SPI_MODE 0 /*!< SPI mode define */
#define SF_CTRL_QPI_MODE 1 /*!< QPI mode define */
/**
* @brief Serail flash controller command mode type definition
*/
#define SF_CTRL_CMD_1_LINE 0 /*!< Command in one line mode */
#define SF_CTRL_CMD_4_LINES 1 /*!< Command in four lines mode */
/**
* @brief Serail flash controller address mode type definition
*/
#define SF_CTRL_ADDR_1_LINE 0 /*!< Address in one line mode */
#define SF_CTRL_ADDR_2_LINES 1 /*!< Address in two lines mode */
#define SF_CTRL_ADDR_4_LINES 2 /*!< Address in four lines mode */
/**
* @brief Serail flash controller dummy mode type definition
*/
#define SF_CTRL_DUMMY_1_LINE 0 /*!< Dummy in one line mode */
#define SF_CTRL_DUMMY_2_LINES 1 /*!< Dummy in two lines mode */
#define SF_CTRL_DUMMY_4_LINES 2 /*!< Dummy in four lines mode */
/**
* @brief Serail flash controller data mode type definition
*/
#define SF_CTRL_DATA_1_LINE 0 /*!< Data in one line mode */
#define SF_CTRL_DATA_2_LINES 1 /*!< Data in two lines mode */
#define SF_CTRL_DATA_4_LINES 2 /*!< Data in four lines mode */
/**
* @brief Serail flash controller AES mode type definition
*/
#define SF_CTRL_AES_CTR_MODE 0 /*!< Serail flash AES CTR mode */
#define SF_CTRL_AES_XTS_MODE 1 /*!< Serail flash AES XTS mode */
/**
* @brief Serail flash controller AES key len type definition
*/
#define SF_CTRL_AES_128BITS 0 /*!< Serail flash AES key 128 bits length */
#define SF_CTRL_AES_256BITS 1 /*!< Serail flash AES key 256 bits length */
#define SF_CTRL_AES_192BITS 2 /*!< Serail flash AES key 192 bits length */
#define SF_CTRL_AES_128BITS_DOUBLE_KEY 3 /*!< Serail flash AES key 128 bits length double key */
/**
* @brief Serail flash controller configuration structure type definition
*/
struct sf_ctrl_cfg_type {
uint8_t owner; /*!< Sflash interface bus owner */
#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
uint8_t en32b_addr; /*!< Sflash enable 32-bits address */
#endif
uint8_t clk_delay; /*!< Clock count for read due to pad delay */
uint8_t clk_invert; /*!< Clock invert */
uint8_t rx_clk_invert; /*!< RX clock invert */
uint8_t do_delay; /*!< Data out delay */
uint8_t di_delay; /*!< Data in delay */
uint8_t oe_delay; /*!< Output enable delay */
};
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
/**
* @brief SF Ctrl bank2 controller configuration structure type definition
*/
struct sf_ctrl_bank2_cfg {
uint8_t sbus2_select; /*!< Select sbus2 as 2nd flash controller */
uint8_t bank2_rx_clk_invert_src; /*!< Select bank2 rx clock invert source */
uint8_t bank2_rx_clk_invert_sel; /*!< Select inveted bank2 rx clock */
uint8_t bank2_delay_src; /*!< Select bank2 read delay source */
uint8_t bank2_clk_delay; /*!< Bank2 read delay cycle = n + 1 */
uint8_t do_delay; /*!< Data out delay */
uint8_t di_delay; /*!< Data in delay */
uint8_t oe_delay; /*!< Output enable delay */
uint8_t remap; /*!< Select dual flash memory remap set */
uint8_t remap_lock; /*!< Select memory remap lock */
};
#endif
#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
/**
* @brief SF Ctrl psram controller configuration structure type definition
*/
struct sf_ctrl_psram_cfg {
uint8_t owner; /*!< Psram interface bus owner */
uint8_t pad_sel; /*!< SF Ctrl pad select */
uint8_t bank_sel; /*!< SF Ctrl bank select */
uint8_t psram_rx_clk_invert_src; /*!< Select psram rx clock invert source */
uint8_t psram_rx_clk_invert_sel; /*!< Select inveted psram rx clock */
uint8_t psram_delay_src; /*!< Select psram read delay source */
uint8_t psram_clk_delay; /*!< Psram read delay cycle = n + 1 */
} ;
#endif
/**
* @brief SF Ctrl cmds configuration structure type definition
*/
struct sf_ctrl_cmds_cfg {
uint8_t ack_latency; /*!< SF Ctrl ack latency cycles */
uint8_t cmds_core_en; /*!< SF Ctrl cmds core enable */
#if defined(BL702)
uint8_t burst_toggle_en; /*!< SF Ctrl burst toggle mode enable */
#endif
uint8_t cmds_en; /*!< SF Ctrl cmds enable */
uint8_t cmds_wrap_mode; /*!< SF Ctrl cmds wrap mode */
uint8_t cmds_wrap_len; /*!< SF Ctrl cmds wrap length */
};
/**
* @brief Serail flash command configuration structure type definition
*/
struct sf_ctrl_cmd_cfg_type {
uint8_t rw_flag; /*!< Read write flag */
uint8_t cmd_mode; /*!< Command mode */
uint8_t addr_mode; /*!< Address mode */
uint8_t addr_size; /*!< Address size */
uint8_t dummy_clks; /*!< Dummy clocks */
uint8_t dummy_mode; /*!< Dummy mode */
uint8_t data_mode; /*!< Data mode */
uint8_t rsv[1]; /*!< Reserved */
uint32_t nb_data; /*!< Transfer number of bytes */
uint32_t cmd_buf[2]; /*!< Command buffer */
};
/*@} end of group SF_CTRL_Public_Types */
/** @defgroup SF_CTRL_Public_Macros
* @{
*/
#if defined(BL602) || defined(BL702) || defined(BL702L)
#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000)
#else
#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000)
#endif
#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF
#define NOR_FLASH_CTRL_BUF_SIZE 256
#define NAND_FLASH_CTRL_BUF_SIZE 512
#if defined(BL628) || defined(BL616)
#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS) || \
((type) == SF_IO_EMB_SWAP_NONE) || \
((type) == SF_IO_EMB_SWAP_IO2CS) || \
((type) == SF_IO_EXT_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EXT_SF3) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) || \
((type) == SF_IO_EXT_SF2) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2) || \
((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2) || \
((type) == SF_IO_EMB_SWAP_NONE_AND_SF2) || \
((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2))
#elif defined(BL808) || defined(BL606P)
#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \
((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \
((type) == SF_IO_EMB_SWAP_NONE) || \
((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \
((type) == SF_IO_EXT_SF2) || \
((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \
((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \
((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \
((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2))
#elif defined(BL702L)
#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_EXTERNAL_FLASH) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) || \
((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH))
#elif defined(BL702)
#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_SF1) || \
((type) == SF_CTRL_SEL_SF2) || \
((type) == SF_CTRL_SEL_SF3) || \
((type) == SF_CTRL_SEL_DUAL_BANK_SF1_SF2) || \
((type) == SF_CTRL_SEL_DUAL_BANK_SF2_SF3) || \
((type) == SF_CTRL_SEL_DUAL_BANK_SF3_SF1) || \
((type) == SF_CTRL_SEL_DUAL_CS_SF2) || \
((type) == SF_CTRL_SEL_DUAL_CS_SF3))
#elif defined(BL602)
#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \
((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \
((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL))
#endif
/*@} end of group SF_CTRL_Public_Macros */
/** @defgroup SF_CTRL_Public_Functions
* @{
*/
void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg);
void bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t dodelay, uint8_t didelay, uint8_t oedelay);
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
void bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2cfg);
void bflb_sf_ctrl_sbus2_hold_sram(void);
void bflb_sf_ctrl_sbus2_release_sram(void);
uint8_t sf_ctrl_is_sbus2_enable(void);
void bflb_sf_ctrl_sbus2_replace(uint8_t pad);
void bflb_sf_ctrl_sbus2_revoke_replace(void);
void bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert);
void bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock);
#endif
#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
void bflb_sf_ctrl_32bits_addr_en(uint8_t en_32bit_saddr);
#endif
#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg);
#endif
uint8_t bflb_sf_ctrl_get_clock_delay(void);
void bflb_sf_ctrl_set_clock_delay(uint8_t delay);
uint8_t bflb_sf_ctrl_get_wrap_queue_value(void);
void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel);
#if defined(BL702L)
void bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode);
#endif
void bflb_sf_ctrl_select_pad(uint8_t sel);
void bflb_sf_ctrl_sbus_select_bank(uint8_t bank);
void bflb_sf_ctrl_set_owner(uint8_t owner);
void bflb_sf_ctrl_disable(void);
void bflb_sf_ctrl_aes_enable_be(void);
void bflb_sf_ctrl_aes_enable_le(void);
void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwkey,
uint32_t start_addr, uint32_t end_addr, uint8_t locked);
void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type);
void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type);
void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset);
void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset);
#ifdef BFLB_SF_CTRL_AES_XTS_ENABLE
void bflb_sf_ctrl_aes_xts_set_key(uint8_t region, uint8_t *key, uint8_t key_type);
void bflb_sf_ctrl_aes_xts_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type);
void bflb_sf_ctrl_aes_xts_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset);
void bflb_sf_ctrl_aes_xts_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset);
#endif
void bflb_sf_ctrl_aes_set_mode(uint8_t mode);
void bflb_sf_ctrl_aes_enable(void);
void bflb_sf_ctrl_aes_disable(void);
uint8_t bflb_sf_ctrl_is_aes_enable(void);
void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank);
uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank);
void bflb_sf_ctrl_lock_flash_image_offset(uint8_t lock);
void bflb_sf_ctrl_select_clock(uint8_t sahb_sram_sel);
void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg);
void bflb_sf_ctrl_disable_wrap_access(uint8_t disable);
void bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
void bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
#endif
#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
void bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
void bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
#endif
uint8_t bflb_sf_ctrl_get_busy_state(void);
#ifndef BFLB_USE_HAL_DRIVER
void bflb_sf_ctrl_irqhandler(void);
#endif
/*@} end of group SF_CTRL_Public_Functions */
/*@} end of group SF_CTRL */
/*@} end of group BL628_Peripheral_Driver */
#endif /* __BL628_SF_CTRL_H__ */

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/**
******************************************************************************
* @file bl628_sflah.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL628_SFLAH_H__
#define __BL628_SFLAH_H__
#include "bflb_sf_ctrl.h"
/** @addtogroup BL628_Peripheral_Driver
* @{
*/
/** @addtogroup SFLAH
* @{
*/
/** @defgroup SFLAH_Public_Types
* @{
*/
/**
* @brief Serial flash configuration structure type definition
*/
typedef struct
{
uint8_t io_mode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */
uint8_t c_read_support; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clk_delay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clk_invert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t reset_en_cmd; /*!< Flash enable reset command */
uint8_t reset_cmd; /*!< Flash reset command */
uint8_t reset_c_read_cmd; /*!< Flash reset continuous read command */
uint8_t reset_c_read_cmd_size; /*!< Flash reset continuous read command size */
uint8_t jedec_id_cmd; /*!< JEDEC ID command */
uint8_t jedec_id_cmd_dmy_clk; /*!< JEDEC ID command dummy clock */
#if defined(BL702L) || defined(BL702) || defined(BL602)
uint8_t qpi_jedec_id_cmd; /*!< QPI JEDEC ID comamnd */
uint8_t qpi_jedec_id_cmd_dmy_clk; /*!< QPI JEDEC ID command dummy clock */
#else
uint8_t enter_32bits_addr_cmd; /*!< Enter 32-bits addr command */
uint8_t exit_32bits_addr_cmd; /*!< Exit 32-bits addr command */
#endif
uint8_t sector_size; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t page_size; /*!< Page size */
uint8_t chip_erase_cmd; /*!< Chip erase cmd */
uint8_t sector_erase_cmd; /*!< Sector erase command */
uint8_t blk32_erase_cmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64_erase_cmd; /*!< Block 64K erase command */
uint8_t write_enable_cmd; /*!< Need before every erase or program */
uint8_t page_program_cmd; /*!< Page program cmd */
uint8_t qpage_program_cmd; /*!< QIO page program cmd */
uint8_t qpp_addr_mode; /*!< QIO page program address mode */
uint8_t fast_read_cmd; /*!< Fast read command */
uint8_t fr_dmy_clk; /*!< Fast read command dummy clock */
uint8_t qpi_fast_read_cmd; /*!< QPI fast read command */
uint8_t qpi_fr_dmy_clk; /*!< QPI fast read command dummy clock */
uint8_t fast_read_do_cmd; /*!< Fast read dual output command */
uint8_t fr_do_dmy_clk; /*!< Fast read dual output command dummy clock */
uint8_t fast_read_dio_cmd; /*!< Fast read dual io comamnd */
uint8_t fr_dio_dmy_clk; /*!< Fast read dual io command dummy clock */
uint8_t fast_read_qo_cmd; /*!< Fast read quad output comamnd */
uint8_t fr_qo_dmy_clk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fast_read_qio_cmd; /*!< Fast read quad io comamnd */
uint8_t fr_qio_dmy_clk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpi_fast_read_qio_cmd; /*!< QPI fast read quad io comamnd */
uint8_t qpi_fr_qio_dmy_clk; /*!< QPI fast read QIO dummy clock */
uint8_t qpi_page_program_cmd; /*!< QPI program command */
uint8_t write_vreg_enable_cmd; /*!< Enable write reg */
uint8_t wr_enable_index; /*!< Write enable register index */
uint8_t qe_index; /*!< Quad mode enable register index */
uint8_t busy_index; /*!< Busy status register index */
uint8_t wr_enable_bit; /*!< Write enable bit pos */
uint8_t qe_bit; /*!< Quad enable bit pos */
uint8_t busy_bit; /*!< Busy status bit pos */
uint8_t wr_enable_write_reg_len; /*!< Register length of write enable */
uint8_t wr_enable_read_reg_len; /*!< Register length of write enable status */
uint8_t qe_write_reg_len; /*!< Register length of contain quad enable */
uint8_t qe_read_reg_len; /*!< Register length of contain quad enable status */
uint8_t release_powerdown; /*!< Release power down command */
uint8_t busy_read_reg_len; /*!< Register length of contain busy status */
uint8_t read_reg_cmd[4]; /*!< Read register command buffer */
uint8_t write_reg_cmd[4]; /*!< Write register command buffer */
uint8_t enter_qpi; /*!< Enter qpi command */
uint8_t exit_qpi; /*!< Exit qpi command */
uint8_t c_read_mode; /*!< Config data for continuous read mode */
uint8_t c_rexit; /*!< Config data for exit continuous read mode */
uint8_t burst_wrap_cmd; /*!< Enable burst wrap command */
uint8_t burst_wrap_cmd_dmy_clk; /*!< Enable burst wrap command dummy clock */
uint8_t burst_wrap_data_mode; /*!< Data and address mode for this command */
uint8_t burst_wrap_data; /*!< Data to enable burst wrap */
uint8_t de_burst_wrap_cmd; /*!< Disable burst wrap command */
uint8_t de_burst_wrap_cmd_dmy_clk; /*!< Disable burst wrap command dummy clock */
uint8_t de_burst_wrap_data_mode; /*!< Data and address mode for this command */
uint8_t de_burst_wrap_data; /*!< Data to disable burst wrap */
uint16_t time_e_sector; /*!< 4K erase time */
uint16_t time_e_32k; /*!< 32K erase time */
uint16_t time_e_64k; /*!< 64K erase time */
uint16_t time_page_pgm; /*!< Page program time */
uint16_t time_ce; /*!< Chip erase time in ms */
uint8_t pd_delay; /*!< Release power down command delay time for wake up */
uint8_t qe_data; /*!< QE set data */
} __attribute__((packed)) spi_flash_cfg_type;
/**
* @brief Serial flash security register configuration
*/
struct sflash_sec_reg_cfg
{
uint8_t erase_cmd; /*!< Erase security register command */
uint8_t program_cmd; /*!< Program security register command */
uint8_t read_cmd; /*!< Read security register command */
uint8_t enter_sec_opt_cmd; /*!< Enter security register option mode command */
uint8_t exit_sec_opt_cmd; /*!< Exit security register option mode command */
uint8_t block_num; /*!< Security register block number */
uint8_t *data; /*!< Data pointer to be program/read */
uint32_t addr; /*!< Start address to be program/read */
uint32_t len; /*!< Data length to be program/read */
};
/*@} end of group SFLAH_Public_Types */
/** @defgroup SFLAH_Public_Constants
* @{
*/
/*@} end of group SFLAH_Public_Constants */
/** @defgroup SFLAH_Public_Macros
* @{
*/
#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
#define BFLB_SPIFLASH_CMD_INVALID 0xff
/*@} end of group SFLAH_Public_Macros */
/** @defgroup SFLAH_Public_Functions
* @{
*/
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
#else
void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg);
#endif
int bflb_sflash_set_spi_mode(uint8_t mode);
int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len);
int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len);
int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value,
uint8_t reg_len);
int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value,
uint8_t reg_len);
int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg);
void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num);
int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num);
int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num);
int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr);
void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len);
void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data);
void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr);
void bflb_sflash_powerdown(void);
void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, uint8_t flash_cont_read, uint8_t bank);
void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg);
void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg);
#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
int bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, uint8_t en_32bits_addr);
#endif
int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg);
void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr,
uint32_t len, uint8_t bank);
int bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank);
void bflb_sflash_xip_read_disable(void);
int bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos);
int bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
int bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg);
int bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg);
int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data,
uint32_t len);
int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
/*@} end of group SFLAH_Public_Functions */
/*@} end of group SFLAH */
/*@} end of group BL628_Peripheral_Driver */
#endif /* __BL628_SFLAH_H__ */

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/**
******************************************************************************
* @file bflb_xip_sflash.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bflb_common.h"
#include "bflb_xip_sflash.h"
/** @addtogroup BL628_Peripheral_Driver
* @{
*/
/** @addtogroup XIP_SFLASH
* @{
*/
/** @defgroup XIP_SFLASH_Private_Macros
* @{
*/
/*@} end of group XIP_SFLASH_Private_Macros */
/** @defgroup XIP_SFLASH_Private_Types
* @{
*/
/*@} end of group XIP_SFLASH_Private_Types */
/** @defgroup XIP_SFLASH_Private_Variables
* @{
*/
/*@} end of group XIP_SFLASH_Private_Variables */
/** @defgroup XIP_SFLASH_Global_Variables
* @{
*/
/*@} end of group XIP_SFLASH_Global_Variables */
/** @defgroup XIP_SFLASH_Private_Fun_Declaration
* @{
*/
/*@} end of group XIP_SFLASH_Private_Fun_Declaration */
/** @defgroup XIP_SFLASH_Private_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Save flash controller state
*
* @param p_flash_cfg: Flash config pointer
* @param offset: CPU XIP flash offset pointer
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset,
uint8_t group, uint8_t bank)
{
/* XIP_SFlash_Delay */
volatile uint32_t i = 32 * 2;
while (i--)
;
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
if (bank == SF_CTRL_FLASH_BANK1) {
bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
}
#endif
bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
/* Exit form continous read for accepting command */
bflb_sflash_reset_continue_read(p_flash_cfg);
/* For disable command that is setting register instaed of send command, we need write enable */
bflb_sflash_disable_burst_wrap(p_flash_cfg);
#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
/* Enable 32Bits addr mode again in case reset command make it reset */
bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1);
#endif
if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
/* Enable QE again in case reset command make it reset */
bflb_sflash_qspi_enable(p_flash_cfg);
}
/* Deburst again to make sure */
bflb_sflash_disable_burst_wrap(p_flash_cfg);
/* Clear offset setting*/
*offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
return 0;
}
/****************************************************************************/ /**
* @brief Restore flash controller state
*
* @param p_flash_cfg: Flash config pointer
* @param offset: CPU XIP flash offset
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset,
uint8_t group, uint8_t bank)
{
uint32_t tmp[1];
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
if(((p_flash_cfg->io_mode>>4)&0x01) == 0) {
if((p_flash_cfg->io_mode&0x0f)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0x0f)==SF_CTRL_QIO_MODE) {
bflb_sflash_set_burst_wrap(p_flash_cfg);
}
}
#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1);
#endif
bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
if (bank == SF_CTRL_FLASH_BANK1) {
bflb_sf_ctrl_sbus2_revoke_replace();
}
#endif
return 0;
}
/*@} end of group XIP_SFLASH_Private_Functions */
/** @defgroup XIP_SFLASH_Public_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Erase flash one region
*
* @param p_flash_cfg: Flash config pointer
* @param start_addr: start address to erase
* @param len: data length to erase
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr,
int len, uint8_t group, uint8_t bank)
{
int stat = 0;
uint32_t offset = 0;
uint8_t aes_enable = 0;
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_xip_sflash_opt_enter(&aes_enable);
stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
if (stat != 0) {
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
} else {
stat = bflb_sflash_erase(p_flash_cfg, start_addr, start_addr + len - 1);
bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
}
bflb_xip_sflash_opt_exit(aes_enable);
return stat;
}
/****************************************************************************/ /**
* @brief Program flash one region
*
* @param p_flash_cfg: Flash config pointer
* @param addr: start address to be programed
* @param data: data pointer to be programed
* @param len: data length to be programed
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
uint32_t len, uint8_t group, uint8_t bank)
{
int stat = 0;
uint32_t offset = 0;
uint8_t aes_enable = 0;
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_xip_sflash_opt_enter(&aes_enable);
stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
if (stat != 0) {
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
} else {
stat = bflb_sflash_program(p_flash_cfg, io_mode, addr, data, len);
bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
}
bflb_xip_sflash_opt_exit(aes_enable);
return stat;
}
/****************************************************************************/ /**
* @brief Read data from flash
*
* @param p_flash_cfg: Flash config pointer
* @param addr: flash read start address
* @param data: data pointer to store data read from flash
* @param len: data length to read
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
uint32_t len, uint8_t group, uint8_t bank)
{
int stat = 0;
uint32_t offset = 0;
uint8_t aes_enable = 0;
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_xip_sflash_opt_enter(&aes_enable);
stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
if (stat != 0) {
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
} else {
stat = bflb_sflash_read(p_flash_cfg, io_mode, 0, addr, data, len);
bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
}
bflb_xip_sflash_opt_exit(aes_enable);
return stat;
}
/****************************************************************************/ /**
* @brief Get Flash Jedec ID
*
* @param p_flash_cfg: Flash config pointer
* @param data: data pointer to store Jedec ID Read from flash
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
uint8_t group, uint8_t bank)
{
int stat = 0;
uint32_t offset = 0;
uint8_t aes_enable = 0;
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_xip_sflash_opt_enter(&aes_enable);
stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
if (stat != 0) {
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
} else {
bflb_sflash_get_jedecid(p_flash_cfg, data);
bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
}
bflb_xip_sflash_opt_exit(aes_enable);
return 0;
}
/****************************************************************************/ /**
* @brief Get Flash Device ID
*
* @param p_flash_cfg: Flash config pointer
* @param is_32bits_addr: Is flash addr mode in 32-bits
* @param data: data pointer to store Device ID Read from flash
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
uint8_t *data, uint8_t group, uint8_t bank)
{
int stat = 0;
uint32_t offset = 0;
uint8_t aes_enable = 0;
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_xip_sflash_opt_enter(&aes_enable);
stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
if (stat != 0) {
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
} else {
bflb_sflash_get_deviceid(data, is_32bits_addr);
bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
}
bflb_xip_sflash_opt_exit(aes_enable);
return 0;
}
/****************************************************************************/ /**
* @brief Get Flash Unique ID
*
* @param p_flash_cfg: Flash config pointer
* @param data: data pointer to store Device ID Read from flash
* @param id_len: Unique id len
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
uint8_t id_len, uint8_t group, uint8_t bank)
{
int stat = 0;
uint32_t offset = 0;
uint8_t aes_enable = 0;
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_xip_sflash_opt_enter(&aes_enable);
stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
if (stat != 0) {
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
} else {
bflb_sflash_get_uniqueid(data, id_len);
bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
}
bflb_xip_sflash_opt_exit(aes_enable);
return 0;
}
/****************************************************************************//**
* @brief Clear flash status register need lock
*
* @param p_flash_cfg: Flash config pointer
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg,
uint8_t group, uint8_t bank)
{
int stat = 0;
uint32_t offset = 0;
uint8_t aes_enable = 0;
uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
bflb_xip_sflash_opt_enter(&aes_enable);
stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
if (stat != 0) {
bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
} else {
stat = bflb_sflash_clear_status_register(p_flash_cfg);
bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
}
bflb_xip_sflash_opt_exit(aes_enable);
return 0;
}
/****************************************************************************/ /**
* @brief Read data from flash via XIP
*
* @param addr: flash read start address
* @param data: data pointer to store data read from flash
* @param len: data length to read
* @param group: CPU group id 0 or 1
* @param bank: Flash bank select
*
* @return BFLB_RET:0 means success and other value means error
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len,
uint8_t group, uint8_t bank)
{
uint32_t offset = 0;
addr = addr & (BFLB_FLASH_XIP_END-BFLB_FLASH_XIP_BASE-1);
addr |= BFLB_FLASH_XIP_BASE;
offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
/* Flash read */
arch_memcpy_fast(data, (void *)(uintptr_t)(addr - bflb_sf_ctrl_get_flash_image_offset(group, bank)), len);
bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
return 0;
}
/****************************************************************************/ /**
* @brief XIP SFlash option save
*
* @param aes_enable: AES enable status pointer
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable)
{
*aes_enable = bflb_sf_ctrl_is_aes_enable();
if (*aes_enable) {
bflb_sf_ctrl_aes_disable();
}
}
/****************************************************************************/ /**
* @brief XIP SFlash option restore
*
* @param aes_enable: AES enable status
*
* @return None
*
*******************************************************************************/
__WEAK
void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable)
{
if (aes_enable) {
bflb_sf_ctrl_aes_enable();
}
}
/*@} end of group XIP_SFLASH_Public_Functions */
/*@} end of group XIP_SFLASH */
/*@} end of group BL628_Peripheral_Driver */

54
drivers/soc/bl702/std/include/bl702_xip_sflash.h → drivers/lhal/src/flash/bflb_xip_sflash.h
View File

@ -1,6 +1,6 @@
/**
******************************************************************************
* @file bl702_xip_sflash.h
* @file bflb_xip_sflash.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
@ -33,13 +33,12 @@
*
******************************************************************************
*/
#ifndef __BL702_XIP_SFLASH_H__
#define __BL702_XIP_SFLASH_H__
#ifndef __BL628_XIP_SFLASH_H__
#define __BL628_XIP_SFLASH_H__
#include "bl702_common.h"
#include "bl702_sflash.h"
#include "bflb_sflash.h"
/** @addtogroup BL702_Peripheral_Driver
/** @addtogroup BL628_Peripheral_Driver
* @{
*/
@ -68,28 +67,33 @@
/** @defgroup XIP_SFLASH_Public_Functions
* @{
*/
void XIP_SFlash_Opt_Enter(void);
void XIP_SFlash_Opt_Exit(void);
BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset);
BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset);
BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
uint32_t startaddr, uint32_t endaddr);
BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr,
uint8_t *data, uint32_t len);
BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr,
uint8_t *data, uint32_t len);
BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
uint8_t *data);
BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
uint8_t *data);
BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
uint8_t *data, uint8_t idLen);
BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len);
int bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset,
uint8_t group, uint8_t bank);
int bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset,
uint8_t group, uint8_t bank);
int bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr,
int len, uint8_t group, uint8_t bank);
int bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
uint8_t *data, uint32_t len, uint8_t group, uint8_t bank);
int bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
uint8_t *data, uint32_t len, uint8_t group, uint8_t bank);
int bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
uint8_t group, uint8_t bank);
int bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
uint8_t *data, uint8_t group, uint8_t bank);
int bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
uint8_t idlen, uint8_t group, uint8_t bank);
int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_Flash_Cfg,
uint8_t group, uint8_t bank);
int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len,
uint8_t group, uint8_t bank);
void bflb_xip_sflash_opt_enter(uint8_t *aes_enable);
void bflb_xip_sflash_opt_exit(uint8_t aes_enable);
/*@} end of group XIP_SFLASH_Public_Functions */
/*@} end of group XIP_SFLASH */
/*@} end of group BL702_Peripheral_Driver */
/*@} end of group BL628_Peripheral_Driver */
#endif /* __BL702_XIP_SFLASH_H__ */
#endif /* __BL628_XIP_SFLASH_H__ */

BIN
drivers/lhal/src/pka/libpka.a
View File

Binary file not shown.

7
drivers/soc/bl602/std/CMakeLists.txt
View File

@ -20,16 +20,11 @@ sdk_library_add_sources(src/bl602_l1c.c)
sdk_library_add_sources(src/bl602_pds.c)
sdk_library_add_sources(src/bl602_tzc_sec.c)
sdk_library_add_sources(src/bl602_sf_cfg.c)
sdk_library_add_sources(src/bl602_sf_cfg_ext.c)
sdk_library_add_sources(src/bl602_sf_ctrl.c)
sdk_library_add_sources(src/bl602_sflash.c)
sdk_library_add_sources(src/bl602_sflash_ext.c)
sdk_library_add_sources(src/bl602_xip_sflash.c)
sdk_library_add_sources(src/bl602_xip_sflash_ext.c)
sdk_library_add_sources(src/bl602_sf_cfg_ext.c)
sdk_library_add_sources(port/bl602_clock.c)
sdk_library_add_sources(port/bl602_flash.c)
sdk_add_include_directories(
include

4
drivers/soc/bl602/std/include/bl602_glb.h
View File

@ -41,11 +41,11 @@
#include "bl602_gpio.h"
#include "bl602_l1c.h"
#include "bl602_hbn.h"
#include "bl602_sf_ctrl.h"
#include "bl602_sf_cfg.h"
#include "bl602_aon.h"
#include "bl602_pds.h"
#include "bl602_common.h"
#include "bflb_sf_ctrl.h"
#include "bflb_sf_cfg.h"
/** @addtogroup BL602_Peripheral_Driver
* @{

6
drivers/soc/bl602/std/include/bl602_hbn.h
View File

@ -38,7 +38,7 @@
#include "hbn_reg.h"
#include "bl602_aon.h"
#include "bl602_sflash.h"
#include "bflb_sflash.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
@ -243,7 +243,7 @@ typedef struct
uint32_t sleepTime; /*!< HBN sleep time */
uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */
HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */
spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */
HBN_LEVEL_Type hbnLevel; /*!< HBN level */
HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
} HBN_APP_CFG_Type;
@ -411,7 +411,7 @@ void HBN_OUT1_IRQHandler(void);
#endif
/*----------*/
void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg);
void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg);
void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg);
void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
BL_Err_Type HBN_Reset(void);
BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv);

4
drivers/soc/bl602/std/include/bl602_pds.h
View File

@ -39,8 +39,8 @@
#include "pds_reg.h"
#include "bl602_aon.h"
#include "bl602_hbn.h"
#include "bl602_sflash.h"
#include "bl602_common.h"
#include "bflb_sflash.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
@ -321,7 +321,7 @@ typedef struct
uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
uint8_t flashContRead; /*!< Whether enable flash continue read */
uint32_t sleepTime; /*!< PDS sleep time */
SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */
spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */
PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */
void (*preCbFun)(void); /*!< Pre callback function */
void (*postCbFun)(void); /*!< Post callback function */

114
drivers/soc/bl602/std/include/bl602_romdriver.h
View File

@ -40,11 +40,11 @@
#include "bl602_aon.h"
#include "bl602_glb.h"
#include "bl602_hbn.h"
#include "bl602_xip_sflash.h"
#include "bl602_sflash.h"
#include "bl602_sf_ctrl.h"
#include "bl602_ef_ctrl.h"
// #include "bl602_sec_eng.h"
#include "bflb_xip_sflash.h"
#include "bflb_sflash.h"
#include "bflb_sf_ctrl.h"
// #include "softcrc.h"
/** @addtogroup BL602_Peripheral_Driver
@ -446,7 +446,7 @@ typedef enum {
((void (*)(HBN_APP_CFG_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter])
#define RomDriver_HBN_Power_Down_Flash \
((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
#define RomDriver_HBN_Enable \
((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])
@ -554,52 +554,52 @@ typedef enum {
((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring])
#define RomDriver_SFlash_Init \
((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
((void (*)(const struct sf_ctrl_cfg_type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
#define RomDriver_SFlash_SetSPIMode \
((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
((int(*)(uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
#define RomDriver_SFlash_Read_Reg \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
#define RomDriver_SFlash_Write_Reg \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
#define RomDriver_SFlash_Busy \
((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
#define RomDriver_SFlash_Write_Enable \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
#define RomDriver_SFlash_Qspi_Enable \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
#define RomDriver_SFlash_Volatile_Reg_Write_Enable \
((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
#define RomDriver_SFlash_Chip_Erase \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
#define RomDriver_SFlash_Sector_Erase \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
((int(*)(spi_flash_cfg_type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
#define RomDriver_SFlash_Blk32_Erase \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
#define RomDriver_SFlash_Blk64_Erase \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
#define RomDriver_SFlash_Erase \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
((int(*)(spi_flash_cfg_type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
#define RomDriver_SFlash_Program \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
#define RomDriver_SFlash_GetUniqueId \
((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
#define RomDriver_SFlash_GetJedecId \
((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
((void (*)(spi_flash_cfg_type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
#define RomDriver_SFlash_GetDeviceId \
((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
@ -608,34 +608,34 @@ typedef enum {
((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
#define RomDriver_SFlash_Releae_Powerdown \
((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown])
((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown])
#define RomDriver_SFlash_SetBurstWrap \
((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
#define RomDriver_SFlash_DisableBurstWrap \
((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
#define RomDriver_SFlash_Software_Reset \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
#define RomDriver_SFlash_Reset_Continue_Read \
((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
#define RomDriver_SFlash_Set_IDbus_Cfg \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
#define RomDriver_SFlash_IDbus_Read_Enable \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
#define RomDriver_SFlash_Cache_Enable_Set \
((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set])
((int(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set])
#define RomDriver_SFlash_Cache_Flush \
((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush])
((int(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush])
#define RomDriver_SFlash_Cache_Read_Enable \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable])
#define RomDriver_SFlash_Cache_Hit_Count_Get \
((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get])
@ -647,46 +647,46 @@ typedef enum {
((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable])
#define RomDriver_SFlash_Read \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
#define RomDriver_SFlash_Read_Reg_With_Cmd \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
#define RomDriver_SFlash_Write_Reg_With_Cmd \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
((int(*)(spi_flash_cfg_type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
#define RomDriver_SFlash_Restore_From_Powerdown \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \
((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \
((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio])
#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \
((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
#define RomDriver_SF_Cfg_Restore_GPIO17_Fun \
((void (*)(uint8_t fun))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun])
#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \
((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
((int(*)(uint32_t flashID, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
#define RomDriver_SF_Cfg_Init_Flash_Gpio \
((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
((int (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
#define RomDriver_SF_Cfg_Flash_Identify \
((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
#define RomDriver_SF_Ctrl_Enable \
((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
((void (*)(const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
#define RomDriver_SF_Ctrl_Select_Pad \
((void (*)(SF_Ctrl_Pad_Sel sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
((void (*)(uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
#define RomDriver_SF_Ctrl_Set_Owner \
((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
((void (*)(uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
#define RomDriver_SF_Ctrl_Disable \
((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
@ -701,10 +701,10 @@ typedef enum {
((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
#define RomDriver_SF_Ctrl_AES_Set_Key \
((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
#define RomDriver_SF_Ctrl_AES_Set_Key_BE \
((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
#define RomDriver_SF_Ctrl_AES_Set_IV \
((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV])
@ -725,19 +725,19 @@ typedef enum {
((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
#define RomDriver_SF_Ctrl_Select_Clock \
((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock])
((void (*)(uint8_t sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock])
#define RomDriver_SF_Ctrl_SendCmd \
((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
((void (*)(struct sf_ctrl_cmd_cfg_type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
#define RomDriver_SF_Ctrl_Icache_Set \
((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set])
((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set])
#define RomDriver_SF_Ctrl_Icache2_Set \
((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set])
((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set])
#define RomDriver_SF_Ctrl_GetBusyState \
((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
((int(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
#define RomDriver_SF_Ctrl_Is_AES_Enable \
((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
@ -749,31 +749,31 @@ typedef enum {
((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
#define RomDriver_XIP_SFlash_State_Save \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
#define RomDriver_XIP_SFlash_State_Restore \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
#define RomDriver_XIP_SFlash_Erase_Need_Lock \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
#define RomDriver_XIP_SFlash_Write_Need_Lock \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Need_Lock \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \
((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \
((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
((int(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
#define RomDriver_XIP_SFlash_Opt_Enter \
((void (*)(uint8_t * aesEnable)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter])

112
drivers/soc/bl602/std/include/bl602_sf_cfg.h
View File

@ -1,112 +0,0 @@
/**
******************************************************************************
* @file bl602_sf_cfg.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SF_CFG_H__
#define __BL602_SF_CFG_H__
#include "string.h"
#include "bl602_sflash.h"
#include "bl602_sf_ctrl.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CFG
* @{
*/
/** @defgroup SF_CFG_Public_Types
* @{
*/
/*@} end of group SF_CFG_Public_Types */
/** @defgroup SF_CFG_Public_Constants
* @{
*/
/*@} end of group SF_CFG_Public_Constants */
/** @defgroup SF_CFG_Public_Macros
* @{
*/
/*Flash option 0*/
/*Flash CLK*/
#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_22
/*FLASH CS*/
#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_21
/*FLASH DATA*/
#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_20
#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_19
#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_18
#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_17
/*Flash option 1*/
/*Flash CLK*/
#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_22
/*FLASH CS*/
#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_21
/*FLASH DATA*/
#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_20
#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_0
#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_1
#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_2
#define BFLB_FLASH_CFG_DESWAP 1
#define BFLB_FLASH_CFG_EXT0_17_22 2
#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3
#define BFLB_FLASH_ID_VALID_FLAG 0x80000000
#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF
/*@} end of group SF_CFG_Public_Macros */
/** @defgroup SF_CFG_Public_Functions
* @{
*/
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault);
void SF_Cfg_Restore_GPIO17_Fun(uint8_t fun);
uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault,
SPI_Flash_Cfg_Type *pFlashCfg);
void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin);
void SF_Cfg_Init_Internal_Flash_Gpio(void);
void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin);
/*@} end of group SF_CFG_Public_Functions */
/*@} end of group SF_CFG */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SF_CFG_H__ */

11
drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h
View File

@ -37,8 +37,8 @@
#define __BL602_SF_CFG_EXT_H__
#include "string.h"
#include "bl602_sflash.h"
#include "bl602_sf_ctrl.h"
#include "bflb_sflash.h"
#include "bflb_sf_ctrl.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
@ -69,9 +69,10 @@
/** @defgroup SF_CFG_EXT_Public_Functions
* @{
*/
BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg,
uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg);
int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
uint8_t group, uint8_t bank);
uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
/*@} end of group SF_CFG_EXT_Public_Functions */

327
drivers/soc/bl602/std/include/bl602_sf_ctrl.h
View File

@ -1,327 +0,0 @@
/**
******************************************************************************
* @file bl602_sf_ctrl.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SF_CTRL_H__
#define __BL602_SF_CTRL_H__
#include "sf_ctrl_reg.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SF_CTRL
* @{
*/
/** @defgroup SF_CTRL_Public_Types
* @{
*/
/**
* @brief Serial flash pad select type definition
*/
typedef enum {
SF_CTRL_EMBEDDED_SEL, /*!< Embedded flash select */
SF_CTRL_EXTERNAL_17TO22_SEL, /*!< External flash select gpio 17-22 */
SF_CTRL_EXTERNAL_0TO2_20TO22_SEL, /*!< External flash select gpio 0-2 and 20-22 */
} SF_Ctrl_Pad_Sel;
/**
* @brief Serial flash controller owner type definition
*/
typedef enum {
SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */
SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */
} SF_Ctrl_Owner_Type;
/**
* @brief Serial flash controller select clock type definition
*/
typedef enum {
SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */
SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */
} SF_Ctrl_Sahb_Type;
/**
* @brief Serial flash controller owner type definition
*/
typedef enum {
HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */
REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */
} SF_Ctrl_Ahb2sif_Type;
/**
* @brief Read and write type definition
*/
typedef enum {
SF_CTRL_READ, /*!< Serail flash read command flag */
SF_CTRL_WRITE, /*!< Serail flash write command flag */
} SF_Ctrl_RW_Type;
/**
* @brief Serail flash interface IO type definition
*/
typedef enum {
SF_CTRL_NIO_MODE, /*!< Normal IO mode define */
SF_CTRL_DO_MODE, /*!< Dual Output mode define */
SF_CTRL_QO_MODE, /*!< Quad Output mode define */
SF_CTRL_DIO_MODE, /*!< Dual IO mode define */
SF_CTRL_QIO_MODE, /*!< Quad IO mode define */
} SF_Ctrl_IO_Type;
/**
* @brief Serail flash controller interface mode type definition
*/
typedef enum {
SF_CTRL_SPI_MODE, /*!< SPI mode define */
SF_CTRL_QPI_MODE, /*!< QPI mode define */
} SF_Ctrl_Mode_Type;
/**
* @brief Serail flash controller command mode type definition
*/
typedef enum {
SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */
SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */
} SF_Ctrl_Cmd_Mode_Type;
/**
* @brief Serail flash controller address mode type definition
*/
typedef enum {
SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */
SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */
SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */
} SF_Ctrl_Addr_Mode_Type;
/**
* @brief Serail flash controller dummy mode type definition
*/
typedef enum {
SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */
SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */
SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */
} SF_Ctrl_Dmy_Mode_Type;
/**
* @brief Serail flash controller data mode type definition
*/
typedef enum {
SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */
SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */
SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */
} SF_Ctrl_Data_Mode_Type;
/**
* @brief Serail flash controller AES type definition
*/
typedef enum {
SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */
SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */
SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */
SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */
} SF_Ctrl_AES_Key_Type;
/**
* @brief Serail flash controller configuration structure type definition
*/
typedef struct
{
SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */
SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */
SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */
uint8_t clkDelay; /*!< Clock count for read due to pad delay */
uint8_t clkInvert; /*!< Clock invert */
uint8_t rxClkInvert; /*!< RX clock invert */
uint8_t doDelay; /*!< Data out delay */
uint8_t diDelay; /*!< Data in delay */
uint8_t oeDelay; /*!< Output enable delay */
} SF_Ctrl_Cfg_Type;
/**
* @brief Serail flash command configuration structure type definition
*/
typedef struct
{
uint8_t rwFlag; /*!< Read write flag */
SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */
SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */
uint8_t addrSize; /*!< Address size */
uint8_t dummyClks; /*!< Dummy clocks */
SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */
SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */
uint8_t rsv[1]; /*!< */
uint32_t nbData; /*!< Transfer number of bytes */
uint32_t cmdBuf[2]; /*!< Command buffer */
} SF_Ctrl_Cmd_Cfg_Type;
/*@} end of group SF_CTRL_Public_Types */
/** @defgroup SF_CTRL_Public_Constants
* @{
*/
/** @defgroup SF_CTRL_PAD_SEL
* @{
*/
#define IS_SF_CTRL_PAD_SEL(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \
((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \
((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL))
/** @defgroup SF_CTRL_OWNER_TYPE
* @{
*/
#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \
((type) == SF_CTRL_OWNER_IAHB))
/** @defgroup SF_CTRL_SAHB_TYPE
* @{
*/
#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \
((type) == SF_CTRL_FLASH_CLOCK))
/** @defgroup SF_CTRL_AHB2SIF_TYPE
* @{
*/
#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \
((type) == REMOVE_CLOCK_CONSTRAIN))
/** @defgroup SF_CTRL_RW_TYPE
* @{
*/
#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \
((type) == SF_CTRL_WRITE))
/** @defgroup SF_CTRL_IO_TYPE
* @{
*/
#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \
((type) == SF_CTRL_DO_MODE) || \
((type) == SF_CTRL_QO_MODE) || \
((type) == SF_CTRL_DIO_MODE) || \
((type) == SF_CTRL_QIO_MODE))
/** @defgroup SF_CTRL_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \
((type) == SF_CTRL_QPI_MODE))
/** @defgroup SF_CTRL_CMD_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \
((type) == SF_CTRL_CMD_4_LINES))
/** @defgroup SF_CTRL_ADDR_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \
((type) == SF_CTRL_ADDR_2_LINES) || \
((type) == SF_CTRL_ADDR_4_LINES))
/** @defgroup SF_CTRL_DMY_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \
((type) == SF_CTRL_DUMMY_2_LINES) || \
((type) == SF_CTRL_DUMMY_4_LINES))
/** @defgroup SF_CTRL_DATA_MODE_TYPE
* @{
*/
#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \
((type) == SF_CTRL_DATA_2_LINES) || \
((type) == SF_CTRL_DATA_4_LINES))
/** @defgroup SF_CTRL_AES_KEY_TYPE
* @{
*/
#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \
((type) == SF_CTRL_AES_256BITS) || \
((type) == SF_CTRL_AES_192BITS) || \
((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY))
/*@} end of group SF_CTRL_Public_Constants */
/** @defgroup SF_CTRL_Public_Macros
* @{
*/
#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF
#define FLASH_CTRL_BUF_SIZE 256
/*@} end of group SF_CTRL_Public_Macros */
/** @defgroup SF_CTRL_Public_Functions
* @{
*/
#ifndef BFLB_USE_HAL_DRIVER
void SF_Ctrl_IRQHandler(void);
#endif
void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg);
void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner);
void SF_Ctrl_Disable(void);
void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel);
void SF_Ctrl_AES_Enable_BE(void);
void SF_Ctrl_AES_Enable_LE(void);
void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr,
uint32_t endAddr,
uint8_t locked);
void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType);
void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset);
void SF_Ctrl_AES_Enable(void);
void SF_Ctrl_AES_Disable(void);
void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset);
uint32_t SF_Ctrl_Get_Flash_Image_Offset(void);
void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType);
void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg);
void SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
void SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid);
BL_Sts_Type SF_Ctrl_GetBusyState(void);
uint8_t SF_Ctrl_Is_AES_Enable(void);
uint8_t SF_Ctrl_Get_Clock_Delay(void);
void SF_Ctrl_Set_Clock_Delay(uint8_t delay);
/*@} end of group SF_CTRL_Public_Functions */
/*@} end of group SF_CTRL */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SF_CTRL_H__ */

199
drivers/soc/bl602/std/include/bl602_sflash.h
View File

@ -1,199 +0,0 @@
/**
******************************************************************************
* @file bl602_sflah.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_SFLAH_H__
#define __BL602_SFLAH_H__
#include "bl602_common.h"
#include "bl602_sf_ctrl.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup SFLAH
* @{
*/
/** @defgroup SFLAH_Public_Types
* @{
*/
/**
* @brief Serial flash configuration structure type definition
*/
typedef struct
{
uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
uint8_t resetEnCmd; /*!< Flash enable reset command */
uint8_t resetCmd; /*!< Flash reset command */
uint8_t resetCreadCmd; /*!< Flash reset continuous read command */
uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */
uint8_t jedecIdCmd; /*!< JEDEC ID command */
uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */
uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */
uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */
uint8_t sectorSize; /*!< *1024bytes */
uint8_t mid; /*!< Manufacturer ID */
uint16_t pageSize; /*!< Page size */
uint8_t chipEraseCmd; /*!< Chip erase cmd */
uint8_t sectorEraseCmd; /*!< Sector erase command */
uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */
uint8_t blk64EraseCmd; /*!< Block 64K erase command */
uint8_t writeEnableCmd; /*!< Need before every erase or program */
uint8_t pageProgramCmd; /*!< Page program cmd */
uint8_t qpageProgramCmd; /*!< QIO page program cmd */
uint8_t qppAddrMode; /*!< QIO page program address mode */
uint8_t fastReadCmd; /*!< Fast read command */
uint8_t frDmyClk; /*!< Fast read command dummy clock */
uint8_t qpiFastReadCmd; /*!< QPI fast read command */
uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */
uint8_t fastReadDoCmd; /*!< Fast read dual output command */
uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */
uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */
uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */
uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */
uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */
uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */
uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */
uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */
uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */
uint8_t qpiPageProgramCmd; /*!< QPI program command */
uint8_t writeVregEnableCmd; /*!< Enable write reg */
uint8_t wrEnableIndex; /*!< Write enable register index */
uint8_t qeIndex; /*!< Quad mode enable register index */
uint8_t busyIndex; /*!< Busy status register index */
uint8_t wrEnableBit; /*!< Write enable bit pos */
uint8_t qeBit; /*!< Quad enable bit pos */
uint8_t busyBit; /*!< Busy status bit pos */
uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */
uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */
uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */
uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */
uint8_t releasePowerDown; /*!< Release power down command */
uint8_t busyReadRegLen; /*!< Register length of contain busy status */
uint8_t readRegCmd[4]; /*!< Read register command buffer */
uint8_t writeRegCmd[4]; /*!< Write register command buffer */
uint8_t enterQpi; /*!< Enter qpi command */
uint8_t exitQpi; /*!< Exit qpi command */
uint8_t cReadMode; /*!< Config data for continuous read mode */
uint8_t cRExit; /*!< Config data for exit continuous read mode */
uint8_t burstWrapCmd; /*!< Enable burst wrap command */
uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */
uint8_t burstWrapDataMode; /*!< Data and address mode for this command */
uint8_t burstWrapData; /*!< Data to enable burst wrap */
uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */
uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */
uint8_t deBurstWrapData; /*!< Data to disable burst wrap */
uint16_t timeEsector; /*!< 4K erase time */
uint16_t timeE32k; /*!< 32K erase time */
uint16_t timeE64k; /*!< 64K erase time */
uint16_t timePagePgm; /*!< Page program time */
uint16_t timeCe; /*!< Chip erase time in ms */
uint8_t pdDelay; /*!< Release power down command delay time for wake up */
uint8_t qeData; /*!< QE set data */
} __attribute__((packed)) SPI_Flash_Cfg_Type;
/*@} end of group SFLAH_Public_Types */
/** @defgroup SFLAH_Public_Constants
* @{
*/
/*@} end of group SFLAH_Public_Constants */
/** @defgroup SFLAH_Public_Macros
* @{
*/
#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
#define BFLB_SPIFLASH_CMD_INVALID 0xff
/*@} end of group SFLAH_Public_Macros */
/** @defgroup SFLAH_Public_Functions
* @{
*/
void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg);
BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode);
BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum);
BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr);
BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen);
void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data);
void SFlash_GetDeviceId(uint8_t *data);
void SFlash_Powerdown(void);
void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg);
void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg);
BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr,
uint32_t len);
BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead);
BL_Err_Type SFlash_Cache_Enable_Set(uint8_t wayDisable);
BL_Err_Type SFlash_Cache_Flush(void);
BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead,
uint8_t wayDisable);
void SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh);
uint32_t SFlash_Cache_Miss_Count_Get(void);
void SFlash_Cache_Read_Disable(void);
BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data,
uint32_t len);
BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
uint8_t regLen);
BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
uint8_t regLen);
/*@} end of group SFLAH_Public_Functions */
/*@} end of group SFLAH */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_SFLAH_H__ */

34
drivers/soc/bl602/std/include/bl602_sflash_ext.h
View File

@ -36,7 +36,7 @@
#ifndef __BL602_SFLAH_EXT_H__
#define __BL602_SFLAH_EXT_H__
#include "bl602_sflash.h"
#include "bflb_sflash.h"
#include "bl602_common.h"
/** @addtogroup BL602_Peripheral_Driver
@ -51,22 +51,6 @@
* @{
*/
/**
* @brief Serial flash security register configuration
*/
typedef struct
{
uint8_t eraseCmd; /*!< Erase security register command */
uint8_t programCmd; /*!< Program security register command */
uint8_t readCmd; /*!< Read security register command */
uint8_t enterSecOptCmd; /*!< Enter security register option mode command */
uint8_t exitSecOptCmd; /*!< Exit security register option mode command */
uint8_t blockNum; /*!< Security register block number */
uint8_t *data; /*!< Data pointer to be program/read */
uint32_t addr; /*!< Start address to be program/read */
uint32_t len; /*!< Data length to be program/read */
} SFlash_Sec_Reg_Cfg;
/*@} end of group SFLAH_EXT_Public_Types */
/** @defgroup SFLAH_EXT_Public_Constants
@ -84,13 +68,15 @@ typedef struct
/** @defgroup SFLAH_EXT_Public_Functions
* @{
*/
BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead);
BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos);
BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg,
SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg);
BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg);
int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flash_cont_read, uint8_t bank);
int bflb_sflash_rcv_enable(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos);
int bflb_sflash_erase_security_register(spi_flash_cfg_type *p_flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
int bflb_sflash_program_security_register(spi_flash_cfg_type *p_flash_cfg,
struct sflash_sec_reg_cfg *p_sec_reg_cfg);
int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg);
int bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg);
int bflb_sflash_cache_enable_set(uint8_t way_disable);
int bflb_sflash_cache_flush(void);
/*@} end of group SFLAH_EXT_Public_Functions */

90
drivers/soc/bl602/std/include/bl602_xip_sflash.h
View File

@ -1,90 +0,0 @@
/**
******************************************************************************
* @file bl602_xip_sflash.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL602_XIP_SFLASH_H__
#define __BL602_XIP_SFLASH_H__
#include "bl602_common.h"
#include "bl602_sflash.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
*/
/** @addtogroup XIP_SFLASH
* @{
*/
/** @defgroup XIP_SFLASH_Public_Types
* @{
*/
/*@} end of group XIP_SFLASH_Public_Types */
/** @defgroup XIP_SFLASH_Public_Constants
* @{
*/
/*@} end of group XIP_SFLASH_Public_Constants */
/** @defgroup XIP_SFLASH_Public_Macros
* @{
*/
/*@} end of group XIP_SFLASH_Public_Macros */
/** @defgroup XIP_SFLASH_Public_Functions
* @{
*/
BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset);
BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset);
BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr);
BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data,
uint32_t len);
BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data);
BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data);
BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen);
BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len);
void XIP_SFlash_Opt_Enter(uint8_t *aesEnable);
void XIP_SFlash_Opt_Exit(uint8_t aesEnable);
/*@} end of group XIP_SFLASH_Public_Functions */
/*@} end of group XIP_SFLASH */
/*@} end of group BL602_Peripheral_Driver */
#endif /* __BL602_XIP_SFLASH_H__ */

36
drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h
View File

@ -37,9 +37,9 @@
#define __BL602_XIP_SFLASH_EXT_H__
#include "bl602_common.h"
#include "bl602_sflash.h"
#include "bl602_sflash_ext.h"
#include "bl602_xip_sflash.h"
#include "bflb_sflash.h"
#include "bflb_xip_sflash.h"
/** @addtogroup BL602_Peripheral_Driver
* @{
@ -70,21 +70,23 @@
/** @defgroup XIP_SFLASH_EXT_Public_Functions
* @{
*/
BL_Err_Type XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset);
BL_Err_Type XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr,
uint32_t endaddr);
BL_Err_Type XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data,
uint32_t len);
BL_Err_Type XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data,
uint32_t len);
BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg);
BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data);
BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data);
BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data,
uint8_t idLen);
BL_Err_Type XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd,
uint8_t bitPos);
BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg);
int bflb_xip_sflash_state_restore_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank);
int bflb_xip_sflash_erase_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr,
uint32_t endaddr, uint8_t group, uint8_t bank);
int bflb_xip_sflash_write_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
uint32_t len, uint8_t group, uint8_t bank);
int bflb_xip_sflash_read_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
uint32_t len, uint8_t group, uint8_t bank);
int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
int bflb_xip_sflash_get_jedecid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
uint8_t group, uint8_t bank);
int bflb_xip_sflash_get_deviceid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
uint8_t *data, uint8_t group, uint8_t bank);
int bflb_xip_sflash_get_uniqueid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint8_t *data,
uint8_t idLen, uint8_t group, uint8_t bank);
int bflb_xip_sflash_rcv_enable_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t rCmd, uint8_t wCmd,
uint8_t bitPos, uint8_t group, uint8_t bank);
int bflb_xip_sflash_init(spi_flash_cfg_type *p_flash_cfg);
/*@} end of group XIP_SFLASH_EXT_Public_Functions */

762
drivers/soc/bl602/std/include/hardware/ef_data_0_reg.h
View File

@ -1,762 +0,0 @@
/**
******************************************************************************
* @file ef_data_0_reg.h
* @version V1.2
* @date 2019-11-22
* @brief This file is the description of.IP register
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __EF_DATA_0_REG_H__
#define __EF_DATA_0_REG_H__
#include "bl602.h"
/* 0x0 : ef_cfg_0 */
#define EF_DATA_0_EF_CFG_0_OFFSET (0x0)
#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE
#define EF_DATA_0_EF_SF_AES_MODE_POS (0U)
#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U)
#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)
#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS))
#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)
#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS))
#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN
#define EF_DATA_0_EF_SBOOT_EN_POS (4U)
#define EF_DATA_0_EF_SBOOT_EN_LEN (2U)
#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)
#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS))
#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN
#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U)
#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U)
#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)
#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS))
#define EF_DATA_0_EF_TRIM_EN EF_DATA_0_EF_TRIM_EN
#define EF_DATA_0_EF_TRIM_EN_POS (12U)
#define EF_DATA_0_EF_TRIM_EN_LEN (1U)
#define EF_DATA_0_EF_TRIM_EN_MSK (((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS)
#define EF_DATA_0_EF_TRIM_EN_UMSK (~(((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS))
#define EF_DATA_0_EF_NO_HD_BOOT_EN EF_DATA_0_EF_NO_HD_BOOT_EN
#define EF_DATA_0_EF_NO_HD_BOOT_EN_POS (13U)
#define EF_DATA_0_EF_NO_HD_BOOT_EN_LEN (1U)
#define EF_DATA_0_EF_NO_HD_BOOT_EN_MSK (((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS)
#define EF_DATA_0_EF_NO_HD_BOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS))
#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN
#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U)
#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)
#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS))
#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)
#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS))
#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE
#define EF_DATA_0_EF_DBG_MODE_POS (28U)
#define EF_DATA_0_EF_DBG_MODE_LEN (4U)
#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)
#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS))
/* 0x4 : ef_dbg_pwd_low */
#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4)
#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW
#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)
#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS))
/* 0x8 : ef_dbg_pwd_high */
#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8)
#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH
#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U)
#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)
#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS))
/* 0xC : ef_ana_trim_0 */
#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC)
#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0
#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U)
#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U)
#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)
#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS))
/* 0x10 : ef_sw_usage_0 */
#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10)
#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0
#define EF_DATA_0_EF_SW_USAGE_0_POS (0U)
#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U)
#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)
#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS))
/* 0x14 : ef_wifi_mac_low */
#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14)
#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW
#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)
#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS))
/* 0x18 : ef_wifi_mac_high */
#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18)
#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH
#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)
#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS))
/* 0x1C : ef_key_slot_0_w0 */
#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0
#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS))
/* 0x20 : ef_key_slot_0_w1 */
#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20)
#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1
#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS))
/* 0x24 : ef_key_slot_0_w2 */
#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24)
#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2
#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS))
/* 0x28 : ef_key_slot_0_w3 */
#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28)
#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3
#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS))
/* 0x2C : ef_key_slot_1_w0 */
#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0
#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS))
/* 0x30 : ef_key_slot_1_w1 */
#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30)
#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1
#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS))
/* 0x34 : ef_key_slot_1_w2 */
#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34)
#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2
#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS))
/* 0x38 : ef_key_slot_1_w3 */
#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38)
#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3
#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS))
/* 0x3C : ef_key_slot_2_w0 */
#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0
#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS))
/* 0x40 : ef_key_slot_2_w1 */
#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40)
#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1
#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS))
/* 0x44 : ef_key_slot_2_w2 */
#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44)
#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2
#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS))
/* 0x48 : ef_key_slot_2_w3 */
#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48)
#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3
#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS))
/* 0x4C : ef_key_slot_3_w0 */
#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0
#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS))
/* 0x50 : ef_key_slot_3_w1 */
#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50)
#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1
#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS))
/* 0x54 : ef_key_slot_3_w2 */
#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54)
#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2
#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS))
/* 0x58 : ef_key_slot_3_w3 */
#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58)
#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3
#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS))
/* 0x5C : ef_key_slot_4_w0 */
#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0
#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS))
/* 0x60 : ef_key_slot_4_w1 */
#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60)
#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1
#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS))
/* 0x64 : ef_key_slot_4_w2 */
#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64)
#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2
#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS))
/* 0x68 : ef_key_slot_4_w3 */
#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68)
#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3
#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS))
/* 0x6C : ef_key_slot_5_w0 */
#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0
#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS))
/* 0x70 : ef_key_slot_5_w1 */
#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70)
#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1
#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS))
/* 0x74 : ef_key_slot_5_w2 */
#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74)
#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2
#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS))
/* 0x78 : ef_key_slot_5_w3 */
#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78)
#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3
#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)
#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS))
/* 0x7C : ef_data_0_lock */
#define EF_DATA_0_LOCK_OFFSET (0x7C)
#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1
#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U)
#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U)
#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)
#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS))
#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE
#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)
#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS))
#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD
#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)
#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS))
#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)
#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS))
#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC
#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)
#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS))
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)
#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS))
#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD
#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U)
#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)
#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS))
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)
#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS))
struct ef_data_0_reg {
/* 0x0 : ef_cfg_0 */
union {
struct
{
uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */
uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */
uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */
uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */
uint32_t ef_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */
uint32_t rsvd0 : 1; /* [ 14], r/w, 0x0 */
uint32_t rsvd1 : 1; /* [ 15], r/w, 0x0 */
uint32_t rsvd2 : 1; /* [ 16], r/w, 0x0 */
uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */
uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */
uint32_t rsvd3 : 1; /* [ 19], r/w, 0x0 */
uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */
uint32_t rsvd4 : 1; /* [ 21], r/w, 0x0 */
uint32_t rsvd5 : 1; /* [ 22], r/w, 0x0 */
uint32_t rsvd6 : 1; /* [ 23], r/w, 0x0 */
uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */
uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */
uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_cfg_0;
/* 0x4 : ef_dbg_pwd_low */
union {
struct
{
uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_low;
/* 0x8 : ef_dbg_pwd_high */
union {
struct
{
uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_dbg_pwd_high;
/* 0xC : ef_ana_trim_0 */
union {
struct
{
uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_ana_trim_0;
/* 0x10 : ef_sw_usage_0 */
union {
struct
{
uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_sw_usage_0;
/* 0x14 : ef_wifi_mac_low */
union {
struct
{
uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_low;
/* 0x18 : ef_wifi_mac_high */
union {
struct
{
uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_wifi_mac_high;
/* 0x1C : ef_key_slot_0_w0 */
union {
struct
{
uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w0;
/* 0x20 : ef_key_slot_0_w1 */
union {
struct
{
uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w1;
/* 0x24 : ef_key_slot_0_w2 */
union {
struct
{
uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w2;
/* 0x28 : ef_key_slot_0_w3 */
union {
struct
{
uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_0_w3;
/* 0x2C : ef_key_slot_1_w0 */
union {
struct
{
uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w0;
/* 0x30 : ef_key_slot_1_w1 */
union {
struct
{
uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w1;
/* 0x34 : ef_key_slot_1_w2 */
union {
struct
{
uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w2;
/* 0x38 : ef_key_slot_1_w3 */
union {
struct
{
uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_1_w3;
/* 0x3C : ef_key_slot_2_w0 */
union {
struct
{
uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w0;
/* 0x40 : ef_key_slot_2_w1 */
union {
struct
{
uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w1;
/* 0x44 : ef_key_slot_2_w2 */
union {
struct
{
uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w2;
/* 0x48 : ef_key_slot_2_w3 */
union {
struct
{
uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_2_w3;
/* 0x4C : ef_key_slot_3_w0 */
union {
struct
{
uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w0;
/* 0x50 : ef_key_slot_3_w1 */
union {
struct
{
uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w1;
/* 0x54 : ef_key_slot_3_w2 */
union {
struct
{
uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w2;
/* 0x58 : ef_key_slot_3_w3 */
union {
struct
{
uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_3_w3;
/* 0x5C : ef_key_slot_4_w0 */
union {
struct
{
uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w0;
/* 0x60 : ef_key_slot_4_w1 */
union {
struct
{
uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w1;
/* 0x64 : ef_key_slot_4_w2 */
union {
struct
{
uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w2;
/* 0x68 : ef_key_slot_4_w3 */
union {
struct
{
uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_4_w3;
/* 0x6C : ef_key_slot_5_w0 */
union {
struct
{
uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w0;
/* 0x70 : ef_key_slot_5_w1 */
union {
struct
{
uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w1;
/* 0x74 : ef_key_slot_5_w2 */
union {
struct
{
uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w2;
/* 0x78 : ef_key_slot_5_w3 */
union {
struct
{
uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_key_slot_5_w3;
/* 0x7C : ef_data_0_lock */
union {
struct
{
uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */
uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */
uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */
uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */
uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */
uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */
uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */
uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */
uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */
uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */
uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */
uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */
uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */
uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */
uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */
uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */
uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */
uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */
} BF;
uint32_t WORD;
} ef_data_0_lock;
};
typedef volatile struct ef_data_0_reg ef_data_0_reg_t;
#endif /* __EF_DATA_0_REG_H__ */

254
drivers/soc/bl602/std/port/bl602_flash.c
View File

@ -1,254 +0,0 @@
#include "bl602_glb.h"
#include "bl602_xip_sflash.h"
#include "bl602_xip_sflash_ext.h"
#include "bl602_sf_cfg.h"
#include "bl602_sf_cfg_ext.h"
#include "bflb_flash.h"
static uint32_t g_jedec_id = 0;
static SPI_Flash_Cfg_Type g_flash_cfg;
void ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg)
{
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
SFlash_Qspi_Enable(p_flash_cfg);
}
}
void ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg)
{
if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) {
L1C_Set_Wrap(DISABLE);
} else {
L1C_Set_Wrap(ENABLE);
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
SFlash_SetBurstWrap(p_flash_cfg);
}
}
}
/**
* @brief flash_config_init
*
* @return int
*/
static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id)
{
int ret = -1;
uint8_t isAesEnable = 0;
uint32_t jid = 0;
uint32_t offset = 0;
uintptr_t flag;
flag = bflb_irq_save();
XIP_SFlash_Opt_Enter(&isAesEnable);
XIP_SFlash_State_Save(p_flash_cfg, &offset);
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
jid &= 0xFFFFFF;
g_jedec_id = jid;
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
if (ret == 0) {
p_flash_cfg->mid = (jid & 0xff);
}
/* Set flash controler from p_flash_cfg */
flash_set_qspi_enable(p_flash_cfg);
flash_set_l1c_wrap(p_flash_cfg);
XIP_SFlash_State_Restore_Ext(p_flash_cfg, offset);
XIP_SFlash_Opt_Exit(isAesEnable);
bflb_irq_restore(flag);
return ret;
}
/**
* @brief multi flash adapter
*
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_init(void)
{
int ret = -1;
uint8_t clkDelay = 1;
uint8_t clkInvert = 1;
uint32_t jedec_id = 0;
uintptr_t flag;
flag = bflb_irq_save();
SFlash_Cache_Flush();
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
SFlash_Cache_Flush();
bflb_irq_restore(flag);
if (g_flash_cfg.mid != 0xff) {
return 0;
}
clkDelay = g_flash_cfg.clkDelay;
clkInvert = g_flash_cfg.clkInvert;
g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f;
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
g_flash_cfg.clkDelay = clkDelay;
g_flash_cfg.clkInvert = clkInvert;
return ret;
}
uint32_t bflb_flash_get_jedec_id(void)
{
uint32_t jid = 0;
jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
return jid;
}
void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
{
*cfg_addr = (uint8_t *)&g_flash_cfg;
*len = sizeof(SPI_Flash_Cfg_Type);
}
void bflb_flash_set_iomode(uint8_t iomode)
{
g_flash_cfg.ioMode &= ~0x1f;
if (iomode == 4) {
g_flash_cfg.ioMode |= iomode;
} else {
g_flash_cfg.ioMode |= 0x10;
g_flash_cfg.ioMode |= iomode;
}
}
ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void)
{
return SF_Ctrl_Get_Flash_Image_Offset();
}
/**
* @brief flash erase
*
* @param startaddr
* @param endaddr
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len)
{
int ret = -1;
uint8_t isAesEnable = 0;
uintptr_t flag;
flag = bflb_irq_save();
XIP_SFlash_Opt_Enter(&isAesEnable);
ret = XIP_SFlash_Erase_Need_Lock_Ext(&g_flash_cfg, startaddr, startaddr + len - 1);
XIP_SFlash_Opt_Exit(isAesEnable);
bflb_irq_restore(flag);
return ret;
}
/**
* @brief flash write data
*
* @param addr
* @param data
* @param len
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len)
{
int ret = -1;
uint8_t isAesEnable = 0;
uintptr_t flag;
flag = bflb_irq_save();
XIP_SFlash_Opt_Enter(&isAesEnable);
ret = XIP_SFlash_Write_Need_Lock_Ext(&g_flash_cfg, addr, data, len);
XIP_SFlash_Opt_Exit(isAesEnable);
bflb_irq_restore(flag);
return ret;
}
/**
* @brief flash read data
*
* @param addr
* @param data
* @param len
* @return int
*/
int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
{
int ret = -1;
uint8_t isAesEnable = 0;
uintptr_t flag;
flag = bflb_irq_save();
XIP_SFlash_Opt_Enter(&isAesEnable);
ret = XIP_SFlash_Read_Need_Lock_Ext(&g_flash_cfg, addr, data, len);
XIP_SFlash_Opt_Exit(isAesEnable);
bflb_irq_restore(flag);
return ret;
}
int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
{
uint8_t isAesEnable = 0;
uint32_t tmp[1];
int stat;
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
XIP_SFlash_Opt_Enter(&isAesEnable);
/* To make it simple, exit cont read anyway */
SFlash_Reset_Continue_Read(&g_flash_cfg);
if (g_flash_cfg.cReadSupport == 0) {
cont_read = 0;
}
if (cont_read == 1) {
stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
if (0 != stat) {
XIP_SFlash_Opt_Exit(isAesEnable);
return -1;
}
}
/* Set default value */
SFlash_Cache_Enable_Set(0xf);
if (cache_enable) {
SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
}
XIP_SFlash_Opt_Exit(isAesEnable);
return 0;
}
void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
{
uint8_t hw_key_enable = 0;
if (config->key == NULL) {
hw_key_enable = 1;
}
SF_Ctrl_AES_Set_Key_BE(config->region, (uint8_t *)config->key, config->keybits);
SF_Ctrl_AES_Set_IV_BE(config->region, (uint8_t *)config->iv, config->start_addr);
SF_Ctrl_AES_Set_Region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable);
}
void bflb_flash_aes_enable(void)
{
SF_Ctrl_AES_Enable();
}
void bflb_flash_aes_disable(void)
{
SF_Ctrl_AES_Disable();
}

72
drivers/soc/bl602/std/src/bl602_clock.c
View File

@ -60,7 +60,7 @@
/** @defgroup CLOCK_Private_Variables
* @{
*/
//static Clock_Cfg_Type clkCfg;
//static inline Clock_Cfg_Type clkCfg;
/*@} end of group CLOCK_Private_Variables */
@ -86,7 +86,7 @@
* @{
*/
static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
static inline uint32_t Clock_Xtal_Output(void)
{
uint32_t tmpVal;
@ -121,7 +121,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
}
}
static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_XClk_Mux_Output(uint8_t sel)
{
if (sel == 0) {
/* rc32m */
@ -132,7 +132,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
static inline uint8_t Clock_Get_MCU_XClk_Sel_Val(void)
{
uint32_t tmpVal = 0;
@ -142,7 +142,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
return (tmpVal & 0x1);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)
static inline uint8_t Clock_Get_MCU_Root_Clk_Sel_Val(void)
{
uint32_t tmpVal;
@ -152,7 +152,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)
return ((tmpVal >> 1) & 0x1);
}
static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_MCU_Clk_Mux_Output(uint8_t sel)
{
if (sel == 0) {
/* pll 48m */
@ -171,7 +171,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)
}
}
static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
{
uint32_t tmpVal;
@ -188,7 +188,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
static inline uint8_t Clock_Get_MCU_HClk_Div_Val(void)
{
uint32_t tmpVal;
@ -197,7 +197,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
static inline uint8_t Clock_Get_Peri_BClk_Div_Val(void)
{
uint32_t tmpVal;
@ -206,7 +206,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
}
static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
static inline uint32_t Clock_F32k_Mux_Output(uint8_t sel)
{
uint32_t tmpVal;
uint32_t div = 0;
@ -225,7 +225,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)
static inline uint8_t Clock_Get_F32k_Sel_Val(void)
{
uint32_t tmpVal;
@ -281,7 +281,7 @@ uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type)
}
}
static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
{
if (sel == 0) {
/* fclk */
@ -292,7 +292,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void)
static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
{
uint32_t tmpVal;
@ -301,7 +301,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void)
static inline uint8_t Clock_Get_UART_Div_Val(void)
{
uint32_t tmpVal;
@ -310,13 +310,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
}
static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(void)
static inline uint32_t Clock_SPI_Clk_Mux_Output(void)
{
/* pbclk */
return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void)
static inline uint8_t Clock_Get_SPI_Div_Val(void)
{
uint32_t tmpVal;
@ -325,13 +325,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
}
static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output()
static inline uint32_t Clock_I2C_Clk_Mux_Output()
{
/* pbclk */
return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void)
static inline uint8_t Clock_Get_I2C_Div_Val(void)
{
uint32_t tmpVal;
@ -340,7 +340,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void)
static inline uint8_t Clock_Get_GPADC_Div_Val(void)
{
uint32_t tmpVal;
@ -349,7 +349,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
}
static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel)
static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
{
if (sel == 0) {
/* 96m */
@ -360,7 +360,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void)
static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
{
uint32_t tmpVal;
@ -369,7 +369,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
}
static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
{
uint32_t div = 0;
@ -382,7 +382,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void)
static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
{
uint32_t tmpVal;
@ -391,7 +391,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN);
}
static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
{
if (sel == 0) {
/* pll 32m */
@ -402,7 +402,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void)
static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
{
uint32_t tmpVal;
@ -411,7 +411,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)
static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
{
uint32_t tmpVal;
@ -420,7 +420,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
}
// static uint32_t ATTR_CLOCK_SECTION Clock_PWM_Clk_Mux_Output(uint8_t sel)
// static inline uint32_t Clock_PWM_Clk_Mux_Output(uint8_t sel)
// {
// if (sel == 0) {
// /* xclk */
@ -434,7 +434,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)
// }
// }
// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Div_Val(void)
// static inline uint8_t Clock_Get_PWM_Div_Val(void)
// {
// uint32_t tmpVal;
@ -443,7 +443,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)
// return tmpVal;
// }
// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Clk_Sel_Val(void)
// static inline uint8_t Clock_Get_PWM_Clk_Sel_Val(void)
// {
// uint32_t tmpVal;
@ -452,13 +452,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)
// return BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL);
// }
static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void)
static inline uint32_t Clock_IR_Clk_Mux_Output(void)
{
/* xclk */
return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void)
static inline uint8_t Clock_Get_IR_Div_Val(void)
{
uint32_t tmpVal;
@ -467,7 +467,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void)
static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
{
uint32_t tmpVal;
@ -476,7 +476,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
}
static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
{
if (sel == 0) {
/* 120m */
@ -490,7 +490,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
}
}
static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
{
if (sel == 0) {
/* sf sel2 */
@ -507,7 +507,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
}
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void)
static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
{
uint32_t tmpVal;
@ -516,7 +516,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void)
return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
}
static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void)
static inline uint8_t Clock_Get_SF_Div_Val(void)
{
uint32_t tmpVal;

1872
drivers/soc/bl602/std/src/bl602_ef_ctrl.c
View File

File diff suppressed because it is too large Load Diff

2
drivers/soc/bl602/std/src/bl602_hbn.c
View File

@ -36,7 +36,7 @@
#include "bl602_hbn.h"
#include "bl602_glb.h"
#include "bl602_xip_sflash.h"
#include "bflb_xip_sflash.h"
// #include "risc-v/Core/Include/clic.h"
/** @addtogroup BL602_Peripheral_Driver

260
drivers/soc/bl602/std/src/bl602_romapi.c
View File

@ -341,9 +341,9 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
#endif
__ALWAYS_INLINE
void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg)
void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_HBN_Power_Down_Flash(flashCfg);
return RomDriver_HBN_Power_Down_Flash(flash_cfg);
}
#if 0
@ -567,461 +567,465 @@ void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void)
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg)
void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg)
{
return RomDriver_SFlash_Init(pSfCtrlCfg);
return RomDriver_SFlash_Init(p_sf_ctrl_cfg);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode)
int ATTR_TCM_SECTION bflb_sflash_setspimode(uint8_t mode)
{
return RomDriver_SFlash_SetSPIMode(mode);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen)
int ATTR_TCM_SECTION bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len)
{
return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen);
return RomDriver_SFlash_Read_Reg(flash_cfg, reg_index, reg_value, reg_len);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen)
int ATTR_TCM_SECTION bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len)
{
return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen);
return RomDriver_SFlash_Write_Reg(flash_cfg, reg_index, reg_value, reg_len);
}
__ALWAYS_INLINE
BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg)
int ATTR_TCM_SECTION bflb_sflash_busy(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Busy(flashCfg);
return RomDriver_SFlash_Busy(flash_cfg);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg)
int ATTR_TCM_SECTION bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Write_Enable(flashCfg);
return RomDriver_SFlash_Write_Enable(flash_cfg);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg)
int ATTR_TCM_SECTION bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Qspi_Enable(flashCfg);
return RomDriver_SFlash_Qspi_Enable(flash_cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg)
void ATTR_TCM_SECTION bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg);
return RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg)
int ATTR_TCM_SECTION bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Chip_Erase(flashCfg);
return RomDriver_SFlash_Chip_Erase(flash_cfg);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum)
int ATTR_TCM_SECTION bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sec_num)
{
return RomDriver_SFlash_Sector_Erase(flashCfg, secNum);
return RomDriver_SFlash_Sector_Erase(flash_cfg, sec_num);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum)
int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
{
return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum);
return RomDriver_SFlash_Blk32_Erase(flash_cfg, blk_num);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum)
int ATTR_TCM_SECTION bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
{
return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum);
return RomDriver_SFlash_Blk64_Erase(flash_cfg, blk_num);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr)
int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t startaddr, uint32_t endaddr)
{
return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr);
return RomDriver_SFlash_Erase(flash_cfg, startaddr, endaddr);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len)
int ATTR_TCM_SECTION bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len)
{
return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len);
return RomDriver_SFlash_Program(flash_cfg, io_mode, addr, data, len);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen)
void ATTR_TCM_SECTION bflb_sflash_get_uniqueid(uint8_t *data, uint8_t idLen)
{
return RomDriver_SFlash_GetUniqueId(data, idLen);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data)
void ATTR_TCM_SECTION bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data)
{
return RomDriver_SFlash_GetJedecId(flashCfg, data);
return RomDriver_SFlash_GetJedecId(flash_cfg, data);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data)
void ATTR_TCM_SECTION bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr)
{
return RomDriver_SFlash_GetDeviceId(data);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_Powerdown(void)
void ATTR_TCM_SECTION bflb_sflash_powerdown(void)
{
return RomDriver_SFlash_Powerdown();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg)
void ATTR_TCM_SECTION bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Releae_Powerdown(flashCfg);
return RomDriver_SFlash_Releae_Powerdown(flash_cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg)
void ATTR_TCM_SECTION bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_SetBurstWrap(flashCfg);
return RomDriver_SFlash_SetBurstWrap(flash_cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg)
void ATTR_TCM_SECTION bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_DisableBurstWrap(flashCfg);
return RomDriver_SFlash_DisableBurstWrap(flash_cfg);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg)
int ATTR_TCM_SECTION bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Software_Reset(flashCfg);
return RomDriver_SFlash_Software_Reset(flash_cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg)
void ATTR_TCM_SECTION bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg)
{
return RomDriver_SFlash_Reset_Continue_Read(flashCfg);
return RomDriver_SFlash_Reset_Continue_Read(flash_cfg);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)
int ATTR_TCM_SECTION bflb_sflash_set_idbus_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank)
{
return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len);
return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg, io_mode, cont_read, addr, len);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)
int ATTR_TCM_SECTION bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank)
{
return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead);
return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg, io_mode, cont_read);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable)
int ATTR_TCM_SECTION bflb_sflash_cache_enable_set(uint8_t way_disable)
{
return RomDriver_SFlash_Cache_Enable_Set(wayDisable);
return RomDriver_SFlash_Cache_Enable_Set(way_disable);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Flush(void)
int ATTR_TCM_SECTION bflb_sflash_cache_flush(void)
{
return RomDriver_SFlash_Cache_Flush();
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)
int ATTR_TCM_SECTION bflb_sflash_cache_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t way_disable)
{
return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable);
return RomDriver_SFlash_Cache_Read_Enable(flash_cfg, io_mode, cont_read, way_disable);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh)
void ATTR_TCM_SECTION bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high)
{
return RomDriver_SFlash_Cache_Hit_Count_Get(hitCountLow, hitCountHigh);
return RomDriver_SFlash_Cache_Hit_Count_Get(hit_count_low, hit_count_high);
}
__ALWAYS_INLINE
uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void)
uint32_t ATTR_TCM_SECTION bflb_l1c_miss_count_get(void)
{
return RomDriver_SFlash_Cache_Miss_Count_Get();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void)
void ATTR_TCM_SECTION bflb_sflash_cache_read_disable(void)
{
return RomDriver_SFlash_Cache_Read_Disable();
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len)
int ATTR_TCM_SECTION bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len)
{
return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len);
return RomDriver_SFlash_Read(flash_cfg, io_mode, cont_read, addr, data, len);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen)
int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
{
return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen);
return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg, read_reg_cmd, reg_value, reg_len);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen)
int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
{
return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen);
return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg, write_reg_cmd, reg_value, reg_len);
}
#if 0
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead)
int ATTR_TCM_SECTION bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flashContRead)
{
return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead);
return RomDriver_SFlash_Restore_From_Powerdown(p_flash_cfg, flashContRead);
}
#endif
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin)
int ATTR_TCM_SECTION bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin)
{
return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin);
return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void)
void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void)
{
return RomDriver_SF_Cfg_Init_Internal_Flash_Gpio();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin)
int ATTR_TCM_SECTION bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin)
{
return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin);
return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Cfg_Restore_GPIO17_Fun(uint8_t fun)
void ATTR_TCM_SECTION bflb_sf_cfg_restore_gpio17_fun(uint8_t fun)
{
return RomDriver_SF_Cfg_Restore_GPIO17_Fun(fun);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg)
int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
{
return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg);
return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault)
int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
{
return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault);
return RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg, restore_default);
}
__ALWAYS_INLINE
uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg)
uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
{
return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg);
uint8_t auto_scan = 0;
uint8_t flash_pin = 0;
auto_scan = ((flash_pin_cfg >> 7) & 1);
flash_pin = (flash_pin_cfg & 0x7F);
return RomDriver_SF_Cfg_Flash_Identify(call_from_flash, auto_scan, flash_pin, restore_default, p_flash_cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg)
void ATTR_TCM_SECTION bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg)
{
return RomDriver_SF_Ctrl_Enable(cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel)
void ATTR_TCM_SECTION bflb_sf_ctrl_select_pad(uint8_t sel)
{
return RomDriver_SF_Ctrl_Select_Pad(sel);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner)
void ATTR_TCM_SECTION bflb_sf_ctrl_set_owner(uint8_t owner)
{
return RomDriver_SF_Ctrl_Set_Owner(owner);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Disable(void)
void ATTR_TCM_SECTION bflb_sf_ctrl_disable(void)
{
return RomDriver_SF_Ctrl_Disable();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_be(void)
{
return RomDriver_SF_Ctrl_AES_Enable_BE();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_le(void)
{
return RomDriver_SF_Ctrl_AES_Enable_LE();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hw_key, uint32_t start_addr, uint32_t end_addr, uint8_t locked)
{
return RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked);
return RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hw_key, start_addr, end_addr, locked);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t keyType)
{
return RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t keyType)
{
return RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset)
{
return RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset);
return RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addr_offset);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset)
{
return RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset);
return RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addr_offset);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable(void)
{
return RomDriver_SF_Ctrl_AES_Enable();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void)
void ATTR_TCM_SECTION bflb_sf_ctrl_aes_disable(void)
{
return RomDriver_SF_Ctrl_AES_Disable();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset)
void ATTR_TCM_SECTION bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank)
{
return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset);
return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset);
}
__ALWAYS_INLINE
uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void)
uint32_t ATTR_TCM_SECTION bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank)
{
return RomDriver_SF_Ctrl_Get_Flash_Image_Offset();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType)
void ATTR_TCM_SECTION bflb_sf_ctrl_select_clock(uint8_t sahb_type)
{
return RomDriver_SF_Ctrl_Select_Clock(sahbType);
return RomDriver_SF_Ctrl_Select_Clock(sahb_type);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg)
void ATTR_TCM_SECTION bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg)
{
return RomDriver_SF_Ctrl_SendCmd(cfg);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
void ATTR_TCM_SECTION bflb_sf_ctrl_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
{
return RomDriver_SF_Ctrl_Icache_Set(cfg, cmdValid);
return RomDriver_SF_Ctrl_Icache_Set(cfg, cmd_valid);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid)
void ATTR_TCM_SECTION bflb_sf_ctrl_icache2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
{
return RomDriver_SF_Ctrl_Icache2_Set(cfg, cmdValid);
return RomDriver_SF_Ctrl_Icache2_Set(cfg, cmd_valid);
}
__ALWAYS_INLINE
BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void)
uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_busy_state(void)
{
return RomDriver_SF_Ctrl_GetBusyState();
}
__ALWAYS_INLINE
uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void)
uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_is_aes_enable(void)
{
return RomDriver_SF_Ctrl_Is_AES_Enable();
}
__ALWAYS_INLINE
uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void)
uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_clock_delay(void)
{
return RomDriver_SF_Ctrl_Get_Clock_Delay();
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay)
void ATTR_TCM_SECTION bflb_sf_ctrl_set_clock_delay(uint8_t delay)
{
return RomDriver_SF_Ctrl_Set_Clock_Delay(delay);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset)
int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset);
return RomDriver_XIP_SFlash_State_Save(p_flash_cfg, offset);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset)
int ATTR_TCM_SECTION bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, offset);
return RomDriver_XIP_SFlash_State_Restore(p_flash_cfg, offset);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr)
int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, startaddr, endaddr);
return RomDriver_XIP_SFlash_Erase_Need_Lock(p_flash_cfg, startaddr, startaddr+len-1);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len)
int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, data, len);
return RomDriver_XIP_SFlash_Write_Need_Lock(p_flash_cfg, addr, data, len);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len)
int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, data, len);
return RomDriver_XIP_SFlash_Read_Need_Lock(p_flash_cfg, addr, data, len);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data)
int ATTR_TCM_SECTION bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, data);
return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(p_flash_cfg, data);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data)
int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, data);
return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(p_flash_cfg, data);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen)
int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t idLen, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, data, idLen);
return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(p_flash_cfg, data, idLen);
}
__ALWAYS_INLINE
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len)
int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
{
return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable)
void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable)
{
return RomDriver_XIP_SFlash_Opt_Enter(aesEnable);
return RomDriver_XIP_SFlash_Opt_Enter(aes_enable);
}
__ALWAYS_INLINE
void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable)
void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable)
{
return RomDriver_XIP_SFlash_Opt_Exit(aesEnable);
return RomDriver_XIP_SFlash_Opt_Exit(aes_enable);
}
__ALWAYS_INLINE

291
drivers/soc/bl602/std/src/bl602_romdriver.c Normal file
View File

@ -0,0 +1,291 @@
/**
******************************************************************************
* @file bl602_romdriver.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "bl602_romdriver.h"
#include <string.h>
/** @addtogroup BL602_Periph_Driver
* @{
*/
/** @defgroup ROMDRIVER
* @brief ROMDRIVER common functions
* @{
*/
/** @defgroup ROMDRIVER_Private_Type
* @{
*/
/*@} end of group ROMDRIVER_Private_Type*/
/** @defgroup ROMDRIVER_Private_Defines
* @{
*/
/*@} end of group ROMDRIVER_Private_Defines */
/** @defgroup ROMDRIVER_Private_Variables
* @{
*/
/*@} end of group ROMDRIVER_Private_Variables */
/** @defgroup ROMDRIVER_Global_Variables
* @{
*/
uint32_t const romDriverTable[] = {
0x06020002,
0x00000000,
0x00000000,
0x00000000,
[ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG,
[ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG,
[ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL,
[ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode,
[ROM_API_INDEX_AON_Get_Xtal_CapCode] = (uint32_t)AON_Get_Xtal_CapCode,
[ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL,
[ROM_API_INDEX_AON_Power_On_BG] = (uint32_t)AON_Power_On_BG,
[ROM_API_INDEX_AON_Power_Off_BG] = (uint32_t)AON_Power_Off_BG,
[ROM_API_INDEX_AON_Power_On_LDO11_SOC] = (uint32_t)AON_Power_On_LDO11_SOC,
[ROM_API_INDEX_AON_Power_Off_LDO11_SOC] = (uint32_t)AON_Power_Off_LDO11_SOC,
[ROM_API_INDEX_AON_Power_On_LDO15_RF] = (uint32_t)AON_Power_On_LDO15_RF,
[ROM_API_INDEX_AON_Power_Off_LDO15_RF] = (uint32_t)AON_Power_Off_LDO15_RF,
[ROM_API_INDEX_AON_Power_On_SFReg] = (uint32_t)AON_Power_On_SFReg,
[ROM_API_INDEX_AON_Power_Off_SFReg] = (uint32_t)AON_Power_Off_SFReg,
[ROM_API_INDEX_AON_LowPower_Enter_PDS0] = (uint32_t)AON_LowPower_Enter_PDS0,
[ROM_API_INDEX_AON_LowPower_Exit_PDS0] = (uint32_t)AON_LowPower_Exit_PDS0,
[ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us,
[ROM_API_INDEX_BL602_Delay_US] = (uint32_t)BL602_Delay_US,
[ROM_API_INDEX_BL602_Delay_MS] = (uint32_t)BL602_Delay_MS,
[ROM_API_INDEX_BL602_MemCpy] = (uint32_t)BL602_MemCpy,
[ROM_API_INDEX_BL602_MemCpy4] = (uint32_t)BL602_MemCpy4,
[ROM_API_INDEX_BL602_MemCpy_Fast] = (uint32_t)BL602_MemCpy_Fast,
[ROM_API_INDEX_BL602_MemSet] = (uint32_t)BL602_MemSet,
[ROM_API_INDEX_BL602_MemSet4] = (uint32_t)BL602_MemSet4,
[ROM_API_INDEX_BL602_MemCmp] = (uint32_t)BL602_MemCmp,
[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0,
[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0] = (uint32_t)EF_Ctrl_Program_Efuse_0,
[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0,
[ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy,
[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done] = (uint32_t)EF_Ctrl_AutoLoad_Done,
[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity,
[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim,
[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim,
[ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear,
[ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel,
[ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div,
[ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div,
[ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div,
[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL] = (uint32_t)Update_SystemCoreClockWith_XTAL,
[ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK,
[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M,
[ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK,
[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel] = (uint32_t)GLB_Set_PKA_CLK_Sel,
[ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset,
[ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset,
[ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset,
[ROM_API_INDEX_GLB_Select_Internal_Flash] = (uint32_t)GLB_Select_Internal_Flash,
[ROM_API_INDEX_GLB_Select_External_Flash] = (uint32_t)GLB_Select_External_Flash,
[ROM_API_INDEX_GLB_Deswap_Flash_Pin] = (uint32_t)GLB_Deswap_Flash_Pin,
[ROM_API_INDEX_GLB_Swap_Flash_Pin] = (uint32_t)GLB_Swap_Flash_Pin,
[ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init,
[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable,
[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable,
[ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ,
[ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun,
[ROM_API_INDEX_HBN_Mode_Enter] = (uint32_t)HBN_Mode_Enter,
[ROM_API_INDEX_HBN_Power_Down_Flash] = (uint32_t)HBN_Power_Down_Flash,
[ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable,
[ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset,
[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout] = (uint32_t)HBN_Set_Ldo11_Aon_Vout,
[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout] = (uint32_t)HBN_Set_Ldo11_Rt_Vout,
[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout] = (uint32_t)HBN_Set_Ldo11_Soc_Vout,
[ROM_API_INDEX_HBN_32K_Sel] = (uint32_t)HBN_32K_Sel,
[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel,
[ROM_API_INDEX_HBN_Power_On_Xtal_32K] = (uint32_t)HBN_Power_On_Xtal_32K,
[ROM_API_INDEX_HBN_Power_Off_Xtal_32K] = (uint32_t)HBN_Power_Off_Xtal_32K,
[ROM_API_INDEX_HBN_Power_On_RC32K] = (uint32_t)HBN_Power_On_RC32K,
[ROM_API_INDEX_HBN_Power_Off_RC32K] = (uint32_t)HBN_Power_Off_RC32K,
[ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K,
[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg] = (uint32_t)HBN_Hw_Pu_Pd_Cfg,
[ROM_API_INDEX_HBN_Pin_WakeUp_Mask] = (uint32_t)HBN_Pin_WakeUp_Mask,
[ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO7_Dbg_Pull_Cfg,
[ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup] = (uint32_t)HBN_Set_Embedded_Flash_Pullup,
[ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap,
[ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable,
[ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set,
[ROM_API_INDEX_PDS_Reset] = (uint32_t)PDS_Reset,
[ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable,
[ROM_API_INDEX_PDS_Force_Config] = (uint32_t)PDS_Force_Config,
[ROM_API_INDEX_PDS_RAM_Config] = (uint32_t)PDS_RAM_Config,
[ROM_API_INDEX_PDS_Default_Level_Config] = (uint32_t)PDS_Default_Level_Config,
[ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M,
[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref,
[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref] = (uint32_t)PDS_Select_XTAL_As_PLL_Ref,
[ROM_API_INDEX_PDS_Power_On_PLL] = (uint32_t)PDS_Power_On_PLL,
[ROM_API_INDEX_PDS_Enable_PLL_All_Clks] = (uint32_t)PDS_Enable_PLL_All_Clks,
[ROM_API_INDEX_PDS_Disable_PLL_All_Clks] = (uint32_t)PDS_Disable_PLL_All_Clks,
[ROM_API_INDEX_PDS_Enable_PLL_Clk] = (uint32_t)PDS_Enable_PLL_Clk,
[ROM_API_INDEX_PDS_Disable_PLL_Clk] = (uint32_t)PDS_Disable_PLL_Clk,
[ROM_API_INDEX_PDS_Power_Off_PLL] = (uint32_t)PDS_Power_Off_PLL,
[ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring] = (uint32_t)SEC_Eng_Turn_On_Sec_Ring,
[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring] = (uint32_t)SEC_Eng_Turn_Off_Sec_Ring,
[ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init,
[ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode,
[ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg,
[ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg,
[ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy,
[ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable,
[ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable,
[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable,
[ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase,
[ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase,
[ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase,
[ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase,
[ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase,
[ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program,
[ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId,
[ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId,
[ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId,
[ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown,
[ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown,
[ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap,
[ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap,
[ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset,
[ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read,
[ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg,
[ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable,
[ROM_API_INDEX_SFlash_Cache_Enable_Set] = (uint32_t)SFlash_Cache_Enable_Set,
[ROM_API_INDEX_SFlash_Cache_Flush] = (uint32_t)SFlash_Cache_Flush,
[ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable,
[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get] = (uint32_t)SFlash_Cache_Hit_Count_Get,
[ROM_API_INDEX_SFlash_Cache_Miss_Count_Get] = (uint32_t)SFlash_Cache_Miss_Count_Get,
[ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable,
[ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read,
[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd,
[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd,
[ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown,
[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio,
[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Internal_Flash_Gpio,
[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio,
[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun] = (uint32_t)SF_Cfg_Restore_GPIO17_Fun,
[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock,
[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio,
[ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify,
[ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable,
[ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad,
[ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner,
[ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable,
[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE,
[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE,
[ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region,
[ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key,
[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE,
[ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV,
[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE,
[ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable,
[ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable,
[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset,
[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset,
[ROM_API_INDEX_SF_Ctrl_Select_Clock] = (uint32_t)SF_Ctrl_Select_Clock,
[ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd,
[ROM_API_INDEX_SF_Ctrl_Icache_Set] = (uint32_t)SF_Ctrl_Icache_Set,
[ROM_API_INDEX_SF_Ctrl_Icache2_Set] = (uint32_t)SF_Ctrl_Icache2_Set,
[ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState,
[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable,
[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay,
[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay,
[ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save,
[ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore,
[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock,
[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock,
[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock,
[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock,
[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock,
[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock,
[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock,
[ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock,
[ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock,
[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock,
[ROM_API_INDEX_XIP_SFlash_Opt_Enter] = (uint32_t)XIP_SFlash_Opt_Enter,
[ROM_API_INDEX_XIP_SFlash_Opt_Exit] = (uint32_t)XIP_SFlash_Opt_Exit,
[ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32,
[ROM_API_INDEX_FUNC_EMPTY_START... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef,
};
/*@} end of group ROMDRIVER_Global_Variables */
/** @defgroup ROMDRIVER_Private_FunctionDeclaration
* @{
*/
/*@} end of group ROMDRIVER_Private_FunctionDeclaration */
/** @defgroup ROMDRIVER_Private_Functions
* @{
*/
/*@} end of group ROMDRIVER_Private_Functions */
/** @defgroup ROMDRIVER_Public_Functions
* @{
*/
/*@} end of group ROMDRIVER_Public_Functions */
/*@} end of group ROMDRIVER_COMMON */
/*@} end of group BL602_Periph_Driver */

2193
drivers/soc/bl602/std/src/bl602_sf_cfg.c
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929
drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c
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1149
drivers/soc/bl602/std/src/bl602_sf_ctrl.c
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