diff --git a/bsp/board/bl602dk/CMakeLists.txt b/bsp/board/bl602dk/CMakeLists.txt index f0e65849..494bd07f 100644 --- a/bsp/board/bl602dk/CMakeLists.txt +++ b/bsp/board/bl602dk/CMakeLists.txt @@ -1,5 +1,8 @@ sdk_add_include_directories(.) target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) +# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c) -sdk_set_linker_script(bl602_flash.ld) \ No newline at end of file +sdk_set_linker_script(bl602_flash.ld) + +# sdk_add_link_options(-ufw_header) \ No newline at end of file diff --git a/bsp/board/bl602dk/bl602_flash.ld b/bsp/board/bl602dk/bl602_flash.ld index ac5abf3f..0ecdc678 100644 --- a/bsp/board/bl602dk/bl602_flash.ld +++ b/bsp/board/bl602dk/bl602_flash.ld @@ -22,6 +22,7 @@ HeapSize = 0x1000; /* 4KB */ MEMORY { + fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K itcm_memory (rx) : ORIGIN = 0x22010000, LENGTH = 16K dtcm_memory (rx) : ORIGIN = 0x42014000, LENGTH = 48K @@ -32,6 +33,11 @@ SECTIONS { PROVIDE(__metal_chicken_bit = 0); + .fw_header : + { + KEEP(*(.fw_header)) + } > fw_header_memory + .text : { . = ALIGN(4); @@ -189,6 +195,10 @@ SECTIONS *(.sdata2.*) . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; __ram_data_end__ = .; } > ram_memory diff --git a/bsp/board/bl602dk/board.c b/bsp/board/bl602dk/board.c index ba428d54..3aeb3da6 100644 --- a/bsp/board/bl602dk/board.c +++ b/bsp/board/bl602dk/board.c @@ -3,27 +3,16 @@ #include "bflb_clock.h" #include "bflb_rtc.h" #include "bflb_flash.h" -#ifdef CONFIG_TLSF -#include "bflb_tlsf.h" -#else -#include "bflb_mmheap.h" -#endif #include "board.h" #include "bl602_glb.h" -#include "bl602_sflash.h" + +#include "mem.h" + +extern void log_start(void); extern uint32_t __HeapBase; extern uint32_t __HeapLimit; -#ifndef CONFIG_TLSF -struct heap_info mmheap_root; - -static struct heap_region system_mmheap[] = { - { NULL, 0 }, - { NULL, 0 }, /* Terminates the array. */ -}; -#endif - static struct bflb_device_s *uart0; #if defined(CONFIG_BFLOG) @@ -72,7 +61,7 @@ void bl_show_log(void) void bl_show_flashinfo(void) { - SPI_Flash_Cfg_Type flashCfg; + spi_flash_cfg_type flashCfg; uint8_t *pFlashCfg = NULL; uint32_t flashCfgLen = 0; uint32_t flashJedecId = 0; @@ -83,17 +72,17 @@ void bl_show_flashinfo(void) printf("=========== flash cfg ==============\r\n"); printf("jedec id 0x%06X\r\n", flashJedecId); printf("mid 0x%02X\r\n", flashCfg.mid); - printf("iomode 0x%02X\r\n", flashCfg.ioMode); - printf("clk delay 0x%02X\r\n", flashCfg.clkDelay); - printf("clk invert 0x%02X\r\n", flashCfg.clkInvert); - printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]); - printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]); - printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]); - printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]); - printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen); - printf("cread support 0x%02X\r\n", flashCfg.cReadSupport); - printf("cread code 0x%02X\r\n", flashCfg.cReadMode); - printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd); + printf("iomode 0x%02X\r\n", flashCfg.io_mode); + printf("clk delay 0x%02X\r\n", flashCfg.clk_delay); + printf("clk invert 0x%02X\r\n", flashCfg.clk_invert); + printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]); + printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]); + printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]); + printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]); + printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len); + printf("cread support 0x%02X\r\n", flashCfg.c_read_support); + printf("cread code 0x%02X\r\n", flashCfg.c_read_mode); + printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd); printf("=====================================\r\n"); } @@ -124,40 +113,38 @@ static void console_init() void board_init(void) { + int ret = -1; uintptr_t flag; flag = bflb_irq_save(); - bflb_flash_init(); + ret = bflb_flash_init(); system_clock_init(); peripheral_clock_init(); bflb_irq_initialize(); - bflb_irq_restore(flag); - -#ifdef CONFIG_TLSF - bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase)); -#else - system_mmheap[0].addr = (uint8_t *)&__HeapBase; - system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); - - if (system_mmheap[0].mem_size > 0) { - bflb_mmheap_init(&mmheap_root, system_mmheap); - } -#endif - console_init(); + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + bl_show_log(); + if (ret != 0) { + printf("flash init fail!!!\r\n"); + } bl_show_flashinfo(); printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); + + log_start(); #if defined(CONFIG_BFLOG) rtc = bflb_device_get_by_name("rtc"); #endif + + bflb_irq_restore(flag); } void board_uartx_gpio_init() @@ -251,4 +238,4 @@ __attribute__((weak)) char *bflog_thread(void) { return ""; } -#endif \ No newline at end of file +#endif diff --git a/bsp/board/bl602dk/fw_header.c b/bsp/board/bl602dk/fw_header.c new file mode 100644 index 00000000..ec581948 --- /dev/null +++ b/bsp/board/bl602dk/fw_header.c @@ -0,0 +1,118 @@ +#include "fw_header.h" + +__attribute__((section(".fw_header"))) struct bootheader_t fw_header = { + .magiccode = 0x504e4642, + .rivison = 0x00000001, + /*flash config */ + .flash_cfg.magiccode = 0x47464346, + .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ + .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ + .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ + .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ + .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ + .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ + .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ + .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ + .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ + .flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */ + .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ + .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ + .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ + .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ + .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ + .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ + .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ + .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ + .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ + .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ + .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ + .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ + .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ + .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ + .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ + .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ + .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ + .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ + .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ + .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ + .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ + .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ + .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ + .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ + .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ + .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ + .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ + .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ + .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ + .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ + .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ + .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ + .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ + .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ + .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ + .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ + .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ + .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ + .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ + .flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */ + .flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */ + .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ + .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ + .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ + .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ + .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ + .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ + .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ + .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ + .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ + .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ + .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ + .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ + .flash_cfg.cfg.qeData = 0, /*!< QE set data */ + .flash_cfg.crc32 = 0xdeadbeef, + /* clock cfg */ + .clk_cfg.magiccode = 0x47464350, + .clk_cfg.cfg.xtal_type = 0x04, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ + .clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M,1:XTAL,2:PLL 48M,3:PLL 120M,4:PLL 160M,5:PLL 192M */ + .clk_cfg.cfg.hclk_div = 0x00, + .clk_cfg.cfg.bclk_div = 0x01, + .clk_cfg.cfg.flash_clk_type = 0x03, /*!< 0:120M,1:XCLK(RC32M or XTAL),2:48M,3:80M,4:BCLK,5:96M */ + .clk_cfg.cfg.flash_clk_div = 0x01, + .clk_cfg.crc32 = 0xdeadbeef, + + /* boot cfg */ + .boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/ + .boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */ + .boot_cfg.bval.key_sel = 0x0, /* [5: 4] for key sel in boot interface*/ + .boot_cfg.bval.rsvd6_7 = 0x0, /* [7: 6] for encrypt*/ + .boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */ + .boot_cfg.bval.cache_select = 0x1, /* [9] for cache */ + .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */ + .boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */ + .boot_cfg.bval.cache_way_disable = 0x3, /* [15: 12] cache way disable info*/ + .boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */ + .boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */ + .boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */ + .boot_cfg.bval.rsvd19_31 = 0x0, /* [31:19] rsvd */ + + .img_segment_info.img_len = 0x00010000, /* image length or segment count */ + .rsvd0 = 0x00000000, + .img_start.flashoffset = 0x00001000, /* flash controller offset */ + .hash = { 0xdeadbeef }, /* hash of the image */ + + .crc32 = 0xdeadbeef /* 4 */ +}; diff --git a/bsp/board/bl602dk/fw_header.h b/bsp/board/bl602dk/fw_header.h new file mode 100644 index 00000000..0833448c --- /dev/null +++ b/bsp/board/bl602dk/fw_header.h @@ -0,0 +1,165 @@ +#ifndef __FW_HEADER_H__ +#define __FW_HEADER_H__ + +#include "stdint.h" +#include "stdio.h" + +struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ + uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +}; + +struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { + uint32_t magiccode; + struct spi_flash_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { + uint8_t xtal_type; + uint8_t pll_clk; + uint8_t hclk_div; + uint8_t bclk_div; + + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t rsvd[2]; +}; + +struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { + uint32_t magiccode; + struct sys_clk_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) aesiv_cfg_t { + uint8_t aesiv[16]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) pkey_cfg_t { + uint8_t eckeyx[32]; /* ec key in boot header */ + uint8_t eckeyy[32]; /* ec key in boot header */ + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sign_cfg_t { + uint32_t sig_len; + uint8_t signature[32]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) bootheader_t { + uint32_t magiccode; /* 4 */ + uint32_t rivison; /* 4 */ + struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */ + struct boot_clk_cfg_t clk_cfg; /* 4 + 8 + 4 */ + union __attribute__((packed, aligned(1))) { + struct __attribute__((packed, aligned(1))) { + uint32_t sign : 2; /* [1: 0] for sign*/ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/ + uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t cache_select : 1; /* [9] for cache */ + uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */ + uint32_t aes_region_lock : 1; /* [11] aes region lock */ + uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash crc */ + uint32_t halt_ap : 1; /* [18] halt ap */ + uint32_t rsvd19_31 : 13; /* [31:19] rsvd */ + } bval; + uint32_t wval; + } boot_cfg; /* 4 */ + + union __attribute__((packed, aligned(1))) { + uint32_t segment_cnt; + uint32_t img_len; + } img_segment_info; /* 4 */ + + uint32_t rsvd0; /* rsvd */ + + union __attribute__((packed, aligned(1))) { + uint32_t ramaddr; + uint32_t flashoffset; + } img_start; /* 4 */ + + uint32_t hash[32 / 4]; /*hash of the image*/ + + uint32_t rsv1; + uint32_t rsv2; + uint32_t crc32; +}; + +#endif \ No newline at end of file diff --git a/bsp/board/bl616dk/CMakeLists.txt b/bsp/board/bl616dk/CMakeLists.txt index ba62bf90..abbb005d 100644 --- a/bsp/board/bl616dk/CMakeLists.txt +++ b/bsp/board/bl616dk/CMakeLists.txt @@ -1,9 +1,12 @@ sdk_add_include_directories(.) target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) +# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c) sdk_set_linker_script(bl616_flash.ld) if(CONFIG_PSRAM) sdk_add_compile_definitions(-DCONFIG_PSRAM) -endif() \ No newline at end of file +endif() + +# sdk_add_link_options(-ufw_header) \ No newline at end of file diff --git a/bsp/board/bl616dk/bl616_flash.ld b/bsp/board/bl616dk/bl616_flash.ld index 8a286a8f..8e81b9fa 100644 --- a/bsp/board/bl616dk/bl616_flash.ld +++ b/bsp/board/bl616dk/bl616_flash.ld @@ -17,29 +17,59 @@ INPUT(-lgcc) /* configure the entry point */ ENTRY(__start) -StackSize = 0x1000; /* 1KB */ +StackSize = 0x1000; /* 4KB */ HeapMinSize = 0x1000; /* 4KB */ +__EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K; +__RFTLV_SIZE_OFFSET = 1K; +__RFTLV_SIZE_HOLE = 2K; +__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */ +__RFTLV_HEAD1_L = (0x41524150); /* PAPA */ + MEMORY { + fw_header_memory (rx) : ORIGIN = 0xA0000000 - 0x1000, LENGTH = 4K xip_memory (rx) : ORIGIN = 0xA0000000, LENGTH = 4M + ram_code (wxa) : ORIGIN = 0xA8000000, LENGTH = 4M itcm_memory (rx) : ORIGIN = 0x62FC0000, LENGTH = 20K dtcm_memory (rx) : ORIGIN = 0x62FC5000, LENGTH = 4K nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K - ram_memory (!rx) : ORIGIN = 0x62FE0000 , LENGTH = 320K+160K-20K-4K-44K-60K + ram_memory (!rx) : ORIGIN = 0x62FE0000, LENGTH = 320K-20K-4K-44K-60K + ram_wifi (wxa) : ORIGIN = 0x23010000, LENGTH = 160K - __EM_SIZE } SECTIONS { + BOOT2_PT_ADDR = 0x63027c00; + + .fw_header : + { + KEEP(*(.fw_header)) + } > fw_header_memory + + .init : + { + *(.text.entry) + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + + } > xip_memory + + .rftlv.tool : + { + . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET; + PROVIDE( _ld_symbol_rftlv_address = . ); + LONG(__RFTLV_HEAD1_H); + LONG(__RFTLV_HEAD1_L); + . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE; + } > xip_memory + .text : { . = ALIGN(4); __text_code_start__ = .; - KEEP (*(SORT_NONE(.init))) - KEEP (*(SORT_NONE(.vector))) - *(.text) *(.text.*) @@ -139,7 +169,9 @@ SECTIONS /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); .nocache_ram_region : AT (__nocache_ram_load_addr) @@ -192,6 +224,10 @@ SECTIONS *(.sdata2.*) . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; __ram_data_end__ = .; } > ram_memory @@ -250,5 +286,42 @@ SECTIONS __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") + .psmram_data (NOLOAD): + { + . = ALIGN(4); + __psram_data_start__ = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.psram_data*)) + + . = ALIGN(4); + __psram_data_end__ = .; + } > ram_code + + .wifibss (NOLOAD) : + { + PROVIDE( __wifi_bss_start = ADDR(.wifibss) ); + PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) ); + _sshram = . ; + *(SHAREDRAMIPC) + *(SHAREDRAM) + _eshram = . ; + *ipc_shared.o(COMMON) + *sdu_shared.o(COMMON) + *hal_desc.o(COMMON) + *txl_buffer_shared.o(COMMON) + *txl_frame_shared.o(COMMON) + *scan_shared.o(COMMON) + *scanu_shared.o(COMMON) + *mfp_bip.o(COMMON) + *me_mic.o(COMMON) + *(.wifi_ram*) + . = ALIGN(16); + } > ram_wifi + + PROVIDE( _heap_wifi_start = . ); + PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start ); + } diff --git a/bsp/board/bl616dk/board.c b/bsp/board/bl616dk/board.c index 789f81cb..edf6bd07 100644 --- a/bsp/board/bl616dk/board.c +++ b/bsp/board/bl616dk/board.c @@ -3,16 +3,12 @@ #include "bflb_clock.h" #include "bflb_rtc.h" #include "bflb_flash.h" -#ifdef CONFIG_TLSF -#include "bflb_tlsf.h" -#else -#include "bflb_mmheap.h" -#endif #include "board.h" #include "bl616_tzc_sec.h" #include "bl616_psram.h" #include "bl616_glb.h" -#include "bl616_sflash.h" + +#include "mem.h" #define WB_4MB_PSRAM (1) @@ -20,18 +16,11 @@ #include "sdh_sdcard.h" #endif +extern void log_start(void); + extern uint32_t __HeapBase; extern uint32_t __HeapLimit; -#ifndef CONFIG_TLSF -struct heap_info mmheap_root; - -static struct heap_region system_mmheap[] = { - { NULL, 0 }, - { NULL, 0 }, /* Terminates the array. */ -}; -#endif - static struct bflb_device_s *uart0; #if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) @@ -40,10 +29,18 @@ static struct bflb_device_s *rtc; static void system_clock_init(void) { +#if 1 /* wifipll/audiopll */ GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL); GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M); - CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_CLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK) / 1000000 - 1); +#else + GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); + GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL); + GLB_Config_AUDIO_PLL_To_384M(); + GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1); + GLB_Set_MCU_System_CLK_Div(0, 3); +#endif + CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1); } static void peripheral_clock_init(void) @@ -110,7 +107,7 @@ static void psram_winbond_default_init(void) .PASR = PSRAM_PARTIAL_REFRESH_FULL, .disDeepPowerDownMode = ENABLE, .fixedLatency = DISABLE, - .brustLen = PSRAM_WINBOND_BURST_LENGTH_32_BYTES, + .brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES, .brustType = PSRAM_WRAPPED_BURST, .latency = PSRAM_WINBOND_6_CLOCKS_LATENCY, .driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M, @@ -152,7 +149,7 @@ void bl_show_log(void) void bl_show_flashinfo(void) { - SPI_Flash_Cfg_Type flashCfg; + spi_flash_cfg_type flashCfg; uint8_t *pFlashCfg = NULL; uint32_t flashCfgLen = 0; uint32_t flashJedecId = 0; @@ -163,17 +160,17 @@ void bl_show_flashinfo(void) printf("=========== flash cfg ==============\r\n"); printf("jedec id 0x%06X\r\n", flashJedecId); printf("mid 0x%02X\r\n", flashCfg.mid); - printf("iomode 0x%02X\r\n", flashCfg.ioMode); - printf("clk delay 0x%02X\r\n", flashCfg.clkDelay); - printf("clk invert 0x%02X\r\n", flashCfg.clkInvert); - printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]); - printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]); - printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]); - printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]); - printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen); - printf("cread support 0x%02X\r\n", flashCfg.cReadSupport); - printf("cread code 0x%02X\r\n", flashCfg.cReadMode); - printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd); + printf("iomode 0x%02X\r\n", flashCfg.io_mode); + printf("clk delay 0x%02X\r\n", flashCfg.clk_delay); + printf("clk invert 0x%02X\r\n", flashCfg.clk_invert); + printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]); + printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]); + printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]); + printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]); + printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len); + printf("cread support 0x%02X\r\n", flashCfg.c_read_support); + printf("cread code 0x%02X\r\n", flashCfg.c_read_mode); + printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd); printf("=====================================\r\n"); } @@ -204,31 +201,26 @@ static void console_init() void board_init(void) { + int ret = -1; uintptr_t flag; flag = bflb_irq_save(); - bflb_flash_init(); + ret = bflb_flash_init(); system_clock_init(); peripheral_clock_init(); bflb_irq_initialize(); - bflb_irq_restore(flag); - -#ifdef CONFIG_TLSF - bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase)); -#else - system_mmheap[0].addr = (uint8_t *)&__HeapBase; - system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); - - if (system_mmheap[0].mem_size > 0) { - bflb_mmheap_init(&mmheap_root, system_mmheap); - } -#endif console_init(); + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + bl_show_log(); + if (ret != 0) { + printf("flash init fail!!!\r\n"); + } bl_show_flashinfo(); printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); @@ -237,6 +229,8 @@ void board_init(void) printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2)); printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); + log_start(); + #if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) rtc = bflb_device_get_by_name("rtc"); #endif @@ -245,6 +239,8 @@ void board_init(void) board_psram_x8_init(); Tzc_Sec_PSRAMB_Access_Release(); #endif + + bflb_irq_restore(flag); } void board_uartx_gpio_init() @@ -438,6 +434,17 @@ void board_dvp_gpio_init(void) #endif } +void board_i2s_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + void board_iso11898_gpio_init() { // struct bflb_device_s *gpio; @@ -494,4 +501,14 @@ __attribute__((weak)) uint32_t get_fattime(void) | ((uint32_t)tm.min << 5) /* Min 0 */ | ((uint32_t)tm.sec >> 1); /* Sec 0 */ } -#endif \ No newline at end of file +#endif + +#ifdef CONFIG_SHELL +#include "shell.h" + +static void reboot_cmd(int argc, char **argv) +{ + GLB_SW_POR_Reset(); +} +SHELL_CMD_EXPORT_ALIAS(reboot_cmd, reboot, reboot); +#endif diff --git a/bsp/board/bl616dk/board.h b/bsp/board/bl616dk/board.h index 33275c70..d21b7a50 100644 --- a/bsp/board/bl616dk/board.h +++ b/bsp/board/bl616dk/board.h @@ -13,6 +13,7 @@ void board_emac_gpio_init(); void board_sdh_gpio_init(); void board_ir_gpio_init(); void board_dvp_gpio_init(); +void board_i2s_gpio_init(); void board_iso11898_gpio_init(); #define DEFAULT_TEST_UART "uart1" diff --git a/bsp/board/bl616dk/fw_header.c b/bsp/board/bl616dk/fw_header.c new file mode 100644 index 00000000..caac91b0 --- /dev/null +++ b/bsp/board/bl616dk/fw_header.c @@ -0,0 +1,165 @@ +#include "fw_header.h" + +__attribute__((section(".fw_header"))) struct bootheader_t fw_header = { + .magiccode = 0x504e4642, + .rivison = 0x00000001, + /*flash config */ + .flash_cfg.magiccode = 0x47464346, + .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ + .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ + .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ + .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ + .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ + .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ + .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ + .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ + .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ + .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ + .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ + .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ + .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ + .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ + .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ + .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ + .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ + .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ + .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ + .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ + .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ + .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ + .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ + .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ + .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ + .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ + .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ + .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ + .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ + .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ + .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ + .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ + .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ + .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ + .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ + .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ + .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ + .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ + .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ + .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ + .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ + .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ + .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ + .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ + .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ + .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ + .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ + .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ + .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ + .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ + .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ + .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ + .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ + .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ + .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ + .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ + .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ + .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ + .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ + .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ + .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ + .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ + .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ + .flash_cfg.cfg.qeData = 0, /*!< QE set data */ + .flash_cfg.crc32 = 0xdeadbeef, + /* clock cfg */ + .clk_cfg.magiccode = 0x47464350, + .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ + .clk_cfg.cfg.mcu_clk = 0x05, /*!< mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M */ + .clk_cfg.cfg.mcu_clk_div = 0x00, /*!< mcu_clk divider */ + .clk_cfg.cfg.mcu_bclk_div = 0x00, /*!< mcu_bclk divider */ + .clk_cfg.cfg.mcu_pbclk_div = 0x03, /*!< mcu_pclk divider */ + .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ + .clk_cfg.cfg.emi_clk_div = 0x01, /*!< emi clock divider */ + .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M */ + .clk_cfg.cfg.flash_clk_div = 0x00, + .clk_cfg.cfg.wifipll_pu = 0x01, + .clk_cfg.cfg.aupll_pu = 0x00, + .clk_cfg.crc32 = 0xdeadbeef, + /* basic cfg */ + .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ + .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ + .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ + .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ + .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ + .basic_cfg.no_segment = 0x1, /* [8] no segment info */ + .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ + .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ + .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ + .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ + .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ + .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ + .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ + .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ + .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ +#if 0 +# 0 : cmds bypass wrap commands to macro, original mode; +# 1 : cmds handle wrap commands, original mode; +# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; +# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 +#endif + .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ +#if 0 +# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, +# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 +#endif + .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ + .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ + .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ + .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ + + .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */ + .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ + + .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */ + .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ + + /* cpu cfg */ + .cpu_cfg.config_enable = 0x01, /* coinfig this cpu */ + .cpu_cfg.halt_cpu = 0x0, /* halt this cpu */ + .cpu_cfg.cache_enable = 0x0, /* cache setting :only for BL Cache */ + .cpu_cfg.cache_wa = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg.cache_wb = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg.cache_wt = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg.cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg.rsvd = 0x0, + + /* image_address_offset */ + .cpu_cfg.image_address_offset = 0x0, + .cpu_cfg.rsvd1 = 0xA0000000, /* rsvd */ + .cpu_cfg.msp_val = 0x00000000, /* msp value */ + + /* address of partition table 0 */ + .boot2_pt_table_0_rsvd = 0x00000000, + /* address of partition table 1 */ + .boot2_pt_table_1_rsvd = 0x00000000, + + /* address of flashcfg table list */ + .flash_cfg_table_addr = 0x00000000, + /* flashcfg table list len */ + .flash_cfg_table_len = 0x00000000, + + .crc32 = 0xdeadbeef +}; diff --git a/bsp/board/bl616dk/fw_header.h b/bsp/board/bl616dk/fw_header.h new file mode 100644 index 00000000..246ed028 --- /dev/null +++ b/bsp/board/bl616dk/fw_header.h @@ -0,0 +1,197 @@ +#ifndef __FW_HEADER_H__ +#define __FW_HEADER_H__ + +#include "stdint.h" +#include "stdio.h" + +struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ + uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +}; + +struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { + uint32_t magiccode; + struct spi_flash_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { + uint8_t xtal_type; + uint8_t mcu_clk; + uint8_t mcu_clk_div; + uint8_t mcu_bclk_div; + + uint8_t mcu_pbclk_div; + uint8_t emi_clk; + uint8_t emi_clk_div; + uint8_t flash_clk_type; + + uint8_t flash_clk_div; + uint8_t wifipll_pu; + uint8_t aupll_pu; + uint8_t rsvd0; +}; + +struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { + uint32_t magiccode; + struct sys_clk_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) boot_basic_cfg_t { + uint32_t sign_type : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] key slot */ + uint32_t xts_mode : 1; /* [6] for xts mode */ + uint32_t aes_region_lock : 1; /* [7] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */ + uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */ + uint32_t cpu_master_id : 4; /* [14: 11] master id */ + uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash ignore */ + uint32_t power_on_mm : 1; /* [18] power on mm */ + uint32_t em_sel : 3; /* [21: 19] em_sel */ + uint32_t cmds_en : 1; /* [22] command spliter enable */ + uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ + uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ + uint32_t icache_invalid : 1; /* [29] icache invalid */ + uint32_t dcache_invalid : 1; /* [30] dcache invalid */ + uint32_t rsvd_3 : 1; /* [31] rsvd_3 */ + + uint32_t group_image_offset; /* flash controller offset */ + uint32_t aes_region_len; /* aes region length */ + + uint32_t img_len_cnt; /* image length or segment count */ + uint32_t hash[32 / 4]; /* hash of the image */ +}; + +struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t { + uint8_t config_enable; /* coinfig this cpu */ + uint8_t halt_cpu; /* halt this cpu */ + uint8_t cache_enable : 1; /* cache setting */ + uint8_t cache_wa : 1; /* cache setting */ + uint8_t cache_wb : 1; /* cache setting */ + uint8_t cache_wt : 1; /* cache setting */ + uint8_t cache_way_dis : 4; /* cache setting */ + uint8_t rsvd; + + uint32_t image_address_offset; /* image_address_offset */ + uint32_t rsvd1; /* rsvd */ + uint32_t msp_val; /* msp value */ +}; + +struct __attribute__((packed, aligned(4))) aesiv_cfg_t { + uint8_t aesiv[16]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) pkey_cfg_t { + uint8_t eckeyx[32]; /* ec key in boot header */ + uint8_t eckeyy[32]; /* ec key in boot header */ + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sign_cfg_t { + uint32_t sig_len; + uint8_t signature[32]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) bootheader_t { + uint32_t magiccode; /* 4 */ + uint32_t rivison; /* 4 */ + + struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */ + struct boot_clk_cfg_t clk_cfg; /* 4 + 12 + 4 */ + + struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */ + + struct boot_cpu_cfg_t cpu_cfg; /* 16 */ + + uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */ + uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */ + + uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */ + uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */ + + uint32_t rsvd0[6]; /* rsvd */ + uint32_t rsvd1[6]; /* rsvd */ + + uint32_t rsvd; /* 4 */ + + uint32_t crc32; /* 4 */ +}; + +#endif \ No newline at end of file diff --git a/bsp/board/bl702dk/CMakeLists.txt b/bsp/board/bl702dk/CMakeLists.txt index bc4d5208..075620ab 100644 --- a/bsp/board/bl702dk/CMakeLists.txt +++ b/bsp/board/bl702dk/CMakeLists.txt @@ -1,9 +1,12 @@ sdk_add_include_directories(.) target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) +# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/fw_header.c) sdk_set_linker_script(bl702_flash.ld) if(CONFIG_PSRAM) sdk_add_compile_definitions(-DCONFIG_PSRAM) -endif() \ No newline at end of file +endif() + +# sdk_add_link_options(-ufw_header) \ No newline at end of file diff --git a/bsp/board/bl702dk/bl702_flash.ld b/bsp/board/bl702dk/bl702_flash.ld index 1773c714..5da6f396 100644 --- a/bsp/board/bl702dk/bl702_flash.ld +++ b/bsp/board/bl702dk/bl702_flash.ld @@ -21,6 +21,7 @@ StackSize = 0x1000; /* 4KB */ MEMORY { + fw_header_memory (rx) : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 12K dtcm_memory (rx) : ORIGIN = 0x42017000, LENGTH = 4K @@ -32,6 +33,11 @@ SECTIONS { PROVIDE(__metal_chicken_bit = 0); + .fw_header : + { + KEEP(*(.fw_header)) + } > fw_header_memory + .text : { . = ALIGN(4); @@ -183,6 +189,10 @@ SECTIONS *(.sdata2.*) . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; __ram_data_end__ = .; } > ram_memory diff --git a/bsp/board/bl702dk/board.c b/bsp/board/bl702dk/board.c index 78a823db..14d0ccbb 100644 --- a/bsp/board/bl702dk/board.c +++ b/bsp/board/bl702dk/board.c @@ -3,28 +3,17 @@ #include "bflb_clock.h" #include "bflb_rtc.h" #include "bflb_flash.h" -#ifdef CONFIG_TLSF -#include "bflb_tlsf.h" -#else -#include "bflb_mmheap.h" -#endif -#include "board.h" +#include "bflb_spi_psram.h" #include "bl702_glb.h" -#include "bl702_sflash.h" -#include "bl702_psram.h" +#include "board.h" + +#include "mem.h" + +extern void log_start(void); extern uint32_t __HeapBase; extern uint32_t __HeapLimit; -#ifndef CONFIG_TLSF -struct heap_info mmheap_root; - -static struct heap_region system_mmheap[] = { - { NULL, 0 }, - { NULL, 0 }, /* Terminates the array. */ -}; -#endif - static struct bflb_device_s *uart0; #if defined(CONFIG_BFLOG) @@ -51,7 +40,7 @@ static void peripheral_clock_init(void) PERIPHERAL_CLOCK_IR_ENABLE(); PERIPHERAL_CLOCK_I2S_ENABLE(); PERIPHERAL_CLOCK_USB_ENABLE(); - GLB_AHB_Slave1_Clock_Gate(DISABLE,BL_AHB_SLAVE1_CAM); + GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM); GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0); GLB_Set_SPI_CLK(ENABLE, 0); @@ -66,45 +55,46 @@ static void peripheral_clock_init(void) /* bsp sf psram private variables */ -SPI_Psram_Cfg_Type apMemory1604 = { - .readIdCmd = 0x9F, - .readIdDmyClk = 0, - .burstToggleCmd = 0xC0, - .resetEnableCmd = 0x66, - .resetCmd = 0x99, - .enterQuadModeCmd = 0x35, - .exitQuadModeCmd = 0xF5, - .readRegCmd = 0xB5, - .readRegDmyClk = 1, - .writeRegCmd = 0xB1, - .readCmd = 0x03, - .readDmyClk = 0, - .fReadCmd = 0x0B, - .fReadDmyClk = 1, - .fReadQuadCmd = 0xEB, - .fReadQuadDmyClk = 3, - .writeCmd = 0x02, - .quadWriteCmd = 0x38, - .pageSize = 512, - .ctrlMode = PSRAM_SPI_CTRL_MODE, - .driveStrength = PSRAM_DRIVE_STRENGTH_50_OHMS, - .burstLength = PSRAM_BURST_LENGTH_512_BYTES, +struct spi_psram_cfg_type ap_memory1604 = { + .read_id_cmd = 0x9F, + .read_id_dmy_clk = 0, + .burst_toggle_cmd = 0xC0, + .reset_enable_cmd = 0x66, + .reset_cmd = 0x99, + .enter_quad_mode_cmd = 0x35, + .exit_quad_mode_cmd = 0xF5, + .read_reg_cmd = 0xB5, + .read_reg_dmy_clk = 1, + .write_reg_cmd = 0xB1, + .read_cmd = 0x03, + .read_dmy_clk = 0, + .f_read_cmd = 0x0B, + .f_read_dmy_clk = 1, + .f_read_quad_cmd = 0xEB, + .f_read_quad_dmy_clk = 3, + .write_cmd = 0x02, + .quad_write_cmd = 0x38, + .page_size = 512, + .ctrl_mode = PSRAM_SPI_CTRL_MODE, + .drive_strength = PSRAM_DRIVE_STRENGTH_50_OHMS, + .burst_length = PSRAM_BURST_LENGTH_512_BYTES, }; -SF_Ctrl_Cmds_Cfg cmdsCfg = { - .cmdsEn = ENABLE, - .burstToggleEn = ENABLE, - .wrapModeEn = DISABLE, - .wrapLen = SF_CTRL_WRAP_LEN_512, +struct sf_ctrl_cmds_cfg cmds_cfg = { + .cmds_core_en = 1, + .cmds_en = 1, + .burst_toggle_en = 1, + .cmds_wrap_mode = 0, + .cmds_wrap_len = SF_CTRL_WRAP_LEN_512, }; -SF_Ctrl_Psram_Cfg sfCtrlPsramCfg = { +struct sf_ctrl_psram_cfg psram_cfg = { .owner = SF_CTRL_OWNER_SAHB, - .padSel = SF_CTRL_PAD_SEL_DUAL_CS_SF2, - .bankSel = SF_CTRL_SEL_PSRAM, - .psramRxClkInvertSrc = ENABLE, - .psramRxClkInvertSel = DISABLE, - .psramDelaySrc = ENABLE, - .psramClkDelay = 1, + .pad_sel = SF_CTRL_SEL_DUAL_CS_SF2, + .bank_sel = SF_CTRL_SEL_PSRAM, + .psram_rx_clk_invert_src = 1, + .psram_rx_clk_invert_sel = 0, + .psram_delay_src = 1, + .psram_clk_delay = 1, }; #define BFLB_EXTFLASH_CS_GPIO GLB_GPIO_PIN_25 @@ -156,12 +146,12 @@ void ATTR_TCM_SECTION board_psram_init(void) { psram_gpio_init(); - Psram_Init(&apMemory1604, &cmdsCfg, &sfCtrlPsramCfg); + bflb_psram_init(&ap_memory1604, &cmds_cfg, &psram_cfg); - Psram_SoftwareReset(&apMemory1604, apMemory1604.ctrlMode); + bflb_psram_softwarereset(&ap_memory1604, ap_memory1604.ctrl_mode); - Psram_ReadId(&apMemory1604, psramId); - Psram_Cache_Write_Set(&apMemory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE); + bflb_psram_readid(&ap_memory1604, psramId); + bflb_psram_cache_write_set(&ap_memory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE); L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE); } @@ -181,7 +171,7 @@ void bl_show_log(void) void bl_show_flashinfo(void) { - SPI_Flash_Cfg_Type flashCfg; + spi_flash_cfg_type flashCfg; uint8_t *pFlashCfg = NULL; uint32_t flashCfgLen = 0; uint32_t flashJedecId = 0; @@ -192,17 +182,17 @@ void bl_show_flashinfo(void) printf("=========== flash cfg ==============\r\n"); printf("jedec id 0x%06X\r\n", flashJedecId); printf("mid 0x%02X\r\n", flashCfg.mid); - printf("iomode 0x%02X\r\n", flashCfg.ioMode); - printf("clk delay 0x%02X\r\n", flashCfg.clkDelay); - printf("clk invert 0x%02X\r\n", flashCfg.clkInvert); - printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]); - printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]); - printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]); - printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]); - printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen); - printf("cread support 0x%02X\r\n", flashCfg.cReadSupport); - printf("cread code 0x%02X\r\n", flashCfg.cReadMode); - printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd); + printf("iomode 0x%02X\r\n", flashCfg.io_mode); + printf("clk delay 0x%02X\r\n", flashCfg.clk_delay); + printf("clk invert 0x%02X\r\n", flashCfg.clk_invert); + printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]); + printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]); + printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]); + printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]); + printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len); + printf("cread support 0x%02X\r\n", flashCfg.c_read_support); + printf("cread code 0x%02X\r\n", flashCfg.c_read_mode); + printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd); printf("=====================================\r\n"); } @@ -233,43 +223,41 @@ static void console_init() void board_init(void) { + int ret = -1; uintptr_t flag; flag = bflb_irq_save(); - bflb_flash_init(); + ret = bflb_flash_init(); system_clock_init(); peripheral_clock_init(); bflb_irq_initialize(); - bflb_irq_restore(flag); - -#ifdef CONFIG_TLSF - bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase)); -#else - system_mmheap[0].addr = (uint8_t *)&__HeapBase; - system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); - - if (system_mmheap[0].mem_size > 0) { - bflb_mmheap_init(&mmheap_root, system_mmheap); - } -#endif - console_init(); + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + bl_show_log(); + if (ret != 0) { + printf("flash init fail!!!\r\n"); + } bl_show_flashinfo(); printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); + + log_start(); #if defined(CONFIG_BFLOG) rtc = bflb_device_get_by_name("rtc"); #endif #ifdef CONFIG_PSRAM board_psram_init(); #endif + + bflb_irq_restore(flag); } void board_uartx_gpio_init() @@ -441,4 +429,4 @@ __attribute__((weak)) char *bflog_thread(void) { return ""; } -#endif \ No newline at end of file +#endif diff --git a/bsp/board/bl702dk/fw_header.c b/bsp/board/bl702dk/fw_header.c new file mode 100644 index 00000000..e3541fd6 --- /dev/null +++ b/bsp/board/bl702dk/fw_header.c @@ -0,0 +1,122 @@ +#include "fw_header.h" + +__attribute__((section(".fw_header"))) struct bootheader_t fw_header = { + .magiccode = 0x504e4642, + .rivison = 0x00000001, + /*flash config */ + .flash_cfg.magiccode = 0x47464346, + .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ + .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ + .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ + .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ + .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ + .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ + .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ + .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ + .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ + .flash_cfg.cfg.mid = 0xff, /*!< Manufacturer ID */ + .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ + .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ + .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ + .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ + .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ + .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ + .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ + .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ + .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ + .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ + .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ + .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ + .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ + .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ + .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ + .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ + .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ + .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ + .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ + .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ + .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ + .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ + .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ + .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ + .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ + .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ + .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ + .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ + .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ + .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ + .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ + .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ + .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ + .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ + .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ + .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ + .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ + .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ + .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ + .flash_cfg.cfg.cReadMode = 0xa0, /*!< Config data for continuous read mode */ + .flash_cfg.cfg.cRExit = 0xff, /*!< Config data for exit continuous read mode */ + .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ + .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ + .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ + .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ + .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ + .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ + .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ + .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ + .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ + .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ + .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ + .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ + .flash_cfg.cfg.qeData = 0, /*!< QE set data */ + .flash_cfg.crc32 = 0xdeadbeef, + /* clock cfg */ + .clk_cfg.magiccode = 0x47464350, + .clk_cfg.cfg.xtal_type = 0x01, /*!< 0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M */ + .clk_cfg.cfg.pll_clk = 0x04, /*!< mcu_clk 0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M */ + .clk_cfg.cfg.hclk_div = 0x00, + .clk_cfg.cfg.bclk_div = 0x01, + .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M */ + .clk_cfg.cfg.flash_clk_div = 0x00, + .clk_cfg.crc32 = 0xdeadbeef, + + /* boot cfg */ + .boot_cfg.bval.sign = 0x0, /* [1: 0] for sign*/ + .boot_cfg.bval.encrypt_type = 0x0, /* [3: 2] for encrypt */ + .boot_cfg.bval.key_sel = 0x01, /* [5: 4] for key sel in boot interface*/ + .boot_cfg.bval.rsvd_7_6 = 0x0, /* [7: 6] for encrypt*/ + .boot_cfg.bval.no_segment = 0x1, /* [8] no segment info */ + .boot_cfg.bval.cache_select = 0x1, /* [9] for cache */ + .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10] not load this img in bootrom */ + .boot_cfg.bval.aes_region_lock = 0x0, /* [11] aes region lock */ + .boot_cfg.bval.cache_way_disable = 0x0, /* [15: 12] cache way disable info*/ + .boot_cfg.bval.crc_ignore = 0x1, /* [16] ignore crc */ + .boot_cfg.bval.hash_ignore = 0x1, /* [17] hash crc */ + .boot_cfg.bval.halt_ap = 0x0, /* [18] halt ap */ + .boot_cfg.bval.boot2_enable = 0x00, /* [19] boot2 enable */ + .boot_cfg.bval.boot2_rollback = 0x00, /* [20] boot2 rollback */ + .boot_cfg.bval.rsvd_31_21 = 0x0, /* [31:21] rsvd */ + + .img_segment_info.img_len = 0x00010000, /* image length or segment count */ + .rsvd0 = 0x00000000, + .img_start.flashoffset = 0x00001000, /* flash controller offset */ + .hash = { 0xdeadbeef }, /* hash of the image */ + + .boot2_pt_table_0 = 0x1000, /* address of partition table 0 */ + .boot2_pt_table_1 = 0x2000, /* address of partition table 1 */ + .crc32 = 0xdeadbeef /* 4 */ +}; diff --git a/bsp/board/bl702dk/fw_header.h b/bsp/board/bl702dk/fw_header.h new file mode 100644 index 00000000..cd526995 --- /dev/null +++ b/bsp/board/bl702dk/fw_header.h @@ -0,0 +1,167 @@ +#ifndef __FW_HEADER_H__ +#define __FW_HEADER_H__ + +#include "stdint.h" +#include "stdio.h" + +struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ + uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +}; + +struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { + uint32_t magiccode; + struct spi_flash_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { + uint8_t xtal_type; + uint8_t pll_clk; + uint8_t hclk_div; + uint8_t bclk_div; + + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t rsvd[2]; +}; + +struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { + uint32_t magiccode; + struct sys_clk_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) aesiv_cfg_t { + uint8_t aesiv[16]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) pkey_cfg_t { + uint8_t eckeyx[32]; /* ec key in boot header */ + uint8_t eckeyy[32]; /* ec key in boot header */ + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sign_cfg_t { + uint32_t sig_len; + uint8_t signature[32]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) bootheader_t { + uint32_t magiccode; /*'BFXP'*/ + uint32_t rivison; + struct boot_flash_cfg_t flash_cfg; + struct boot_clk_cfg_t clk_cfg; + union __attribute__((packed, aligned(1))) { + struct __attribute__((packed, aligned(1))) { + uint32_t sign : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface */ + uint32_t rsvd_7_6 : 2; /* [7: 6] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t cache_select : 1; /* [9] cache enable */ + uint32_t notload_in_bootrom : 1; /* [10] not load this img in bootrom */ + uint32_t aes_region_lock : 1; /* [11] aes region lock */ + uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] ignore hash */ + uint32_t halt_ap : 1; /* [18] halt ap */ + uint32_t boot2_enable : 1; /* [19] boot2 enable */ + uint32_t boot2_rollback : 1; /* [20] boot2 rollback */ + uint32_t rsvd_31_21 : 11; /* [31: 21] rsvd */ + } bval; + uint32_t wval; + } boot_cfg; + + union __attribute__((packed, aligned(1))) { + uint32_t segment_cnt; + uint32_t img_len; + } img_segment_info; + + uint32_t rsvd0; /* rsvd */ + + union __attribute__((packed, aligned(1))) { + uint32_t ramaddr; + uint32_t flashoffset; + } img_start; + + uint32_t hash[32 / 4]; /*hash of the image*/ + + uint32_t boot2_pt_table_0; /* address of partition table 0 */ + uint32_t boot2_pt_table_1; /* address of partition table 1 */ + uint32_t crc32; +}; + +#endif \ No newline at end of file diff --git a/bsp/board/bl808dk/CMakeLists.txt b/bsp/board/bl808dk/CMakeLists.txt index 21a01bde..b56a9037 100644 --- a/bsp/board/bl808dk/CMakeLists.txt +++ b/bsp/board/bl808dk/CMakeLists.txt @@ -2,7 +2,16 @@ sdk_add_include_directories(.) target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/board.c) -sdk_set_linker_script(bl808_flash_${CPU_ID}.ld) +if(CONFIG_IOT) +# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/iot/fw_header.c) +sdk_set_linker_script(iot/bl808_flash_${CPU_ID}.ld) +# sdk_add_link_options(-ufw_header) +else() +# target_sources(app PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/mcu/fw_header.c) +sdk_set_linker_script(mcu/bl808_flash_${CPU_ID}.ld) +# sdk_add_link_options(-ufw_header0) +# sdk_add_link_options(-ufw_header1) +endif() if(CONFIG_PSRAM) sdk_add_compile_definitions(-DCONFIG_PSRAM) diff --git a/bsp/board/bl808dk/board.c b/bsp/board/bl808dk/board.c index 1fd7b80c..846b9f19 100644 --- a/bsp/board/bl808dk/board.c +++ b/bsp/board/bl808dk/board.c @@ -3,35 +3,24 @@ #include "bflb_clock.h" #include "bflb_rtc.h" #include "bflb_flash.h" -#ifdef CONFIG_TLSF -#include "bflb_tlsf.h" -#else -#include "bflb_mmheap.h" -#endif #include "bl808_glb.h" -#include "bl808_sflash.h" #include "bl808_psram_uhs.h" #include "bl808_tzc_sec.h" #include "bl808_ef_cfg.h" #include "bl808_uhs_phy.h" #include "board.h" +#include "mem.h" + #ifdef CONFIG_BSP_SDH_SDCARD #include "sdh_sdcard.h" #endif +extern void log_start(void); + extern uint32_t __HeapBase; extern uint32_t __HeapLimit; -#ifndef CONFIG_TLSF -struct heap_info mmheap_root; - -static struct heap_region system_mmheap[] = { - { NULL, 0 }, - { NULL, 0 }, /* Terminates the array. */ -}; -#endif - static struct bflb_device_s *uart0; #if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) @@ -94,13 +83,12 @@ static void peripheral_clock_init(void) BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val); GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH); #endif - GLB_Set_USB_CLK_From_WIFIPLL(1); - #ifdef CONFIG_BSP_CSI GLB_CSI_Config_MIPIPLL(2, 0x21000); GLB_CSI_Power_Up_MIPIPLL(); GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1); #endif + GLB_Set_USB_CLK_From_WIFIPLL(1); } #ifdef CONFIG_PSRAM @@ -175,7 +163,7 @@ void bl_show_log(void) void bl_show_flashinfo(void) { - SPI_Flash_Cfg_Type flashCfg; + spi_flash_cfg_type flashCfg; uint8_t *pFlashCfg = NULL; uint32_t flashCfgLen = 0; uint32_t flashJedecId = 0; @@ -186,17 +174,17 @@ void bl_show_flashinfo(void) printf("=========== flash cfg ==============\r\n"); printf("jedec id 0x%06X\r\n", flashJedecId); printf("mid 0x%02X\r\n", flashCfg.mid); - printf("iomode 0x%02X\r\n", flashCfg.ioMode); - printf("clk delay 0x%02X\r\n", flashCfg.clkDelay); - printf("clk invert 0x%02X\r\n", flashCfg.clkInvert); - printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]); - printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]); - printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]); - printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]); - printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen); - printf("cread support 0x%02X\r\n", flashCfg.cReadSupport); - printf("cread code 0x%02X\r\n", flashCfg.cReadMode); - printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd); + printf("iomode 0x%02X\r\n", flashCfg.io_mode); + printf("clk delay 0x%02X\r\n", flashCfg.clk_delay); + printf("clk invert 0x%02X\r\n", flashCfg.clk_invert); + printf("read reg cmd0 0x%02X\r\n", flashCfg.read_reg_cmd[0]); + printf("read reg cmd1 0x%02X\r\n", flashCfg.read_reg_cmd[1]); + printf("write reg cmd0 0x%02X\r\n", flashCfg.write_reg_cmd[0]); + printf("write reg cmd1 0x%02X\r\n", flashCfg.write_reg_cmd[1]); + printf("qe write len 0x%02X\r\n", flashCfg.qe_write_reg_len); + printf("cread support 0x%02X\r\n", flashCfg.c_read_support); + printf("cread code 0x%02X\r\n", flashCfg.c_read_mode); + printf("burst wrap cmd 0x%02X\r\n", flashCfg.burst_wrap_cmd); printf("=====================================\r\n"); } @@ -211,8 +199,9 @@ static void console_init() bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX); bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX); #elif defined(CPU_D0) - bflb_gpio_init(gpio, GPIO_PIN_8, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - //bflb_gpio_init(gpio, GPIO_PIN_9, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* sipeed m1s dock */ + bflb_gpio_init(gpio, GPIO_PIN_16, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_17, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); #endif struct bflb_uart_config_s cfg; cfg.baudrate = 2000000; @@ -234,50 +223,37 @@ static void console_init() #if defined(CPU_M0) void board_init(void) { + int ret = -1; uintptr_t flag; flag = bflb_irq_save(); - bflb_flash_init(); + ret = bflb_flash_init(); GLB_Halt_CPU(GLB_CORE_ID_D0); - GLB_Halt_CPU(GLB_CORE_ID_LP); system_clock_init(); peripheral_clock_init(); bflb_irq_initialize(); - GLB_Release_CPU(GLB_CORE_ID_D0); - GLB_Release_CPU(GLB_CORE_ID_LP); - - bflb_irq_restore(flag); - -#ifdef CONFIG_TLSF - bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase)); -#else - system_mmheap[0].addr = (uint8_t *)&__HeapBase; - system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); - - if (system_mmheap[0].mem_size > 0) { - bflb_mmheap_init(&mmheap_root, system_mmheap); - } -#endif - console_init(); + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); + bl_show_log(); + if (ret != 0) { + printf("flash init fail!!!\r\n"); + } bl_show_flashinfo(); -#ifdef CONFIG_TLSF - bflb_tlsf_size_container_t *tlsf_size = bflb_tlsf_stats(); - printf("TLSF Dynamic Memory Init Success: Heap Size = %d Kbyte, Used Size = %d Kbyte, Free Size = %d Kbyte\r\n", - tlsf_size->free + tlsf_size->used / 1024, tlsf_size->used / 1024, tlsf_size->free / 1024); -#else - printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024); -#endif + + printf("dynamic memory init success,heap size = %d Kbyte \r\n", ((size_t)&__HeapLimit - (size_t)&__HeapBase) / 1024); printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1)); printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2)); + log_start(); + #if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS)) rtc = bflb_device_get_by_name("rtc"); #endif @@ -288,6 +264,18 @@ void board_init(void) } } #endif + /* set CPU D0 boot XIP address and flash address */ + // Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1); + // /* D0 boot from 0x58000000 */ + // GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000); + // /* D0 image offset on flash is 0x100000+0x1000(header) */ + // bflb_sf_ctrl_set_flash_image_offset(0x101000, 1, SF_CTRL_FLASH_BANK0); + + bflb_irq_restore(flag); + + /* we do not check header at 0x10000, just boot */ + GLB_Release_CPU(GLB_CORE_ID_D0); + /* release d0 and then do can run */ BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG); BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG); @@ -300,16 +288,8 @@ void board_init(void) bflb_irq_initialize(); -#ifdef CONFIG_TLSF - bflb_mmheap_init((void *)&__HeapBase, ((size_t)&__HeapLimit - (size_t)&__HeapBase)); -#else - system_mmheap[0].addr = (uint8_t *)&__HeapBase; - system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase); - - if (system_mmheap[0].mem_size > 0) { - bflb_mmheap_init(&mmheap_root, system_mmheap); - } -#endif + size_t heap_len = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + kmem_init((void *)&__HeapBase, heap_len); console_init(); @@ -320,6 +300,8 @@ void board_init(void) printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1)); printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2)); printf("cgen1:%08x\r\n", getreg32(BFLB_GLB_CGEN1_BASE)); + + log_start(); } #endif @@ -502,25 +484,43 @@ void board_csi_gpio_init(void) gpio = bflb_device_get_by_name("gpio"); + GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V); +#if 1 /* sipeed m1s dock */ /* I2C GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - - /* Power down GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_set(gpio, GPIO_PIN_22); - - /* Reset GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - bflb_gpio_set(gpio, GPIO_PIN_21); + bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); /* MCLK GPIO */ - bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_33, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); - GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_1P20V); + /* Power down GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_40, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_reset(gpio, GPIO_PIN_40); + + /* Reset GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_41, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_mtimer_delay_us(20); + bflb_gpio_set(gpio, GPIO_PIN_41); +#else + /* I2C GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_21, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_init(gpio, GPIO_PIN_22, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* MCLK GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* Power down GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_6, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_gpio_reset(gpio, GPIO_PIN_6); + + /* Reset GPIO */ + bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + bflb_mtimer_delay_us(20); + bflb_gpio_set(gpio, GPIO_PIN_23); +#endif } -void board_iso11898_gpio_init(void) +void board_iso11898_gpio_init() { // struct bflb_device_s *gpio; @@ -576,4 +576,4 @@ __attribute__((weak)) uint32_t get_fattime(void) | ((uint32_t)tm.min << 5) /* Min 0 */ | ((uint32_t)tm.sec >> 1); /* Sec 0 */ } -#endif \ No newline at end of file +#endif diff --git a/bsp/board/bl808dk/iot/bl808_flash_d0.ld b/bsp/board/bl808dk/iot/bl808_flash_d0.ld new file mode 100644 index 00000000..5ef17d30 --- /dev/null +++ b/bsp/board/bl808dk/iot/bl808_flash_d0.ld @@ -0,0 +1,266 @@ +/**************************************************************************************** +* @file flash.ld +* +* @brief This file is the link script file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2021 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x0400; /* 1KB */ +HeapMinSize = 0x1000; /* 4KB */ + +MEMORY +{ + fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K + xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M + itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K + dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K + nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K + ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 32K + 32K + xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K +} + +SECTIONS +{ + .fw_header : + { + KEEP(*(.fw_header)) + } > fw_header_memory + + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(SORT_NONE(.init))) + + *(.text) + *(.text.*) + + /* section information for shell */ + . = ALIGN(8); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl808_glb*.o* \ + *bl808_glb_gpio*.o* \ + *bl808_pds*.o* \ + *bl808_aon*.o* \ + *bl808_hbn*.o* \ + *bl808_l1c*.o* \ + *bl808_common*.o* \ + *bl808_clock*.o* \ + *bl808_ef_ctrl*.o* \ + *bl808_sf_cfg*.o* \ + *bl808_sf_ctrl*.o* \ + *bl808_sflash*.o* \ + *bl808_xip_sflash*.o* \ + *bl808_romapi_patch*.o* ) .rodata*) + + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + + *bl808_glb*.o*(.rodata*) + *bl808_glb_gpio*.o*(.rodata*) + *bl808_pds*.o*(.rodata*) + *bl808_aon*.o*(.rodata*) + *bl808_hbn*.o*(.rodata*) + *bl808_l1c*.o*(.rodata*) + *bl808_common*.o*(.rodata*) + *bl808_clock*.o*(.rodata*) + *bl808_ef_ctrl*.o*(.rodata*) + *bl808_sf_cfg*.o*(.rodata*) + *bl808_sf_ctrl*.o*(.rodata*) + *bl808_sflash*.o*(.rodata*) + *bl808_xip_sflash*.o*(.rodata*) + *bl808_romapi_patch*.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr) + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > nocache_ram_memory + + __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + .system_ram_noinit_data_region (NOLOAD) : + { + . = ALIGN(4); + *(.system_ram_noinit) + + . = ALIGN(4); + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; + __ram_data_end__ = .; + } > ram_memory + + __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); + ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .nocache_noinit_ram_region (NOLOAD) : + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_noinit_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > nocache_ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") + +} + diff --git a/bsp/board/bl808dk/bl808_flash_m0.ld b/bsp/board/bl808dk/iot/bl808_flash_m0.ld similarity index 96% rename from bsp/board/bl808dk/bl808_flash_m0.ld rename to bsp/board/bl808dk/iot/bl808_flash_m0.ld index 3b5cfc94..371d716f 100644 --- a/bsp/board/bl808dk/bl808_flash_m0.ld +++ b/bsp/board/bl808dk/iot/bl808_flash_m0.ld @@ -22,6 +22,7 @@ HeapMinSize = 0x1000; /* 4KB */ MEMORY { + fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K @@ -32,6 +33,10 @@ MEMORY SECTIONS { + .fw_header : + { + KEEP(*(.fw_header)) + } > fw_header_memory .text : { @@ -202,6 +207,10 @@ SECTIONS *(.sdata2.*) . = ALIGN(4); + __bflog_tags_start__ = .; + *(.bflog_tags_array) + . = ALIGN(4); + __bflog_tags_end__ = .; __ram_data_end__ = .; } > ram_memory diff --git a/bsp/board/bl808dk/iot/fw_header.c b/bsp/board/bl808dk/iot/fw_header.c new file mode 100644 index 00000000..833d99d5 --- /dev/null +++ b/bsp/board/bl808dk/iot/fw_header.c @@ -0,0 +1,199 @@ +#include "fw_header.h" + +__attribute__((section(".fw_header"))) struct bootheader_t fw_header = { + .magiccode = 0x504e4642, + .rivison = 0x00000001, + /*flash config */ + .flash_cfg.magiccode = 0x47464346, + .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ + .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ + .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ + .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ + .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ + .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ + .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ + .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ + .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ + .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ + .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ + .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ + .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ + .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ + .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ + .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ + .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ + .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ + .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ + .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ + .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ + .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ + .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ + .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ + .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ + .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ + .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ + .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ + .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ + .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ + .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ + .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ + .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ + .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ + .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ + .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ + .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ + .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ + .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ + .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ + .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ + .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ + .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ + .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ + .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ + .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ + .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ + .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ + .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ + .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ + .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ + .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ + .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ + .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ + .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ + .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ + .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ + .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ + .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ + .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ + .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ + .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ + .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ + .flash_cfg.cfg.qeData = 0, /*!< QE set data */ + .flash_cfg.crc32 = 0xdeadbeef, + /* clock cfg */ + .clk_cfg.magiccode = 0x47464350, + .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ + .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */ + .clk_cfg.cfg.mcu_clk_div = 0x00, + .clk_cfg.cfg.mcu_bclk_div = 0x00, + + .clk_cfg.cfg.mcu_pbclk_div = 0x03, + .clk_cfg.cfg.lp_div = 0x01, + .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */ + .clk_cfg.cfg.dsp_clk_div = 0x00, + + .clk_cfg.cfg.dsp_bclk_div = 0x01, + .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */ + .clk_cfg.cfg.dsp_pbclk_div = 0x00, + .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ + + .clk_cfg.cfg.emi_clk_div = 0x01, + .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */ + .clk_cfg.cfg.flash_clk_div = 0x00, + .clk_cfg.cfg.wifipll_pu = 0x01, + + .clk_cfg.cfg.aupll_pu = 0x01, + .clk_cfg.cfg.cpupll_pu = 0x01, + .clk_cfg.cfg.mipipll_pu = 0x01, + .clk_cfg.cfg.uhspll_pu = 0x01, + + .clk_cfg.crc32 = 0xdeadbeef, + + /* basic cfg */ + .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ + .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ + .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ + .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ + .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ + .basic_cfg.no_segment = 0x1, /* [8] no segment info */ + .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ + .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ + .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ + .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ + .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ + .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ + .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ + .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ + .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ +#if 0 +# 0 : cmds bypass wrap commands to macro, original mode; +# 1 : cmds handle wrap commands, original mode; +# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; +# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 +#endif + .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ +#if 0 +# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, +# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 +#endif + .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ + .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ + .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ + .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ + + .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */ + .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ + + .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */ + .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ + + /* cpu cfg */ + .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */ + .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */ + .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */ + .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].rsvd = 0x0, + + .cpu_cfg[0].cache_range_h = 0x00000000, + .cpu_cfg[0].cache_range_l = 0x00000000, + /* image_address_offset */ + .cpu_cfg[0].image_address_offset = 0x0, + .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */ + .cpu_cfg[0].msp_val = 0x00000000, /* msp value */ + + /* cpu cfg */ + .cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */ + .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */ + .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */ + .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].rsvd = 0x0, + + .cpu_cfg[1].cache_range_h = 0x00000000, + .cpu_cfg[1].cache_range_l = 0x00000000, + /* image_address_offset */ + .cpu_cfg[1].image_address_offset = 0x0, + .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */ + .cpu_cfg[1].msp_val = 0x00000000, /* msp value */ + + /* address of partition table 0 */ /* 4 */ + .boot2_pt_table_0_rsvd = 0x00000000, + /* address of partition table 1 */ /* 4 */ + .boot2_pt_table_1_rsvd = 0x00000000, + + /* address of flashcfg table list */ /* 4 */ + .flash_cfg_table_addr = 0x00000000, + /* flashcfg table list len */ /* 4 */ + .flash_cfg_table_len = 0x00000000, + + .crc32 = 0xdeadbeef /* 4 */ +}; diff --git a/bsp/board/bl808dk/iot/fw_header.h b/bsp/board/bl808dk/iot/fw_header.h new file mode 100644 index 00000000..f9dbc39f --- /dev/null +++ b/bsp/board/bl808dk/iot/fw_header.h @@ -0,0 +1,210 @@ +#ifndef __FW_HEADER_H__ +#define __FW_HEADER_H__ + +#include "stdint.h" +#include "stdio.h" + +struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ + uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +}; + +struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { + uint32_t magiccode; + struct spi_flash_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { + uint8_t xtal_type; + uint8_t mcu_clk; + uint8_t mcu_clk_div; + uint8_t mcu_bclk_div; + + uint8_t mcu_pbclk_div; + uint8_t lp_div; + uint8_t dsp_clk; + uint8_t dsp_clk_div; + + uint8_t dsp_bclk_div; + uint8_t dsp_pbclk; + uint8_t dsp_pbclk_div; + uint8_t emi_clk; + + uint8_t emi_clk_div; + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t wifipll_pu; + + uint8_t aupll_pu; + uint8_t cpupll_pu; + uint8_t mipipll_pu; + uint8_t uhspll_pu; +}; + +struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { + uint32_t magiccode; + struct sys_clk_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) boot_basic_cfg_t { + uint32_t sign_type : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] key slot */ + uint32_t xts_mode : 1; /* [6] for xts mode */ + uint32_t aes_region_lock : 1; /* [7] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */ + uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */ + uint32_t cpu_master_id : 4; /* [14: 11] master id */ + uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash ignore */ + uint32_t power_on_mm : 1; /* [18] power on mm */ + uint32_t em_sel : 3; /* [21: 19] em_sel */ + uint32_t cmds_en : 1; /* [22] command spliter enable */ + uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ + uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ + uint32_t icache_invalid : 1; /* [29] icache invalid */ + uint32_t dcache_invalid : 1; /* [30] dcache invalid */ + uint32_t rsvd_3 : 1; /* [31] rsvd_3 */ + + uint32_t group_image_offset; /* flash controller offset */ + uint32_t aes_region_len; /* aes region length */ + + uint32_t img_len_cnt; /* image length or segment count */ + uint32_t hash[32 / 4]; /* hash of the image */ +}; + +struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t { + uint8_t config_enable; /* coinfig this cpu */ + uint8_t halt_cpu; /* halt this cpu */ + uint8_t cache_enable : 1; /* cache setting */ + uint8_t cache_wa : 1; /* cache setting */ + uint8_t cache_wb : 1; /* cache setting */ + uint8_t cache_wt : 1; /* cache setting */ + uint8_t cache_way_dis : 4; /* cache setting */ + uint8_t rsvd; + + uint32_t cache_range_h; /* cache range high */ + uint32_t cache_range_l; /* cache range low */ + + uint32_t image_address_offset; /* image_address_offset */ + uint32_t rsvd0; /* rsvd0 */ + uint32_t msp_val; /* msp value */ +}; + +struct __attribute__((packed, aligned(4))) aesiv_cfg_t { + uint8_t aesiv[16]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) pkey_cfg_t { + uint8_t eckeyx[32]; /* ec key in boot header */ + uint8_t eckeyy[32]; /* ec key in boot header */ + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sign_cfg_t { + uint32_t sig_len; + uint8_t signature[32]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) bootheader_t { + uint32_t magiccode; /* 4 */ + uint32_t rivison; /* 4 */ + + struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */ + struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */ + + struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */ + + struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */ + + uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */ + uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */ + + uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */ + uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */ + + uint32_t rsvd0[6]; /* rsvd */ + uint32_t rsvd1[6]; /* rsvd */ + + uint32_t rsvd3[5]; /* 4 */ + + uint32_t crc32; /* 4 */ +}; + +#endif \ No newline at end of file diff --git a/bsp/board/bl808dk/bl808_flash_d0.ld b/bsp/board/bl808dk/mcu/bl808_flash_d0.ld similarity index 97% rename from bsp/board/bl808dk/bl808_flash_d0.ld rename to bsp/board/bl808dk/mcu/bl808_flash_d0.ld index c7077ffc..f527e25a 100644 --- a/bsp/board/bl808dk/bl808_flash_d0.ld +++ b/bsp/board/bl808dk/mcu/bl808_flash_d0.ld @@ -22,6 +22,7 @@ HeapMinSize = 0x1000; /* 4KB */ MEMORY { + fw_header_memory (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K @@ -32,6 +33,10 @@ MEMORY SECTIONS { + .fw_header : + { + KEEP(*(.fw_header0)) + } > fw_header_memory .text : { diff --git a/bsp/board/bl808dk/mcu/bl808_flash_m0.ld b/bsp/board/bl808dk/mcu/bl808_flash_m0.ld new file mode 100644 index 00000000..0e16e8c6 --- /dev/null +++ b/bsp/board/bl808dk/mcu/bl808_flash_m0.ld @@ -0,0 +1,314 @@ +/**************************************************************************************** +* @file flash.ld +* +* @brief This file is the link script file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2021 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x0400; /* 1KB */ +HeapMinSize = 0x1000; /* 4KB */ + +MEMORY +{ + fw_header_memory0 (rx) : ORIGIN = 0x58000000 - 0x2000, LENGTH = 4K + fw_header_memory1 (rx) : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K + xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M + itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 20K + dtcm_memory (rx) : ORIGIN = 0x62025000, LENGTH = 4K + nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K + ram_memory (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K + xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K +} + +SECTIONS +{ + .fw_header0 : + { + KEEP(*(.fw_header0)) + } > fw_header_memory0 + + .fw_header1 : + { + KEEP(*(.fw_header1)) + } > fw_header_memory1 + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + + *(.text) + *(.text.*) + + /* section information for shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for usb usbh_class_info */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + . = ALIGN(4); + __usbh_class_info_end__ = .; + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl808_glb*.o* \ + *bl808_glb_gpio*.o* \ + *bl808_pds*.o* \ + *bl808_aon*.o* \ + *bl808_hbn*.o* \ + *bl808_l1c*.o* \ + *bl808_common*.o* \ + *bl808_clock*.o* \ + *bl808_ef_ctrl*.o* \ + *bl808_sf_cfg*.o* \ + *bl808_sf_ctrl*.o* \ + *bl808_sflash*.o* \ + *bl808_xip_sflash*.o* \ + *bl808_romapi_patch*.o* ) .rodata*) + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + + *bl808_glb*.o*(.rodata*) + *bl808_glb_gpio*.o*(.rodata*) + *bl808_pds*.o*(.rodata*) + *bl808_aon*.o*(.rodata*) + *bl808_hbn*.o*(.rodata*) + *bl808_l1c*.o*(.rodata*) + *bl808_common*.o*(.rodata*) + *bl808_clock*.o*(.rodata*) + *bl808_ef_ctrl*.o*(.rodata*) + *bl808_sf_cfg*.o*(.rodata*) + *bl808_sf_ctrl*.o*(.rodata*) + *bl808_sflash*.o*(.rodata*) + *bl808_xip_sflash*.o*(.rodata*) + *bl808_romapi_patch*.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + + /*************************************************************************/ + + __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .nocache_ram_region : AT (__nocache_ram_load_addr) + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > nocache_ram_memory + + __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + .system_ram_noinit_data_region (NOLOAD) : + { + . = ALIGN(4); + *(.system_ram_noinit) + + . = ALIGN(4); + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); + ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") + + .bss (NOLOAD) : + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .nocache_noinit_ram_region (NOLOAD) : + { + . = ALIGN(4); + __nocache_noinit_ram_data_start__ = .; + + *(.nocache_noinit_ram) + *(.noncacheable) + + . = ALIGN(4); + __nocache_noinit_ram_data_end__ = .; + } > nocache_ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") + + .psmram_data (NOLOAD): + { + . = ALIGN(4); + __psram_data_start__ = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.psram_data*)) + + . = ALIGN(4); + __psram_data_end__ = .; + } > ram_code + + .wifibss (NOLOAD) : + { + PROVIDE( __wifi_bss_start = ADDR(.wifibss) ); + PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) ); + _sshram = . ; + *(SHAREDRAMIPC) + *(SHAREDRAM) + _eshram = . ; + *ipc_shared.o(COMMON) + *sdu_shared.o(COMMON) + *hal_desc.o(COMMON) + *txl_buffer_shared.o(COMMON) + *txl_frame_shared.o(COMMON) + *scan_shared.o(COMMON) + *scanu_shared.o(COMMON) + *mfp_bip.o(COMMON) + *me_mic.o(COMMON) + *(.wifi_ram*) + . = ALIGN(16); + } > ram_wifi + + PROVIDE( _heap_wifi_start = . ); + PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start ); + +} + diff --git a/bsp/board/bl808dk/mcu/fw_header.c b/bsp/board/bl808dk/mcu/fw_header.c new file mode 100644 index 00000000..3a788bc5 --- /dev/null +++ b/bsp/board/bl808dk/mcu/fw_header.c @@ -0,0 +1,403 @@ +#include "fw_header.h" + +__attribute__((section(".fw_header0"))) struct bootheader_t fw_header0 = { + .magiccode = 0x504e4642, + .rivison = 0x00000001, + /*flash config */ + .flash_cfg.magiccode = 0x47464346, + .flash_cfg.cfg.ioMode = 0x11, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ + .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ + .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ + .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ + .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ + .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ + .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ + .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ + .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ + .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ + .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ + .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ + .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ + .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ + .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ + .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ + .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ + .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ + .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ + .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ + .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ + .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ + .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ + .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ + .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ + .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ + .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ + .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ + .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ + .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ + .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ + .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ + .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ + .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ + .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ + .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ + .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ + .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ + .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ + .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ + .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ + .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ + .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ + .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ + .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ + .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ + .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ + .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ + .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ + .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ + .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ + .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ + .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ + .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ + .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ + .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ + .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ + .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ + .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ + .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ + .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ + .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ + .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ + .flash_cfg.cfg.qeData = 0, /*!< QE set data */ + .flash_cfg.crc32 = 0xdeadbeef, + /* clock cfg */ + .clk_cfg.magiccode = 0x47464350, + .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ + .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */ + .clk_cfg.cfg.mcu_clk_div = 0x00, + .clk_cfg.cfg.mcu_bclk_div = 0x00, + + .clk_cfg.cfg.mcu_pbclk_div = 0x03, + .clk_cfg.cfg.lp_div = 0x01, + .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */ + .clk_cfg.cfg.dsp_clk_div = 0x00, + + .clk_cfg.cfg.dsp_bclk_div = 0x01, + .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */ + .clk_cfg.cfg.dsp_pbclk_div = 0x00, + .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ + + .clk_cfg.cfg.emi_clk_div = 0x01, + .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */ + .clk_cfg.cfg.flash_clk_div = 0x00, + .clk_cfg.cfg.wifipll_pu = 0x01, + + .clk_cfg.cfg.aupll_pu = 0x01, + .clk_cfg.cfg.cpupll_pu = 0x01, + .clk_cfg.cfg.mipipll_pu = 0x01, + .clk_cfg.cfg.uhspll_pu = 0x01, + + .clk_cfg.crc32 = 0xdeadbeef, + + /* basic cfg */ + .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ + .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ + .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ + .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ + .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ + .basic_cfg.no_segment = 0x1, /* [8] no segment info */ + .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ + .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ + .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ + .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ + .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ + .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ + .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ + .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ + .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ +#if 0 +# 0 : cmds bypass wrap commands to macro, original mode; +# 1 : cmds handle wrap commands, original mode; +# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; +# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 +#endif + .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ +#if 0 +# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, +# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 +#endif + .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ + .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ + .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ + .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ + + .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */ + .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ + + .basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */ + .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ + + /* cpu cfg */ + .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */ + .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */ + .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */ + .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].rsvd = 0x0, + + .cpu_cfg[0].cache_range_h = 0x00000000, + .cpu_cfg[0].cache_range_l = 0x00000000, + /* image_address_offset */ + .cpu_cfg[0].image_address_offset = 0x0, + .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */ + .cpu_cfg[0].msp_val = 0x00000000, /* msp value */ + + /* cpu cfg */ + .cpu_cfg[1].config_enable = 0x00, /* coinfig this cpu */ + .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */ + .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */ + .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].rsvd = 0x0, + + .cpu_cfg[1].cache_range_h = 0x00000000, + .cpu_cfg[1].cache_range_l = 0x00000000, + /* image_address_offset */ + .cpu_cfg[1].image_address_offset = 0x0, + .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */ + .cpu_cfg[1].msp_val = 0x00000000, /* msp value */ + + /* address of partition table 0 */ /* 4 */ + .boot2_pt_table_0_rsvd = 0x00000000, + /* address of partition table 1 */ /* 4 */ + .boot2_pt_table_1_rsvd = 0x00000000, + + /* address of flashcfg table list */ /* 4 */ + .flash_cfg_table_addr = 0x00000000, + /* flashcfg table list len */ /* 4 */ + .flash_cfg_table_len = 0x00000000, + + .rsvd1[0] = 0x20000320, + .rsvd1[1] = 0x00000000, + .rsvd1[2] = 0x2000F038, + .rsvd1[3] = 0x18000000, + + .crc32 = 0xdeadbeef /* 4 */ +}; + +__attribute__((section(".fw_header1"))) struct bootheader_t fw_header1 = { + .magiccode = 0x50414642, + .rivison = 0x00000001, + /*flash config */ + .flash_cfg.magiccode = 0x47464346, + .flash_cfg.cfg.ioMode = 0x10, /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + .flash_cfg.cfg.cReadSupport = 0x00, /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + .flash_cfg.cfg.clkDelay = 0x01, /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + .flash_cfg.cfg.clkInvert = 0x01, /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + .flash_cfg.cfg.resetEnCmd = 0x66, /*!< Flash enable reset command */ + .flash_cfg.cfg.resetCmd = 0x99, /*!< Flash reset command */ + .flash_cfg.cfg.resetCreadCmd = 0xff, /*!< Flash reset continuous read command */ + .flash_cfg.cfg.resetCreadCmdSize = 0x03, /*!< Flash reset continuous read command size */ + .flash_cfg.cfg.jedecIdCmd = 0x9f, /*!< JEDEC ID command */ + .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00, /*!< JEDEC ID command dummy clock */ + .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7, /*!< Enter 32-bits addr command */ + .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9, /*!< Exit 32-bits addr command */ + .flash_cfg.cfg.sectorSize = 0x04, /*!< *1024bytes */ + .flash_cfg.cfg.mid = 0x00, /*!< Manufacturer ID */ + .flash_cfg.cfg.pageSize = 0x100, /*!< Page size */ + .flash_cfg.cfg.chipEraseCmd = 0xc7, /*!< Chip erase cmd */ + .flash_cfg.cfg.sectorEraseCmd = 0x20, /*!< Sector erase command */ + .flash_cfg.cfg.blk32EraseCmd = 0x52, /*!< Block 32K erase command,some Micron not support */ + .flash_cfg.cfg.blk64EraseCmd = 0xd8, /*!< Block 64K erase command */ + .flash_cfg.cfg.writeEnableCmd = 0x06, /*!< Need before every erase or program */ + .flash_cfg.cfg.pageProgramCmd = 0x02, /*!< Page program cmd */ + .flash_cfg.cfg.qpageProgramCmd = 0x32, /*!< QIO page program cmd */ + .flash_cfg.cfg.qppAddrMode = 0x00, /*!< QIO page program address mode */ + .flash_cfg.cfg.fastReadCmd = 0x0b, /*!< Fast read command */ + .flash_cfg.cfg.frDmyClk = 0x01, /*!< Fast read command dummy clock */ + .flash_cfg.cfg.qpiFastReadCmd = 0x0b, /*!< QPI fast read command */ + .flash_cfg.cfg.qpiFrDmyClk = 0x01, /*!< QPI fast read command dummy clock */ + .flash_cfg.cfg.fastReadDoCmd = 0x3b, /*!< Fast read dual output command */ + .flash_cfg.cfg.frDoDmyClk = 0x01, /*!< Fast read dual output command dummy clock */ + .flash_cfg.cfg.fastReadDioCmd = 0xbb, /*!< Fast read dual io comamnd */ + .flash_cfg.cfg.frDioDmyClk = 0x00, /*!< Fast read dual io command dummy clock */ + .flash_cfg.cfg.fastReadQoCmd = 0x6b, /*!< Fast read quad output comamnd */ + .flash_cfg.cfg.frQoDmyClk = 0x01, /*!< Fast read quad output comamnd dummy clock */ + .flash_cfg.cfg.fastReadQioCmd = 0xeb, /*!< Fast read quad io comamnd */ + .flash_cfg.cfg.frQioDmyClk = 0x02, /*!< Fast read quad io comamnd dummy clock */ + .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb, /*!< QPI fast read quad io comamnd */ + .flash_cfg.cfg.qpiFrQioDmyClk = 0x02, /*!< QPI fast read QIO dummy clock */ + .flash_cfg.cfg.qpiPageProgramCmd = 0x02, /*!< QPI program command */ + .flash_cfg.cfg.writeVregEnableCmd = 0x50, /*!< Enable write reg */ + .flash_cfg.cfg.wrEnableIndex = 0x00, /*!< Write enable register index */ + .flash_cfg.cfg.qeIndex = 0x01, /*!< Quad mode enable register index */ + .flash_cfg.cfg.busyIndex = 0x00, /*!< Busy status register index */ + .flash_cfg.cfg.wrEnableBit = 0x01, /*!< Write enable bit pos */ + .flash_cfg.cfg.qeBit = 0x01, /*!< Quad enable bit pos */ + .flash_cfg.cfg.busyBit = 0x00, /*!< Busy status bit pos */ + .flash_cfg.cfg.wrEnableWriteRegLen = 0x02, /*!< Register length of write enable */ + .flash_cfg.cfg.wrEnableReadRegLen = 0x01, /*!< Register length of write enable status */ + .flash_cfg.cfg.qeWriteRegLen = 0x02, /*!< Register length of contain quad enable */ + .flash_cfg.cfg.qeReadRegLen = 0x01, /*!< Register length of contain quad enable status */ + .flash_cfg.cfg.releasePowerDown = 0xab, /*!< Release power down command */ + .flash_cfg.cfg.busyReadRegLen = 0x01, /*!< Register length of contain busy status */ + .flash_cfg.cfg.readRegCmd[0] = 0x05, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[1] = 0x35, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[2] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.readRegCmd[3] = 0x00, /*!< Read register command buffer */ + .flash_cfg.cfg.writeRegCmd[0] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[1] = 0x01, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[2] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.writeRegCmd[3] = 0x00, /*!< Write register command buffer */ + .flash_cfg.cfg.enterQpi = 0x38, /*!< Enter qpi command */ + .flash_cfg.cfg.exitQpi = 0xff, /*!< Exit qpi command */ + .flash_cfg.cfg.cReadMode = 0x20, /*!< Config data for continuous read mode */ + .flash_cfg.cfg.cRExit = 0xf0, /*!< Config data for exit continuous read mode */ + .flash_cfg.cfg.burstWrapCmd = 0x77, /*!< Enable burst wrap command */ + .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03, /*!< Enable burst wrap command dummy clock */ + .flash_cfg.cfg.burstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.burstWrapData = 0x40, /*!< Data to enable burst wrap */ + .flash_cfg.cfg.deBurstWrapCmd = 0x77, /*!< Disable burst wrap command */ + .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */ + .flash_cfg.cfg.deBurstWrapDataMode = 0x02, /*!< Data and address mode for this command */ + .flash_cfg.cfg.deBurstWrapData = 0xf0, /*!< Data to disable burst wrap */ + .flash_cfg.cfg.timeEsector = 300, /*!< 4K erase time */ + .flash_cfg.cfg.timeE32k = 1200, /*!< 32K erase time */ + .flash_cfg.cfg.timeE64k = 1200, /*!< 64K erase time */ + .flash_cfg.cfg.timePagePgm = 50, /*!< Page program time */ + .flash_cfg.cfg.timeCe = 30000, /*!< Chip erase time in ms */ + .flash_cfg.cfg.pdDelay = 20, /*!< Release power down command delay time for wake up */ + .flash_cfg.cfg.qeData = 0, /*!< QE set data */ + .flash_cfg.crc32 = 0xdeadbeef, + /* clock cfg */ + .clk_cfg.magiccode = 0x47464350, + .clk_cfg.cfg.xtal_type = 0x07, /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M */ + .clk_cfg.cfg.mcu_clk = 0x04, /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */ + .clk_cfg.cfg.mcu_clk_div = 0x00, + .clk_cfg.cfg.mcu_bclk_div = 0x00, + + .clk_cfg.cfg.mcu_pbclk_div = 0x03, + .clk_cfg.cfg.lp_div = 0x01, + .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */ + .clk_cfg.cfg.dsp_clk_div = 0x00, + + .clk_cfg.cfg.dsp_bclk_div = 0x01, + .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */ + .clk_cfg.cfg.dsp_pbclk_div = 0x00, + .clk_cfg.cfg.emi_clk = 0x02, /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */ + + .clk_cfg.cfg.emi_clk_div = 0x01, + .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */ + .clk_cfg.cfg.flash_clk_div = 0x00, + .clk_cfg.cfg.wifipll_pu = 0x01, + + .clk_cfg.cfg.aupll_pu = 0x01, + .clk_cfg.cfg.cpupll_pu = 0x01, + .clk_cfg.cfg.mipipll_pu = 0x01, + .clk_cfg.cfg.uhspll_pu = 0x01, + + .clk_cfg.crc32 = 0xdeadbeef, + + /* basic cfg */ + .basic_cfg.sign_type = 0x0, /* [1: 0] for sign */ + .basic_cfg.encrypt_type = 0x0, /* [3: 2] for encrypt */ + .basic_cfg.key_sel = 0x0, /* [5: 4] key slot */ + .basic_cfg.xts_mode = 0x0, /* [6] for xts mode */ + .basic_cfg.aes_region_lock = 0x0, /* [7] rsvd */ + .basic_cfg.no_segment = 0x1, /* [8] no segment info */ + .basic_cfg.rsvd_0 = 0x0, /* [9] boot2 enable(rsvd_0) */ + .basic_cfg.rsvd_1 = 0x0, /* [10] boot2 rollback(rsvd_1) */ + .basic_cfg.cpu_master_id = 0x0, /* [14: 11] master id */ + .basic_cfg.notload_in_bootrom = 0x0, /* [15] notload in bootrom */ + .basic_cfg.crc_ignore = 0x1, /* [16] ignore crc */ + .basic_cfg.hash_ignore = 0x1, /* [17] hash ignore */ + .basic_cfg.power_on_mm = 0x1, /* [18] power on mm */ + .basic_cfg.em_sel = 0x1, /* [21: 19] em_sel */ + .basic_cfg.cmds_en = 0x1, /* [22] command spliter enable */ +#if 0 +# 0 : cmds bypass wrap commands to macro, original mode; +# 1 : cmds handle wrap commands, original mode; +# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4; +# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4 +#endif + .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */ +#if 0 +# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32, +# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096 +#endif + .basic_cfg.cmds_wrap_len = 0x9, /* [28: 25] cmds wrap len */ + .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */ + .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */ + .basic_cfg.rsvd_3 = 0x0, /* [31] rsvd_3 */ + + .basic_cfg.group_image_offset = 0x00011000, /* flash controller offset */ + .basic_cfg.aes_region_len = 0x00000000, /* aes region length */ + + .basic_cfg.img_len_cnt = 0x00004000, /* image length or segment count */ + .basic_cfg.hash = { 0xdeadbeef }, /* hash of the image */ + + /* cpu cfg */ + .cpu_cfg[0].config_enable = 0x00, /* coinfig this cpu */ + .cpu_cfg[0].halt_cpu = 0x0, /* halt this cpu */ + .cpu_cfg[0].cache_enable = 0x0, /* cache setting :only for BL Cache */ + .cpu_cfg[0].cache_wa = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_wb = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_wt = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[0].rsvd = 0x0, + + .cpu_cfg[0].cache_range_h = 0x00000000, + .cpu_cfg[0].cache_range_l = 0x00000000, + /* image_address_offset */ + .cpu_cfg[0].image_address_offset = 0x0, + + .cpu_cfg[0].rsvd0 = 0x58000000, /* rsvd0 */ + .cpu_cfg[0].msp_val = 0x00000000, /* msp value */ + + /* cpu cfg */ + .cpu_cfg[1].config_enable = 0x01, /* coinfig this cpu */ + .cpu_cfg[1].halt_cpu = 0x0, /* halt this cpu */ + .cpu_cfg[1].cache_enable = 0x0, /* cache setting :only for BL Cache */ + .cpu_cfg[1].cache_wa = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_wb = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_wt = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/ + .cpu_cfg[1].rsvd = 0x0, + + .cpu_cfg[1].cache_range_h = 0x00000000, + .cpu_cfg[1].cache_range_l = 0x00000000, + /* image_address_offset */ + .cpu_cfg[1].image_address_offset = 0x0, + .cpu_cfg[1].rsvd0 = 0x58000000, /* rsvd0 */ + .cpu_cfg[1].msp_val = 0x00000000, /* msp value */ + + /* address of partition table 0 */ /* 4 */ + .boot2_pt_table_0_rsvd = 0x00000000, + /* address of partition table 1 */ /* 4 */ + .boot2_pt_table_1_rsvd = 0x00000000, + + /* address of flashcfg table list */ /* 4 */ + .flash_cfg_table_addr = 0x00000000, + /* flashcfg table list len */ /* 4 */ + .flash_cfg_table_len = 0x00000000, + + .crc32 = 0xdeadbeef /* 4 */ +}; diff --git a/bsp/board/bl808dk/mcu/fw_header.h b/bsp/board/bl808dk/mcu/fw_header.h new file mode 100644 index 00000000..f9dbc39f --- /dev/null +++ b/bsp/board/bl808dk/mcu/fw_header.h @@ -0,0 +1,210 @@ +#ifndef __FW_HEADER_H__ +#define __FW_HEADER_H__ + +#include "stdint.h" +#include "stdio.h" + +struct __attribute__((packed, aligned(4))) spi_flash_cfg_t { + uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ + uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t resetEnCmd; /*!< Flash enable reset command */ + uint8_t resetCmd; /*!< Flash reset command */ + uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ + uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ + uint8_t jedecIdCmd; /*!< JEDEC ID command */ + uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ + uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ + uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ + uint8_t sectorSize; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t pageSize; /*!< Page size */ + uint8_t chipEraseCmd; /*!< Chip erase cmd */ + uint8_t sectorEraseCmd; /*!< Sector erase command */ + uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64EraseCmd; /*!< Block 64K erase command */ + uint8_t writeEnableCmd; /*!< Need before every erase or program */ + uint8_t pageProgramCmd; /*!< Page program cmd */ + uint8_t qpageProgramCmd; /*!< QIO page program cmd */ + uint8_t qppAddrMode; /*!< QIO page program address mode */ + uint8_t fastReadCmd; /*!< Fast read command */ + uint8_t frDmyClk; /*!< Fast read command dummy clock */ + uint8_t qpiFastReadCmd; /*!< QPI fast read command */ + uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ + uint8_t fastReadDoCmd; /*!< Fast read dual output command */ + uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ + uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ + uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ + uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ + uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ + uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpiPageProgramCmd; /*!< QPI program command */ + uint8_t writeVregEnableCmd; /*!< Enable write reg */ + uint8_t wrEnableIndex; /*!< Write enable register index */ + uint8_t qeIndex; /*!< Quad mode enable register index */ + uint8_t busyIndex; /*!< Busy status register index */ + uint8_t wrEnableBit; /*!< Write enable bit pos */ + uint8_t qeBit; /*!< Quad enable bit pos */ + uint8_t busyBit; /*!< Busy status bit pos */ + uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ + uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ + uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ + uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ + uint8_t releasePowerDown; /*!< Release power down command */ + uint8_t busyReadRegLen; /*!< Register length of contain busy status */ + uint8_t readRegCmd[4]; /*!< Read register command buffer */ + uint8_t writeRegCmd[4]; /*!< Write register command buffer */ + uint8_t enterQpi; /*!< Enter qpi command */ + uint8_t exitQpi; /*!< Exit qpi command */ + uint8_t cReadMode; /*!< Config data for continuous read mode */ + uint8_t cRExit; /*!< Config data for exit continuous read mode */ + uint8_t burstWrapCmd; /*!< Enable burst wrap command */ + uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ + uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t burstWrapData; /*!< Data to enable burst wrap */ + uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ + uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ + uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ + uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ + uint16_t timeEsector; /*!< 4K erase time */ + uint16_t timeE32k; /*!< 32K erase time */ + uint16_t timeE64k; /*!< 64K erase time */ + uint16_t timePagePgm; /*!< Page program time */ + uint16_t timeCe; /*!< Chip erase time in ms */ + uint8_t pdDelay; /*!< Release power down command delay time for wake up */ + uint8_t qeData; /*!< QE set data */ +}; + +struct __attribute__((packed, aligned(4))) boot_flash_cfg_t { + uint32_t magiccode; + struct spi_flash_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sys_clk_cfg_t { + uint8_t xtal_type; + uint8_t mcu_clk; + uint8_t mcu_clk_div; + uint8_t mcu_bclk_div; + + uint8_t mcu_pbclk_div; + uint8_t lp_div; + uint8_t dsp_clk; + uint8_t dsp_clk_div; + + uint8_t dsp_bclk_div; + uint8_t dsp_pbclk; + uint8_t dsp_pbclk_div; + uint8_t emi_clk; + + uint8_t emi_clk_div; + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t wifipll_pu; + + uint8_t aupll_pu; + uint8_t cpupll_pu; + uint8_t mipipll_pu; + uint8_t uhspll_pu; +}; + +struct __attribute__((packed, aligned(4))) boot_clk_cfg_t { + uint32_t magiccode; + struct sys_clk_cfg_t cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) boot_basic_cfg_t { + uint32_t sign_type : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] key slot */ + uint32_t xts_mode : 1; /* [6] for xts mode */ + uint32_t aes_region_lock : 1; /* [7] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t rsvd_0 : 1; /* [9] boot2 enable(rsvd_0) */ + uint32_t rsvd_1 : 1; /* [10] boot2 rollback(rsvd_1) */ + uint32_t cpu_master_id : 4; /* [14: 11] master id */ + uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash ignore */ + uint32_t power_on_mm : 1; /* [18] power on mm */ + uint32_t em_sel : 3; /* [21: 19] em_sel */ + uint32_t cmds_en : 1; /* [22] command spliter enable */ + uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ + uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ + uint32_t icache_invalid : 1; /* [29] icache invalid */ + uint32_t dcache_invalid : 1; /* [30] dcache invalid */ + uint32_t rsvd_3 : 1; /* [31] rsvd_3 */ + + uint32_t group_image_offset; /* flash controller offset */ + uint32_t aes_region_len; /* aes region length */ + + uint32_t img_len_cnt; /* image length or segment count */ + uint32_t hash[32 / 4]; /* hash of the image */ +}; + +struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t { + uint8_t config_enable; /* coinfig this cpu */ + uint8_t halt_cpu; /* halt this cpu */ + uint8_t cache_enable : 1; /* cache setting */ + uint8_t cache_wa : 1; /* cache setting */ + uint8_t cache_wb : 1; /* cache setting */ + uint8_t cache_wt : 1; /* cache setting */ + uint8_t cache_way_dis : 4; /* cache setting */ + uint8_t rsvd; + + uint32_t cache_range_h; /* cache range high */ + uint32_t cache_range_l; /* cache range low */ + + uint32_t image_address_offset; /* image_address_offset */ + uint32_t rsvd0; /* rsvd0 */ + uint32_t msp_val; /* msp value */ +}; + +struct __attribute__((packed, aligned(4))) aesiv_cfg_t { + uint8_t aesiv[16]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) pkey_cfg_t { + uint8_t eckeyx[32]; /* ec key in boot header */ + uint8_t eckeyy[32]; /* ec key in boot header */ + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) sign_cfg_t { + uint32_t sig_len; + uint8_t signature[32]; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) bootheader_t { + uint32_t magiccode; /* 4 */ + uint32_t rivison; /* 4 */ + + struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */ + struct boot_clk_cfg_t clk_cfg; /* 4 + 20 + 4 */ + + struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */ + + struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */ + + uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */ + uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */ + + uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */ + uint32_t flash_cfg_table_len; /* flashcfg table list len */ /* 4 */ + + uint32_t rsvd0[6]; /* rsvd */ + uint32_t rsvd1[6]; /* rsvd */ + + uint32_t rsvd3[5]; /* 4 */ + + uint32_t crc32; /* 4 */ +}; + +#endif \ No newline at end of file diff --git a/bsp/common/CMakeLists.txt b/bsp/common/CMakeLists.txt index b75d36e7..073cc5bd 100644 --- a/bsp/common/CMakeLists.txt +++ b/bsp/common/CMakeLists.txt @@ -23,6 +23,7 @@ endif() if(CONFIG_BSP_LCD) target_sources(app PRIVATE lcd/lcd.c) target_sources(app PRIVATE lcd/font.c) + target_sources(app PRIVATE lcd/spi/ili9341_spi.c) target_sources(app PRIVATE lcd/spi/ili9488_spi.c) target_sources(app PRIVATE lcd/spi/st7796_spi.c) @@ -30,8 +31,19 @@ target_sources(app PRIVATE lcd/spi/st7789v_spi.c) sdk_add_include_directories(lcd) endif() +# touch sensor driver +if(CONFIG_BSP_TOUCH) +target_sources(app PRIVATE touch/touch.c) +target_sources(app PRIVATE touch/ft6x36_i2c.c) +target_sources(app PRIVATE touch/gt911_i2c.c) +sdk_add_include_directories(touch) +endif() + # image sensor driver if(CONFIG_BSP_IMAGE_SENSOR) target_sources(app PRIVATE image_sensor/image_sensor.c) sdk_add_include_directories(image_sensor) +if(CONFIG_BSP_CSI) +sdk_add_compile_definitions(-DCONFIG_BSP_CSI) +endif() endif() \ No newline at end of file diff --git a/bsp/common/image_sensor/gc2053.h b/bsp/common/image_sensor/gc2053.h index 70908901..78fd2434 100644 --- a/bsp/common/image_sensor/gc2053.h +++ b/bsp/common/image_sensor/gc2053.h @@ -26,6 +26,165 @@ #include "image_sensor.h" static struct image_sensor_command_s gc2053_init_list[] = { +#ifdef CONFIG_BSP_CSI + { 0xfe, 0x80 }, + { 0xfe, 0x80 }, + { 0xfe, 0x80 }, + { 0xfe, 0x00 }, + { 0xf2, 0x00 }, + { 0xf3, 0x00 }, + { 0xf4, 0x36 }, + { 0xf5, 0xc0 }, + { 0xf6, 0x84 }, + { 0xf7, 0x11 }, + { 0xf8, 0x37 }, + { 0xf9, 0x82 }, + { 0xfc, 0x8e }, + + { 0xfe, 0x00 },//mirror and flip + { 0x17, 0x83 }, + + { 0xfe, 0x00 }, + { 0x87, 0x18 }, + { 0xee, 0x30 }, + { 0xd0, 0xb7 }, + { 0x03, 0x04 }, + { 0x04, 0x60 }, + { 0x05, 0x04 }, + { 0x06, 0x4c }, + { 0x07, 0x00 }, + { 0x08, 0x64 }, + { 0x09, 0x00 }, + { 0x0a, 0x02 }, + { 0x0b, 0x00 }, + { 0x0c, 0x02 }, + { 0x0d, 0x04 }, + { 0x0e, 0x40 }, + { 0x12, 0xe2 }, + { 0x13, 0x16 }, + { 0x19, 0x0a }, + { 0x21, 0x1c }, + { 0x28, 0x0a }, + { 0x29, 0x24 }, + { 0x2b, 0x04 }, + { 0x32, 0xf8 }, + { 0x37, 0x03 }, + { 0x39, 0x15 }, + { 0x43, 0x07 }, + { 0x44, 0x40 }, + { 0x46, 0x0b }, + { 0x4b, 0x20 }, + { 0x4e, 0x08 }, + { 0x55, 0x20 }, + { 0x66, 0x05 }, + { 0x67, 0x05 }, + { 0x77, 0x01 }, + { 0x78, 0x00 }, + { 0x7c, 0x93 }, + { 0x8c, 0x12 }, + { 0x8d, 0x92 }, + { 0x90, 0x00 }, + { 0x41, 0x04 }, + { 0x42, 0xb0 }, + { 0x9d, 0x10 }, + { 0xce, 0x7c }, + { 0xd2, 0x41 }, + { 0xd3, 0xdc }, + { 0xe6, 0x50 }, + + { 0xb6, 0xc0 }, + { 0xb0, 0x70 }, + { 0xb1, 0x01 }, + { 0xb2, 0x00 }, + { 0xb3, 0x00 }, + { 0xb4, 0x00 }, + { 0xb8, 0x01 }, + { 0xb9, 0x00 }, + + { 0x26, 0x30 }, + { 0xfe, 0x01 }, + { 0x40, 0x23 }, + { 0x55, 0x07 }, + { 0x60, 0x40 }, + { 0xfe, 0x04 }, + { 0x14, 0x78 }, + { 0x15, 0x78 }, + { 0x16, 0x78 }, + { 0x17, 0x78 }, + + { 0xfe, 0x01 }, + { 0x92, 0x01 }, + { 0x94, 0x04 }, + { 0x95, 0x04 }, + { 0x96, 0x38 }, + { 0x97, 0x07 }, + { 0x98, 0x80 }, + /*skip frame*/ + { 0xfe, 0x01 }, + { 0x83, 0x01 }, + { 0x87, 0x50 },//0x50, skip 0, default:0x53,skip 3 + { 0xfe, 0x00 }, + + { 0xfe, 0x01 }, + { 0x01, 0x05 }, + { 0x02, 0x89 }, + { 0x04, 0x00 },//DD_en + { 0x07, 0xa6 }, + { 0x08, 0xa9 }, + { 0x09, 0xa8 }, + { 0x0a, 0xa7 }, + { 0x0b, 0xff }, + { 0x0c, 0xff }, + { 0x0f, 0x00 }, + { 0x50, 0x1c }, + { 0x89, 0x03 }, + { 0xfe, 0x04 }, + { 0x28, 0x86 }, + { 0x29, 0x86 }, + { 0x2a, 0x86 }, + { 0x2b, 0x68 }, + { 0x2c, 0x68 }, + { 0x2d, 0x68 }, + { 0x2e, 0x68 }, + { 0x2f, 0x68 }, + { 0x30, 0x4f }, + { 0x31, 0x68 }, + { 0x32, 0x67 }, + { 0x33, 0x66 }, + { 0x34, 0x66 }, + { 0x35, 0x66 }, + { 0x36, 0x66 }, + { 0x37, 0x66 }, + { 0x38, 0x62 }, + { 0x39, 0x62 }, + { 0x3a, 0x62 }, + { 0x3b, 0x62 }, + { 0x3c, 0x62 }, + { 0x3d, 0x62 }, + { 0x3e, 0x62 }, + { 0x3f, 0x62 }, + + { 0xfe, 0x01 }, + //{ 0x8c, 0x01 }, // test mode + { 0x9a, 0x06 }, + { 0xfe, 0x00 }, + { 0x7b, 0x2a }, + //{ 0x22, 0x0a }, // jz tmp + { 0x23, 0x2d }, + { 0xfe, 0x03 }, + { 0x01, 0x27 }, + { 0x02, 0x56 }, + //{ 0x03, 0xb6 }, // default is 0xb6 + { 0x03, 0x8e }, + { 0x12, 0x80 }, + { 0x13, 0x07 }, + { 0x15, 0x12 }, + + { 0xfe, 0x01 }, + { 0x8c, 0x10 }, + { 0xfe, 0x00 }, + { 0x3e, 0x91 }, +#else { 0xfe, 0x80 }, // page select { 0xfe, 0x80 }, { 0xfe, 0x80 }, @@ -155,7 +314,7 @@ static struct image_sensor_command_s gc2053_init_list[] = { { 0x3f, 0x62 }, /****DVP & MIPI****/ { 0xfe, 0x01 }, - // {0x8c,0x01}, // test mode + //{0x8c,0x01}, // test mode //{0x9a,0x06}, /* VSYNC low pulse */ { 0x9a, 0x02 }, /* VSYNC high pulse */ { 0xfe, 0x00 }, @@ -170,6 +329,7 @@ static struct image_sensor_command_s gc2053_init_list[] = { { 0xfe, 0x00 }, { 0x3e, 0x40 }, +#endif }; static struct image_sensor_config_s gc2053_config = { @@ -183,7 +343,11 @@ static struct image_sensor_config_s gc2053_config = { .resolution_y = 1080, .id_addr = 0xf0f1, .id_value = 0x2053, +#ifdef CONFIG_BSP_CSI + .pixel_clock = 66000000, +#else .pixel_clock = 24000000, +#endif .init_list_len = sizeof(gc2053_init_list)/sizeof(gc2053_init_list[0]), .init_list = gc2053_init_list, }; diff --git a/bsp/common/image_sensor/image_sensor.c b/bsp/common/image_sensor/image_sensor.c index b103f86b..03906b44 100644 --- a/bsp/common/image_sensor/image_sensor.c +++ b/bsp/common/image_sensor/image_sensor.c @@ -25,16 +25,18 @@ #include "gc0308.h" #include "gc0328.h" #include "gc2053.h" +#include "ov2685.h" #include "bflb_i2c.h" static struct image_sensor_config_s *sensor_list[] = { - NULL, &bf2013_config, &gc0308_config, &gc0328_config, &gc2053_config + NULL, &bf2013_config, &gc0308_config, &gc0328_config, &gc2053_config, &ov2685_config }; void image_sensor_read(struct bflb_device_s *i2c, uint32_t sensor_index, struct image_sensor_command_s *read_list, uint32_t list_len) { uint32_t i; struct bflb_i2c_msg_s msgs[2]; + uint8_t buffer[2]; msgs[0].addr = sensor_list[sensor_index]->slave_addr; msgs[0].flags = I2C_M_NOSTOP; @@ -47,7 +49,14 @@ void image_sensor_read(struct bflb_device_s *i2c, uint32_t sensor_index, struct msgs[1].length = 1; for(i=0;ireg_size == 1) { + buffer[0] = read_list[i].address & 0xff; + } else { + buffer[0] = read_list[i].address >> 8; + buffer[1] = read_list[i].address & 0xff; + } + + msgs[0].buffer = buffer; msgs[1].buffer = &read_list[i].paramete; bflb_i2c_transfer(i2c, msgs, 2); } @@ -57,6 +66,7 @@ void image_sensor_write(struct bflb_device_s *i2c, uint32_t sensor_index, struct { uint32_t i; struct bflb_i2c_msg_s msgs[2]; + uint8_t buffer[2]; msgs[0].addr = sensor_list[sensor_index]->slave_addr; msgs[0].flags = I2C_M_NOSTOP; @@ -69,7 +79,14 @@ void image_sensor_write(struct bflb_device_s *i2c, uint32_t sensor_index, struct msgs[1].length = 1; for(i=0;ireg_size == 1) { + buffer[0] = read_list[i].address & 0xff; + } else { + buffer[0] = read_list[i].address >> 8; + buffer[1] = read_list[i].address & 0xff; + } + + msgs[0].buffer = buffer; msgs[1].buffer = &read_list[i].paramete; bflb_i2c_transfer(i2c, msgs, 2); } diff --git a/bsp/common/image_sensor/ov2685.h b/bsp/common/image_sensor/ov2685.h new file mode 100644 index 00000000..dbbe8341 --- /dev/null +++ b/bsp/common/image_sensor/ov2685.h @@ -0,0 +1,296 @@ +/** + * @file image_sensor.h + * @brief + * + * Copyright (c) 2022 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef __OV2685_H__ +#define __OV2685_H__ + +#include "image_sensor.h" + +static struct image_sensor_command_s ov2685_init_list[] = { + {0x0103, 0x0001}, + {0xffff, 0x0005}, + {0x3002, 0x0000}, + {0x3016, 0x001c}, + {0x3018, 0x0084}, + {0x301d, 0x00f0}, + {0x3020, 0x0000}, + {0x3082, 0x002c}, + {0x3083, 0x0003}, + {0x3084, 0x0007}, + {0x3085, 0x0003}, + {0x3086, 0x0000}, + {0x3087, 0x0000}, + {0x3501, 0x004e}, + {0x3502, 0x00e0}, + {0x3503, 0x0003}, + {0x350b, 0x0036}, + {0x3600, 0x00b4}, + {0x3603, 0x0035}, + {0x3604, 0x0024}, + {0x3605, 0x0000}, + {0x3620, 0x0024}, + {0x3621, 0x0034}, + {0x3622, 0x0003}, + {0x3628, 0x0010}, + {0x3705, 0x003c}, + {0x370a, 0x0021}, + {0x370c, 0x0050}, + {0x370d, 0x00c0}, + {0x3717, 0x0058}, + {0x3718, 0x0080}, + {0x3720, 0x0000}, + {0x3721, 0x0009}, + {0x3722, 0x0006}, + {0x3723, 0x0059}, + {0x3738, 0x0099}, + {0x3781, 0x0080}, + {0x3784, 0x000c}, + {0x3789, 0x0060}, + {0x3800, 0x0000}, + {0x3801, 0x0000}, + {0x3802, 0x0000}, + {0x3803, 0x0000}, + {0x3804, 0x0006}, + {0x3805, 0x004f}, + {0x3806, 0x0004}, + {0x3807, 0x00bf}, + {0x3808, 0x0006}, + {0x3809, 0x0040}, + {0x380a, 0x0004}, + {0x380b, 0x00b0}, + {0x380c, 0x0006}, + {0x380d, 0x00a4}, + {0x380e, 0x0005}, + {0x380f, 0x000e}, + {0x3810, 0x0000}, + {0x3811, 0x0008}, + {0x3812, 0x0000}, + {0x3813, 0x0008}, + {0x3814, 0x0011}, + {0x3815, 0x0011}, + {0x3819, 0x0004}, + {0x3820, 0x00c0}, + {0x3821, 0x0000}, + {0x3a06, 0x0001}, + {0x3a07, 0x0084}, + {0x3a08, 0x0001}, + {0x3a09, 0x0043}, + {0x3a0a, 0x0024}, + {0x3a0b, 0x0060}, + {0x3a0c, 0x0028}, + {0x3a0d, 0x0060}, + {0x3a0e, 0x0004}, + {0x3a0f, 0x008c}, + {0x3a10, 0x0005}, + {0x3a11, 0x000c}, + {0x4000, 0x0081}, + {0x4001, 0x0040}, + {0x4008, 0x0002}, + {0x4009, 0x0009}, + {0x4300, 0x0032},//output format + {0x430e, 0x0000}, + {0x4602, 0x0002}, + {0x4837, 0x001e}, + {0x5000, 0x00ff}, + {0x5001, 0x0005}, + {0x5002, 0x0032}, + {0x5003, 0x0004}, + {0x5004, 0x00ff}, + {0x5005, 0x0012}, + //{0x5080, 0x0092},//test pattern + {0x0100, 0x0001}, + {0x0101, 0x0001}, + {0x1000, 0x0003}, + {0x0129, 0x0010}, + {0x5180, 0x00f4}, + {0x5181, 0x0011}, + {0x5182, 0x0041}, + {0x5183, 0x0042}, + {0x5184, 0x0078}, + {0x5185, 0x0058}, + {0x5186, 0x00b5}, + {0x5187, 0x00b2}, + {0x5188, 0x0008}, + {0x5189, 0x000e}, + {0x518a, 0x000c}, + {0x518b, 0x004c}, + {0x518c, 0x0038}, + {0x518d, 0x00f8}, + {0x518e, 0x0004}, + {0x518f, 0x007f}, + {0x5190, 0x0040}, + {0x5191, 0x005f}, + {0x5192, 0x0040}, + {0x5193, 0x00ff}, + {0x5194, 0x0040}, + {0x5195, 0x0007}, + {0x5196, 0x0004}, + {0x5197, 0x0004}, + {0x5198, 0x0000}, + {0x5199, 0x0005}, + {0x519a, 0x00d2}, + {0x519b, 0x0010}, + {0x5200, 0x0009}, + {0x5201, 0x0000}, + {0x5202, 0x0006}, + {0x5203, 0x0020}, + {0x5204, 0x0041}, + {0x5205, 0x0016}, + {0x5206, 0x0000}, + {0x5207, 0x0005}, + {0x520b, 0x0030}, + {0x520c, 0x0075}, + {0x520d, 0x0000}, + {0x520e, 0x0030}, + {0x520f, 0x0075}, + {0x5210, 0x0000}, + {0x5280, 0x0014}, + {0x5281, 0x0002}, + {0x5282, 0x0002}, + {0x5283, 0x0004}, + {0x5284, 0x0006}, + {0x5285, 0x0008}, + {0x5286, 0x000c}, + {0x5287, 0x0010}, + {0x5300, 0x00c5}, + {0x5301, 0x00a0}, + {0x5302, 0x0006}, + {0x5303, 0x000a}, + {0x5304, 0x0030}, + {0x5305, 0x0060}, + {0x5306, 0x0090}, + {0x5307, 0x00c0}, + {0x5308, 0x0082}, + {0x5309, 0x0000}, + {0x530a, 0x0026}, + {0x530b, 0x0002}, + {0x530c, 0x0002}, + {0x530d, 0x0000}, + {0x530e, 0x000c}, + {0x530f, 0x0014}, + {0x5310, 0x001a}, + {0x5311, 0x0020}, + {0x5312, 0x0080}, + {0x5313, 0x004b}, + {0x5380, 0x0001}, + {0x5381, 0x0052}, + {0x5382, 0x0000}, + {0x5383, 0x004a}, + {0x5384, 0x0000}, + {0x5385, 0x00b6}, + {0x5386, 0x0000}, + {0x5387, 0x008d}, + {0x5388, 0x0000}, + {0x5389, 0x003a}, + {0x538a, 0x0000}, + {0x538b, 0x00a6}, + {0x538c, 0x0000}, + {0x5400, 0x000d}, + {0x5401, 0x0018}, + {0x5402, 0x0031}, + {0x5403, 0x005a}, + {0x5404, 0x0065}, + {0x5405, 0x006f}, + {0x5406, 0x0077}, + {0x5407, 0x0080}, + {0x5408, 0x0087}, + {0x5409, 0x008f}, + {0x540a, 0x00a2}, + {0x540b, 0x00b2}, + {0x540c, 0x00cc}, + {0x540d, 0x00e4}, + {0x540e, 0x00f0}, + {0x540f, 0x00a0}, + {0x5410, 0x006e}, + {0x5411, 0x0006}, + {0x5480, 0x0019}, + {0x5481, 0x0000}, + {0x5482, 0x0009}, + {0x5483, 0x0012}, + {0x5484, 0x0004}, + {0x5485, 0x0006}, + {0x5486, 0x0008}, + {0x5487, 0x000c}, + {0x5488, 0x0010}, + {0x5489, 0x0018}, + {0x5500, 0x0002}, + {0x5501, 0x0003}, + {0x5502, 0x0004}, + {0x5503, 0x0005}, + {0x5504, 0x0006}, + {0x5505, 0x0008}, + {0x5506, 0x0000}, + {0x5600, 0x0002}, + {0x5603, 0x0040}, + {0x5604, 0x0028}, + {0x5609, 0x0020}, + {0x560a, 0x0060}, + {0x5800, 0x0003}, + {0x5801, 0x0024}, + {0x5802, 0x0002}, + {0x5803, 0x0040}, + {0x5804, 0x0034}, + {0x5805, 0x0005}, + {0x5806, 0x0012}, + {0x5807, 0x0005}, + {0x5808, 0x0003}, + {0x5809, 0x003c}, + {0x580a, 0x0002}, + {0x580b, 0x0040}, + {0x580c, 0x0026}, + {0x580d, 0x0005}, + {0x580e, 0x0052}, + {0x580f, 0x0006}, + {0x5810, 0x0003}, + {0x5811, 0x0028}, + {0x5812, 0x0002}, + {0x5813, 0x0040}, + {0x5814, 0x0024}, + {0x5815, 0x0005}, + {0x5816, 0x0042}, + {0x5817, 0x0006}, + {0x5818, 0x000d}, + {0x5819, 0x0040}, + {0x581a, 0x0004}, + {0x581b, 0x000c}, + {0x3a03, 0x004c}, + {0x3a04, 0x0040}, + {0x3503, 0x0000}, +}; + +static struct image_sensor_config_s ov2685_config = { + .name = "OV2685", + .output_format = IMAGE_SENSOR_FORMAT_YUV422_YUYV, + .slave_addr = 0x3c, + .id_size = 2, + .reg_size = 2, + .h_blank = 0xde, + .resolution_x = 1600, + .resolution_y = 1200, + .id_addr = 0x300a300b, + .id_value = 0x2685, + .pixel_clock = 66000000, + .init_list_len = sizeof(ov2685_init_list)/sizeof(ov2685_init_list[0]), + .init_list = ov2685_init_list, +}; + +#endif /* __OV2685_H__ */ diff --git a/bsp/common/touch/ft6x36_i2c.c b/bsp/common/touch/ft6x36_i2c.c new file mode 100644 index 00000000..67d91a7e --- /dev/null +++ b/bsp/common/touch/ft6x36_i2c.c @@ -0,0 +1,165 @@ +/** + * @file ft6x36_i2c.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "touch.h" + +#ifdef TOUCH_I2C_FT6X36 +#include "bflb_mtimer.h" +#include "bflb_gpio.h" +#include "bflb_i2c.h" +#include "ft6x36_i2c.h" + +static struct bflb_device_s *touch_ft6x36_i2c = NULL; + +static void ft6x36_i2c_gpio_init(void) +{ + struct bflb_device_s *ft63x6_i2c_gpio = NULL; + ft63x6_i2c_gpio = bflb_device_get_by_name("gpio"); + + /* I2C0_SCL */ + bflb_gpio_init(ft63x6_i2c_gpio, GPIO_PIN_10, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + /* I2C0_SDA */ + bflb_gpio_init(ft63x6_i2c_gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); +} + +static int ft6x36_i2c_peripheral_init(void) +{ + touch_ft6x36_i2c = bflb_device_get_by_name("i2c0"); + + if (touch_ft6x36_i2c) { + // printf("ft6x36 i2c gpio init\r\n"); + /* init i2c gpio */ + ft6x36_i2c_gpio_init(); + /* init i2c 200k */ + bflb_i2c_init(touch_ft6x36_i2c, 200000); + } else { + printf("i2c device get fail\r\n"); + return -1; + } + + return 0; +} + +static int ft6x36_i2c_read_byte(uint8_t register_addr, uint8_t *data_buf, uint16_t len) +{ + static struct bflb_i2c_msg_s msg[2]; + + msg[0].addr = FT6236_I2C_SLAVE_ADDR; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®ister_addr; + msg[0].length = 1; + + msg[1].flags = I2C_M_READ; + msg[1].buffer = data_buf; + msg[1].length = len; + bflb_i2c_transfer(touch_ft6x36_i2c, msg, 2); + + return 0; +} + +int ft6x36_get_gesture_id() +{ + uint8_t data_buf = FT6X36_GEST_ID_NO_GESTURE; + + if (ft6x36_i2c_read_byte(FT6X36_GEST_ID_REG, &data_buf, 1)) { + return -1; + } + + return data_buf; +} + +int ft6x36_i2c_init(touch_coord_t *max_value) +{ + uint8_t data_buf; + printf("ft6x36 i2c init\r\n"); + + ft6x36_i2c_peripheral_init(); + + if (ft6x36_i2c_read_byte(FT6X36_PANEL_ID_REG, &data_buf, 1)) { + return -1; + } + printf("Touch Device ID: 0x%02x\r\n", data_buf); + + if (ft6x36_i2c_read_byte(FT6X36_CHIPSELECT_REG, &data_buf, 1)) { + return -1; + } + printf("Touch Chip ID: 0x%02x\r\n", data_buf); + + if (ft6x36_i2c_read_byte(FT6X36_DEV_MODE_REG, &data_buf, 1)) { + return -1; + } + printf("Touch Device mode: 0x%02x\r\n", data_buf); + + if (ft6x36_i2c_read_byte(FT6X36_FIRMWARE_ID_REG, &data_buf, 1)) { + return -1; + } + printf("Touch Firmware ID: 0x%02x\r\n", data_buf); + + if (ft6x36_i2c_read_byte(FT6X36_RELEASECODE_REG, &data_buf, 1)) { + return -1; + } + printf("Touch Release code: 0x%02x\r\n", data_buf); + + return 0; +} + +int ft6x36_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num) +{ + uint8_t data_buf[5]; + *point_num = 0; + + if (point_num == NULL || touch_coord == NULL || max_num == 0) { + return -1; + } + + if (ft6x36_i2c_read_byte(FT6X36_TD_STAT_REG, &data_buf[0], 1)) { + return -1; + } + data_buf[0] &= FT6X36_TD_STAT_MASK; + + /* no touch or err */ + if (data_buf[0] == 0 || data_buf[0] > 2) { + if (data_buf[0] > 2) { + return -2; + } else { + return 0; + } + } + + /* Get the first point */ + ft6x36_i2c_read_byte(FT6X36_P1_XH_REG, &data_buf[1], 4); + touch_coord[0].coord_x = (data_buf[1] & FT6X36_MSB_MASK) << 8 | (data_buf[2] & FT6X36_LSB_MASK); + touch_coord[0].coord_y = (data_buf[3] & FT6X36_MSB_MASK) << 8 | (data_buf[4] & FT6X36_LSB_MASK); + *point_num = 1; + + /* Get the second point */ + if (data_buf[0] > 1 && max_num > 1) { + ft6x36_i2c_read_byte(FT6X36_P2_XH_REG, &data_buf[1], 4); + touch_coord[1].coord_x = (data_buf[1] & FT6X36_MSB_MASK) << 8 | (data_buf[2] & FT6X36_LSB_MASK); + touch_coord[1].coord_y = (data_buf[3] & FT6X36_MSB_MASK) << 8 | (data_buf[4] & FT6X36_LSB_MASK); + *point_num = 2; + } + return 0; +} + +#endif diff --git a/bsp/common/touch/ft6x36_i2c.h b/bsp/common/touch/ft6x36_i2c.h new file mode 100644 index 00000000..443b3faa --- /dev/null +++ b/bsp/common/touch/ft6x36_i2c.h @@ -0,0 +1,140 @@ +/** + * @file ft6x36_i2c.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _FT6X36_I2C_H +#define _FT6X36_I2C_H + +#include "bflb_core.h" +#include "touch.h" + +#define FT6236_I2C_SLAVE_ADDR 0x38 + +/* Maximum border values of the touchscreen pad that the chip can handle */ +#define FT6X36_MAX_WIDTH ((uint16_t)800) +#define FT6X36_MAX_HEIGHT ((uint16_t)480) + +/* Max detectable simultaneous touch points */ +#define FT6X36_I2C_MAX_POINT 2 + +/* Register of the current mode */ +#define FT6X36_DEV_MODE_REG 0x00 + +/* Possible modes as of FT6X36_DEV_MODE_REG */ +#define FT6X36_DEV_MODE_WORKING 0x00 +#define FT6X36_DEV_MODE_FACTORY 0x04 + +#define FT6X36_DEV_MODE_MASK 0x70 +#define FT6X36_DEV_MODE_SHIFT 4 + +/* Gesture ID register */ +#define FT6X36_GEST_ID_REG 0x01 + +/* Possible values returned by FT6X36_GEST_ID_REG */ +#define FT6X36_GEST_ID_NO_GESTURE 0x00 +#define FT6X36_GEST_ID_MOVE_UP 0x10 +#define FT6X36_GEST_ID_MOVE_RIGHT 0x14 +#define FT6X36_GEST_ID_MOVE_DOWN 0x18 +#define FT6X36_GEST_ID_MOVE_LEFT 0x1C +#define FT6X36_GEST_ID_ZOOM_IN 0x48 +#define FT6X36_GEST_ID_ZOOM_OUT 0x49 + +/* Status register: stores number of active touch points (0, 1, 2) */ +#define FT6X36_TD_STAT_REG 0x02 +#define FT6X36_TD_STAT_MASK 0x0F +#define FT6X36_TD_STAT_SHIFT 0x00 + +/* Touch events */ +#define FT6X36_TOUCH_EVT_FLAG_PRESS_DOWN 0x00 +#define FT6X36_TOUCH_EVT_FLAG_LIFT_UP 0x01 +#define FT6X36_TOUCH_EVT_FLAG_CONTACT 0x02 +#define FT6X36_TOUCH_EVT_FLAG_NO_EVENT 0x03 + +#define FT6X36_TOUCH_EVT_FLAG_SHIFT 6 +#define FT6X36_TOUCH_EVT_FLAG_MASK (3 << FT6X36_TOUCH_EVT_FLAG_SHIFT) + +#define FT6X36_MSB_MASK 0x0F +#define FT6X36_MSB_SHIFT 0 +#define FT6X36_LSB_MASK 0xFF +#define FT6X36_LSB_SHIFT 0 + +#define FT6X36_P1_XH_REG 0x03 +#define FT6X36_P1_XL_REG 0x04 +#define FT6X36_P1_YH_REG 0x05 +#define FT6X36_P1_YL_REG 0x06 + +#define FT6X36_P1_WEIGHT_REG 0x07 /* Register reporting touch pressure - read only */ +#define FT6X36_TOUCH_WEIGHT_MASK 0xFF +#define FT6X36_TOUCH_WEIGHT_SHIFT 0 + +#define FT6X36_P1_MISC_REG 0x08 /* Touch area register */ + +#define FT6X36_TOUCH_AREA_MASK (0x04 << 4) /* Values related to FT6X36_Pn_MISC_REG */ +#define FT6X36_TOUCH_AREA_SHIFT 0x04 + +#define FT6X36_P2_XH_REG 0x09 +#define FT6X36_P2_XL_REG 0x0A +#define FT6X36_P2_YH_REG 0x0B +#define FT6X36_P2_YL_REG 0x0C +#define FT6X36_P2_WEIGHT_REG 0x0D +#define FT6X36_P2_MISC_REG 0x0E + +/* Threshold for touch detection */ +#define FT6X36_TH_GROUP_REG 0x80 +#define FT6X36_THRESHOLD_MASK 0xFF /* Values FT6X36_TH_GROUP_REG : threshold related */ +#define FT6X36_THRESHOLD_SHIFT 0 + +#define FT6X36_TH_DIFF_REG 0x85 /* Filter function coefficients */ + +#define FT6X36_CTRL_REG 0x86 /* Control register */ + +#define FT6X36_CTRL_KEEP_ACTIVE_MODE 0x00 /* Will keep the Active mode when there is no touching */ +#define FT6X36_CTRL_KEEP_AUTO_SWITCH_MONITOR_MODE 0x01 /* Switching from Active mode to Monitor mode automatically when there is no touching */ + +#define FT6X36_TIME_ENTER_MONITOR_REG 0x87 /* The time period of switching from Active mode to Monitor mode when there is no touching */ + +#define FT6X36_PERIOD_ACTIVE_REG 0x88 /* Report rate in Active mode */ +#define FT6X36_PERIOD_MONITOR_REG 0x89 /* Report rate in Monitor mode */ + +#define FT6X36_RADIAN_VALUE_REG 0x91 /* The value of the minimum allowed angle while Rotating gesture mode */ + +#define FT6X36_OFFSET_LEFT_RIGHT_REG 0x92 /* Maximum offset while Moving Left and Moving Right gesture */ +#define FT6X36_OFFSET_UP_DOWN_REG 0x93 /* Maximum offset while Moving Up and Moving Down gesture */ + +#define FT6X36_DISTANCE_LEFT_RIGHT_REG 0x94 /* Minimum distance while Moving Left and Moving Right gesture */ +#define FT6X36_DISTANCE_UP_DOWN_REG 0x95 /* Minimum distance while Moving Up and Moving Down gesture */ + +#define FT6X36_LIB_VER_H_REG 0xA1 /* High 8-bit of LIB Version info */ +#define FT6X36_LIB_VER_L_REG 0xA2 /* Low 8-bit of LIB Version info */ + +#define FT6X36_CHIPSELECT_REG 0xA3 /* 0x36 for ft6236; 0x06 for ft6206 */ + +#define FT6X36_POWER_MODE_REG 0xA5 +#define FT6X36_FIRMWARE_ID_REG 0xA6 +#define FT6X36_RELEASECODE_REG 0xAF +#define FT6X36_PANEL_ID_REG 0xA8 +#define FT6X36_OPMODE_REG 0xBC + +int ft6x36_i2c_init(touch_coord_t *max_value); +int ft6x36_i2c_get_gesture_id(); +int ft6x36_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num); + +#endif /* __FT6X36_H */ diff --git a/bsp/common/touch/gt911_i2c.c b/bsp/common/touch/gt911_i2c.c new file mode 100644 index 00000000..e9e9ca04 --- /dev/null +++ b/bsp/common/touch/gt911_i2c.c @@ -0,0 +1,211 @@ +/** + * @file gt911_i2c.c + * @brief + * + * Copyright (c) 2022 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "touch.h" + +#ifdef TOUCH_I2C_GT911 +#include "bflb_mtimer.h" +#include "bflb_gpio.h" +#include "bflb_i2c.h" +#include "gt911_i2c.h" + +#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) + +static struct bflb_device_s *touch_gt911_i2c = NULL; + +static void gt911_i2c_gpio_init(void) +{ + struct bflb_device_s *gt911_i2c_gpio = NULL; + gt911_i2c_gpio = bflb_device_get_by_name("gpio"); + + /* I2C0_SCL */ + bflb_gpio_init(gt911_i2c_gpio, GPIO_PIN_6, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + /* I2C0_SDA */ + bflb_gpio_init(gt911_i2c_gpio, GPIO_PIN_9, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); +} + +static int gt911_i2c_peripheral_init(void) +{ + touch_gt911_i2c = bflb_device_get_by_name("i2c0"); + + if (touch_gt911_i2c) { + // printf("gt911 i2c gpio init\r\n"); + /* init i2c gpio */ + gt911_i2c_gpio_init(); + /* init i2c 200k */ + bflb_i2c_init(touch_gt911_i2c, 200000); + } else { + printf("i2c device get fail\r\n"); + return -1; + } + return 0; +} + +static int gt911_i2c_read_byte(uint16_t register_addr, uint8_t *data_buf, uint16_t len) +{ + static struct bflb_i2c_msg_s msg[2]; + + msg[0].addr = GT911_I2C_SLAVE_ADDR; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = (uint8_t *)(®ister_addr); + msg[0].length = 2; + + msg[1].addr = GT911_I2C_SLAVE_ADDR; + msg[1].flags = I2C_M_READ; + msg[1].buffer = data_buf; + msg[1].length = len; + bflb_i2c_transfer(touch_gt911_i2c, msg, 2); + return 0; +} + +static int gt911_i2c_write_byte(uint16_t register_addr, uint8_t *data_buf, uint16_t len) +{ + static struct bflb_i2c_msg_s msg[2]; + + msg[0].addr = GT911_I2C_SLAVE_ADDR; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = (uint8_t *)(®ister_addr); + msg[0].length = 2; + + msg[1].addr = GT911_I2C_SLAVE_ADDR; + msg[1].flags = 0; + msg[1].buffer = data_buf; + msg[1].length = len; + + bflb_i2c_transfer(touch_gt911_i2c, msg, 2); + return 0; +} + +int gt911_i2c_get_gesture_id() +{ + uint8_t data_buf = 0; + + if (gt911_i2c_read_byte(GT911_READ_XY_REG, &data_buf, 1)) { + return -1; + } + + return data_buf; +} + +int gt911_i2c_init(touch_coord_t *max_value) +{ + uint8_t data_buf[5] = { 0 }; + uint32_t product_id = 0; + uint16_t x_max = 0, y_max = 0; + + gt911_i2c_peripheral_init(); + + if (gt911_i2c_read_byte(GT911_PRODUCT_ID_REG, data_buf, 4)) { + printf("touch i2c read error\r\n"); + return -1; + } + product_id = BL_RDWD_FRM_BYTEP(data_buf); + printf("Touch Product ID: 0x%08x\r\n", product_id); + + if (product_id == GT911_PRODUCT_ID) { +#if 0 + data_buf[0] = 0; + data_buf[1] = (uint8_t)(max_value->coord_x << 8); + data_buf[2] = (uint8_t)(max_value->coord_x); + data_buf[3] = (uint8_t)(max_value->coord_y << 8); + data_buf[4] = (uint8_t)(max_value->coord_y); + + if (gt911_i2c_write_byte(GT911_CONFIG_REG, data_buf, 5)) { + return -1; + } + + if (gt911_i2c_write_byte(GT911_CONFIG_REG + (0x0005 << 8), (void *)g_gt911_cfg_params + 5, (sizeof(g_gt911_cfg_params) / sizeof(g_gt911_cfg_params[0]) - 5))) { + return -1; + } +#else + if (gt911_i2c_write_byte(GT911_CONFIG_REG, (void *)g_gt911_cfg_params, (sizeof(g_gt911_cfg_params) / sizeof(g_gt911_cfg_params[0])))) { + return -1; + } +#endif + + } else { + printf("Touch Product ID read fail!\r\n"); + return -1; + } + + if (gt911_i2c_read_byte(GT911_FIRMWARE_VERSION_REG, data_buf, 2)) { + return -1; + } + printf("Touch Firmware Version: 0x%04x\r\n", data_buf); + + if (gt911_i2c_read_byte(GT911_X_RESOLUTION, data_buf, 4)) { + return -1; + } + x_max = (((uint16_t)data_buf[1] << 8) | data_buf[0]); + y_max = (((uint16_t)data_buf[3] << 8) | data_buf[2]); + + printf("Touch Resolution %dx%d \r\n", x_max, y_max); + + return 0; +} + +int gt911_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num) +{ + uint8_t data_buf[8 * GT911_I2C_MAX_POINT] = { 0 }; + uint8_t read_num; + + *point_num = 0; + + if (point_num == NULL || touch_coord == NULL || max_num == 0) { + return -1; + } + + if (gt911_i2c_read_byte(GT911_READ_XY_REG, data_buf, 1)) { + return -1; + } + + /* no touch */ + if (data_buf[0] == 0) { + return 0; + } + + if (data_buf[0] > GT911_I2C_MAX_POINT) { + data_buf[0] = GT911_I2C_MAX_POINT; + } + + read_num = (data_buf[0] > max_num) ? max_num : data_buf[0]; + + /* read gt911 reg */ + gt911_i2c_read_byte(GT911_READ_XY_REG, data_buf, (8 * read_num)); + + /* get point coordinates */ + for (uint8_t i = 0; i < read_num; i++) { + uint8_t *p_data = &data_buf[i * 8]; + touch_coord[i].coord_x = (uint16_t)p_data[3] << 8 | p_data[2]; + touch_coord[i].coord_y = (uint16_t)p_data[5] << 8 | p_data[4]; + } + + *point_num = read_num; + + data_buf[0] = 0; + gt911_i2c_write_byte(GT911_READ_XY_REG, data_buf, 1); + + return 0; +} + +#endif diff --git a/bsp/common/touch/gt911_i2c.h b/bsp/common/touch/gt911_i2c.h new file mode 100644 index 00000000..6e82d64a --- /dev/null +++ b/bsp/common/touch/gt911_i2c.h @@ -0,0 +1,255 @@ +/** + * @file gt911_i2c.h + * @brief + * + * Copyright (c) 2022 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#ifndef _GT911_I2C_H +#define _GT911_I2C_H + +#include "bflb_core.h" +#include "touch.h" + +#define GT911_CUSTOM_CFG (1) +#define GT911_I2C_SLAVE_ADDR (0xBA >> 1) // #define GT911_ADDR (0xBA) //(0x28) /* slave addr */ +#define GT911_READ_XY_REG (0x4E81) //(0x814E) /* 坐标寄存器 */ +#define GT911_CLEARBUF_REG (0x4E81) //(0x814E) /* 清除坐标寄存器 */ +#define GT911_POINT1_REG (0x4F81) //(0x814f) /* point 1 reg */ +#define GT911_POINT2_REG (0x5781) //(0x8157) /* point 2 reg */ +#define GT911_POINT3_REG (0x5F81) //(0x815f) /* point 3 reg */ +#define GT911_POINT4_REG (0x6781) //(0x8167) /* point 4 reg */ +#define GT911_POINT5_REG (0x6F81) //(0x816f) /* point 5 reg */ +#define GT911_CONFIG_REG (0x4780) //(0x8047) /* 配置参数寄存器 */ +#define GT911_COMMAND_REG (0x4080) //(0x8040) /* 实时命令 */ +#define GT911_PRODUCT_ID_REG (0x4081) //(0x8140) /* 芯片ID */ +#define GT911_VENDOR_ID_REG (0x4A81) //(0x814A) /* 当前模组选项信息 */ +#define GT911_CONFIG_VERSION_REG (0x4780) //(0x8047) /* 配置文件版本号 */ +#define GT911_CONFIG_CHECKSUM_REG (0xFF80) //(0x80FF) /* 配置文件校验码 */ +#define GT911_FIRMWARE_VERSION_REG (0x4481) //(0x8144) /* 固件版本号 */ +#define GT911_X_RESOLUTION (0x4681) //(0x8146) /* x 坐标分辨率 */ +#define GT911_Y_RESOLUTION (0x4881) //(0x8148) /* y 坐标分辨率 */ + +#define GT911_PRODUCT_ID (0x00313139) + +/* Maximum border values of the touchscreen pad that the chip can handle */ +#if GT911_CUSTOM_CFG +#define GT911_MAX_WIDTH ((uint16_t)320) +#define GT911_MAX_HEIGHT ((uint16_t)480) +#define GT911_INT_TRIGGER (0) +#else +#define GT911_MAX_WIDTH ((uint16_t)4096) +#define GT911_MAX_HEIGHT ((uint16_t)4096) +#define GT911_INT_TRIGGER (1) +#endif + +/* Max detectable simultaneous touch points */ +#define GT911_I2C_MAX_POINT 5 + +/* GT911 配置参数，一次性写入 */ +static const uint8_t g_gt911_cfg_params[] = { + +#if 1 + /*KDC CFG*/ + 0x00, 0x40, 0x01, 0xE0, 0x01, 0x0A, 0x05, 0x00, + 0x01, 0x08, 0x28, 0x05, 0x50, 0x32, 0x03, 0x05, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x86, 0x26, 0x07, 0x17, 0x15, + 0x31, 0x0D, 0x00, 0x00, 0x01, 0xBA, 0x03, 0x1D, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x64, 0x32, + 0x00, 0x00, 0x00, 0x0F, 0x4B, 0x94, 0xC5, 0x02, + 0x07, 0x00, 0x00, 0x04, 0x9B, 0x11, 0x00, 0x72, + 0x18, 0x00, 0x57, 0x21, 0x00, 0x42, 0x2E, 0x00, + 0x35, 0x40, 0x00, 0x35, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x12, 0x10, 0x0E, 0x0C, 0x0A, 0x08, 0x06, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x21, + 0x20, 0x1F, 0x1E, 0x1D, 0x00, 0x02, 0x04, 0x06, + 0x08, 0x0A, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xDC, 0x01 +#else + 0x00, //0x8047 版本号 发送 0x00 初始化为 A + 0x40, 0x01, //0x8048/8049 X坐标输出最大值 320 + 0xE0, 0x01, //0x804a/804b Y坐标输出最大值 480 + 0x0A, //0x804c 输出触点个数上限 + 0x05, //0x804d x2y 坐标交换，软件降噪，下降沿触发 + 0x00, //0x804e reserved + 0x01, //0x804f 手指按下去抖动次数 + 0x08, //0x8050 原始坐标窗口滤波值 + 0x28, //0x8051 大面积触点个数 + 0x05, //0x8052 噪声消除值 + 0x50, //0x8053 屏上触摸点从无到有的阈值 + 0x32, //0x8054 屏上触摸点从有到无的阈值 + 0x03, //0x8055 进低功耗时间 s + 0x05, //0x8056 坐标上报率 + 0x00, //0x8057 X坐标输出门上限 + 0x00, //0x8058 Y坐标输出门上限 + 0x00, 0X00, //0x8059-0x805a reserved + 0x00, //0x805b reserved + 0x00, //0x805c reserved + 0x00, //0x805d 划线过程中小filter设置 + 0x00, //0x805e 拉伸区间 1 系数 + 0x00, //0x805f 拉伸区间 2 系数 + 0x00, //0x8060 拉伸区间 3 系数 + 0x00, //0x8061 各拉伸区间基数 + 0x00, //0x8062 Driver Group A number + 0x00, //0x8063 Driver Group B number + 0x00, //0x8064 Sensor Group B | A number + 0x00, //0x8065 驱动组A的驱动频率倍频系数 + 0x00, //0x8066 驱动组B的驱动频率倍频系数 + 0x00, //0x8067 驱动组A、B的基频 + 0x04, //0x8068 + 0x00, //0x8069 相邻两次驱动信号输出时间间隔 + 0x00, //0x806a + 0x00, //0x806b 、、 + 0x02, //0x806c 、、 + 0x03, //0x806d 原始值放大系数 + 0x1D, //0x806e 、、 + 0x00, //0x806f reserved + 0x01, //0x8070 、、 + 0x00, 0x00, //reserved + 0x00, //0x8073 、、 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x8071 - 0x8079 reserved + 0x50, //0x807a 跳频范围的起点频率 + 0xA0, //0x807b 跳频范围的终点频率 + 0x94, //0x807c 多次噪声检测后确定噪声量，1-63有效 + 0xD5, //0x807d 噪声检测超时时间 + 0x02, //0x807e 、、 + 0x07, //0x807f 判别有干扰的门限 + 0x00, 0x00, //0x8081 reserved + 0x04, //0x8082 跳频检测区间频段1中心点基频（适用于驱动A、B） + 0xA4, //0x8083 + 0x55, //0x8084 跳频检测区间频段1中心点倍频系数 + 0x00, //0x8085 跳频检测区间频段2中心点基频(驱动A、B在此基础上换算) + 0x91, //0x8086 + 0x62, //0x8087 跳频检测区间频段2中心点倍频系数 + 0x00, //0x8088 跳频检测区间频段3中心点基频（适用于驱动A、B） + 0x80, //0x8089 + 0x71, //0x808a 跳频检测区间频段3中心点倍频系数 + 0x00, //0x808b 跳频检测区间频段4中心点基频（适用于驱动A、B） + 0x71, //0x808c + 0x82, //0x808d 跳频检测区间频段4中心点倍频系数 + 0x00, //0x808e 跳频检测区间频段5中心点基频（适用于驱动A、B） + 0x65, //0x808f + 0x95, //0x8090 跳频检测区间频段5中心点倍频系数 + 0x00, 0x65, //reserved + 0x00, //0x8093 key1位置 0：无按键 + 0x00, //0x8094 key2位置 0：无按键 + 0x00, //0x8095 key3位置 0：无按键 + 0x00, //0x8096 key4位置 0：无按键 + 0x00, //0x8097 reserved + 0x00, //0x8098 reserved + 0x00, //0x8099 reserved + 0x00, //0x809a reserved + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x809b-0x80b2 reserved + 0x00, //0x80b3 合框距离 + 0x00, //0x80b4 + 0x00, 0x00, //0x80b6 reserved + 0x06, //0x80b7 + 0x08, //0x80b8 + 0x0A, //0x80b9 + 0x0C, //0x80ba + 0x0E, //0x80bb + 0x10, //0x80bc + 0x12, //0x80bd + 0x14, //0x80be + 0x16, //0x80bf + 0x18, //0x80c0 + 0x1A, //0x80c1 + 0x1C, //0x80c2 + 0xFF, //0x80c3 + 0xFF, //0x80c4 + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80c5-0x80d4 reserved + 0x00, //0x80d5 + 0x02, //0x80d6 + 0x04, //0x80d7 + 0x06, //0x80d8 + 0x08, //0x80d9 + 0x0A, //0x80da + 0x0C, //0x80db + 0x0F, //0x80dc + 0x10, //0x80dd + 0x12, //0x80de + 0x13, //0x80df + 0x14, //0x80e0 + 0x16, //0x80e1 + 0x18, //0x80e2 + 0x1C, //0x80e3 + 0x1D, //0x80e4 + 0x1E, //0x80e5 + 0x1F, //0x80e6 + 0x20, //0x80e7 + 0x21, //0x80e8 + 0xFF, //0x80e9 + 0xFF, //0x80ea + 0xFF, //0x80eb + 0xFF, //0x80ec + 0xFF, //0x80ed + 0xFF, //0x80ee + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //0x80ef-0x80fe reserved + 0x0B, //0x80ff 配置信息校验 + 0x01 //0x8100 配置以更新标记 +#endif +}; + +typedef struct +{ + uint8_t touch_point_flag; + uint8_t touch_key_sts; + + uint16_t x0; + uint16_t y0; + uint16_t p0; + + uint16_t x1; + uint16_t y1; + uint16_t p1; + + uint16_t x2; + uint16_t y2; + uint16_t p2; + + uint16_t x3; + uint16_t y3; + uint16_t p3; + + uint16_t x4; + uint16_t y4; + uint16_t p4; +} gt911_point_t; + +int gt911_i2c_init(touch_coord_t *max_value); +int gt911_i2c_get_gesture_id(); +int gt911_i2c_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num); + +#endif /* __gt911_H */ diff --git a/bsp/common/touch/touch.c b/bsp/common/touch/touch.c new file mode 100644 index 00000000..f9a838a3 --- /dev/null +++ b/bsp/common/touch/touch.c @@ -0,0 +1,33 @@ +/** + * @file touch.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +#include "touch.h" + +int touch_init(touch_coord_t *max_value) +{ + return _TOUCH_FUNC_DEFINE(init, max_value); +} + +int touch_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num) +{ + return _TOUCH_FUNC_DEFINE(read, point_num, touch_coord, max_num); +} diff --git a/bsp/common/touch/touch.h b/bsp/common/touch/touch.h new file mode 100644 index 00000000..7e83c242 --- /dev/null +++ b/bsp/common/touch/touch.h @@ -0,0 +1,78 @@ +/** + * @file touch.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _TOUCH_H_ +#define _TOUCH_H_ + +#include "bflb_core.h" + +/* spi interface + TOUCH_SPI_XPT2046 // Not currently supported +*/ + +/* i2c interface + TOUCH_I2C_FT6X36 + TOUCH_I2C_GT911 +*/ + +/* Select Touch Type */ +#define TOUCH_I2C_FT6X36 + +#define TOUCH_INTERFACE_SPI 1 +#define TOUCH_INTERFACE_I2C 2 + +typedef struct +{ + uint16_t coord_x; + uint16_t coord_y; +} touch_coord_t; + +#if defined TOUCH_SPI_XPT2046 + +#include "xpt2046_spi.h" +#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_SPI +#define TOUCH_MAX_POINT XPT2046_MAX_POINT +#define _TOUCH_FUNC_DEFINE(_func, ...) xpt2046_spi_##_func(__VA_ARGS__) + +#elif defined TOUCH_I2C_FT6X36 + +#include "ft6x36_i2c.h" +#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_I2C +#define TOUCH_MAX_POINT FT6X36_I2C_MAX_POINT +#define _TOUCH_FUNC_DEFINE(_func, ...) ft6x36_i2c_##_func(__VA_ARGS__) + +#elif defined TOUCH_I2C_GT911 + +#include "gt911_i2c.h" +#define TOUCH_INTERFACE_TYPE TOUCH_INTERFACE_I2C +#define TOUCH_MAX_POINT GT911_I2C_MAX_POINT +#define _TOUCH_FUNC_DEFINE(_func, ...) gt911_i2c_##_func(__VA_ARGS__) + +#elif +#error "Please select a touch type" +#endif + +int touch_init(touch_coord_t *max_value); +int touch_read(uint8_t *point_num, touch_coord_t *touch_coord, uint8_t max_num); + +#endif \ No newline at end of file diff --git a/cmake/bflb_flash.cmake b/cmake/bflb_flash.cmake new file mode 100644 index 00000000..945dd085 --- /dev/null +++ b/cmake/bflb_flash.cmake @@ -0,0 +1,36 @@ + +if(MINGW OR CYGWIN OR WIN32) +set(TOOL_SUFFIX ".exe") +elseif(UNIX OR APPLE) +set(TOOL_SUFFIX "") +endif() + +set(BL_FW_POST_PROC ${BL_SDK_BASE}/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc${TOOL_SUFFIX}) + +set(BL_FW_POST_PROC_CONFIG --chipname=${CHIP} --imgfile=${BIN_FILE}) + +if(BOARD_DIR) +list(APPEND BL_FW_POST_PROC_CONFIG --brdcfgdir=${BOARD_DIR}/${BOARD}/config) +else() +list(APPEND BL_FW_POST_PROC_CONFIG --brdcfgdir=${BL_SDK_BASE}/bsp/board/${BOARD}/config) +endif() + +if(CONFIG_AES_KEY) +list(APPEND BL_FW_POST_PROC_CONFIG --key=${CONFIG_AES_KEY}) +endif() + +if(CONFIG_AES_IV) +list(APPEND BL_FW_POST_PROC_CONFIG --iv=${CONFIG_AES_IV}) +endif() + +if(CONFIG_PUBLIC_KEY) +list(APPEND BL_FW_POST_PROC_CONFIG --publickey=${CONFIG_PUBLIC_KEY}) +endif() + +if(CONFIG_PRIVATE_KEY) +list(APPEND BL_FW_POST_PROC_CONFIG --privatekey=${CONFIG_PRIVATE_KEY}) +endif() + +add_custom_target(combine + WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR} + COMMAND ${BL_FW_POST_PROC} ${BL_FW_POST_PROC_CONFIG}) \ No newline at end of file diff --git a/cmake/extension.cmake b/cmake/extension.cmake index 31dbf912..6c7fd499 100644 --- a/cmake/extension.cmake +++ b/cmake/extension.cmake @@ -1,8 +1,6 @@ macro(sdk_generate_library) if(${ARGC}) - foreach(var ${ARGN}) - set(library_name ${var}) - endforeach() + set(library_name ${ARGV0}) else() get_filename_component(library_name ${CMAKE_CURRENT_LIST_DIR} NAME) endif() @@ -47,42 +45,89 @@ function(sdk_add_include_directories) endforeach() endfunction() +function(sdk_add_private_include_directories) + foreach(arg ${ARGV}) + if(IS_ABSOLUTE ${arg}) + set(path ${arg}) + else() + set(path ${CMAKE_CURRENT_SOURCE_DIR}/${arg}) + endif() + target_include_directories(${CURRENT_STATIC_LIBRARY} PRIVATE ${path}) + endforeach() +endfunction() + function(sdk_add_include_directories_ifdef feature) if(${${feature}}) sdk_add_include_directories(${ARGN}) endif() endfunction() +function(sdk_add_private_include_directories_ifdef feature) + if(${${feature}}) + sdk_add_private_include_directories(${ARGN}) + endif() +endfunction() + function(sdk_add_compile_definitions) target_compile_definitions(sdk_intf_lib INTERFACE ${ARGV}) endfunction() +function(sdk_add_private_compile_definitions) + target_compile_definitions(${CURRENT_STATIC_LIBRARY} PRIVATE ${ARGV}) +endfunction() + function(sdk_add_compile_definitions_ifdef feature) if(${${feature}}) sdk_add_compile_definitions(${ARGN}) endif() endfunction() +function(sdk_add_private_compile_definitions_ifdef feature) + if(${${feature}}) + sdk_add_private_compile_definitions(${ARGN}) + endif() +endfunction() + function(sdk_add_compile_options) target_compile_options(sdk_intf_lib INTERFACE ${ARGV}) endfunction() +function(sdk_add_private_compile_options) + target_compile_options(${CURRENT_STATIC_LIBRARY} PRIVATE ${ARGV}) +endfunction() + function(sdk_add_compile_options_ifdef feature) if(${${feature}}) sdk_add_compile_options(${ARGN}) endif() endfunction() +function(sdk_add_private_compile_options_ifdef feature) + if(${${feature}}) + sdk_add_private_compile_options(${ARGN}) + endif() +endfunction() + function(sdk_add_link_options) target_link_options(sdk_intf_lib INTERFACE ${ARGV}) endfunction() +function(sdk_add_private_link_options) + target_link_options(${CURRENT_STATIC_LIBRARY} PRIVATE ${ARGV}) +endfunction() + function(sdk_add_link_options_ifdef feature) if(${${feature}}) sdk_add_link_options(${ARGN}) endif() endfunction() +function(sdk_add_private_link_options_ifdef feature) + if(${${feature}}) + sdk_add_private_link_options(${ARGN}) + endif() +endfunction() + function(sdk_add_link_libraries) target_link_libraries(sdk_intf_lib INTERFACE ${ARGV}) endfunction() @@ -99,21 +144,6 @@ function(sdk_add_subdirectory_ifdef feature dir) endif() endfunction() -macro(sdk_ifndef define val) - if(NOT DEFINED ${define}) - set(${define} ${val}) - endif() -endmacro() - -function(sdk_set_linker_script ld) - if(IS_ABSOLUTE ${ld}) - set(path ${ld}) - else() - set(path ${CMAKE_CURRENT_SOURCE_DIR}/${ld}) - endif() - set_property(GLOBAL PROPERTY LINKER_SCRIPT ${path}) -endfunction() - function(sdk_add_static_library) foreach(arg ${ARGV}) if(IS_DIRECTORY ${arg}) @@ -131,6 +161,35 @@ function(sdk_add_static_library) endforeach() endfunction() +function(sdk_add_static_library_ifdef feature) + if(${${feature}}) + sdk_add_static_library(${ARGN}) + endif() +endfunction() + +macro(sdk_ifndef define val) + if(NOT DEFINED ${define}) + set(${define} ${val}) + endif() +endmacro() + +function(sdk_set_linker_script ld) + if(IS_ABSOLUTE ${ld}) + set(path ${ld}) + else() + set(path ${CMAKE_CURRENT_SOURCE_DIR}/${ld}) + endif() + set_property(GLOBAL PROPERTY LINKER_SCRIPT ${path}) +endfunction() + +macro(sdk_set_vscode_dir dir) + if(IS_ABSOLUTE ${dir}) + set(VSCODE_DIR ${dir}) + else() + set(VSCODE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/${dir}) + endif() +endmacro() + macro(sdk_set_main_file) if(IS_ABSOLUTE ${ARGV0}) set(path ${ARGV0}) @@ -190,4 +249,6 @@ macro(project name) ) endif() + # include(${BL_SDK_BASE}/cmake/bflb_flash.cmake) + # include(${BL_SDK_BASE}/cmake/gen_c_cpp_properties_json.cmake) endmacro() \ No newline at end of file diff --git a/cmake/gen_c_cpp_properties_json.cmake b/cmake/gen_c_cpp_properties_json.cmake new file mode 100644 index 00000000..fc997844 --- /dev/null +++ b/cmake/gen_c_cpp_properties_json.cmake @@ -0,0 +1,28 @@ +cmake_minimum_required(VERSION 3.19.3) + +get_target_property(C_CPP_PROPERTIES_INCLUDE sdk_intf_lib INTERFACE_INCLUDE_DIRECTORIES) +get_target_property(C_CPP_PROPERTIES_DEFINES sdk_intf_lib INTERFACE_COMPILE_DEFINITIONS) +list(SORT C_CPP_PROPERTIES_INCLUDE) +list(SORT C_CPP_PROPERTIES_DEFINES) + +foreach(item ${C_CPP_PROPERTIES_INCLUDE}) + string(APPEND C_CPP_PROPERTIES_INCLUDE_IN "\n \"${item}\",") +endforeach() + +foreach(item ${C_CPP_PROPERTIES_DEFINES}) + string(APPEND C_CPP_PROPERTIES_DEFINES_IN "\n \"${item}\",") +endforeach() + +get_filename_component(SYS_INCLUDE_PATH ${CMAKE_C_COMPILER} DIRECTORY) +string(APPEND C_CPP_PROPERTIES_INCLUDE_IN "\n \"${SYS_INCLUDE_PATH}/../riscv64-unknown-elf/include\",") + +get_filename_component(BL_SDK_CMAKE_DIR ${BL_SDK_BASE}/cmake/extension.cmake ABSOLUTE) +get_filename_component(BL_SDK_CMAKE_DIR ${BL_SDK_CMAKE_DIR} DIRECTORY) + +if(VSCODE_DIR) + set(VSCODE_DIR_ ${VSCODE_DIR}/.vscode) +else() + set(VSCODE_DIR_ ${BL_SDK_CMAKE_DIR}/../.vscode) +endif() + +configure_file(${BL_SDK_BASE}/tools/vscode/c_cpp_properties.json ${VSCODE_DIR_}/c_cpp_properties.json) \ No newline at end of file diff --git a/drivers/lhal/CMakeLists.txt b/drivers/lhal/CMakeLists.txt index 760fa295..52fc55dd 100644 --- a/drivers/lhal/CMakeLists.txt +++ b/drivers/lhal/CMakeLists.txt @@ -23,6 +23,11 @@ src/bflb_spi.c src/bflb_timer.c src/bflb_uart.c src/bflb_wdg.c +src/bflb_flash.c +src/flash/bflb_sf_cfg.c +src/flash/bflb_xip_sflash.c +src/flash/bflb_sflash.c +src/flash/bflb_sf_ctrl.c ) if("${CHIP}" STREQUAL "bl602") @@ -38,12 +43,13 @@ src/bflb_emac.c src/bflb_ir.c src/bflb_pwm_v1.c src/bflb_cam.c +src/bflb_spi_psram.c ) elseif("${CHIP}" STREQUAL "bl702l") sdk_library_add_sources( -src/bflb_kys.c src/bflb_pwm_v1.c src/bflb_pwm_v2.c +src/bflb_spi_psram.c ) elseif("${CHIP}" STREQUAL "bl616") sdk_library_add_sources( @@ -54,6 +60,7 @@ src/bflb_mjpeg.c src/bflb_pwm_v2.c src/bflb_cam.c src/bflb_iso11898.c +src/bflb_i2s.c ) elseif("${CHIP}" STREQUAL "bl628") sdk_library_add_sources( @@ -72,6 +79,8 @@ src/bflb_mjpeg.c src/bflb_pwm_v2.c src/bflb_cam.c src/bflb_iso11898.c +src/bflb_csi.c +src/bflb_i2s.c ) endif() @@ -96,6 +105,7 @@ sdk_add_include_directories(include/arch) sdk_add_include_directories(include/arch/risc-v/t-head) sdk_add_include_directories(include/arch/risc-v/t-head/Core/Include) sdk_add_include_directories(config/${CHIP}) +sdk_add_include_directories(src/flash) if((NOT ("${CHIP}" STREQUAL "bl702")) AND (NOT ("${CHIP}" STREQUAL "bl602")) AND (NOT ("${CHIP}" STREQUAL "bl702l"))) sdk_library_add_sources(include/arch/risc-v/t-head/rv_hart.c) @@ -113,4 +123,7 @@ sdk_add_compile_definitions(-DCPU_${CPU_ID_NAME}) endif() sdk_add_static_library(src/pka/libpka.a) -#add_subdirectory(src/pka) \ No newline at end of file +# add_subdirectory(src/pka) +if(("${CHIP}" STREQUAL "bl616") OR ("${CHIP}" STREQUAL "bl628")) +# keep +endif() diff --git a/drivers/lhal/bouffalo.mk b/drivers/lhal/bouffalo.mk deleted file mode 100644 index 09d039a2..00000000 --- a/drivers/lhal/bouffalo.mk +++ /dev/null @@ -1,41 +0,0 @@ -# Component Makefile -# -## These include paths would be exported to project level -COMPONENT_ADD_INCLUDEDIRS += include -COMPONENT_ADD_INCLUDEDIRS += include/arch -COMPONENT_ADD_INCLUDEDIRS += include/arch/risc-v/t-head -COMPONENT_ADD_INCLUDEDIRS += include/arch/risc-v/t-head/Core/Include - -## not be exported to project level -COMPONENT_PRIV_INCLUDEDIRS := - -## This component's src -COMPONENT_SRCS := src/bflb_gpio.c \ - src/bflb_irq.c \ - src/bflb_l1c.c \ - src/bflb_mtimer.c \ - src/bflb_sec_aes.c \ - src/bflb_uart.c \ - -CHIP_NAME = $(shell echo $(CONFIG_CHIP_NAME) | tr A-Z a-z) - -COMPONENT_SRCS += config/$(CHIP_NAME)/device_table.c -COMPONENT_ADD_INCLUDEDIRS += config/$(CHIP_NAME) - -CFLAGS += -D$(CONFIG_CHIP_NAME) -CFLAGS += -DCONFIG_IRQ_NUM=80 -CFLAGS += -DBL_IOT_SDK - -ifeq ($(CONFIG_CHIP_NAME),BL616) -COMPONENT_SRCS += include/arch/risc-v/t-head/rv_hart.c -COMPONENT_SRCS += include/arch/risc-v/t-head/rv_pmp.c - -ifeq ($(CONFIG_CHERRYUSB),1) -COMPONENT_SRCS += src/bflb_usb_v2.c -endif - -endif - -COMPONENT_OBJS := $(patsubst %.c,%.o, $(COMPONENT_SRCS)) - -COMPONENT_SRCDIRS := src include/arch/risc-v/t-head config/$(CHIP_NAME) \ No newline at end of file diff --git a/drivers/lhal/config/bl616/bl616_irq.h b/drivers/lhal/config/bl616/bl616_irq.h index 57b66ea3..3980a33f 100644 --- a/drivers/lhal/config/bl616/bl616_irq.h +++ b/drivers/lhal/config/bl616/bl616_irq.h @@ -62,7 +62,7 @@ #define BL616_IRQ_TIMER1 (BL616_IRQ_NUM_BASE + 37) #define BL616_IRQ_WDG (BL616_IRQ_NUM_BASE + 38) #define BL616_IRQ_I2C1 (BL616_IRQ_NUM_BASE + 39) -#define BL616_IRQ_I2CS (BL616_IRQ_NUM_BASE + 40) +#define BL616_IRQ_I2S (BL616_IRQ_NUM_BASE + 40) #define BL616_IRQ_ANA_OCP_OUT_TO_CPU_0 (BL616_IRQ_NUM_BASE + 41) #define BL616_IRQ_ANA_OCP_OUT_TO_CPU_1 (BL616_IRQ_NUM_BASE + 42) #define BL616_IRQ_XTAL_RDY_SCAN (BL616_IRQ_NUM_BASE + 43) diff --git a/drivers/lhal/config/bl616/device_table.c b/drivers/lhal/config/bl616/device_table.c index 0c1c1ee3..049ce78b 100644 --- a/drivers/lhal/config/bl616/device_table.c +++ b/drivers/lhal/config/bl616/device_table.c @@ -121,6 +121,13 @@ struct bflb_device_s bl616_device_table[] = { .sub_idx = 0, .dev_type = BFLB_DEVICE_TYPE_I2C, .user_data = NULL }, + { .name = "i2s0", + .reg_base = I2S_BASE, + .irq_num = BL616_IRQ_I2S, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_I2S, + .user_data = NULL }, { .name = "timer0", .reg_base = TIMER_BASE, .irq_num = BL616_IRQ_TIMER0, diff --git a/drivers/lhal/config/bl808/bl808_irq.h b/drivers/lhal/config/bl808/bl808_irq.h index 10efff1c..406b8ae5 100644 --- a/drivers/lhal/config/bl808/bl808_irq.h +++ b/drivers/lhal/config/bl808/bl808_irq.h @@ -9,7 +9,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define BL808_IRQ_NUM_BASE 16 +#define BL808_IRQ_NUM_BASE 16 #define BL808_IRQ_SSOFT 1 #define BL808_IRQ_MSOFT 3 diff --git a/drivers/lhal/include/bflb_cam.h b/drivers/lhal/include/bflb_cam.h index b074a998..44db5401 100644 --- a/drivers/lhal/include/bflb_cam.h +++ b/drivers/lhal/include/bflb_cam.h @@ -193,120 +193,120 @@ extern "C" { #endif /** - * @brief + * @brief Initialize cam. * - * @param [in] dev - * @param [in] config + * @param [in] dev device handle + * @param [in] config pointer to cam configure structure */ void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config); /** - * @brief + * @brief Enable cam. * - * @param [in] dev + * @param [in] dev device handle */ void bflb_cam_start(struct bflb_device_s *dev); /** - * @brief + * @brief Disable cam. * - * @param [in] dev + * @param [in] dev device handle */ void bflb_cam_stop(struct bflb_device_s *dev); /** - * @brief + * @brief Mask or unmask cam interrupt. * - * @param [in] dev - * @param [in] int_type - * @param [in] mask + * @param [in] dev device handle + * @param [in] int_type cam interrupt mask type, use @ref CAM_INTMASK + * @param [in] mask mask or unmask */ void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask); /** - * @brief + * @brief Clear cam interrupt. * - * @param [in] dev - * @param [in] int_type + * @param [in] dev device handle + * @param [in] int_type int_type cam interrupt clear type, use @ref CAM_INTCLR */ void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type); /** - * @brief + * @brief Crop vsync. * - * @param [in] dev - * @param [in] start_line - * @param [in] end_line + * @param [in] dev device handle + * @param [in] start_line start line of window + * @param [in] end_line end line of window, not include */ void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line); /** - * @brief + * @brief Crop hsync. * - * @param [in] dev - * @param [in] start_pixel - * @param [in] end_pixel + * @param [in] dev device handle + * @param [in] start_pixel start pixel of each line + * @param [in] end_pixel end pixel of each line, not include */ void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel); /** - * @brief + * @brief Pop one frame. * - * @param [in] dev + * @param [in] dev device handle */ void bflb_cam_pop_one_frame(struct bflb_device_s *dev); #if !defined(BL702) /** - * @brief + * @brief Swap input order of y and uv. * - * @param [in] dev - * @param [in] enable + * @param [in] dev device handle + * @param [in] enable enable or disable */ void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable); /** - * @brief + * @brief Set frame filter, if frame_count = 3, frame_valid = 101b, second frame will be dropped every 3 frames. * - * @param [in] dev - * @param [in] frame_count - * @param [in] frame_valid + * @param [in] dev device handle + * @param [in] frame_count frame filter period + * @param [in] frame_valid frame valid */ void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid); #endif /** - * @brief + * @brief Get frame count. * - * @param [in] dev - * @return uint8_t + * @param [in] dev device handle + * @return Frame count */ uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev); /** - * @brief + * @brief Get frame information. * - * @param [in] dev - * @param [in] pic - * @return uint32_t + * @param [in] dev device handle + * @param [out] pic pointer to frame start address + * @return Size of frame */ uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic); /** - * @brief + * @brief Get interrupt status. * - * @param [in] dev - * @return uint32_t + * @param [in] dev device handle + * @return Interrupt status */ uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev); /** - * @brief + * @brief Control cam feature. * - * @param [in] dev - * @param [in] cmd - * @param [in] arg - * @return int + * @param [in] dev device handle + * @param [in] cmd feature command + * @param [in] arg user data + * @return A negated errno value on failure */ int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); diff --git a/drivers/lhal/include/bflb_csi.h b/drivers/lhal/include/bflb_csi.h new file mode 100644 index 00000000..d430a4e3 --- /dev/null +++ b/drivers/lhal/include/bflb_csi.h @@ -0,0 +1,158 @@ +#ifndef _BFLB_CSI_H +#define _BFLB_CSI_H + +#include "bflb_core.h" + +/** @addtogroup LHAL + * @{ + */ + +/** @addtogroup CSI + * @{ + */ + +/** @defgroup CSI_LANE_NUMBER CSI lane number definition + * @{ + */ +#define CSI_LANE_NUMBER_1 0 +#define CSI_LANE_NUMBER_2 1 +/** + * @} + */ + +/** @defgroup CSI_INTSTS CSI interrupt status definition + * @{ + */ +#define CSI_INTSTS_GENERIC_PACKET (1 << 0) +#define CSI_INTSTS_LANE_MERGE_ERROR (1 << 1) +#define CSI_INTSTS_ECC_ERROR (1 << 2) +#define CSI_INTSTS_CRC_ERROR (1 << 3) +#define CSI_INTSTS_PHY_HS_SOT_ERROR (1 << 4) +#define CSI_INTSTS_PHY_HS_SOT_SYNC_ERROR (1 << 5) +/** + * @} + */ + +/** @defgroup CSI_INTMASK CSI interrupt mask definition + * @{ + */ +#define CSI_INTMASK_GENERIC_PACKET (1 << 0) +#define CSI_INTMASK_LANE_MERGE_ERROR (1 << 1) +#define CSI_INTMASK_ECC_ERROR (1 << 2) +#define CSI_INTMASK_CRC_ERROR (1 << 3) +#define CSI_INTMASK_PHY_HS_SOT_ERROR (1 << 4) +#define CSI_INTMASK_PHY_HS_SOT_SYNC_ERROR (1 << 5) +/** + * @} + */ + +/** @defgroup CSI_INTCLR CSI interrupt clear definition + * @{ + */ +#define CSI_INTCLR_GENERIC_PACKET (1 << 0) +#define CSI_INTCLR_LANE_MERGE_ERROR (1 << 1) +#define CSI_INTCLR_ECC_ERROR (1 << 2) +#define CSI_INTCLR_CRC_ERROR (1 << 3) +#define CSI_INTCLR_PHY_HS_SOT_ERROR (1 << 4) +#define CSI_INTCLR_PHY_HS_SOT_SYNC_ERROR (1 << 5) +/** + * @} + */ + +/** + * @brief CSI configuration structure + * + * @param lane_number CSI lane number, use @ref CSI_LANE_NUMBER + * @param tx_clk_escape CSI tx clock in escape mode + * @param data_rate CSI data rate + */ +struct bflb_csi_config_s { + uint8_t lane_number; + uint32_t tx_clk_escape; + uint32_t data_rate; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize csi. + * + * @param [in] dev device handle + * @param [in] config pointer to csi configure structure + */ +void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config); + +/** + * @brief Enable csi. + * + * @param [in] dev device handle + */ +void bflb_csi_start(struct bflb_device_s *dev); + +/** + * @brief Disable csi. + * + * @param [in] dev device handle + */ +void bflb_csi_stop(struct bflb_device_s *dev); + +/** + * @brief Set threshold of line buffer, data will be sent to following module when threshold reached. + * + * @param [in] dev device handle + * @param [in] resolution_x number of columns + * @param [in] pixel_clock pixel clock + * @param [in] dsp_clock dsp clock + */ +void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock); + +/** + * @brief Mask or unmask csi interrupt. + * + * @param [in] dev device handle + * @param [in] int_type csi interrupt mask type, use @ref CSI_INTMASK + * @param [in] mask mask or unmask + */ +void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask); + +/** + * @brief Clear csi interrupt. + * + * @param [in] dev device handle + * @param [in] int_type csi interrupt clear type, use @ref CSI_INTCLR + */ +void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type); + +/** + * @brief Get csi interrupt status. + * + * @param [in] dev device handle + * @return Interrupt status + */ +uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev); + +/** + * @brief Control csi feature. + * + * @param [in] dev device handle + * @param [in] cmd feature command + * @param [in] arg user data + * @return A negated errno value on failure + */ +int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/drivers/lhal/include/bflb_dma.h b/drivers/lhal/include/bflb_dma.h index 5d9727e2..8dd94599 100644 --- a/drivers/lhal/include/bflb_dma.h +++ b/drivers/lhal/include/bflb_dma.h @@ -144,7 +144,8 @@ #define DMA_REQUEST_I2C0_TX 0x00000007 #define DMA_REQUEST_SPI0_RX 0x0000000A #define DMA_REQUEST_SPI0_TX 0x0000000B -#define DMA_REQUEST_AUDIO_TX 0x0000000D +#define DMA_REQUEST_AUADC_RX 0x00000015 +#define DMA_REQUEST_AUDAC_TX 0x0000000D #define DMA_REQUEST_I2S_RX 0x00000010 #define DMA_REQUEST_I2S_TX 0x00000011 #define DMA_REQUEST_ADC 0x00000016 diff --git a/drivers/lhal/include/bflb_flash.h b/drivers/lhal/include/bflb_flash.h index a78a5f4b..6c3d4782 100644 --- a/drivers/lhal/include/bflb_flash.h +++ b/drivers/lhal/include/bflb_flash.h @@ -2,6 +2,7 @@ #define _BFLB_FLASH_H #include "bflb_core.h" +#include "bflb_sflash.h" /** @addtogroup LHAL * @{ diff --git a/drivers/lhal/include/bflb_gpio.h b/drivers/lhal/include/bflb_gpio.h index 98d853e0..7e109f00 100644 --- a/drivers/lhal/include/bflb_gpio.h +++ b/drivers/lhal/include/bflb_gpio.h @@ -119,6 +119,7 @@ #define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_AUDAC_PWM (25 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT) #elif defined(BL606P) || defined(BL808) #define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) @@ -156,6 +157,7 @@ #define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PEC (27 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT) #endif @@ -282,6 +284,38 @@ void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin); */ bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin); +/** + * @brief Write gpio pin 0~31. + * + * @param [in] dev device handle + * @param [in] val gpio pin 0~31 value + */ +void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val); + +/** + * @brief Write gpio pin 32~63. + * + * @param [in] dev device handle + * @param [in] val gpio pin 32~63 value + */ +void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val); + +/** + * @brief Read level from gpio pin 0~31. + * + * @param [in] dev device handle + * @return level of gpio pin 0~31 + */ +uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev); + +/** + * @brief Read level from gpio pin 32~63. + * + * @param [in] dev device handle + * @return level of gpio pin32~63 + */ +uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev); + /** * @brief Config gpio pin interrupt. * diff --git a/drivers/lhal/include/bflb_i2s.h b/drivers/lhal/include/bflb_i2s.h new file mode 100644 index 00000000..a9ae0ddf --- /dev/null +++ b/drivers/lhal/include/bflb_i2s.h @@ -0,0 +1,204 @@ +#ifndef _BFLB_I2S_H +#define _BFLB_I2S_H + +#include "bflb_core.h" + +/** @addtogroup LHAL + * @{ + */ + +/** @addtogroup I2S + * @{ + */ + +/** @defgroup I2S_ROLE i2s role definition + * @{ + */ +#define I2S_ROLE_MASTER 0 +#define I2S_ROLE_SLAVE 1 +/** + * @} + */ + +/** @defgroup I2S_FORMAT_MODE i2s mode definition + * @{ + */ +#define I2S_MODE_LEFT_JUSTIFIED 0 /* left-justified or Phillips standard */ +#define I2S_MODE_RIGHT_JUSTIFIED 1 /* right-justified */ +#define I2S_MODE_DSP_SHORT_FRAME_SYNC 2 /* dsp modeA/B short frame sync */ +#define I2S_MODE_DSP_LONG_FRAME_SYNC 3 /* dsp modeA/B long frame sync */ +/** + * @} + */ + +/** @defgroup I2S_CHANNEL_MODE i2s mode definition + * @{ + */ +#define I2S_CHANNEL_MODE_NUM_1 0 +#define I2S_CHANNEL_MODE_NUM_2 1 +#define I2S_CHANNEL_MODE_NUM_3 2 /* only DSP mode, frame_size must equal data_size */ +#define I2S_CHANNEL_MODE_NUM_4 3 /* only DSP mode, frame_size must equal data_size */ +#define I2S_CHANNEL_MODE_NUM_6 4 /* only DSP mode, frame_size must equal data_size */ +/** + * @} + */ + +/** @defgroup I2S_SLOT_WIDTH i2s slot width definition + * @{ + */ +#define I2S_SLOT_WIDTH_8 0 +#define I2S_SLOT_WIDTH_16 1 +#define I2S_SLOT_WIDTH_24 2 +#define I2S_SLOT_WIDTH_32 3 +/** + * @} + */ + +/** @defgroup I2S_INTSTS i2s interrupt status definition + * @{ + */ +#define I2S_INTSTS_TX_FIFO (1 << 1) +#define I2S_INTSTS_RX_FIFO (1 << 2) +#define I2S_INTSTS_FIFO_ERR (1 << 3) +/** + * @} + */ + +/** @defgroup I2S_CMD i2s feature control cmd definition + * @{ + */ +#define I2S_CMD_CLEAR_TX_FIFO (0x01) +#define I2S_CMD_CLEAR_RX_FIFO (0x02) +#define I2S_CMD_RX_DEGLITCH (0x03) +#define I2S_CMD_DATA_ENABLE (0x04) +#define I2S_CMD_CHANNEL_LR_MERGE (0x05) +#define I2S_CMD_CHANNEL_LR_EXCHG (0x06) +#define I2S_CMD_MUTE (0x07) +#define I2S_CMD_BIT_REVERSE (0x08) + +/** @defgroup I2S_CMD_DATA_ENABLE_TYPE i2s data enable type + * @{ + */ +#define I2S_CMD_DATA_ENABLE_TX (1 << 1) +#define I2S_CMD_DATA_ENABLE_RX (1 << 2) + +/** + * @} + */ + +/** + * @brief I2S configuration structure + * + * @param bclk_freq_hz I2S bit frequence, Sampling_rate = bclk_freq_hz / frame_width / channel_num. + * @param role I2S role, use @ref I2S_ROLE + * @param format_mode I2S mode, use @ref I2S_FORMAT_MODE + * @param channel_mode I2S channel num, Only DSP mode supports more than 2 channels, use @ref I2S_CHANNEL_MODE + * @param frame_width I2S frame width, use @ref I2S_SLOT_WIDTH + * @param data_width I2S data order, frame_size must equal data_size in 3/4/6-channel mode, use @ref I2S_SLOT_WIDTH + * @param fs_offset_cycle I2S first bit offset of the data + * @param tx_fifo_threshold I2S tx fifo threshold, should be less than 16 + * @param rx_fifo_threshold I2S rx fifo threshold, should be less than 16 + */ +struct bflb_i2s_config_s { + uint32_t bclk_freq_hz; + uint8_t role; + uint8_t format_mode; + uint8_t channel_mode; + uint8_t frame_width; + uint8_t data_width; + uint8_t fs_offset_cycle; + + uint8_t tx_fifo_threshold; + uint8_t rx_fifo_threshold; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize i2s. + * + * @param [in] dev device handle + * @param [in] config pointer to save i2s config + */ +void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config); + +/** + * @brief Deinitialize i2s. + * + * @param [in] dev device handle + */ +void bflb_i2s_deinit(struct bflb_device_s *dev); + +/** + * @brief Enable i2s tx dma. + * + * @param [in] dev device handle + * @param [in] enable true means enable, otherwise disable. + */ +void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable); + +/** + * @brief Enable i2s rx dma. + * + * @param [in] dev device handle + * @param [in] enable true means enable, otherwise disable. + */ +void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable); + +/** + * @brief Enable or disable i2s rx fifo threhold interrupt. + * + * @param [in] dev device handle + * @param [in] mask true means disable, false means enable + */ +void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask); + +/** + * @brief Enable or disable i2s rx fifo threhold interrupt. + * + * @param [in] dev device handle + * @param [in] mask true means disable, false means enable + */ +void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask); + +/** + * @brief Enable or disable i2s error interrupt. + * + * @param [in] dev device handle + * @param [in] mask true means disable, false means enable + */ +void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask); + +/** + * @brief Get i2s interrupt status. + * + * @param [in] dev device handle + * @return interrupt status, use @ref I2S_INTSTS + */ +uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev); + +/** + * @brief Control i2s feature. + * + * @param [in] dev device handle + * @param [in] cmd feature command, use @ref I2S_CMD + * @param [in] arg user data + * @return A negated errno value on failure. + */ +int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +#endif diff --git a/drivers/lhal/include/bflb_ir.h b/drivers/lhal/include/bflb_ir.h index 5274f047..821f5766 100644 --- a/drivers/lhal/include/bflb_ir.h +++ b/drivers/lhal/include/bflb_ir.h @@ -102,7 +102,7 @@ /** * @brief IR TX configuration structure * - * @param tx_mode TX mode select,NEC protocol/RC-5 protocol/software mode/customize + * @param tx_mode TX mode select, use @ref IR_TX_MODE * @param data_bits Bit count of data phase (don't care if tx freerun mode is enabled) * @param tail_inverse Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) * @param tail_enable Enable or disable signal of tail pulse (don't care if SWM is enabled) @@ -116,7 +116,7 @@ * @param output_inverse Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high * @param freerun_enable Enable or disable tx freerun mode (don't care if SWM is enabled) * @param continue_enable Disable:idle time between frames = (tailPulseWidth_0+tailPulseWidth_1)*pulseWidthUnit,Enable:no idle time between frames - * @param fifo_width IR frame size(also the valid width for each fifo entry) + * @param fifo_width IR frame size(also the valid width for each fifo entry), use @ref IR_TX_FIFO_WIDTH * @param fifo_threshold TX FIFO threshold * @param logic0_pulse_width_1 Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) * @param logic0_pulse_width_0 Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) @@ -165,7 +165,7 @@ struct bflb_ir_tx_config_s { /** * @brief IR RX configuration structure * - * @param rx_mode RX mode select,NEC protocol/RC-5 protocol/software mode + * @param rx_mode RX mode select, use @ref IR_RX_MODE * @param input_inverse Enable or disable signal of input inverse * @param deglitch_enable Enable or disable signal of rx input de-glitch function * @param deglitch_cnt De-glitch function cycle count @@ -190,84 +190,84 @@ extern "C" { #if !defined(BL616) /** - * @brief + * @brief Initialize ir tx. * - * @param [in] dev - * @param [in] config + * @param [in] dev device handle + * @param [in] config pointer to ir tx configure structure */ void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config); /** - * @brief + * @brief Send data in NEC/RC5/customize mode. * - * @param [in] dev - * @param [in] data - * @param [in] length + * @param [in] dev device handle + * @param [in] data data buffer to send + * @param [in] length length of data buffer */ void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length); /** - * @brief + * @brief Send data in software mode. * - * @param [in] dev - * @param [in] data - * @param [in] length + * @param [in] dev device handle + * @param [in] data data data buffer to send + * @param [in] length length of data buffer */ void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length); /** - * @brief + * @brief Enable or disable ir tx. * - * @param [in] dev - * @param [in] enable + * @param [in] dev device handle + * @param [in] enable enable or disable */ void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable); /** - * @brief + * @brief Mask or unmask ir tx interrupt. * - * @param [in] dev - * @param [in] int_type - * @param [in] mask + * @param [in] dev device handle + * @param [in] int_type ir tx interrupt type, use @ref IR_TX_INTEN + * @param [in] mask mask or unmask */ void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask); /** - * @brief + * @brief Get ir tx interrupt status. * - * @param [in] dev - * @return uint32_t + * @param [in] dev device handle + * @return Ir tx interrupt status */ uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev); /** - * @brief + * @brief Clear ir tx interrupt. * - * @param [in] dev + * @param [in] dev device handle */ void bflb_ir_txint_clear(struct bflb_device_s *dev); #if !defined(BL602) && !defined(BL702) /** - * @brief + * @brief Enable or disable ir tx dma mode. * - * @param [in] dev - * @param [in] enable + * @param [in] dev device handle + * @param [in] enable enable or disable */ void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable); /** - * @brief + * @brief Get ir tx fifo available count. * - * @param [in] dev - * @return uint8_t + * @param [in] dev device handle + * @return Ir tx fifo available count */ uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev); /** - * @brief + * @brief Clear ir tx fifo. * - * @param [in] dev + * @param [in] dev device handle */ void bflb_ir_txfifo_clear(struct bflb_device_s *dev); #endif @@ -275,88 +275,88 @@ void bflb_ir_txfifo_clear(struct bflb_device_s *dev); #if !defined(BL702L) /** - * @brief + * @brief Initialize ir rx. * - * @param [in] dev - * @param [in] config + * @param [in] dev device handle + * @param [in] config config pointer to ir rx configure structure */ void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config); /** - * @brief + * @brief Receive data in NEC/RC5/customize mode. * - * @param [in] dev - * @param [in] data - * @return uint8_t + * @param [in] dev device handle + * @param [out] data data received + * @return Bit count of data received */ uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data); /** - * @brief + * @brief Receive data in software mode. * - * @param [in] dev - * @param [in] data - * @param [in] length - * @return uint8_t + * @param [in] dev device handle + * @param [out] data data buffer to receive + * @param [in] length of data buffer + * @return Length of data received */ uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length); /** - * @brief + * @brief Enable or disable ir rx. * - * @param [in] dev - * @param [in] enable + * @param [in] dev device handle + * @param [in] enable enable or disable */ void bflb_ir_rx_enable(struct bflb_device_s *dev, bool enable); /** - * @brief + * @brief Get ir rx fifo available count. * - * @param [in] dev - * @return uint8_t + * @param [in] dev device handle + * @return Ir rx fifo available count */ uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev); /** - * @brief + * @brief Clear ir rx fifo. * - * @param [in] dev + * @param [in] dev device handle */ void bflb_ir_rxfifo_clear(struct bflb_device_s *dev); /** - * @brief + * @brief Mask ir rx interrupt. * - * @param [in] dev - * @param [in] int_type - * @param [in] mask + * @param [in] dev device handle + * @param [in] int_type ir rx interrupt type, use @ref IR_RX_INTEN + * @param [in] mask mask or unmask */ void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask); /** - * @brief + * @brief Get ir rx interrupt status. * - * @param [in] dev - * @return uint32_t + * @param [in] dev device handle + * @return Ir rx interrupt status */ uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev); /** - * @brief + * @brief Clear ir rx interrupt. * - * @param [in] dev + * @param [in] dev device handle */ void bflb_ir_rxint_clear(struct bflb_device_s *dev); #endif /** - * @brief + * @brief Control ir feature. * - * @param [in] dev - * @param [in] cmd - * @param [in] arg - * @return int + * @param [in] dev device handle + * @param [in] cmd feature command + * @param [in] arg user data + * @return A negated errno value on failure */ int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); diff --git a/drivers/lhal/include/bflb_l1c.h b/drivers/lhal/include/bflb_l1c.h index aa112251..7d15367f 100644 --- a/drivers/lhal/include/bflb_l1c.h +++ b/drivers/lhal/include/bflb_l1c.h @@ -83,6 +83,10 @@ void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size); */ void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size); +void bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high); +uint32_t bflb_l1c_miss_count_get(void); +void bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en); + /** * @} */ diff --git a/drivers/lhal/include/bflb_spi_psram.h b/drivers/lhal/include/bflb_spi_psram.h new file mode 100644 index 00000000..33969d84 --- /dev/null +++ b/drivers/lhal/include/bflb_spi_psram.h @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file bflb_spi_psram.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BFLB_SPI_PSRAM_H__ +#define __BFLB_SPI_PSRAM_H__ + +#include "sf_ctrl_reg.h" +#include "bflb_common.h" +#include "bflb_sf_ctrl.h" + +/** @addtogroup BFLB_Peripheral_Driver + * @{ + */ + +/** @addtogroup PSRAM + * @{ + */ + +/** @defgroup PSRAM_Public_Types + * @{ + */ + +/** + * @brief Psram drive strength type definition + */ + +#define PSRAM_DRIVE_STRENGTH_50_OHMS 0 /*!< Drive strength 50 ohms(default) */ +#define PSRAM_DRIVE_STRENGTH_100_OHMS 1 /*!< Drive strength 100 ohms */ +#define PSRAM_DRIVE_STRENGTH_200_OHMS 2 /*!< Drive strength 200 ohms */ + +/** + * @brief Psram burst length size type definition + */ +#define PSRAM_BURST_LENGTH_16_BYTES 0 /*!< Burst Length 16 bytes */ +#define PSRAM_BURST_LENGTH_32_BYTES 1 /*!< Burst Length 32 bytes */ +#define PSRAM_BURST_LENGTH_64_BYTES 2 /*!< Burst Length 64 bytes */ +#define PSRAM_BURST_LENGTH_512_BYTES 3 /*!< Burst Length 512 bytes(default) */ + +/** + * @brief Psram ctrl mode type definition + */ +#define PSRAM_SPI_CTRL_MODE 0 /*!< Psram SPI ctrl mode */ +#define PSRAM_QPI_CTRL_MODE 1 /*!< Psram QPI ctrl mode */ + +/** + * @brief Psram ctrl configuration structure type definition + */ +struct spi_psram_cfg_type { + uint8_t read_id_cmd; /*!< Read ID command */ + uint8_t read_id_dmy_clk; /*!< Read ID command dummy clock */ + uint8_t burst_toggle_cmd; /*!< Burst toggle length command */ + uint8_t reset_enable_cmd; /*!< Psram reset enable command */ + uint8_t reset_cmd; /*!< Psram reset command */ + uint8_t enter_quad_mode_cmd; /*!< Psram enter quad mode command */ + uint8_t exit_quad_mode_cmd; /*!< Psram exit quad mode command */ + uint8_t read_reg_cmd; /*!< Read register command */ + uint8_t read_reg_dmy_clk; /*!< Read register command dummy clock */ + uint8_t write_reg_cmd; /*!< Write register command */ + uint8_t read_cmd; /*!< Psram read command */ + uint8_t read_dmy_clk; /*!< Psram read command dummy clock */ + uint8_t f_read_cmd; /*!< Psram fast read command */ + uint8_t f_read_dmy_clk; /*!< Psram fast read command dummy clock */ + uint8_t f_read_quad_cmd; /*!< Psram fast read quad command */ + uint8_t f_read_quad_dmy_clk; /*!< Psram fast read quad command dummy clock */ + uint8_t write_cmd; /*!< Psram write command */ + uint8_t quad_write_cmd; /*!< Psram quad write command */ + uint16_t page_size; /*!< Psram page size */ +#if defined(BL702L) + uint8_t burst_toggle_en; /*!< Psram burst toggle mode enable */ +#endif + uint8_t ctrl_mode; /*!< Psram ctrl mode */ + uint8_t drive_strength; /*!< Psram drive strength */ + uint8_t burst_length; /*!< Psram burst length size */ +}; + +/*@} end of group PSRAM_Public_Types */ + +/** @defgroup PSRAM_Public_Constants + * @{ + */ + +/*@} end of group PSRAM_Public_Constants */ + +/** @defgroup PSRAM_Public_Macros + * @{ + */ + +/*@} end of group PSRAM_Public_Macros */ + +/** @defgroup PSRAM_Public_Functions + * @{ + */ + +/** + * @brief PSRAM Functions + */ +void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg, + struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg); +void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value); +void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value); +int bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg); +int bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg); +void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data); +int bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg); +int bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg); +int bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode); +int bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode); +int bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint32_t len); +int bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint8_t wt_en, + uint8_t wb_en, uint8_t wa_en); +int bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len); +int bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len); + +/*@} end of group PSRAM_Public_Functions */ + +/*@} end of group PSRAM */ + +/*@} end of group BFLB_Peripheral_Driver */ + +#endif /* __BFLB_SPI_PSRAM_H__ */ diff --git a/drivers/lhal/include/bflb_timer.h b/drivers/lhal/include/bflb_timer.h index 2398664a..43a09d2e 100644 --- a/drivers/lhal/include/bflb_timer.h +++ b/drivers/lhal/include/bflb_timer.h @@ -184,6 +184,11 @@ bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no); */ void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no); +#if !defined(BL702) || !defined(BL602) +void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config); +uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev); +#endif + #ifdef __cplusplus } #endif diff --git a/drivers/lhal/include/hardware/csi_reg.h b/drivers/lhal/include/hardware/csi_reg.h new file mode 100644 index 00000000..36a1f5ad --- /dev/null +++ b/drivers/lhal/include/hardware/csi_reg.h @@ -0,0 +1,165 @@ +/** + ****************************************************************************** + * @file csi_reg.h + * @version V1.0 + * @date 2022-12-13 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HARDWARE_CSI_H__ +#define __HARDWARE_CSI_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define CSI_MIPI_CONFIG_OFFSET (0x0)/* mipi_config */ +#define CSI_INT_STATUS_OFFSET (0x10)/* csi_int_status */ +#define CSI_INT_MASK_OFFSET (0x14)/* csi_int_mask */ +#define CSI_INT_CLEAR_OFFSET (0x18)/* csi_int_clear */ +#define CSI_INT_ENABLE_OFFSET (0x1C)/* csi_int_enable */ +#define CSI_GNR_BUF_STATUS_OFFSET (0x20)/* gnr_buf_status */ +#define CSI_GNR_BUF_RDATA_OFFSET (0x24)/* gnr_buf_rdata */ +#define CSI_DPHY_CONFIG_0_OFFSET (0x80)/* dphy_config_0 */ +#define CSI_DPHY_CONFIG_1_OFFSET (0x84)/* dphy_config_1 */ +#define CSI_DPHY_CONFIG_2_OFFSET (0x88)/* dphy_config_2 */ +#define CSI_DPHY_CONFIG_3_OFFSET (0x8C)/* dphy_config_3 */ +#define CSI_DPHY_CONFIG_4_OFFSET (0x90)/* dphy_config_4 */ +#define CSI_DPHY_CONFIG_5_OFFSET (0x94)/* dphy_config_5 */ +#define CSI_DUMMY_REG_OFFSET (0xFC)/* dummy_reg */ + +/* Register Bitfield definitions *****************************************************/ + +/* 0x0 : mipi_config */ +#define CSI_CR_CSI_EN (1<<0U) +#define CSI_CR_LANE_NUM (1<<1U) +#define CSI_CR_LANE_INV (1<<3U) +#define CSI_CR_DATA_BIT_INV (1<<4U) +#define CSI_CR_SYNC_SP_EN (1<<5U) +#define CSI_CR_UNPACK_EN (1<<6U) +#define CSI_CR_VC_DVP0_SHIFT (12U) +#define CSI_CR_VC_DVP0_MASK (0x3<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HARDWARE_DTSRC_H__ +#define __HARDWARE_DTSRC_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define DTSRC_CONFIG_OFFSET (0x0)/* config */ +#define DTSRC_FRAME_SIZE_H_OFFSET (0x4)/* frame_size_h */ +#define DTSRC_FRAME_SIZE_V_OFFSET (0x8)/* frame_size_v */ +#define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC)/* frame_size_cea_861 */ +#define DTSRC_PIX_DATA_RANGE_OFFSET (0x10)/* pix_data_range */ +#define DTSRC_PIX_DATA_STEP_OFFSET (0x14)/* pix_data_step */ +#define DTSRC_AXI2DVP_SETTING_OFFSET (0x20)/* axi2dvp_setting */ +#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24)/* axi2dvp_start_addr_by */ +#define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28)/* axi2dvp_burst_cnt */ +#define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C)/* axi2dvp_status */ +#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30)/* axi2dvp_swap_addr_by */ +#define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34)/* axi2dvp_prefetch */ +#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38)/* snsr2dvp_wait_pos */ +#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40)/* axi2dvp_start_addr_uv */ +#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44)/* axi2dvp_swap_addr_uv */ + +/* Register Bitfield definitions *****************************************************/ + +/* 0x0 : config */ +#define DTSRC_CR_ENABLE (1<<0U) +#define DTSRC_CR_AXI_EN (1<<1U) +#define DTSRC_CR_MODE_CEA_861 (1<<2U) +#define DTSRC_CR_SNSR_EN (1<<3U) +#define DTSRC_CR_SNSR_HSYNC_INV (1<<4U) +#define DTSRC_CR_SNSR_VSYNC_INV (1<<5U) +#define DTSRC_CR_AXI_SWAP_MODE (1<<7U) +#define DTSRC_CR_AXI_SWAP_IDX_SEL_SHIFT (8U) +#define DTSRC_CR_AXI_SWAP_IDX_SEL_MASK (0xf<
© COPYRIGHT(c) 2020 Bouffalo Lab
+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __I2S_REG_H__ +#define __I2S_REG_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define I2S_CONFIG_OFFSET (0x0) /* i2s_config */ +#define I2S_INT_STS_OFFSET (0x4) /* i2s_int_sts */ +#define I2S_BCLK_CONFIG_OFFSET (0x10) /* i2s_bclk_config */ +#define I2S_FIFO_CONFIG_0_OFFSET (0x80) /* i2s_fifo_config_0 */ +#define I2S_FIFO_CONFIG_1_OFFSET (0x84) /* i2s_fifo_config_1 */ +#define I2S_FIFO_WDATA_OFFSET (0x88) /* i2s_fifo_wdata */ +#define I2S_FIFO_RDATA_OFFSET (0x8C) /* i2s_fifo_rdata */ +#define I2S_IO_CONFIG_OFFSET (0xFC) /* i2s_io_config */ + +/* Register Bitfield definitions *****************************************************/ + +/* 0x0 : i2s_config */ +#define I2S_CR_I2S_M_EN (1 << 0U) +#define I2S_CR_I2S_S_EN (1 << 1U) +#define I2S_CR_I2S_TXD_EN (1 << 2U) +#define I2S_CR_I2S_RXD_EN (1 << 3U) +#define I2S_CR_MONO_MODE (1 << 4U) +#define I2S_CR_MUTE_MODE (1 << 5U) +#define I2S_CR_FS_1T_MODE (1 << 6U) +#define I2S_CR_FS_CH_CNT_SHIFT (7U) +#define I2S_CR_FS_CH_CNT_MASK (0x3 << I2S_CR_FS_CH_CNT_SHIFT) +#define I2S_CR_FRAME_SIZE_SHIFT (12U) +#define I2S_CR_FRAME_SIZE_MASK (0x3 << I2S_CR_FRAME_SIZE_SHIFT) +#define I2S_CR_DATA_SIZE_SHIFT (14U) +#define I2S_CR_DATA_SIZE_MASK (0x3 << I2S_CR_DATA_SIZE_SHIFT) +#define I2S_CR_I2S_MODE_SHIFT (16U) +#define I2S_CR_I2S_MODE_MASK (0x3 << I2S_CR_I2S_MODE_SHIFT) +#define I2S_CR_ENDIAN (1 << 18U) +#define I2S_CR_MONO_RX_CH (1 << 19U) +#define I2S_CR_OFS_CNT_SHIFT (20U) +#define I2S_CR_OFS_CNT_MASK (0x1f << I2S_CR_OFS_CNT_SHIFT) +#define I2S_CR_OFS_EN (1 << 25U) + +/* 0x4 : i2s_int_sts */ +#define I2S_TXF_INT (1 << 0U) +#define I2S_RXF_INT (1 << 1U) +#define I2S_FER_INT (1 << 2U) +#define I2S_CR_I2S_TXF_MASK (1 << 8U) +#define I2S_CR_I2S_RXF_MASK (1 << 9U) +#define I2S_CR_I2S_FER_MASK (1 << 10U) +#define I2S_CR_I2S_TXF_EN (1 << 24U) +#define I2S_CR_I2S_RXF_EN (1 << 25U) +#define I2S_CR_I2S_FER_EN (1 << 26U) + +/* 0x10 : i2s_bclk_config */ +#define I2S_CR_BCLK_DIV_L_SHIFT (0U) +#define I2S_CR_BCLK_DIV_L_MASK (0xfff << I2S_CR_BCLK_DIV_L_SHIFT) +#define I2S_CR_BCLK_DIV_H_SHIFT (16U) +#define I2S_CR_BCLK_DIV_H_MASK (0xfff << I2S_CR_BCLK_DIV_H_SHIFT) + +/* 0x80 : i2s_fifo_config_0 */ +#define I2S_DMA_TX_EN (1 << 0U) +#define I2S_DMA_RX_EN (1 << 1U) +#define I2S_TX_FIFO_CLR (1 << 2U) +#define I2S_RX_FIFO_CLR (1 << 3U) +#define I2S_TX_FIFO_OVERFLOW (1 << 4U) +#define I2S_TX_FIFO_UNDERFLOW (1 << 5U) +#define I2S_RX_FIFO_OVERFLOW (1 << 6U) +#define I2S_RX_FIFO_UNDERFLOW (1 << 7U) +#define I2S_CR_FIFO_LR_MERGE (1 << 8U) +#define I2S_CR_FIFO_LR_EXCHG (1 << 9U) +#define I2S_CR_FIFO_24B_LJ (1 << 10U) + +/* 0x84 : i2s_fifo_config_1 */ +#define I2S_TX_FIFO_CNT_SHIFT (0U) +#define I2S_TX_FIFO_CNT_MASK (0x1f << I2S_TX_FIFO_CNT_SHIFT) +#define I2S_RX_FIFO_CNT_SHIFT (8U) +#define I2S_RX_FIFO_CNT_MASK (0x1f << I2S_RX_FIFO_CNT_SHIFT) +#define I2S_TX_FIFO_TH_SHIFT (16U) +#define I2S_TX_FIFO_TH_MASK (0xf << I2S_TX_FIFO_TH_SHIFT) +#define I2S_RX_FIFO_TH_SHIFT (24U) +#define I2S_RX_FIFO_TH_MASK (0xf << I2S_RX_FIFO_TH_SHIFT) + +/* 0x88 : i2s_fifo_wdata */ +#define I2S_FIFO_WDATA_SHIFT (0U) +#define I2S_FIFO_WDATA_MASK (0xffffffff << I2S_FIFO_WDATA_SHIFT) + +/* 0x8C : i2s_fifo_rdata */ +#define I2S_FIFO_RDATA_SHIFT (0U) +#define I2S_FIFO_RDATA_MASK (0xffffffff << I2S_FIFO_RDATA_SHIFT) + +/* 0xFC : i2s_io_config */ +#define I2S_CR_I2S_TXD_INV (1 << 0U) +#define I2S_CR_I2S_RXD_INV (1 << 1U) +#define I2S_CR_I2S_FS_INV (1 << 2U) +#define I2S_CR_I2S_BCLK_INV (1 << 3U) +#define I2S_CR_DEG_CNT_SHIFT (4U) +#define I2S_CR_DEG_CNT_MASK (0x7 << I2S_CR_DEG_CNT_SHIFT) +#define I2S_CR_DEG_EN (1 << 7U) + +#endif /* __I2S_REG_H__ */ diff --git a/drivers/lhal/include/hardware/kys_reg.h b/drivers/lhal/include/hardware/kys_reg.h new file mode 100644 index 00000000..342c9011 --- /dev/null +++ b/drivers/lhal/include/hardware/kys_reg.h @@ -0,0 +1,154 @@ +/** + ****************************************************************************** + * @file kys_reg.h + * @version V1.0 + * @date 2022-11-17 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2022 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without + *modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + *ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + *LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + *INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + *CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + *ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + *POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HARDWARE_KYS_H__ +#define __HARDWARE_KYS_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ +#define KYS_KS_CTRL_OFFSET (0x0) +#define KYS_KS_INT_EN_OFFSET (0x10) +#define KYS_KS_INT_STS_OFFSET (0x14) +#define KYS_KEYCODE_CLR_OFFSET (0x18) +#if defined(bl702) +#define KYS_KEYFIFO_VALUE_OFFSET (0x1C) +#else +#define KYS_KEYFIFO_IDX_OFFSET (0x30) +#define KYS_KEYFIFO_VALUE_OFFSET (0x34) +#endif + +/* 0x0 : ks_ctrl */ +#define KYS_KS_EN_SHIFT (0U) +#define KYS_KS_EN_MASK (0x1 << KYS_KS_EN_SHIFT) +#define KYS_GHOST_EN_SHIFT (2U) +#define KYS_GHOST_EN_MASK (0x1 << KYS_GHOST_EN_SHIFT) +#define KYS_DEG_EN_SHIFT (3U) +#define KYS_DEG_EN_MASK (0x1 << KYS_DEG_EN_SHIFT) +#define KYS_DEG_CNT_SHIFT (4U) +#define KYS_DEG_CNT_MASK (0xf << KYS_DEG_CNT_SHIFT) +#define KYS_RC_EXT_SHIFT (8U) +#define KYS_RC_EXT_MASK (0x3 << KYS_RC_EXT_SHIFT) +#define KYS_ROW_NUM_SHIFT (16U) +#define KYS_ROW_NUM_MASK (0x7 << KYS_ROW_NUM_SHIFT) +#if defined(bl702) +#define KYS_COL_NUM_SHIFT (20U) +#define KYS_COL_NUM_MASK (0x7 << KYS_COL_NUM_SHIFT) +#else +#define KYS_FIFO_MODE_SHIFT (1U) +#define KYS_FIFO_MODE_MASK (0x1 << KYS_FIFO_MODE_SHIFT) +#define KYS_COL_NUM_SHIFT (20U) +#define KYS_COL_NUM_MASK (0x1f << KYS_COL_NUM_SHIFT) +#endif + +/* 0x10 : ks_int_en */ +#if defined(bl702) +#define KYS_KS_INT_EN_SHIFT (0U) +#define KYS_KS_INT_EN_MASK (0x1 << KYS_KS_INT_EN_SHIFT) +#else +#define KYS_KS_DONE_INT_EN_SHIFT (7U) +#define KYS_KS_DONE_INT_EN_MASK (0x1 << KYS_KS_DONE_INT_EN_SHIFT) +#define KYS_KEYFIFO_FULL_INT_EN_SHIFT (8U) +#define KYS_KEYFIFO_FULL_INT_EN_MASK (0x1 << KYS_KEYFIFO_FULL_INT_EN_SHIFT) +#define KYS_KEYFIFO_HALF_INT_EN_SHIFT (9U) +#define KYS_KEYFIFO_HALF_INT_EN_MASK (0x1 << KYS_KEYFIFO_HALF_INT_EN_SHIFT) +#define KYS_KEYFIFO_QUARTER_INT_EN_SHIFT (10U) +#define KYS_KEYFIFO_QUARTER_INT_EN_MASK (0x1 << KYS_KEYFIFO_QUARTER_INT_EN_SHIFT) +#define KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT (11U) +#define KYS_KEYFIFO_NONEMPTY_INT_EN_MASK (0x1 << KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT) +#define KYS_GHOST_INT_EN_SHIFT (12U) +#define KYS_GHOST_INT_EN_MASK (0x1 << KYS_GHOST_INT_EN_SHIFT) +#endif + +/* 0x14 : ks_int_sts */ +#if defined(bl702) +#define KYS_KEYCODE_VALID_SHIFT (0U) +#define KYS_KEYCODE_VALID_MASK (0xf << KYS_KEYCODE_VALID_SHIFT) +#else +#define KYS_KEYCODE_DONE_SHIFT (7U) +#define KYS_KEYCODE_DONE_MASK (0x1 << KYS_KEYCODE_DONE_SHIFT) +#define KYS_KEYFIFO_FULL_SHIFT (8U) +#define KYS_KEYFIFO_FULL_MASK (0x1 << KYS_KEYFIFO_FULL_SHIFT) +#define KYS_KEYFIFO_HALF_SHIFT (9U) +#define KYS_KEYFIFO_HALF_MSK (0x1 << KYS_KEYFIFO_HALF_SHIFT) +#define KYS_KEYFIFO_QUARTER_SHIFT (10U) +#define KYS_KEYFIFO_QUARTER_MSK (0x1 << KYS_KEYFIFO_QUARTER_SHIFT) +#define KYS_KEYFIFO_NONEMPTY_SHIFT (11U) +#define KYS_KEYFIFO_NONEMPTY_MSK (0x1 << KYS_KEYFIFO_NONEMPTY_SHIFT) +#define KYS_GHOST_DET_SHIFT (12U) +#define KYS_GHOST_DET_MASK (0x1 << KYS_GHOST_DET_SHIFT) +#endif + +/* 0x18 : keycode_clr */ +#if defined(bl702) +#define KYS_KEYCODE_CLR_SHIFT (0U) +#define KYS_KEYCODE_CLR_MASK (0xf << KYS_KEYCODE_CLR_SHIFT) +#else +#define KYS_KS_DONE_CLR_SHIFT (7U) +#define KYS_KS_DONE_CLR_MASK (0x1 << KYS_KS_DONE_CLR_SHIFT) +#define KYS_KEYFIFO_FULL_CLR_SHIFT (8U) +#define KYS_KEYFIFO_FULL_CLR_MASK (0x1 << KYS_KEYFIFO_FULL_CLR_SHIFT) +#define KYS_GHOST_CLR_SHIFT (12U) +#define KYS_GHOST_CLR_MASK (0x1 << KYS_GHOST_CLR_SHIFT) +#endif + +#if defined(bl702) +/* 0x1c : keycode value */ +#define KYS_KEYCODE0_SHIFT (0U) +#define KYS_KEYCODE0_MASK (0xff << KYS_KEYCODE0_SHIFT) +#define KYS_KEYCODE1_SHIFT (8U) +#define KYS_KEYCODE1_MASK (0xff << KYS_KEYCODE1_SHIFT) +#define KYS_KEYCODE2_SHIFT (16U) +#define KYS_KEYCODE2_MASK (0xff << KYS_KEYCODE2_SHIFT) +#define KYS_KEYCODE3_SHIFT (24U) +#define KYS_KEYCODE3_MASK (0xff << KYS_KEYCODE3_SHIFT) +#endif + +#if defined(bl702l) +/* 0x30 : keyfifo_idx */ +#define KYS_KEYFIFO_HEAD_SHIFT (0U) +#define KYS_KEYFIFO_HEAD_MASK (0x7 << KYS_KEYFIFO_HEAD_SHIFT) +#define KYS_KEYFIFO_TAIL_SHIFT (8U) +#define KYS_KEYFIFO_TAIL_MASK (0x7 << KYS_KEYFIFO_TAIL_SHIFT) + +/* 0x34 : keyfifo_value */ +#define KYS_KEYFIFO_VALUE_SHIFT (0U) +#define KYS_KEYFIFO_VALUE_MASK (0xff << KYS_KEYFIFO_VALUE_SHIFT) +#endif + +#endif /* __HARDWARE_KYS_H__ */ diff --git a/drivers/lhal/include/hardware/sdio2_reg.h b/drivers/lhal/include/hardware/sdio2_reg.h new file mode 100644 index 00000000..9862a41e --- /dev/null +++ b/drivers/lhal/include/hardware/sdio2_reg.h @@ -0,0 +1,139 @@ +/** + ****************************************************************************** + * @file sdio2.h + * @version V1.0 + * @date 2022-08-03 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __HARDWARE_SDIO2_H__ +#define __HARDWARE_SDIO2_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define SDIO2_IO_ENABLE_OFFSET (0x0002) /* SDIO I/O Enable */ +#define SDIO2_FN1_BLK_SIZE_0_OFFSET (0x0028) /* SDIO block size infor */ +#define SDIO2_FN1_BLK_SIZE_1_OFFSET (0x0029) /* SDIO block size infor */ +#define SDIO2_DEV_SLEEP_OFFSET (0x0092) /* SDIO Device Sleep */ +#define SDIO2_CCR_FUNC_OFFSET (0x0100) /* Address offset of CCR between two functions */ +#define SDIO2_HOST_TO_CARD_EVENT_OFFSET (0x0100) +#define SDIO2_HOST_INT_CAUSE_OFFSET (0x0101) +#define SDIO2_HOST_INT_MASK_OFFSET (0x0102) +#define SDIO2_HOST_INT_STATUS_OFFSET (0x0103) +#define SDIO2_RD_BIT_MAP_OFFSET (0x0104) +#define SDIO2_WR_BIT_MAP_OFFSET (0x0106) +#define SDIO2_RD_LEN_OFFSET (0x0108) +#define SDIO2_HOST_TRANS_STATUS_OFFSET (0x0128) +#define SDIO2_CARD_TO_HOST_EVENT_OFFSET (0x0130) +#define SDIO2_CARD_INT_MASK_OFFSET (0x0134) +#define SDIO2_CARD_INT_STATUS_OFFSET (0x0138) +#define SDIO2_CARD_INT_MODE_OFFSET (0x013C) +#define SDIO2_SQ_READ_BASE_OFFSET (0x0140) +#define SDIO2_SQ_WRITE_BASE_OFFSET (0x0144) +#define SDIO2_READ_INDEX_OFFSET (0x0148) +#define SDIO2_WRITE_INDEX_OFFSET (0x0149) +#define SDIO2_DNLD_QUEUE_WRPTR_OFFSET (0x014A) +#define SDIO2_UPLD_QUEUE_WRPTR_OFFSET (0x014B) +#define SDIO2_DNLD_QUEUE_OFFSET (0x014C) +#define SDIO2_UPLD_QUEUE_OFFSET (0x0154) +#define SDIO2_CHIP_VERSION_OFFSET (0x015C) +#define SDIO2_IP_VERSION0_OFFSET (0x015E) +#define SDIO2_IP_VERSION1_OFFSET (0x015F) +#define SDIO2_SCRATCH2_OFFSET (0x0164) +#define SDIO2_SCRATCH1_OFFSET (0x0166) +#define SDIO2_OCR0_OFFSET (0x0168) +#define SDIO2_OCR1_OFFSET (0x0169) +#define SDIO2_OCR2_OFFSET (0x016A) +#define SDIO2_CONFIG_OFFSET (0x016B) +#define SDIO2_CONFIG2_OFFSET (0x016C) +#define SDIO2_DEBUG_OFFSET (0x0170) +#define SDIO2_DMA_ADDR_OFFSET (0x0174) +#define SDIO2_IO_PORT_OFFSET (0x0178) + + +// Bit Def. Scratch register 0 +#define SDIO2_SCRATCH_OFFSET (0x0160) + +// Bit Def. Block size 1 mask (Offset 0x29) +#define SDIO2_FN1_BLK_SIZE_1_MASK 0x01 + +// Bit Def. Host To Card Interrupt Event (Offset 0x100/200) +#define SDIO2_HCR_CONFIG_HostPwrUp (1 << 1) + +// Bit Def. Host Transfer Status (Offset 0x128/228) +#define SDIO2_CCR_HOST_INT_DnLdReStart (1 << 0) +#define SDIO2_CCR_HOST_INT_UpLdReStart (1 << 1) +#define SDIO2_CCR_HOST_INT_DnLdCRC_err (1 << 2) + +// Bit Def. Card To Host Interrupt Event (Offset 0x130/230) +#define SDIO2_CCR_CS_DnLdRdy (1 << 0) +#define SDIO2_CCR_CS_UpLdRdy (1 << 1) +#define SDIO2_CCR_CS_ReadCISRdy (1 << 2) +#define SDIO2_CCR_CS_IORdy (1 << 3) + +// Bit Def. Card Interrupt Mask (Offset 0x134/234) +#define SDIO2_CCR_CIM_DnLdOvr (1 << 0) +#define SDIO2_CCR_CIM_UpLdOvr (1 << 1) +#define SDIO2_CCR_CIM_Abort (1 << 2) +#define SDIO2_CCR_CIM_PwrDn (1 << 3) +#define SDIO2_CCR_CIM_PwrUp (1 << 4) + +#define SDIO2_CCR_CIM_MASK 0x0007 + +// Bit Def. Card Interrupt Status (Offset 0x138/238) +#define SDIO2_CCR_CIC_DnLdOvr (1 << 0) +#define SDIO2_CCR_CIC_UpLdOvr (1 << 1) +#define SDIO2_CCR_CIC_Abort (1 << 2) +#define SDIO2_CCR_CIC_PwrDn (1 << 3) +#define SDIO2_CCR_CIC_PwrUp (1 << 4) + +#define SDIO2_CCR_CIC_MASK 0x001F + +// Bit Def. Card Interrupt RSR (Offset 0x13C/23C) +#define SDIO2_CCR_CIO_DnLdOvr (1 << 0) +#define SDIO2_CCR_CIO_UpLdOvr (1 << 1) +#define SDIO2_CCR_CIO_Abort (1 << 2) +#define SDIO2_CCR_CIO_PwrDn (1 << 3) +#define SDIO2_CCR_CIO_PwrUp (1 << 4) +#define SDIO2_CCR_CIO_MASK 0x001F + +//Config2 register mask +#define SDIO2_CONFIG2_MSK 0x00000C00 + +//CardIntMode register mask + +#define SDIO2_CARD_INT_MODE_MSK 0x00000003 +#define SDIO2_HOST_INT_MSK 0x00000002 + +#endif /* __HARDWARE_SDIO2_H__ */ diff --git a/drivers/lhal/include/hardware/sf_ctrl_reg.h b/drivers/lhal/include/hardware/sf_ctrl_reg.h new file mode 100644 index 00000000..2f1b5ee4 --- /dev/null +++ b/drivers/lhal/include/hardware/sf_ctrl_reg.h @@ -0,0 +1,983 @@ +/** + ****************************************************************************** + * @file sf_ctrl_reg.h + * @version V1.0 + * @date 2022-10-20 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __SF_CTRL_REG_H__ +#define __SF_CTRL_REG_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define SF_CTRL_0_OFFSET (0x0)/* sf_ctrl_0 */ +#define SF_CTRL_1_OFFSET (0x4)/* sf_ctrl_1 */ +#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8)/* sf_if_sahb_0 */ +#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC)/* sf_if_sahb_1 */ +#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10)/* sf_if_sahb_2 */ +#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14)/* sf_if_iahb_0 */ +#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18)/* sf_if_iahb_1 */ +#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C)/* sf_if_iahb_2 */ +#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)/* sf_if_status_0 */ +#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)/* sf_if_status_1 */ +#define SF_CTRL_SF_AES_OFFSET (0x28)/* sf_aes */ +#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)/* sf_ahb2sif_status */ +#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30)/* sf_if_io_dly_0 */ +#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34)/* sf_if_io_dly_1 */ +#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38)/* sf_if_io_dly_2 */ +#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C)/* sf_if_io_dly_3 */ +#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40)/* sf_if_io_dly_4 */ +#define SF_CTRL_SF_RESERVED_OFFSET (0x44)/* sf_reserved */ +#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48)/* sf2_if_io_dly_0 */ +#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C)/* sf2_if_io_dly_1 */ +#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50)/* sf2_if_io_dly_2 */ +#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54)/* sf2_if_io_dly_3 */ +#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58)/* sf2_if_io_dly_4 */ +#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C)/* sf3_if_io_dly_0 */ +#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60)/* sf3_if_io_dly_1 */ +#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64)/* sf3_if_io_dly_2 */ +#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68)/* sf3_if_io_dly_3 */ +#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C)/* sf3_if_io_dly_4 */ +#define SF_CTRL_2_OFFSET (0x70)/* sf_ctrl_2 */ +#define SF_CTRL_3_OFFSET (0x74)/* sf_ctrl_3 */ +#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78)/* sf_if_iahb_3 */ +#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C)/* sf_if_iahb_4 */ +#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80)/* sf_if_iahb_5 */ +#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84)/* sf_if_iahb_6 */ +#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88)/* sf_if_iahb_7 */ +#define SF_CTRL_SF_IF_IAHB_8_OFFSET (0x8C)/* sf_if_iahb_8 */ +#define SF_CTRL_SF_IF_IAHB_9_OFFSET (0x90)/* sf_if_iahb_9 */ +#define SF_CTRL_SF_IF_IAHB_10_OFFSET (0x94)/* sf_if_iahb_10 */ +#define SF_CTRL_SF_IF_IAHB_11_OFFSET (0x98)/* sf_if_iahb_11 */ +#define SF_CTRL_SF_IF_IAHB_12_OFFSET (0x9C)/* sf_if_iahb_12 */ +#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0xA0)/* sf_id0_offset */ +#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0xA4)/* sf_id1_offset */ +#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0xA8)/* sf_bk2_id0_offset */ +#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0xAC)/* sf_bk2_id1_offset */ +#define SF_CTRL_SF_DBG_OFFSET (0xB0)/* sf_dbg */ +#define SF_CTRL_SF_IF2_CTRL_0_OFFSET (0xC0)/* sf_if2_ctrl_0 */ +#define SF_CTRL_SF_IF2_CTRL_1_OFFSET (0xC4)/* sf_if2_ctrl_1 */ +#define SF_CTRL_SF_IF2_SAHB_0_OFFSET (0xC8)/* sf_if2_sahb_0 */ +#define SF_CTRL_SF_IF2_SAHB_1_OFFSET (0xCC)/* sf_if2_sahb_1 */ +#define SF_CTRL_SF_IF2_SAHB_2_OFFSET (0xD0)/* sf_if2_sahb_2 */ +#define SF_CTRL_PROT_EN_RD_OFFSET (0x100)/* sf_ctrl_prot_en_rd */ +#define SF_CTRL_PROT_EN_OFFSET (0x104)/* sf_ctrl_prot_en */ +#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)/* sf_aes_key_r0_0 */ +#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)/* sf_aes_key_r0_1 */ +#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)/* sf_aes_key_r0_2 */ +#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)/* sf_aes_key_r0_3 */ +#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)/* sf_aes_key_r0_4 */ +#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)/* sf_aes_key_r0_5 */ +#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)/* sf_aes_key_r0_6 */ +#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)/* sf_aes_key_r0_7 */ +#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)/* sf_aes_iv_r0_w0 */ +#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)/* sf_aes_iv_r0_w1 */ +#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)/* sf_aes_iv_r0_w2 */ +#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)/* sf_aes_iv_r0_w3 */ +#define SF_CTRL_SF_AES_R0_START_OFFSET (0x230)/* sf_aes_r0_start */ +#define SF_CTRL_SF_AES_R0_END_OFFSET (0x234)/* sf_aes_r0_end */ +#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x280)/* sf_aes_key_r1_0 */ +#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x284)/* sf_aes_key_r1_1 */ +#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x288)/* sf_aes_key_r1_2 */ +#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x28C)/* sf_aes_key_r1_3 */ +#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x290)/* sf_aes_key_r1_4 */ +#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x294)/* sf_aes_key_r1_5 */ +#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x298)/* sf_aes_key_r1_6 */ +#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x29C)/* sf_aes_key_r1_7 */ +#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x2A0)/* sf_aes_iv_r1_w0 */ +#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x2A4)/* sf_aes_iv_r1_w1 */ +#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x2A8)/* sf_aes_iv_r1_w2 */ +#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x2AC)/* sf_aes_iv_r1_w3 */ +#define SF_CTRL_SF_AES_R1_START_OFFSET (0x2B0)/* sf_aes_r1_start */ +#define SF_CTRL_SF_AES_R1_END_OFFSET (0x2B4)/* sf_aes_r1_end */ +#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x300)/* sf_aes_key_r2_0 */ +#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x304)/* sf_aes_key_r2_1 */ +#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x308)/* sf_aes_key_r2_2 */ +#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x30C)/* sf_aes_key_r2_3 */ +#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x310)/* sf_aes_key_r2_4 */ +#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x314)/* sf_aes_key_r2_5 */ +#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x318)/* sf_aes_key_r2_6 */ +#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x31C)/* sf_aes_key_r2_7 */ +#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x320)/* sf_aes_iv_r2_w0 */ +#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x324)/* sf_aes_iv_r2_w1 */ +#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x328)/* sf_aes_iv_r2_w2 */ +#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x32C)/* sf_aes_iv_r2_w3 */ +#define SF_CTRL_SF_AES_R2_START_OFFSET (0x330)/* sf_aes_r2_start */ +#define SF_CTRL_SF_AES_R2_END_OFFSET (0x334)/* sf_aes_r2_end */ + +/* Register Bitfield definitions *****************************************************/ + +/* 0x0 : sf_ctrl_0 */ +#define SF_CTRL_SF_CLK_SF_RX_INV_SEL (1<<2U) +#define SF_CTRL_SF_CLK_OUT_GATE_EN (1<<3U) +#define SF_CTRL_SF_CLK_OUT_INV_SEL (1<<4U) +#define SF_CTRL_SF_IF_READ_DLY_N_SHIFT (8U) +#define SF_CTRL_SF_IF_READ_DLY_N_MASK (0x7<reg_base; - regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); - regval |= CAM_REG_DVP_ENABLE; - putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); #if !defined(BL702) #if defined(BL808) - regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET); - if (regval & CAM_FRONT_REG_ISP_DTSRC_SRC) { + if (config->input_source == 0) { regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET); regval |= CAM_FRONT_RG_DVPAS_ENABLE; putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET); @@ -397,6 +385,17 @@ void bflb_cam_start(struct bflb_device_s *dev) #endif } +void bflb_cam_start(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); + regval |= CAM_REG_DVP_ENABLE; + putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); +} + void bflb_cam_stop(struct bflb_device_s *dev) { uint32_t reg_base; @@ -406,12 +405,6 @@ void bflb_cam_stop(struct bflb_device_s *dev) regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); regval &= ~CAM_REG_DVP_ENABLE; putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET); - -#if !defined(BL702) - regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET); - regval &= ~CAM_FRONT_RG_DVPAS_ENABLE; - putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET); -#endif } void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask) diff --git a/drivers/lhal/src/bflb_clock.c b/drivers/lhal/src/bflb_clock.c new file mode 100644 index 00000000..e46bfd78 --- /dev/null +++ b/drivers/lhal/src/bflb_clock.c @@ -0,0 +1,93 @@ +#include "bflb_clock.h" +#if defined(BL702) +#include "bl702_clock.h" +#elif defined(BL702L) +#include "bl702l_clock.h" +#elif defined(BL606P) +#include "bl606p_clock.h" +#elif defined(BL808) +#include "bl808_clock.h" +#elif defined(BL616) +#include "bl616_clock.h" +#elif defined(WB03) +#include "wb03_clock.h" +#elif defined(BL628) +#include "bl628_clock.h" +#endif + +/****************************************************************************/ /** + * @brief get system clock + * + * @param type: BFLB_SYSTEM_XXX + * + * @return NONE + * +*******************************************************************************/ +uint32_t ATTR_CLOCK_SECTION bflb_clk_get_system_clock(uint8_t type) +{ + switch (type) { + case BFLB_SYSTEM_ROOT_CLOCK: + return bflb_clock_get_root(); + case BFLB_SYSTEM_CPU_CLK: + return bflb_clock_get_fclk(); + case BFLB_SYSTEM_PBCLK: + return bflb_clock_get_bclk(); + case BFLB_SYSTEM_XCLK: + return bflb_clock_get_xclk(); + case BFLB_SYSTEM_32K_CLK: + return bflb_clock_get_f32k(); + default: + return 0; + } + return 0; +} + +/****************************************************************************/ /** + * @brief get peripheral clock + * + * @param type: BFLB_DEVICE_TYPE_XXX + * @param idx: peripheral index + * + * @return NONE + * +*******************************************************************************/ +uint32_t ATTR_CLOCK_SECTION bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx) +{ + switch (type) { + case BFLB_DEVICE_TYPE_ADC: + return bflb_clock_get_adc(); + case BFLB_DEVICE_TYPE_DAC: + return bflb_clock_get_dac(); + case BFLB_DEVICE_TYPE_UART: + return bflb_clock_get_uart(); + case BFLB_DEVICE_TYPE_SPI: + return bflb_clock_get_spi(); + case BFLB_DEVICE_TYPE_I2C: + return bflb_clock_get_i2c(); + case BFLB_DEVICE_TYPE_PWM: + return bflb_clock_get_pwm(); + case BFLB_DEVICE_TYPE_TIMER: + return bflb_clock_get_timer(idx); + case BFLB_DEVICE_TYPE_WDT: + return bflb_clock_get_wdt(); + case BFLB_DEVICE_TYPE_FLASH: + return bflb_clock_get_flash(); + case BFLB_DEVICE_TYPE_IR: + return bflb_clock_get_ir(); + case BFLB_DEVICE_TYPE_PKA: + return bflb_clock_get_pka(); + case BFLB_DEVICE_TYPE_SDH: + return bflb_clock_get_sdh(); + case BFLB_DEVICE_TYPE_CAMERA: + return bflb_clock_get_cam(); + case BFLB_DEVICE_TYPE_DBI: + return bflb_clock_get_dbi(); + case BFLB_DEVICE_TYPE_PEC: + return bflb_clock_get_pec(); + case BFLB_DEVICE_TYPE_I2S: + return bflb_clock_get_i2s(); + default: + return 0; + } + return 0; +} diff --git a/drivers/lhal/src/bflb_csi.c b/drivers/lhal/src/bflb_csi.c new file mode 100644 index 00000000..7237e2c3 --- /dev/null +++ b/drivers/lhal/src/bflb_csi.c @@ -0,0 +1,143 @@ +#include "bflb_csi.h" +#include "hardware/csi_reg.h" +#include "hardware/dtsrc_reg.h" + +#define DTSRC_BASE 0x30012800 + +static void bflb_csi_phy_config(struct bflb_device_s *dev, uint32_t tx_clk_escape, uint32_t data_rate) +{ + uint32_t reg_base; + uint32_t regval; + + /* Unit: ns */ + float TD_TERM_EN_MAX = 35 + 4 * (1e3) / data_rate; + uint32_t TD_TERM_EN = (TD_TERM_EN_MAX * data_rate / 2 / (1e3)) - 1; + float THS_SETTLE_MAX = 145 + 10 * (1e3) / data_rate; + /* THS_SETTLE = reg_time_hs_settle + reg_time_hs_term_en */ + uint32_t THS_SETTLE = ((THS_SETTLE_MAX - TD_TERM_EN * 2 * (1e3) / data_rate) * data_rate / 2 / (1e3)) - 1; + uint32_t TCLK_TERM_EN_MAX = 38; + uint32_t TCLK_TERM_EN = (tx_clk_escape * TCLK_TERM_EN_MAX) / (1e3); + uint32_t TCLK_SETTLE_MAX = 300; + /* TCLK_SETTLE = reg_time_ck_settle + reg_time_ck_term_en */ + uint32_t TCLK_SETTLE = ((TCLK_SETTLE_MAX - TCLK_TERM_EN * (1e3) / tx_clk_escape) * tx_clk_escape / (1e3)) - 1; + + uint32_t ANA_TERM_EN = 0x8; + + reg_base = dev->reg_base; + regval = TD_TERM_EN << CSI_REG_TIME_HS_TERM_EN_SHIFT & CSI_REG_TIME_HS_TERM_EN_MASK; + regval |= THS_SETTLE << CSI_REG_TIME_HS_SETTLE_SHIFT & CSI_REG_TIME_HS_SETTLE_MASK; + regval |= TCLK_TERM_EN << CSI_REG_TIME_CK_TERM_EN_SHIFT & CSI_REG_TIME_CK_TERM_EN_MASK; + regval |= TCLK_SETTLE << CSI_REG_TIME_CK_SETTLE_SHIFT & CSI_REG_TIME_CK_SETTLE_MASK; + putreg32(regval, reg_base + CSI_DPHY_CONFIG_1_OFFSET); + + regval = getreg32(DTSRC_BASE + CSI_DPHY_CONFIG_2_OFFSET); + regval &= ~CSI_REG_ANA_TERM_EN_MASK; + regval |= ANA_TERM_EN << CSI_REG_ANA_TERM_EN_SHIFT & CSI_REG_ANA_TERM_EN_MASK; + putreg32(regval, reg_base + CSI_DPHY_CONFIG_2_OFFSET); +} + +void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET); + regval |= DTSRC_CR_SNSR_EN; + putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET); + + regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET); + regval &= ~(CSI_DL0_ENABLE | CSI_DL1_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE | CSI_DL1_FORCERXMODE | CSI_RESET_N); + putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET); + regval |= CSI_RESET_N; + putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET); + + regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET); + if (config->lane_number) { + regval |= CSI_CR_LANE_NUM; + } else { + regval &= ~CSI_CR_LANE_NUM; + } + regval |= CSI_CR_UNPACK_EN | CSI_CR_SYNC_SP_EN; + putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET); + + bflb_csi_phy_config(dev, config->tx_clk_escape / 1000000, config->data_rate / 1000000); + + regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET); + regval |= CSI_DL0_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE; + if (config->lane_number) { + regval |= CSI_DL1_ENABLE | CSI_DL1_FORCERXMODE; + } + putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET); + + regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET); + regval |= DTSRC_CR_ENABLE; + putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET); +} + +void bflb_csi_start(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET); + regval |= CSI_CR_CSI_EN; + putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET); +} + +void bflb_csi_stop(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET); + regval &= ~CSI_CR_CSI_EN; + putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET); +} + +void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock) +{ + uint32_t threshold; + + threshold = (dsp_clock - pixel_clock) / 1000 * resolution_x / (dsp_clock / 1000) + 10; + putreg32(threshold, DTSRC_BASE + DTSRC_SNSR2DVP_WAIT_POS_OFFSET); +} + +void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + CSI_INT_MASK_OFFSET); + if (mask) { + regval |= int_type; + } else { + regval &= ~int_type; + } + putreg32(regval, reg_base + CSI_INT_MASK_OFFSET); +} + +void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type) +{ + putreg32(int_type, dev->reg_base + CSI_INT_CLEAR_OFFSET); +} + +uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev) +{ + return(getreg32(dev->reg_base + CSI_INT_STATUS_OFFSET)); +} + +int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +{ + int ret = 0; + + switch (cmd) { + default: + ret = -EPERM; + break; + } + return ret; +} diff --git a/drivers/lhal/src/bflb_dma.c b/drivers/lhal/src/bflb_dma.c index 656e3b05..4c47772a 100644 --- a/drivers/lhal/src/bflb_dma.c +++ b/drivers/lhal/src/bflb_dma.c @@ -112,7 +112,7 @@ void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_chan regval |= (config->direction << DMA_FLOWCNTRL_SHIFT); putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET); - /* disable dma error and tc interrupt */ + /* enable dma error and tc interrupt */ regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET); regval |= (DMA_ITC | DMA_IE); putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET); diff --git a/drivers/lhal/src/bflb_flash.c b/drivers/lhal/src/bflb_flash.c new file mode 100644 index 00000000..1d8dd26b --- /dev/null +++ b/drivers/lhal/src/bflb_flash.c @@ -0,0 +1,789 @@ + +#if defined(BL616) +#include "bl616_memorymap.h" +#include "bl616_glb.h" +#include "bl616_ef_cfg.h" +#elif defined(BL606P) +#include "bl606p_memorymap.h" +#include "bl606p_glb.h" +#elif defined(BL808) +#include "bl808_memorymap.h" +#include "bl808_glb.h" +#elif defined(BL602) +#include "bl602_glb.h" +#include "bl602_sflash_ext.h" +#include "bl602_xip_sflash_ext.h" +#include "bl602_sf_cfg_ext.h" +#elif defined(BL702) +#include "bl702_glb.h" +#include "bl702_xip_sflash_ext.h" +#include "bl702_sf_cfg_ext.h" +#endif +#include "bflb_xip_sflash.h" +#include "bflb_sf_cfg.h" +#include "bflb_flash.h" +#include "hardware/sf_ctrl_reg.h" + +#if defined(BL616) +static uint32_t flash1_size = 4 * 1024 * 1024; +static uint32_t flash2_size = 2 * 1024 * 1024; +static uint32_t g_jedec_id2 = 0; +#endif +static uint32_t g_jedec_id = 0; +static spi_flash_cfg_type g_flash_cfg = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc8, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = 0x11, + .clk_delay = 0, + .clk_invert = 0x03, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; +#if defined(BL616) +static spi_flash_cfg_type g_flash2_cfg = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc8, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = 0x10, + .clk_delay = 0, + .clk_invert = 0x03, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static bflb_efuse_device_info_type deviceInfo; +#endif + +#if defined(BL616) +uint32_t bflb_flash2_get_jedec_id(void) +{ + uint32_t jid = 0; + + jid = ((g_jedec_id2 & 0xff) << 16) + (g_jedec_id2 & 0xff00) + ((g_jedec_id2 & 0xff0000) >> 16); + return jid; +} +#endif + +#if defined(BL616) || defined(BL606P) || defined(BL808) +static int flash_get_clock_delay(spi_flash_cfg_type *cfg) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_0_OFFSET); + /* bit0-3 for clk delay */ + if (regval & SF_CTRL_SF_IF_READ_DLY_EN) { + cfg->clk_delay = ((regval & SF_CTRL_SF_IF_READ_DLY_N_MASK) >> SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1; + } else { + cfg->clk_delay = 0; + } + cfg->clk_invert = 0; + /* bit0 for clk invert */ + cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_OUT_INV_SEL) ? 1 : 0) << 0); + /* bit1 for rx clk invert */ + cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_SF_RX_INV_SEL) ? 1 : 0) << 1); + + regval = getreg32(reg_base + SF_CTRL_SF_IF_IO_DLY_1_OFFSET); + /* bit4-6 for do delay */ + cfg->clk_delay |= (((regval & SF_CTRL_SF_IO_0_DO_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DO_DLY_SEL_SHIFT) << 4); + /* bit2-4 for di delay */ + cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_DI_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DI_DLY_SEL_SHIFT) << 2); + /* bit5-7 for oe delay */ + cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_OE_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_OE_DLY_SEL_SHIFT) << 5); + + return 0; +} + +static void ATTR_TCM_SECTION flash_set_cmds(spi_flash_cfg_type *p_flash_cfg) +{ + struct sf_ctrl_cmds_cfg cmds_cfg; + + cmds_cfg.ack_latency = 1; + cmds_cfg.cmds_core_en = 1; + cmds_cfg.cmds_en = 1; + cmds_cfg.cmds_wrap_mode = 1; + cmds_cfg.cmds_wrap_len = 9; + + if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) { + cmds_cfg.cmds_wrap_mode = 2; + cmds_cfg.cmds_wrap_len = 2; + } + bflb_sf_ctrl_cmds_set(&cmds_cfg, 0); +} +#endif + +static void ATTR_TCM_SECTION flash_set_qspi_enable(spi_flash_cfg_type *p_flash_cfg) +{ + if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) { + bflb_sflash_qspi_enable(p_flash_cfg); + } +} + +static void ATTR_TCM_SECTION flash_set_l1c_wrap(spi_flash_cfg_type *p_flash_cfg) +{ + if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) { + L1C_Set_Wrap(ENABLE); + bflb_sflash_set_burst_wrap(p_flash_cfg); + } else { + L1C_Set_Wrap(DISABLE); + bflb_sflash_disable_burst_wrap(p_flash_cfg); + } +} + +/** + * @brief flash_config_init + * + * @return int + */ +static int ATTR_TCM_SECTION flash_config_init(spi_flash_cfg_type *p_flash_cfg, uint8_t *jedec_id) +{ + int ret = -1; + uint8_t is_aes_enable = 0; + uint32_t jid = 0; + uint32_t offset = 0; + uintptr_t flag; + + flag = bflb_irq_save(); + bflb_xip_sflash_opt_enter(&is_aes_enable); + bflb_xip_sflash_state_save(p_flash_cfg, &offset, 0, 0); + bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jid); + arch_memcpy(jedec_id, (uint8_t *)&jid, 3); + jid &= 0xFFFFFF; + g_jedec_id = jid; + ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jid, p_flash_cfg, 0, 0); + if (ret == 0) { + p_flash_cfg->mid = (jid & 0xff); + } + + // p_flash_cfg->io_mode = 0x11; + // p_flash_cfg->c_read_support = 0x00; + + /* Set flash controler from p_flash_cfg */ +#if defined(BL616) || defined(BL606P) || defined(BL808) + flash_set_cmds(p_flash_cfg); +#endif + flash_set_qspi_enable(p_flash_cfg); + flash_set_l1c_wrap(p_flash_cfg); +#if defined(BL602) + bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, 0, 0); +#else + bflb_xip_sflash_state_restore(p_flash_cfg, offset, 0, 0); +#endif + bflb_xip_sflash_opt_exit(is_aes_enable); + bflb_irq_restore(flag); + + return ret; +} + +#if defined(BL616) +/** + * @brief flash2 init + * + * @return int + */ +static int ATTR_TCM_SECTION flash2_init(void) +{ + int stat = -1; + uint32_t ret = 0; + uint32_t jid = 0; + + struct sf_ctrl_bank2_cfg sf_bank2_cfg; + struct sf_ctrl_cmds_cfg cmds_cfg; + + sf_bank2_cfg.sbus2_select = 1; + sf_bank2_cfg.bank2_rx_clk_invert_src = 0; + sf_bank2_cfg.bank2_rx_clk_invert_sel = 0; + sf_bank2_cfg.bank2_delay_src = 0; + sf_bank2_cfg.bank2_clk_delay = 1; + sf_bank2_cfg.do_delay = 0; + sf_bank2_cfg.di_delay = 0; + sf_bank2_cfg.oe_delay = 0; + sf_bank2_cfg.remap = SF_CTRL_REMAP_4MB; + sf_bank2_cfg.remap_lock = 1; + + cmds_cfg.ack_latency = 1; + cmds_cfg.cmds_core_en = 1; + cmds_cfg.cmds_en = 1; + cmds_cfg.cmds_wrap_mode = 1; + cmds_cfg.cmds_wrap_len = SF_CTRL_WRAP_LEN_4096; + + if (deviceInfo.memoryInfo == 0) { + /* memoryInfo==0, external flash */ + flash1_size = 64 * 1024 * 1024; + flash2_size = 0; + } else if (deviceInfo.memoryInfo == 1) { + flash1_size = 2 * 1024 * 1024; + flash2_size = 0; + } else if (deviceInfo.memoryInfo == 2) { + flash1_size = 4 * 1024 * 1024; + flash2_size = 0; + } else if (deviceInfo.memoryInfo == 3) { + /* memoryInfo==3, embedded 4MB+2MB flash */ + flash1_size = 4 * 1024 * 1024; + flash2_size = 2 * 1024 * 1024; + } else { + flash1_size = 8 * 1024 * 1024; + flash2_size = 0; + } + + if (flash2_size > 0) { + bflb_sf_cfg_sbus2_flash_init(SF_IO_EMB_SWAP_IO3IO0_AND_SF2, &sf_bank2_cfg); + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + ret = bflb_sf_cfg_flash_identify_ext(0, SF_IO_EMB_SWAP_IO3IO0_AND_SF2, 0, &g_flash2_cfg, 0, SF_CTRL_FLASH_BANK1); + if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) { + return -1; + } + g_flash2_cfg.io_mode = 0x11; + g_flash2_cfg.c_read_support = 0; + g_flash2_cfg.c_read_mode = 0xff; + bflb_sflash_get_jedecid(&g_flash2_cfg, (uint8_t *)&jid); + jid &= 0xFFFFFF; + g_jedec_id2 = jid; + + bflb_sf_ctrl_cmds_set(&cmds_cfg, SF_CTRL_FLASH_BANK1); + stat = bflb_sflash_xip_read_enable(&g_flash2_cfg, (g_flash2_cfg.io_mode & 0xf), 0, SF_CTRL_FLASH_BANK1); + if (0 != stat) { + return -1; + } + bflb_sf_ctrl_sbus2_revoke_replace(); + } + + return 0; +} +#endif + +/** + * @brief multi flash adapter + * + * @return int + */ +int ATTR_TCM_SECTION bflb_flash_init(void) +{ + int ret = -1; + uint32_t jedec_id = 0; +#if defined(BL602) || defined(BL702) + uint8_t clk_delay = 1; + uint8_t clk_invert = 1; + uintptr_t flag; +#endif + +#if defined(BL616) + bflb_ef_ctrl_get_device_info(&deviceInfo); +#endif + +#if defined(BL602) || defined(BL702) + flag = bflb_irq_save(); +#if defined(BL602) + bflb_sflash_cache_flush(); +#else + L1C_Cache_Flush(); +#endif + bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0); +#if defined(BL602) + bflb_sflash_cache_flush(); +#else + L1C_Cache_Flush(); +#endif + bflb_irq_restore(flag); + if (g_flash_cfg.mid != 0xff) { + return 0; + } + clk_delay = g_flash_cfg.clk_delay; + clk_invert = g_flash_cfg.clk_invert; + g_flash_cfg.io_mode &= 0x0f; + + ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); + + g_flash_cfg.clk_delay = clk_delay; + g_flash_cfg.clk_invert = clk_invert; +#else + jedec_id = GLB_Get_Flash_Id_Value(); + if (jedec_id != 0) { + ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0); + if (ret == 0) { + g_jedec_id = jedec_id; + g_flash_cfg.io_mode &= 0x0f; + flash_get_clock_delay(&g_flash_cfg); +#if defined(BL616) + flash2_init(); +#endif + return 0; + } + } + + g_flash_cfg.io_mode &= 0x0f; + ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); + + g_flash_cfg.io_mode &= 0x0f; + flash_get_clock_delay(&g_flash_cfg); + GLB_Set_Flash_Id_Value(g_jedec_id); +#endif + +#if defined(BL616) + flash2_init(); +#endif + + return ret; +} + +uint32_t bflb_flash_get_jedec_id(void) +{ + uint32_t jid = 0; + + jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16); + return jid; +} + +void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) +{ + *cfg_addr = (uint8_t *)&g_flash_cfg; + *len = sizeof(spi_flash_cfg_type); +} + +void ATTR_TCM_SECTION bflb_flash_set_iomode(uint8_t iomode) +{ + uintptr_t flag = 0; + uint8_t is_aes_enable = 0; + uint32_t offset = 0; + + flag = bflb_irq_save(); + bflb_xip_sflash_opt_enter(&is_aes_enable); + bflb_xip_sflash_state_save(&g_flash_cfg, &offset, 0, 0); + + g_flash_cfg.io_mode &= ~0x1f; + if (iomode&4) { + g_flash_cfg.io_mode |= iomode; + } else { + g_flash_cfg.io_mode |= 0x10; + g_flash_cfg.io_mode |= iomode; + } + +#if defined(BL616) || defined(BL606P) || defined(BL808) + flash_set_cmds(&g_flash_cfg); +#endif + flash_set_qspi_enable(&g_flash_cfg); + flash_set_l1c_wrap(&g_flash_cfg); +#if defined(BL602) + bflb_xip_sflash_state_restore_ext(&g_flash_cfg, offset, 0, 0); +#else + bflb_xip_sflash_state_restore(&g_flash_cfg, offset, 0, 0); +#endif + bflb_xip_sflash_opt_exit(is_aes_enable); + bflb_irq_restore(flag); +} + +ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void) +{ + return bflb_sf_ctrl_get_flash_image_offset(0, 0); +} + +/** + * @brief erase flash via sbus + * + * @param flash absolute startaddr + * @param flash absolute endaddr + * @return int + */ +int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len) +{ + int stat = -1; + uintptr_t flag; + +#if defined(BL616) + if ((startaddr + len) > (flash1_size + flash2_size)) { + return -ENOMEM; + } else if ((startaddr + len) <= flash1_size) { + flag = bflb_irq_save(); + stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0); + bflb_irq_restore(flag); + } else if (startaddr >= flash1_size) { + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + stat = bflb_sflash_erase(&g_flash2_cfg, startaddr, startaddr + len - 1); + bflb_sf_ctrl_sbus2_revoke_replace(); + } else { + flag = bflb_irq_save(); + stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, flash1_size - startaddr, 0, 0); + bflb_irq_restore(flag); + if (stat != 0) { + return stat; + } + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + stat = bflb_sflash_erase(&g_flash2_cfg, flash1_size, startaddr + len - flash1_size - 1); + bflb_sf_ctrl_sbus2_revoke_replace(); + } +#else + if (startaddr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) { + return -ENOMEM; + } + + flag = bflb_irq_save(); +#if defined(BL602) + stat = bflb_xip_sflash_erase_need_lock_ext(&g_flash_cfg, startaddr, startaddr+len-1, 0, 0); +#else + stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0); +#endif + bflb_irq_restore(flag); +#endif + + return stat; +} + +/** + * @brief write flash data via sbus + * + * @param flash absolute addr + * @param data + * @param len + * @return int + */ +int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len) +{ + int stat = -1; + uintptr_t flag; + +#if defined(BL616) + if ((addr + len) > (flash1_size + flash2_size)) { + return -ENOMEM; + } else if ((addr + len) <= flash1_size) { + flag = bflb_irq_save(); + stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0); + bflb_irq_restore(flag); + } else if (addr >= flash1_size) { + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, addr, data, len); + bflb_sf_ctrl_sbus2_revoke_replace(); + } else { + flag = bflb_irq_save(); + stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0); + bflb_irq_restore(flag); + if (stat != 0) { + return stat; + } + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, flash1_size, data + (flash1_size - addr), addr + len - flash1_size); + bflb_sf_ctrl_sbus2_revoke_replace(); + } +#else + if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) { + return -ENOMEM; + } + + flag = bflb_irq_save(); +#if defined(BL602) + stat = bflb_xip_sflash_write_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0); +#else + stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0); +#endif + bflb_irq_restore(flag); +#endif + + return stat; +} + +/** + * @brief read flash data via sbus + * + * @param flash absolute addr + * @param data + * @param len + * @return int + */ +int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len) +{ + int stat = -1; + uintptr_t flag; + +#if defined(BL616) + if ((addr + len) > (flash1_size + flash2_size)) { + return -ENOMEM; + } else if ((addr + len) <= flash1_size) { + flag = bflb_irq_save(); + stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0); + bflb_irq_restore(flag); + } else if (addr >= flash1_size) { + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, addr, data, len); + bflb_sf_ctrl_sbus2_revoke_replace(); + } else { + flag = bflb_irq_save(); + stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0); + bflb_irq_restore(flag); + if (stat != 0) { + return stat; + } + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, flash1_size, data + (flash1_size - addr), addr + len - flash1_size); + bflb_sf_ctrl_sbus2_revoke_replace(); + } +#else + if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) { + return -ENOMEM; + } + + flag = bflb_irq_save(); +#if defined(BL602) + stat = bflb_xip_sflash_read_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0); +#else + stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0); +#endif + bflb_irq_restore(flag); +#endif + + return stat; +} + +int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) +{ + uint8_t is_aes_enable = 0; + uint32_t tmp[1]; + int stat; + + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + + bflb_xip_sflash_opt_enter(&is_aes_enable); + /* To make it simple, exit cont read anyway */ + bflb_sflash_reset_continue_read(&g_flash_cfg); + + if (g_flash_cfg.c_read_support == 0) { + cont_read = 0; + } + + if (cont_read == 1) { + stat = bflb_sflash_read(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + + if (0 != stat) { + bflb_xip_sflash_opt_exit(is_aes_enable); + return -1; + } + } + +#if defined(BL602) || defined(BL702) +#if defined(BL602) + bflb_sflash_cache_enable_set(0xf); +#else + L1C_Cache_Enable_Set(0xf); +#endif + + if (cache_enable) { + bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0); + bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0); + } +#if defined(BL602) + bflb_sflash_cache_enable_set(cache_way_disable); +#else + L1C_Cache_Enable_Set(cache_way_disable); +#endif +#else + bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0); + bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0); +#endif + + bflb_xip_sflash_opt_exit(is_aes_enable); + + return 0; +} + +void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config) +{ + uint8_t hw_key_enable = 0; + + if (config->key == NULL) { + hw_key_enable = 1; + } + + bflb_sf_ctrl_aes_set_key_be(config->region, (uint8_t *)config->key, config->keybits); + bflb_sf_ctrl_aes_set_iv_be(config->region, (uint8_t *)config->iv, config->start_addr); + bflb_sf_ctrl_aes_set_region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable); +} + +void bflb_flash_aes_enable(void) +{ + bflb_sf_ctrl_aes_enable(); +} + +void bflb_flash_aes_disable(void) +{ + bflb_sf_ctrl_aes_disable(); +} \ No newline at end of file diff --git a/drivers/lhal/src/bflb_gpio.c b/drivers/lhal/src/bflb_gpio.c index e89948ba..6393bc7a 100644 --- a/drivers/lhal/src/bflb_gpio.c +++ b/drivers/lhal/src/bflb_gpio.c @@ -151,6 +151,38 @@ bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin) #endif } +void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val) +{ +#if defined(BL702) || defined(BL602) || defined(BL702L) + putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET); +#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) + putreg32(val, dev->reg_base + GLB_GPIO_CFG136_OFFSET); +#endif +} +void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val) +{ +#if defined(BL702) || defined(BL602) || defined(BL702L) + putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL33_OFFSET); +#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) + putreg32(val, dev->reg_base + GLB_GPIO_CFG137_OFFSET); +#endif +} +uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev) +{ +#if defined(BL702) || defined(BL602) || defined(BL702L) + return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET)); +#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) + return (getreg32(dev->reg_base + GLB_GPIO_CFG128_OFFSET)); +#endif +} +uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev) +{ +#if defined(BL702) || defined(BL602) || defined(BL702L) + return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL31_OFFSET)); +#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) + return (getreg32(dev->reg_base + GLB_GPIO_CFG129_OFFSET)); +#endif +} void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode) { uint32_t reg_base; diff --git a/drivers/lhal/src/bflb_i2s.c b/drivers/lhal/src/bflb_i2s.c new file mode 100644 index 00000000..95b1074a --- /dev/null +++ b/drivers/lhal/src/bflb_i2s.c @@ -0,0 +1,341 @@ +#include "bflb_i2s.h" +#include "bflb_clock.h" +#include "hardware/i2s_reg.h" + +void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config) +{ + uint32_t reg_base; + uint32_t regval; + uint32_t div; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + I2S_CONFIG_OFFSET); + /* disable I2S */ + regval &= ~I2S_CR_I2S_M_EN; + regval &= ~I2S_CR_I2S_S_EN; + regval &= ~I2S_CR_I2S_TXD_EN; + regval &= ~I2S_CR_I2S_TXD_EN; + putreg32(regval, reg_base + I2S_CONFIG_OFFSET); + + if (config->channel_mode == I2S_CHANNEL_MODE_NUM_1) { + /* Mono mode */ + regval |= I2S_CR_MONO_MODE; + regval &= ~I2S_CR_FS_CH_CNT_MASK; + } else { + regval &= ~I2S_CR_MONO_MODE; + regval &= ~I2S_CR_FS_CH_CNT_MASK; + regval |= (config->channel_mode - 1) << I2S_CR_FS_CH_CNT_SHIFT; + } + + /* disable mute */ + regval &= ~I2S_CR_MUTE_MODE; + + if (config->format_mode == I2S_MODE_DSP_SHORT_FRAME_SYNC) { + /* dsp modeA/B short frame sync, there is only one bclk cycle */ + regval |= I2S_CR_FS_1T_MODE; + } else { + regval &= ~I2S_CR_FS_1T_MODE; + } + + /* frame/data width */ + regval &= ~I2S_CR_FRAME_SIZE_MASK; + regval &= ~I2S_CR_DATA_SIZE_MASK; + regval |= config->frame_width << I2S_CR_FRAME_SIZE_SHIFT; + regval |= config->data_width << I2S_CR_DATA_SIZE_SHIFT; + + if (config->format_mode == I2S_MODE_LEFT_JUSTIFIED) { + /* left justified*/ + regval &= ~I2S_CR_I2S_MODE_MASK; + } else if (config->format_mode == I2S_MODE_RIGHT_JUSTIFIED) { + /* right justified*/ + regval &= ~I2S_CR_I2S_MODE_MASK; + regval |= 1 << I2S_CR_I2S_MODE_SHIFT; + } else { + /* dsp mode */ + regval &= ~I2S_CR_I2S_MODE_MASK; + regval |= 2 << I2S_CR_I2S_MODE_SHIFT; + } + + /* fs_offset_cycle */ + if (config->fs_offset_cycle) { + regval |= I2S_CR_OFS_EN; + regval &= ~I2S_CR_OFS_CNT_MASK; + regval |= ((config->fs_offset_cycle - 1) << I2S_CR_OFS_CNT_SHIFT) & I2S_CR_OFS_CNT_MASK; + } else { + regval &= ~I2S_CR_OFS_EN; + } + + /* rx mono mode L-channel */ + regval &= ~I2S_CR_MONO_RX_CH; + /* MSB */ + regval &= ~I2S_CR_ENDIAN; + + putreg32(regval, reg_base + I2S_CONFIG_OFFSET); + + /* integer frequency segmentation by rounding */ + div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2S, dev->idx) / 2 * 10 / config->bclk_freq_hz + 5) / 10; + div = (div) ? (div - 1) : 0; + div = (div > 0xfff) ? 0xfff : div; + + /* bclk timing config */ + regval = getreg32(reg_base + I2S_BCLK_CONFIG_OFFSET); + regval &= ~I2S_CR_BCLK_DIV_L_MASK; + regval &= ~I2S_CR_BCLK_DIV_H_MASK; + regval |= div << I2S_CR_BCLK_DIV_L_SHIFT; + regval |= div << I2S_CR_BCLK_DIV_H_SHIFT; + putreg32(regval, reg_base + I2S_BCLK_CONFIG_OFFSET); + + /* fifo threshold config */ + regval = getreg32(reg_base + I2S_FIFO_CONFIG_1_OFFSET); + regval &= ~I2S_TX_FIFO_TH_MASK; + regval &= ~I2S_RX_FIFO_TH_MASK; + regval |= (config->tx_fifo_threshold << I2S_TX_FIFO_TH_SHIFT) & I2S_TX_FIFO_TH_MASK; + regval |= (config->tx_fifo_threshold << I2S_RX_FIFO_TH_SHIFT) & I2S_RX_FIFO_TH_MASK; + putreg32(regval, reg_base + I2S_FIFO_CONFIG_1_OFFSET); + + regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); + /* 32bit to 24bit */ + regval &= ~I2S_CR_FIFO_24B_LJ; + /* Exchange L/R channel data */ + regval &= ~I2S_CR_FIFO_LR_EXCHG; + /* Each FIFO entry contains both L/R channel data */ + regval &= ~I2S_CR_FIFO_LR_MERGE; + /* disable dma */ + regval &= ~I2S_DMA_TX_EN; + regval &= ~I2S_DMA_RX_EN; + /* clean fifo */ + regval |= I2S_TX_FIFO_CLR; + regval |= I2S_RX_FIFO_CLR; + putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET); + + regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET); + /* disable deglitch */ + regval &= ~I2S_CR_DEG_EN; + /* disable inverse signal */ + regval &= ~I2S_CR_I2S_BCLK_INV; + regval &= ~I2S_CR_I2S_FS_INV; + regval &= ~I2S_CR_I2S_RXD_INV; + regval &= ~I2S_CR_I2S_TXD_INV; + putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET); + + /* enable I2S, but disable tx and rx */ + regval = getreg32(reg_base + I2S_CONFIG_OFFSET); + if (config->role == I2S_ROLE_MASTER) { + regval |= I2S_CR_I2S_M_EN; + } else { + regval |= I2S_CR_I2S_S_EN; + } + putreg32(regval, reg_base + I2S_CONFIG_OFFSET); +} + +void bflb_i2s_deinit(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + /* disable I2S */ + regval = getreg32(reg_base + I2S_CONFIG_OFFSET); + regval &= ~I2S_CR_I2S_S_EN; + regval &= ~I2S_CR_I2S_M_EN; + putreg32(regval, reg_base + I2S_CONFIG_OFFSET); +} + +void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); + if (enable) { + regval |= I2S_DMA_TX_EN; + } else { + regval &= ~I2S_DMA_TX_EN; + } + putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET); +} + +void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); + if (enable) { + regval |= I2S_DMA_RX_EN; + } else { + regval &= ~I2S_DMA_RX_EN; + } + putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET); +} + +void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask) +{ + uint32_t regval; + uint32_t reg_base = dev->reg_base; + + regval = getreg32(reg_base + I2S_INT_STS_OFFSET); + if (mask) { + regval |= I2S_CR_I2S_TXF_MASK; + } else { + regval &= ~I2S_CR_I2S_TXF_MASK; + } + putreg32(regval, reg_base + I2S_INT_STS_OFFSET); +} + +void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask) +{ + uint32_t regval; + uint32_t reg_base = dev->reg_base; + + regval = getreg32(reg_base + I2S_INT_STS_OFFSET); + if (mask) { + regval |= I2S_CR_I2S_RXF_MASK; + } else { + regval &= ~I2S_CR_I2S_RXF_MASK; + } + putreg32(regval, reg_base + I2S_INT_STS_OFFSET); +} + +void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask) +{ + uint32_t regval; + uint32_t reg_base = dev->reg_base; + + regval = getreg32(reg_base + I2S_INT_STS_OFFSET); + if (mask) { + regval |= I2S_CR_I2S_FER_MASK; + } else { + regval &= ~I2S_CR_I2S_FER_MASK; + } + putreg32(regval, reg_base + I2S_INT_STS_OFFSET); +} + +uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t int_status; + uint32_t int_mask; + + reg_base = dev->reg_base; + + int_status = getreg32(reg_base + I2S_INT_STS_OFFSET) & 0x1f; + + int_mask = (getreg32(reg_base + I2S_INT_STS_OFFSET) >> 8) & 0x1f; + + return (int_status & ~int_mask); +} + +int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +{ + int ret = 0; + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + + switch (cmd) { + case I2S_CMD_CLEAR_TX_FIFO: + /* clear tx fifo */ + regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); + regval |= I2S_TX_FIFO_CLR; + putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET); + break; + + case I2S_CMD_CLEAR_RX_FIFO: + /* clear rx fifo */ + regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); + regval |= I2S_RX_FIFO_CLR; + putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET); + break; + + case I2S_CMD_RX_DEGLITCH: + /* set rx deglitch, arg: deglitch cycle count (unit: cycle of I2S kernel clock) */ + regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET); + if (arg) { + regval |= I2S_CR_DEG_EN; + regval &= ~I2S_CR_DEG_CNT_MASK; + regval |= (arg << I2S_CR_DEG_CNT_SHIFT) & I2S_CR_DEG_CNT_MASK; + } else { + regval &= ~I2S_CR_DEG_EN; + } + putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET); + break; + + case I2S_CMD_DATA_ENABLE: + /* data enable, arg: use @ref I2S_CMD_DATA_ENABLE_TYPE */ + regval = getreg32(reg_base + I2S_CONFIG_OFFSET); + /* enable tx data signal */ + if (arg & I2S_CMD_DATA_ENABLE_TX) { + regval |= I2S_CR_I2S_TXD_EN; + } else { + regval &= ~I2S_CR_I2S_TXD_EN; + } + /* enable rx data signal */ + if (arg & I2S_CMD_DATA_ENABLE_RX) { + regval |= I2S_CR_I2S_RXD_EN; + } else { + regval &= ~I2S_CR_I2S_RXD_EN; + } + putreg32(regval, reg_base + I2S_CONFIG_OFFSET); + break; + + case I2S_CMD_CHANNEL_LR_MERGE: + /* Each FIFO entry contains both L/R channel data , + can only be enabled if data size is 8 or 16 bits, + arg use true or false */ + regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); + if (arg) { + regval |= I2S_CR_FIFO_LR_MERGE; + } else { + regval &= ~I2S_CR_FIFO_LR_MERGE; + } + putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET); + break; + + case I2S_CMD_CHANNEL_LR_EXCHG: + /* The position of L/R channel data within each entry is exchanged, + can only be enabled if data size is 8 or 16 bits and I2S_CMD_CHANNEL_LR_MERGE is enabled, + arg use true or false */ + regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET); + if (arg) { + regval |= I2S_CR_FIFO_LR_EXCHG; + } else { + regval &= ~I2S_CR_FIFO_LR_EXCHG; + } + putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET); + break; + + case I2S_CMD_MUTE: + /* Enable mute, arg use true or false */ + regval = getreg32(reg_base + I2S_CONFIG_OFFSET); + if (arg) { + regval |= I2S_CR_MUTE_MODE; + } else { + regval &= ~I2S_CR_MUTE_MODE; + } + putreg32(regval, reg_base + I2S_CONFIG_OFFSET); + break; + + case I2S_CMD_BIT_REVERSE: + /* Data endian (bit reverse), arg use true or false, true: MSB goes out first, false: LSB goes out first*/ + regval = getreg32(reg_base + I2S_CONFIG_OFFSET); + if (arg) { + regval |= I2S_CR_MUTE_MODE; + } else { + regval &= ~I2S_CR_MUTE_MODE; + } + putreg32(regval, reg_base + I2S_CONFIG_OFFSET); + break; + + default: + ret = -EPERM; + break; + } + + return ret; +} \ No newline at end of file diff --git a/drivers/lhal/src/bflb_l1c.c b/drivers/lhal/src/bflb_l1c.c index 0b8af078..d0f61c2a 100644 --- a/drivers/lhal/src/bflb_l1c.c +++ b/drivers/lhal/src/bflb_l1c.c @@ -115,4 +115,74 @@ ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size #endif } +#if defined(BL702) || defined(BL702L) +/****************************************************************************/ /** + * @brief L1C cache write set + * + * @param wt_en: L1C write through enable + * @param wb_en: L1C write back enable + * @param wa_en: L1C write allocate enable + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en) +{ + uint32_t regval = 0; + + regval = getreg32(0x40009000 + 0x0); + + if (wt_en) { + regval |= (1<<4); + } else { + regval &= ~(1<<4); + } + + if (wb_en) { + regval |= (1<<5); + } else { + regval &= ~(1<<5); + } + + if (wa_en) { + regval |= (1<<6); + } else { + regval &= ~(1<<6); + } + + putreg32(regval, 0x40009000+0x0); +} +#endif + +/****************************************************************************/ /** + * @brief Get hit count + * + * @param hit_count_low: hit count low 32 bits pointer + * @param hit_count_high: hit count high 32 bits pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high) +{ + *hit_count_low = getreg32(0x40009000 + 0x4); + *hit_count_high = getreg32(0x40009000 + 0x8); +} + +/****************************************************************************/ /** + * @brief Get miss count + * + * @param None + * + * @return Miss count + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION bflb_l1c_miss_count_get(void) +{ + return getreg32(0x40009000 + 0xC); +} + #endif \ No newline at end of file diff --git a/drivers/lhal/src/bflb_spi_psram.c b/drivers/lhal/src/bflb_spi_psram.c new file mode 100644 index 00000000..566663ae --- /dev/null +++ b/drivers/lhal/src/bflb_spi_psram.c @@ -0,0 +1,774 @@ +/** + ****************************************************************************** + * @file bflb_spi_psram.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bflb_spi_psram.h" +#include "bflb_l1c.h" + +/** @addtogroup BFLB_Peripheral_Driver + * @{ + */ + +/** @addtogroup PSRAM + * @{ + */ + +/** @defgroup PSRAM_Private_Macros + * @{ + */ + +/*@} end of group PSRAM_Private_Macros */ + +/** @defgroup PSRAM_Private_Types + * @{ + */ + +/*@} end of group PSRAM_Private_Types */ + +/** @defgroup PSRAM_Private_Variables + * @{ + */ + +/*@} end of group PSRAM_Private_Variables */ + +/** @defgroup PSRAM_Global_Variables + * @{ + */ + +/*@} end of group PSRAM_Global_Variables */ + +/** @defgroup PSRAM_Private_Fun_Declaration + * @{ + */ + +/*@} end of group PSRAM_Private_Fun_Declaration */ + +/** @defgroup PSRAM_Private_Functions + * @{ + */ + +/*@} end of group PSRAM_Private_Functions */ + +/** @defgroup PSRAM_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init serial psram control interface + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param cmds_cfg: Serial Serial Flash controller configuration pointer + * @param sf_ctrl_psram_cfg: Serial psram controller configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg, + struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg) +{ + bflb_sf_ctrl_psram_init(sf_ctrl_psram_cfg); + bflb_sf_ctrl_cmds_set(cmds_cfg, 0); + +#if defined(BL702L) + bflb_sf_ctrl_burst_toggle_set(psram_cfg->burst_toggle_en, psram_cfg->ctrl_mode); +#endif + bflb_psram_setdrivestrength(psram_cfg); + bflb_psram_setburstwrap(psram_cfg); +} + +/****************************************************************************/ /** + * @brief Read psram register + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param reg_value: Register value pointer to store data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value) +{ + uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type psram_cmd; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) { + psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES; + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + } + + psram_cmd.cmd_buf[0] = (psram_cfg->read_reg_cmd) << 24; + psram_cmd.rw_flag = SF_CTRL_READ; + psram_cmd.addr_size = 3; + psram_cmd.dummy_clks = psram_cfg->read_reg_dmy_clk; + psram_cmd.nb_data = 1; + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return; + } + } + + arch_memcpy(reg_value, psram_ctrl_buf, 1); +} + +/****************************************************************************/ /** + * @brief Write psram register + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param reg_value: Register value pointer storing data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value) +{ + uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE; + struct sf_ctrl_cmd_cfg_type psram_cmd; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + arch_memcpy(psram_ctrl_buf, reg_value, 1); + + if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) { + psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES; + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + } + + psram_cmd.cmd_buf[0] = (psram_cfg->write_reg_cmd) << 24; + psram_cmd.rw_flag = SF_CTRL_WRITE; + psram_cmd.addr_size = 3; + psram_cmd.nb_data = 1; + + bflb_sf_ctrl_sendcmd(&psram_cmd); +} + +/****************************************************************************/ /** + * @brief Set psram driver strength + * + * @param psram_cfg: Serial psram parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg) +{ + uint32_t stat = 0; + + bflb_psram_readreg(psram_cfg, (uint8_t *)&stat); + + if ((stat & 0x3) == psram_cfg->drive_strength) { + return 0; + } + + stat &= (~0x3); + stat |= psram_cfg->drive_strength; + + bflb_psram_writereg(psram_cfg, (uint8_t *)&stat); + /* Wait for write done */ + + bflb_psram_readreg(psram_cfg, (uint8_t *)&stat); + + if ((stat & 0x3) == psram_cfg->drive_strength) { + return 0; + } + + return -1; +} + +/****************************************************************************/ /** + * @brief Set psram burst wrap size + * + * @param psram_cfg: Serial psram parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg) +{ + uint32_t stat = 0; + + bflb_psram_readreg(psram_cfg, (uint8_t *)&stat); + + if (((stat >> 5) & 0x3) == psram_cfg->burst_length) { + return 0; + } + + stat &= (~(0x3 << 5)); + stat |= (psram_cfg->burst_length << 5); + + bflb_psram_writereg(psram_cfg, (uint8_t *)&stat); + /* Wait for write done */ + + bflb_psram_readreg(psram_cfg, (uint8_t *)&stat); + + if (((stat >> 5) & 0x3) == psram_cfg->burst_length) { + return 0; + } + + return -1; +} + +/****************************************************************************/ /** + * @brief Get psram ID + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param data: Data pointer to store read data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data) +{ + uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type psram_cmd; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + psram_cmd.cmd_buf[0] = (psram_cfg->read_id_cmd) << 24; + psram_cmd.rw_flag = SF_CTRL_READ; + psram_cmd.addr_size = 3; + psram_cmd.dummy_clks = psram_cfg->read_id_dmy_clk; + psram_cmd.nb_data = 8; + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return; + } + } + + arch_memcpy(data, psram_ctrl_buf, 8); +} + +/****************************************************************************/ /** + * @brief Psram enter quad mode + * + * @param psram_cfg: Serial psram parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg) +{ + struct sf_ctrl_cmd_cfg_type psram_cmd; + uint32_t timeout = 0; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + psram_cmd.cmd_buf[0] = (psram_cfg->enter_quad_mode_cmd) << 24; + psram_cmd.rw_flag = SF_CTRL_READ; + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Psram exit quad mode + * + * @param psram_cfg: Serial psram parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg) +{ + struct sf_ctrl_cmd_cfg_type psram_cmd; + uint32_t timeout = 0; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES; + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + + psram_cmd.cmd_buf[0] = (psram_cfg->exit_quad_mode_cmd) << 24; + psram_cmd.rw_flag = SF_CTRL_READ; + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Psram toggle burst length + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param ctrl_mode: Psram ctrl mode type + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode) +{ + struct sf_ctrl_cmd_cfg_type psram_cmd; + uint32_t timeout = 0; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + if (ctrl_mode == PSRAM_QPI_CTRL_MODE) { + psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES; + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + } + + psram_cmd.cmd_buf[0] = (psram_cfg->burst_toggle_cmd) << 24; + psram_cmd.rw_flag = SF_CTRL_READ; + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Psram software reset + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param ctrl_mode: Psram ctrl mode type + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode) +{ + struct sf_ctrl_cmd_cfg_type psram_cmd; + uint32_t timeout = 0; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + if (ctrl_mode == PSRAM_QPI_CTRL_MODE) { + psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES; + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + } + + /* Reset enable */ + psram_cmd.cmd_buf[0] = (psram_cfg->reset_enable_cmd) << 24; + /* rw_flag don't care */ + psram_cmd.rw_flag = SF_CTRL_READ; + /* Wait for write done */ + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + /* Reset */ + psram_cmd.cmd_buf[0] = (psram_cfg->reset_cmd) << 24; + /* rw_flag don't care */ + psram_cmd.rw_flag = SF_CTRL_READ; + bflb_sf_ctrl_sendcmd(&psram_cmd); + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + arch_delay_us(50); + return 0; +} + +/****************************************************************************/ /** + * @brief Psram set IDbus config + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param io_mode: Psram ctrl mode type + * @param addr: Address to read/write + * @param len: Data length to read/write + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, + uint8_t io_mode, uint32_t addr, uint32_t len) +{ + uint8_t cmd, dummy_clks; + struct sf_ctrl_cmd_cfg_type psram_cmd; + uint8_t cmd_valid = 1; + + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB); + + /* read mode cache set */ + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + if (SF_CTRL_NIO_MODE == io_mode) { + cmd = psram_cfg->f_read_cmd; + dummy_clks = psram_cfg->f_read_dmy_clk; + } else if (SF_CTRL_QIO_MODE == io_mode) { + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = psram_cfg->f_read_quad_cmd; + dummy_clks = psram_cfg->f_read_quad_dmy_clk; + } else { + return -1; + } + + /* prepare command */ + psram_cmd.rw_flag = SF_CTRL_READ; + psram_cmd.addr_size = 3; + psram_cmd.cmd_buf[0] = (cmd << 24) | addr; + psram_cmd.dummy_clks = dummy_clks; + psram_cmd.nb_data = len; + bflb_sf_ctrl_psram_read_set(&psram_cmd, cmd_valid); + + /* write mode cache set */ + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + if (SF_CTRL_NIO_MODE == io_mode) { + cmd = psram_cfg->write_cmd; + } else if (SF_CTRL_QIO_MODE == io_mode) { + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = psram_cfg->quad_write_cmd; + } else { + return -1; + } + + dummy_clks = 0; + + /* prepare command */ + psram_cmd.rw_flag = SF_CTRL_WRITE; + psram_cmd.addr_size = 3; + psram_cmd.cmd_buf[0] = (cmd << 24) | addr; + psram_cmd.dummy_clks = dummy_clks; + psram_cmd.nb_data = len; + bflb_sf_ctrl_psram_write_set(&psram_cmd, cmd_valid); + return 0; +} + +/****************************************************************************/ /** + * @brief Set cache write to psram with cache + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param io_mode: Psram controller interface mode + * @param wt_en: Psram cache write through enable + * @param wb_en: Psram cache write back enable + * @param wa_en: Psram cache write allocate enable + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, + uint8_t wt_en, uint8_t wb_en, uint8_t wa_en) +{ + int stat = -1; + + /* Cache now only support 32 bytes read */ + stat = bflb_psram_set_idbus_cfg(psram_cfg, io_mode, 0, 32); + + if (0 != stat) { + return stat; + } + + bflb_l1c_cache_write_set(wt_en, wb_en, wa_en); + return 0; +} + +/****************************************************************************/ /** + * @brief Write psram one region + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param io_mode: Write mode: SPI mode or QPI mode + * @param addr: Start address to be write + * @param data: Data pointer to be write + * @param len: Data length to be write + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, + uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE; + uint32_t i = 0, cur_len = 0; + uint32_t burst_len = 512; + uint8_t cmd; + struct sf_ctrl_cmd_cfg_type psram_cmd; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + if (SF_CTRL_NIO_MODE == io_mode) { + cmd = psram_cfg->write_cmd; + } else if (SF_CTRL_QIO_MODE == io_mode) { + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = psram_cfg->quad_write_cmd; + } else { + return -1; + } + + /* Prepare command */ + psram_cmd.rw_flag = SF_CTRL_WRITE; + psram_cmd.addr_size = 3; + + if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) { + burst_len = 16; + } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) { + burst_len = 32; + } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) { + burst_len = 64; + } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) { + burst_len = 512; + } + + for (i = 0; i < len;) { + /* Get current programmed length within page size */ + cur_len = burst_len - addr % burst_len; + + if (cur_len > len - i) { + cur_len = len - i; + } + + /* Prepare command */ + arch_memcpy_fast(psram_ctrl_buf, data, cur_len); + psram_cmd.cmd_buf[0] = (cmd << 24) | (addr); + psram_cmd.nb_data = cur_len; + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + /* Adjust address and programmed length */ + addr += cur_len; + i += cur_len; + data += cur_len; + + /* Wait for write done */ + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Read data from psram + * + * @param psram_cfg: Serial psram parameter configuration pointer + * @param io_mode: IoMode: psram controller interface mode + * @param addr: Psram read start address + * @param data: Data pointer to store data read from psram + * @param len: Data length to read + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, + uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE; + uint32_t cur_len, i; + uint32_t burst_len = 512; + uint32_t timeout = 0; + uint8_t cmd, dummy_clks; + struct sf_ctrl_cmd_cfg_type psram_cmd; + + if (((uint32_t)&psram_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4); + } else { + arch_memset(&psram_cmd, 0, sizeof(psram_cmd)); + } + + if (SF_CTRL_NIO_MODE == io_mode) { + cmd = psram_cfg->f_read_cmd; + dummy_clks = psram_cfg->f_read_dmy_clk; + } else if (SF_CTRL_QIO_MODE == io_mode) { + psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + psram_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = psram_cfg->f_read_quad_cmd; + dummy_clks = psram_cfg->f_read_quad_dmy_clk; + } else { + return -1; + } + + /* Prepare command */ + psram_cmd.rw_flag = SF_CTRL_READ; + psram_cmd.addr_size = 3; + psram_cmd.dummy_clks = dummy_clks; + + if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) { + burst_len = 16; + } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) { + burst_len = 32; + } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) { + burst_len = 64; + } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) { + burst_len = 512; + } + + /* Read data */ + for (i = 0; i < len;) { + /* Prepare command */ + psram_cmd.cmd_buf[0] = (cmd << 24) | (addr); + cur_len = burst_len - addr % burst_len; + + if (cur_len > len - i) { + cur_len = len - i; + } + + if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) { + cur_len = NOR_FLASH_CTRL_BUF_SIZE; + psram_cmd.nb_data = cur_len; + } else { + /* Make sf_ctrl word read */ + psram_cmd.nb_data = ((cur_len + 3) >> 2) << 2; + } + + bflb_sf_ctrl_sendcmd(&psram_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + arch_memcpy_fast(data, psram_ctrl_buf, cur_len); + + addr += cur_len; + i += cur_len; + data += cur_len; + } + + return 0; +} + +/*@} end of group PSRAM_Public_Functions */ + +/*@} end of group PSRAM */ + +/*@} end of group BFLB_Peripheral_Driver */ diff --git a/drivers/lhal/src/bflb_timer.c b/drivers/lhal/src/bflb_timer.c index 697aa4c0..7e93a146 100644 --- a/drivers/lhal/src/bflb_timer.c +++ b/drivers/lhal/src/bflb_timer.c @@ -199,4 +199,94 @@ void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no) regval = getreg32(reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx); regval |= (1 << cmp_no); putreg32(regval, reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx); -} \ No newline at end of file +} + +#if !defined(BL702) && !defined(BL602) +void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; +#if defined(BL702L) + regval = getreg32(0x20000000 + 0xc); + regval &= ~(0x3 << 14); + switch (config->pin & 0x03) { + case 0: + regval &= ~(1 << 10); + regval |= (0 << 14); + break; + case 1: + regval &= ~(1 << 11); + regval |= (1 << 14); + break; + case 2: + regval &= ~(1 << 12); + regval |= (2 << 14); + break; + case 3: + regval &= ~(1 << 13); + regval |= (3 << 14); + break; + + default: + break; + } + putreg32(regval, 0x20000000 + 0xc); + struct bflb_device_s *gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, config->pin, (0 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1); +#else + regval = getreg32(0x20000000 + 0x258); + regval &= ~(3 << 12); + switch (config->pin & 0x03) { + case 0: + regval &= ~(1 << 8); + regval |= (0 << 12); + break; + case 1: + regval &= ~(1 << 9); + regval |= (1 << 12); + break; + case 2: + regval &= ~(1 << 10); + regval |= (2 << 12); + break; + case 3: + regval &= ~(1 << 11); + regval |= (3 << 12); + break; + + default: + break; + } + putreg32(regval, 0x20000000 + 0x258); + struct bflb_device_s *gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, config->pin, (31 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1); +#endif + + regval = getreg32(reg_base + TIMER_GPIO_OFFSET); + /* polarity: 1->neg, 0->pos */ + if (config->polarity == TIMER_CAPTURE_POLARITY_NEGATIVE) { + regval |= (1 << (5 + dev->idx)); + } else { + regval &= ~(1 << (5 + dev->idx)); + } + regval |= TIMER0_GPIO_EN; + putreg32(regval, reg_base + TIMER_GPIO_OFFSET); +} + +uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t lat1 = 0; + uint32_t lat2 = 0; + reg_base = dev->reg_base; + + do { + lat1 = getreg32(reg_base + TIMER_GPIO_LAT1_OFFSET); + lat2 = getreg32(reg_base + TIMER_GPIO_LAT2_OFFSET); + } while (!(getreg32(reg_base + TIMER_GPIO_OFFSET) & TIMER_GPIO_LAT_OK) || (lat1 >= lat2)); + + return (lat2 - lat1); +} +#endif diff --git a/drivers/lhal/src/flash/bflb_sf_cfg.c b/drivers/lhal/src/flash/bflb_sf_cfg.c new file mode 100644 index 00000000..95a21f1d --- /dev/null +++ b/drivers/lhal/src/flash/bflb_sf_cfg.c @@ -0,0 +1,3704 @@ +/** + ****************************************************************************** + * @file bflb_sf_cfg.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" +#include "bflb_xip_sflash.h" +#include "soft_crc.h" + +/** @addtogroup BL628_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Private_Macros + * @{ + */ +#define BFLB_FLASH_CFG_MAGIC "FCFG" + +/*@} end of group SF_CFG_Private_Macros */ + +/** @defgroup SF_CFG_Private_Types + * @{ + */ +typedef struct +{ + uint32_t jedec_id; + char *name; + const spi_flash_cfg_type *cfg; +}flash_info_t; + +/*@} end of group SF_CFG_Private_Types */ + +/** @defgroup SF_CFG_Private_Variables + * @{ + */ +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_80dv = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xef, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0xFF, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3d, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 3, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_16jv = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xef, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3d, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 3, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_80ew_16fw_32jw_32fw_32fv = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xef, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xa0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 400, + .time_e_32k = 1600, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 3, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_128jw_128jv = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xef, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0xFF, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 400, + .time_e_32k = 1600, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 3, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_issi = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x9d, + + .de_burst_wrap_cmd = 0xC0, + .de_burst_wrap_cmd_dmy_clk = 0x00, + .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .de_burst_wrap_data = 0x00, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0, + .qe_bit = 0x06, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xA0, + + .burst_wrap_cmd = 0xC0, + .burst_wrap_cmd_dmy_clk = 0x00, + .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .burst_wrap_data = 0x06, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 5, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_md_40d = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x51, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0xA0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_DO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_lq08c_le16c_lq32d_wq32e = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc8, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_q80e_q16e = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc8, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xA0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_wq80e_wq16e = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc8, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 32 / 8, + .c_read_support = 1, + .c_read_mode = 0xA0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 8 / 8, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 20, + .qe_data = 0x12, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_q32e_q128e = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc8, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xC2, + + .de_burst_wrap_cmd = 0xC0, + .de_burst_wrap_cmd_dmy_clk = 0x00, + .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .de_burst_wrap_data = 0x10, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0, + .qe_bit = 0x06, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xA5, + + .burst_wrap_cmd = 0xC0, + .burst_wrap_cmd_dmy_clk = 0x00, + .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .burst_wrap_data = 0x02, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x38, + .qpp_addr_mode = SF_CTRL_ADDR_4_LINES, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 45, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic_1635f = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xC2, + + .de_burst_wrap_cmd = 0xC0, + .de_burst_wrap_cmd_dmy_clk = 0x00, + .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .de_burst_wrap_data = 0x10, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0, + .qe_bit = 0x06, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xA5, + + .burst_wrap_cmd = 0xC0, + .burst_wrap_cmd_dmy_clk = 0x00, + .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .burst_wrap_data = 0x02, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x38, + .qpp_addr_mode = SF_CTRL_ADDR_4_LINES, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 45, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic_25l256 = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc2, + + .de_burst_wrap_cmd = 0xC0, + .de_burst_wrap_cmd_dmy_clk = 0x00, + .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .de_burst_wrap_data = 0x10, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0, + .qe_bit = 0x06, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x15, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xA5, + + .burst_wrap_cmd = 0xC0, + .burst_wrap_cmd_dmy_clk = 0x00, + .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .burst_wrap_data = 0x02, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x38, + .qpp_addr_mode = SF_CTRL_ADDR_4_LINES, + + .io_mode = (SF_CTRL_QIO_MODE | 0x20), + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 400, + .time_e_32k = 1000, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_xtx = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x0B, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0x01, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 6000, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_puya_q80l_q80h_q16h = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x85, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0x01, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3d, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 8, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_puya_q32h = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x85, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0x01, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 8, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_boya40 = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x68, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0xA0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_DO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_boya = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x68, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0x01, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mx_kh25 = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xc2, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x00, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x00, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0x20, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = (SF_CTRL_DO_MODE | 0x10), + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_256fv= { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0xef, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xa0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = 0x24, + .clk_delay = 1, + .clk_invert = 0x3f, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 400, + .time_e_32k = 1600, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 3, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_xtx_q80b_f16b = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, + .mid = 0x85, + + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, + + /*reg*/ + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, + + .qe_index = 0x01, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, + + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, + + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, + + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xa0, + + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, + /*write*/ + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, + + .io_mode = 0x14, + .clk_delay = 1, + .clk_invert = 0x01, + + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, + /*id*/ + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, +#if defined(BL702L) || defined(BL702) || defined(BL602) + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, +#else + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, +#endif + .sector_size = 4, + .page_size = 256, + + /*read*/ + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, + + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, + + /* qpi mode */ + .enter_qpi = 0x38, + .exit_qpi = 0xff, + + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33000, + .pd_delay = 20, + .qe_data = 0, +}; + +static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[] = { + { + .jedec_id = 0x1440ef, + //.name="winb_80dv_08_33", + .cfg = &flash_cfg_winb_80dv, + }, + { + .jedec_id = 0x1540ef, + //.name="winb_16dv_16_33", + .cfg = &flash_cfg_winb_16jv, + }, + { + .jedec_id = 0x1570ef, + //.name="wb_16jv_16_33", + .cfg = &flash_cfg_winb_16jv, + }, + { + .jedec_id = 0x1640ef, + //.name="winb_32fv_32_33", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x1740ef, + //.name="wb_64jv_64_33", + .cfg = &flash_cfg_winb_128jw_128jv, + }, + { + .jedec_id = 0x1840ef, + //.name="winb_128jv_128_33", + .cfg = &flash_cfg_winb_128jw_128jv, + }, + { + .jedec_id = 0x1870ef, + //.name="winb_128jv_128_33", + .cfg = &flash_cfg_winb_128jw_128jv, + }, + { + .jedec_id = 0x1940ef, + //.name="wb_256fv_256_33", + .cfg = &flash_cfg_winb_256fv, + }, + { + .jedec_id = 0x1460ef, + //.name="winb_80ew_08_18", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x1560ef, + //.name="winb_16fw_16_18", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x1660ef, + //.name="winb_32fw_32_18", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x1760ef, + //.name="wb_64jw_64_18", + .cfg = &flash_cfg_winb_128jw_128jv, + }, + { + .jedec_id = 0x1860ef, + //.name="winb_128jw_128_18", + .cfg = &flash_cfg_winb_128jw_128jv, + }, + { + .jedec_id = 0x1680ef, + //.name="winb_32jw_32_18", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x1880ef, + //.name="winb_128jw_128_18", + .cfg = &flash_cfg_winb_128jw_128jv, + }, + { + .jedec_id = 0x134051, + //.name="gd_md04d_04_33", + .cfg = &flash_cfg_gd_md_40d, + }, + { + .jedec_id = 0x1440c8, + //.name="gd_q08e_08_33", + .cfg = &flash_cfg_gd_q80e_q16e, + }, + { + .jedec_id = 0x1540c8, + //.name="gd_q16e_16_33", + .cfg = &flash_cfg_gd_q80e_q16e, + }, + { + .jedec_id = 0x1640c8, + //.name="gd_q32c_32_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x1740c8, + //.name="gd_64e_64_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x1840c8, + //.name="gd_q128e_128_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x1460c8, + //.name="gd_lq08c_08_18", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x1560c8, + //.name="gd_le16c_16_18", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x1660c8, + //.name="gd_lq32d_32_18", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x1760c8, + //.name="gd_lq64e_64_18", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x1860c8, + //.name="gd_lq128e_128_18", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x1465c8, + //.name="gd_wq80e_80_33", + .cfg = &flash_cfg_gd_wq80e_wq16e, + }, + { + .jedec_id = 0x1565c8, + //.name="gd_wq16e_16_33", + .cfg = &flash_cfg_gd_wq80e_wq16e, + }, + { + .jedec_id = 0x1665c8, + //.name="gd_wq32e_32_33", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x1320c2, + //.name="mx_kh40_04_33", + .cfg = &flash_cfg_mx_kh25, + }, + { + .jedec_id = 0x1420c2, + //.name="mx_kh80_08_33", + .cfg = &flash_cfg_mx_kh25, + }, + { + .jedec_id = 0x1520c2, + //.name="mx_kh16_16_33", + .cfg = &flash_cfg_mx_kh25, + }, + { + .jedec_id = 0x3425c2, + //.name="mx_25v80_08_18", + .cfg = &flash_cfg_mxic, + }, + { + .jedec_id = 0x3525c2, + //.name="mx_25u16_35_18", + .cfg = &flash_cfg_mxic_1635f, + }, + { + .jedec_id = 0x3625c2, + //.name="mx_25v32_32_18", + .cfg = &flash_cfg_mxic, + }, + { + .jedec_id = 0x3925c2, + //.name="mx_u25643g_256_18", + .cfg = &flash_cfg_mxic_25l256, + }, + { + .jedec_id = 0x1820c2, + //.name="mx_25l128_128_33", + .cfg = &flash_cfg_mxic_1635f, + }, + { + .jedec_id = 0x1920c2, + //.name="mx_25l256_256_33", + .cfg = &flash_cfg_mxic_25l256, + }, + { + .jedec_id = 0x13400b, + //.name="xt_25f04d_04_33", + .cfg = &flash_cfg_xtx, + }, + { + .jedec_id = 0x15400b, + //.name="xt_25f16b_16_33", + .cfg = &flashcfg_xtx_q80b_f16b, + }, + { + .jedec_id = 0x16400b, + //.name="xt_25f32b_32_33", + .cfg = &flash_cfg_xtx, + }, + { + .jedec_id = 0x17400b, + //.name="xt_f64b_64_33", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x18400b, + //.name="xt_25f128b_128_33", + .cfg = &flash_cfg_xtx, + }, + { + .jedec_id = 0x14600b, + //.name="xt_25q80b_08_18", + .cfg = &flashcfg_xtx_q80b_f16b, + }, + { + .jedec_id = 0x16600b, + //.name="xt_25q32b_32_18", + .cfg = &flash_cfg_xtx, + }, + { + .jedec_id = 0x134068, + //.name="boya_q04b_04_33", + .cfg = &flash_cfg_boya40, + }, + { + .jedec_id = 0x144068, + //.name="boya_q08b_08_33", + .cfg = &flash_cfg_boya, + }, + { + .jedec_id = 0x154068, + //.name="boya_q16b_16_33", + .cfg = &flash_cfg_boya, + }, + { + .jedec_id = 0x164068, + //.name="boya_q32b_32_33", + .cfg = &flash_cfg_boya, + }, + { + .jedec_id = 0x174068, + //.name="boya_q64a_64_33", + .cfg = &flash_cfg_boya, + }, + { + .jedec_id = 0x184068, + //.name="boya_q128a_128_33", + .cfg = &flash_cfg_boya, + }, + { + .jedec_id = 0x13325e, + //.name="zbit_04_33", + .cfg = &flash_cfg_mx_kh25, + }, + { + .jedec_id = 0x14325e, + //.name="zbit_08_33", + .cfg = &flash_cfg_mx_kh25, + }, + { + .jedec_id = 0x15345e, + //.name="zb_wq16a_16_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x13605e, + //.name="zbit_04_33", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x14605e, + //.name="zbit_08_33", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x15605e, + //.name="zb_vq16_16_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x15405e, + //.name="zb_16b_16_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x16405e, + //.name="zb_32b_32_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x17405e, + //.name="zb_vq64_64_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x18405e, + //.name="zb_vq128_128_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x144020, + //.name="xm_qh80_08_33", + .cfg = &flash_cfg_winb_16jv, + }, + { + .jedec_id = 0x154020, + //.name="xm_qh16_16_33", + .cfg = &flash_cfg_winb_16jv, + }, + { + .jedec_id = 0x164020, + //.name="xm_qh32_32_33", + .cfg = &flash_cfg_winb_16jv, + }, + { + .jedec_id = 0x174020, + //.name="xm_qh64_64_33", + .cfg = &flash_cfg_winb_16jv, + }, + { + .jedec_id = 0x184020, + //.name="xm_qh128_128_33", + .cfg = &flash_cfg_gd_q32e_q128e, + }, + { + .jedec_id = 0x174220, + //.name="xm_qw64_64_1833", + .cfg = &flash_cfg_winb_16jv, + }, + { + .jedec_id = 0x1440a1, + //.name="fm25q80_80_33", + .cfg = &flash_cfg_gd_q80e_q16e, + }, + { + .jedec_id = 0x1740a1, + //.name="fm25q64_64_33", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x1840a1, + //.name="fm25q128_128_33", + .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv, + }, + { + .jedec_id = 0x146085, + //.name="puya_q80l/h_08_18/33", + .cfg = &flash_cfg_puya_q80l_q80h_q16h, + }, + { + .jedec_id = 0x156085, + //.name="puya_q16h_16_33", + .cfg = &flash_cfg_puya_q80l_q80h_q16h, + }, + { + .jedec_id = 0x166085, + //.name="puya_q32h_32_33", + .cfg = &flash_cfg_puya_q32h, + }, + { + .jedec_id = 0x176085, + //.name="puya_q64h_64_33", + .cfg = &flash_cfg_puya_q32h, + }, + { + .jedec_id = 0x186085, + //.name="puya_q128h_128_33", + .cfg = &flash_cfg_puya_q32h, + }, + { + .jedec_id = 0x14609d, + //.name="issi_08_33", + .cfg = &flash_cfg_issi, + }, + { + .jedec_id = 0x15609d, + //.name="issi_16_33", + .cfg = &flash_cfg_issi, + }, + { + .jedec_id = 0x16609d, + //.name="issi_32_33", + .cfg = &flash_cfg_issi, + }, + { + .jedec_id = 0x14709d, + //.name="issi_08_18", + .cfg = &flash_cfg_issi, + }, + { + .jedec_id = 0x15709d, + //.name="issi_16_18", + .cfg = &flash_cfg_issi, + }, + { + .jedec_id = 0x16709d, + //.name="issi_32_18", + .cfg = &flash_cfg_issi, + }, + { + .jedec_id = 0x1460cd, + //.name="th25q80_80_33", + .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e, + }, + { + .jedec_id = 0x1560eb, + //.name="th25q16_16_33", + .cfg = &flash_cfg_gd_q80e_q16e, + }, + { + .jedec_id = 0x1560ba, + //.name="zd25a16_16_33", + .cfg = &flashcfg_xtx_q80b_f16b, + }, +}; + +/*@} end of group SF_CFG_Private_Variables */ + +/** @defgroup SF_CFG_Global_Variables + * @{ + */ + +/*@} end of group SF_CFG_Global_Variables */ + +/** @defgroup SF_CFG_Private_Fun_Declaration + * @{ + */ + +#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)\ + || defined(BL602) || defined(BL702) || defined(BL702L) +/** + * @brief Error type definition + */ +typedef enum { + SUCCESS = 0, + ERROR = 1, + TIMEOUT = 2, + INVALID = 3, /* invalid arguments */ + NORESC = 4 /* no resource or resource temperary unavailable */ +} BL_Err_Type; +#endif +#if defined(BL808) || defined(BL606P) +extern BL_Err_Type GLB_Set_Flash_IO_PARM(uint8_t sel_embedded, uint8_t swap); +#elif defined(BL616) +extern BL_Err_Type GLB_Set_SFlash_IO_PARM(uint8_t sel_embedded, uint8_t swapIo3Io0, uint8_t swapIo2Cs); +extern BL_Err_Type GLB_Set_SFlash2_IO_PARM(uint8_t swapIo3Io0); +#elif defined(BL702L) +extern BL_Err_Type GLB_Set_Embedded_FLash_IO_PARM(uint8_t reverse, uint8_t swapIo3Io0, uint8_t swapIo2Cs); +#elif defined(BL628) +extern void bflb_glb_set_sflash_io_parm(uint8_t sel_embedded, uint8_t swap_io3_io0, uint8_t swap_io2_cs); +extern void bflb_glb_set_sflash2_io_parm(uint8_t swap_io3_io0); +#elif defined(BL602) +extern BL_Err_Type GLB_Select_Internal_Flash(void); +extern BL_Err_Type GLB_Select_External_Flash(void); +extern BL_Err_Type GLB_Deswap_Flash_Pin(void); +extern BL_Err_Type GLB_Swap_Flash_Pin(void); +#endif + +/*@} end of group SF_CFG_Private_Fun_Declaration */ + +/** @defgroup SF_CFG_Private_Functions + * @{ + */ + +#if defined(BL702L) +/****************************************************************************/ /** + * @brief Embedded flash set input function enable + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void) +{ +#define GLB_BASE_ADDR 0x40000000 +#define GLB_GPIO_OFFSET_ADDR 0x100 + uint32_t regval; + uint32_t gpio_pin; + uint32_t pin_offset; + + for (gpio_pin = 32; gpio_pin < 38; gpio_pin++) { + pin_offset = (gpio_pin >> 1) << 2; + regval = *(uint32_t *)(GLB_BASE_ADDR + GLB_GPIO_OFFSET_ADDR + pin_offset); + if (gpio_pin % 2 == 0) { + /* [0] is ie */ + regval |= (1 << 0); + } else { + /* [16] is ie */ + regval |= (1 << 16); + } + *(uint32_t *)(GLB_BASE_ADDR + GLB_GPIO_OFFSET_ADDR + pin_offset) = regval; + } +} +#elif defined(BL702) || defined(BL602) +/****************************************************************************/ /** + * @brief Init internal flash GPIO + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void) +{ + struct bflb_device_s *gpio; + uint8_t gpio_pins[6]; + uint8_t i = 0; + + gpio = bflb_device_get_by_name("gpio"); + for (i = 0; i < sizeof(gpio_pins); i++) { + gpio_pins[i] = 23+i; + bflb_gpio_init(gpio, gpio_pins[i], + BFLB_GPIO_FUNC_SF | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + } +} +#endif + +#if defined(BL602) +/****************************************************************************/ /** + * @brief Restore GPIO17 function + * + * @param fun: GPIO17 function + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_cfg_restore_gpio17_fun(uint8_t fun) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, GPIO_PIN_17, + fun | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); +} +#endif + +/****************************************************************************/ /** + * @brief Init external flash GPIO according to flash GPIO config + * + * @param ext_flash_pin: Flash GPIO config + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin) +{ + struct bflb_device_s *gpio; + uint8_t gpio_pins[6]; + uint8_t i = 0; + + gpio = bflb_device_get_by_name("gpio"); + if (ext_flash_pin == 0) { + gpio_pins[0] = BFLB_EXTFLASH_CLK0_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS0_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA00_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA10_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA20_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA30_GPIO; +#if defined(BL628) || defined(BL616) + } else if (ext_flash_pin == 1) { + gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO; +#elif defined(BL702) + } else if (ext_flash_pin == 1) { + gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO; + } else if (ext_flash_pin == 2) { + gpio_pins[0] = BFLB_EXTFLASH_CLK2_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS2_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA02_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA12_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA22_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA32_GPIO; +#elif defined(BL602) + } else if (ext_flash_pin == 1) { + gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO; +#endif + } else { + return -1; + } + + for (i = 0; i < sizeof(gpio_pins); i++) { + bflb_gpio_init(gpio, gpio_pins[i], + BFLB_GPIO_FUNC_SF | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Deinit external flash GPIO according to flash GPIO config + * + * @param ext_flash_pin: Flash GPIO config + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin) +{ + struct bflb_device_s *gpio; + uint8_t gpio_pins[6]; + uint8_t i = 0; + + gpio = bflb_device_get_by_name("gpio"); + if (ext_flash_pin == 0) { + gpio_pins[0] = BFLB_EXTFLASH_CLK0_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS0_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA00_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA10_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA20_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA30_GPIO; +#if defined(BL628) || defined(BL616) + } else if (ext_flash_pin == 1) { + gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO; +#elif defined(BL702) + } else if (ext_flash_pin == 1) { + gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO; + } else if (ext_flash_pin == 2) { + gpio_pins[0] = BFLB_EXTFLASH_CLK2_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS2_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA02_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA12_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA22_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA32_GPIO; +#elif defined(BL602) + } else if (ext_flash_pin == 1) { + gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO; + gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO; + gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO; + gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO; + gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO; + gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO; +#endif + } else { + return -1; + } + + for (i = 0; i < sizeof(gpio_pins); i++) { + bflb_gpio_init(gpio, gpio_pins[i], GPIO_INPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + } + + return 0; +} + +/*@} end of group SF_CFG_Private_Functions */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Get flash config according to flash ID + * + * @param flash_id: Flash ID + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) +{ + uint32_t i = 0; + uint8_t buf[sizeof(spi_flash_cfg_type) + 8]; + uint32_t crc = 0, *p_crc; + uint32_t xip_offset = 0; + + if (flash_id == 0) { + xip_offset = bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); + bflb_xip_sflash_read_via_cache_need_lock(8 + BFLB_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank); + bflb_sf_ctrl_set_flash_image_offset(xip_offset, group, bank); + + if (arch_memcmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { + crc = bflb_soft_crc32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); + p_crc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type)); + + if (*p_crc == crc) { + arch_memcpy_fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); + return 0; + } + } + } else { + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == flash_id) { + arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); + return 0; + } + } + } + + return -1; +} + +#if defined(BL616) || defined(BL606P) || defined(BL808) +/****************************************************************************/ /** + * @brief Get flash config according to flash ID patch + * + * @param flash_id: Flash ID + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) +{ + return bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank); +} +#endif + +/****************************************************************************/ /** + * @brief Init flash GPIO according to flash Pin config + * + * @param flash_pin_cfg: Specify flash Pin config + * @param restore_default: Wether to restore default setting + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +#if defined(BL628) || defined(BL616) +int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default) +{ + uint8_t sel_embedded = 0; + uint8_t swap_io2_cs = 0; + uint8_t swap_io3_io0 = 0; + + if (restore_default) { + /* Set Default first */ +#if defined(BL628) + bflb_glb_set_sflash_io_parm(1, 1, 0); +#else + GLB_Set_SFlash_IO_PARM(1, 1, 0); +#endif + bflb_sf_ctrl_select_pad(SF_IO_EMB_SWAP_IO3IO0); + + /* Default is set, so return */ + if (flash_pin_cfg == SF_IO_EMB_SWAP_IO3IO0) { + return 0; + } + } + + if (flash_pin_cfg & (1 << 2)) { + /* Init sf2 gpio */ + bflb_sf_cfg_init_flash2_gpio(!((flash_pin_cfg >> 5) & 1)); + sel_embedded = 0; + } else if (flash_pin_cfg & (1 << 3)) { + /* Init sf3 gpio */ + bflb_sf_cfg_init_ext_flash_gpio(1); + sel_embedded = 0; + } else { + sel_embedded = 1; + } + /* if pin select dual flash, embedded is default */ + if ((flash_pin_cfg & (1 << 4))) { + sel_embedded = 1; + } + + swap_io3_io0 = ((flash_pin_cfg >> 1) & 1); + swap_io3_io0 = (!swap_io3_io0); + swap_io2_cs = ((flash_pin_cfg >> 0) & 1); +#if defined(BL628) + bflb_glb_set_sflash_io_parm(sel_embedded, swap_io3_io0, swap_io2_cs); +#else + GLB_Set_SFlash_IO_PARM(sel_embedded, swap_io3_io0, swap_io2_cs); +#endif + bflb_sf_ctrl_select_pad(flash_pin_cfg); + + return 0; +} +#elif defined(BL808) || defined(BL606P) +int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default) +{ + uint8_t sel_embedded = 0; + uint8_t swap = 0; + + if ((flash_pin_cfg&(1<<3)) > 0) { + return ERROR; + } + + if (restore_default) { + /* Set Default first */ + GLB_Set_Flash_IO_PARM(1, 1); + bflb_sf_ctrl_select_pad(SF_IO_EMB_SWAP_IO0_IO3); + + /* Default is set, so return */ + if (flash_pin_cfg == SF_IO_EMB_SWAP_IO0_IO3) { + return SUCCESS; + } + } + + if (flash_pin_cfg & (1 << 2)) { + /* Init sf2 gpio */ + bflb_sf_cfg_init_ext_flash_gpio(0); + sel_embedded = 0; + } else { + sel_embedded = 1; + } + /* if pin select dual flash, embedded is default */ + if ((flash_pin_cfg & (1 << 4))) { + sel_embedded = 1; + } + + swap = ((flash_pin_cfg >> 1) & 1); + swap = (!swap); + GLB_Set_Flash_IO_PARM(sel_embedded, swap); + bflb_sf_ctrl_select_pad(flash_pin_cfg); + + return SUCCESS; +} +#elif defined(BL702L) +/****************************************************************************/ /** + * @brief Init flash GPIO according to flash Pin config + * + * @param flash_pin_cfg: Specify flash Pin config + * @param restore_default: Wether to restore default setting + * + * @return None + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default) +{ + if (restore_default) { + GLB_Set_Embedded_FLash_IO_PARM(0, 0, 0); + + bflb_sf_cfg_init_internal_flash_gpio(); + bflb_sf_ctrl_select_pad(SF_CTRL_PAD1); + + /* Default is set, so return */ + if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) { + return 0; + } + } + + if (flash_pin_cfg == SF_CTRL_SEL_EXTERNAL_FLASH) { + bflb_sf_cfg_init_ext_flash_gpio(0); + bflb_sf_ctrl_select_pad(SF_CTRL_PAD2); + } else { + if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) { + GLB_Set_Embedded_FLash_IO_PARM(0, 0, 0); + } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) { + GLB_Set_Embedded_FLash_IO_PARM(0, 0, 1); + } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) { + GLB_Set_Embedded_FLash_IO_PARM(0, 1, 0); + } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) { + GLB_Set_Embedded_FLash_IO_PARM(0, 1, 1); + } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) { + GLB_Set_Embedded_FLash_IO_PARM(1, 0, 0); + } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) { + GLB_Set_Embedded_FLash_IO_PARM(1, 0, 1); + } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) { + GLB_Set_Embedded_FLash_IO_PARM(1, 1, 0); + } else { + GLB_Set_Embedded_FLash_IO_PARM(1, 1, 1); + } + + bflb_sf_cfg_init_internal_flash_gpio(); + bflb_sf_ctrl_select_pad(SF_CTRL_PAD1); + } + + return 0; +} +#elif defined(BL702) +/****************************************************************************/ /** + * @brief Init flash GPIO according to flash Pin config + * + * @param flash_pin_cfg: Specify flash Pin config + * @param restore_default: Wether to restore default setting + * + * @return None + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default) +{ +#define GLB_BASE_ADDR 0x40000000 +#define GLB_PARM_OFFSET_ADDR 0x80 +#define GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR 0x88 + uint8_t flash_cfg; + uint8_t swap_cfg; + uint32_t regval; + + flash_cfg = (flash_pin_cfg >> 2) & 0x03; + swap_cfg = flash_pin_cfg & 0x03; + + if (restore_default) { + /* Set Default first */ + regval = getreg32(GLB_BASE_ADDR + GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR); + + /* Bit0~5 is sf io select */ + if ((regval&0x3F) == 0x00) { + bflb_sf_cfg_init_ext_flash_gpio(1); + } + + regval = getreg32(GLB_BASE_ADDR + GLB_PARM_OFFSET_ADDR); + /* Bit9 is flash2 swap cs with io2 */ + regval &= ~(1 << 9); + /* Bit8 is flash2 swap io0 with io3 */ + regval &= ~(1 << 8); + putreg32(regval, GLB_BASE_ADDR+GLB_PARM_OFFSET_ADDR); + + bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF2); + + /* Default is set, so return */ + if (flash_cfg == BFLB_FLASH_CFG_SF2_EXT_23_28 && swap_cfg == BFLB_SF2_SWAP_NONE) { + return 0; + } + } + + if (flash_cfg == BFLB_FLASH_CFG_SF1_EXT_17_22) { + bflb_sf_cfg_init_ext_flash_gpio(0); + bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF1); + } else { + regval = getreg32(GLB_BASE_ADDR + GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR); + + /* Bit0~5 is sf io select */ + if ((regval&0x3F) == 0x00) { + bflb_sf_cfg_init_ext_flash_gpio(1); + } + + regval = getreg32(GLB_BASE_ADDR + GLB_PARM_OFFSET_ADDR); + if (swap_cfg == BFLB_SF2_SWAP_NONE) { + /* Bit9 is flash2 swap cs with io2 */ + regval &= ~(1 << 9); + /* Bit8 is flash2 swap io0 with io3 */ + regval &= ~(1 << 8); + } else if (swap_cfg == BFLB_SF2_SWAP_CS_IO2) { + /* Bit9 is flash2 swap cs with io2 */ + regval |= (1 << 9); + /* Bit8 is flash2 swap io0 with io3 */ + regval &= ~(1 << 8); + } else if (swap_cfg == BFLB_SF2_SWAP_IO0_IO3) { + /* Bit9 is flash2 swap cs with io2 */ + regval &= ~(1 << 9); + /* Bit8 is flash2 swap io0 with io3 */ + regval |= (1 << 8); + } else { + /* Bit9 is flash2 swap cs with io2 */ + regval |= (1 << 9); + /* Bit8 is flash2 swap io0 with io3 */ + regval |= (1 << 8); + } + putreg32(regval, GLB_BASE_ADDR+GLB_PARM_OFFSET_ADDR); + + bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF2); + } + + return 0; +} +#elif defined(BL602) +/****************************************************************************/ /** + * @brief Init flash GPIO according to flash Pin config + * + * @param flash_pin_cfg: Specify flash Pin config + * @param restore_default: Wether to restore default setting + * + * @return None + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default) +{ + if (restore_default) { + /* Set Default first */ + bflb_sf_ctrl_select_pad(SF_CTRL_EMBEDDED_SEL); + GLB_Select_Internal_Flash(); + GLB_Swap_Flash_Pin(); + //SF_Cfg_Deinit_Ext_Flash_Gpio(0); + bflb_sf_cfg_deinit_ext_flash_gpio(1); + bflb_sf_cfg_init_internal_flash_gpio(); + } + + if (flash_pin_cfg > 0) { + /*01: deswap flash PIN + 10: use ext flash 1(GPIO17-22) + 11: use ext flash 0(GPIO0-2, 20-22) + */ + if (flash_pin_cfg == BFLB_FLASH_CFG_DESWAP) { + bflb_sf_ctrl_select_pad(SF_CTRL_EMBEDDED_SEL); + /*DONOT Swap flash PIN*/ + GLB_Deswap_Flash_Pin(); + } else { + bflb_sf_ctrl_select_pad(flash_pin_cfg - 1); + GLB_Select_External_Flash(); + bflb_sf_cfg_init_ext_flash_gpio(flash_pin_cfg - BFLB_FLASH_CFG_EXT0_17_22); + } + } + + return 0; +} +#endif + +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +/****************************************************************************/ /** + * @brief Init flash2 GPIO + * + * @param swap: Select embedded flash2 swap io3 with io0 + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_init_flash2_gpio(uint8_t swap) +{ + bflb_sf_cfg_init_ext_flash_gpio(0); +#if defined(BL628) + bflb_glb_set_sflash2_io_parm(swap); +#elif defined(BL616) + GLB_Set_SFlash2_IO_PARM(swap); +#endif + + return 0; +} +#endif + +/****************************************************************************/ /** + * @brief Identify one flash + * + * @param call_from_flash: code run at flash or ram + * @param flash_pin_cfg: Bit 7: auto_scan, Bit6-0: flash GPIO config + * @param restore_default: Wether restore default flash GPIO config + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return Flash ID + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, + spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) +{ + uint8_t auto_scan = 0; + uint8_t flash_pin = 0; + uint32_t jedec_id = 0; + uint32_t i = 0; + uint32_t offset = 0; + uint8_t stat = 0; +#if defined(BL602) + uint8_t gpio17_fun = 0; +#endif + + auto_scan = ((flash_pin_cfg >> 7) & 1); + flash_pin = (flash_pin_cfg & 0x7F); + + arch_memcpy_fast(p_flash_cfg, &flash_cfg_winb_16jv, sizeof(spi_flash_cfg_type)); + + if (call_from_flash == 1) { + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB); + return 0; + } + } + + if (auto_scan) { + flash_pin = 0; + do { +#if defined(BL628) || defined(BL616) + if (!IS_SF_CTRL_PIN_SELECT(flash_pin)) { + flash_pin++; + continue; + } + if (bank == SF_CTRL_FLASH_BANK1) { + if (flash_pin > SF_IO_EMB_SWAP_IO2CS_AND_SF2) { + jedec_id = 0; + break; + } + if (flash_pin < SF_IO_EXT_SF3) { + flash_pin = SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0; + } + if (flash_pin == SF_IO_EXT_SF2) { + flash_pin++; + } + bflb_sf_cfg_init_flash2_gpio(!((flash_pin >> 5) & 1)); + } else { + if (flash_pin > SF_IO_EXT_SF2) { + jedec_id = 0; + break; + } + if (flash_pin > SF_IO_EXT_SF3) { + flash_pin = SF_IO_EXT_SF2; + } + bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default); + } +#elif defined(BL808) || defined(BL606P) + if (flash_pin > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { + jedec_id = 0; + break; + } + if (!IS_SF_CTRL_PIN_SELECT(flash_pin) || (flash_pin&(1<<3)) > 0) { + flash_pin++; + continue; + } + bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default); +#elif defined(BL702L) + if (flash_pin > SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH) { + jedec_id = 0; + break; + } + bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default); +#elif defined(BL702) + if (flash_pin > 0x0f) { + jedec_id = 0; + break; + } + bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default); +#elif defined(BL602) +#define GLB_BASE_ADDR 0x40000000 +#define GLB_GPIO17_OFFSET_ADDR 0x120 + if (flash_pin > BFLB_FLASH_CFG_EXT1_0_2_20_22) { + jedec_id = 0; + break; + } + + if (flash_pin > BFLB_FLASH_CFG_EXT0_17_22) { + /*flash_pin=2 has make gpio17 into jtag,but not success*/ + bflb_sf_cfg_restore_gpio17_fun(gpio17_fun); + } + + /* select media gpio */ + if (flash_pin == BFLB_FLASH_CFG_EXT0_17_22) { + gpio17_fun = ((getreg32(GLB_BASE_ADDR + GLB_GPIO17_OFFSET_ADDR)>>24) & 0xf); + } + + bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default); +#endif + bflb_sflash_release_powerdown(p_flash_cfg); + bflb_sflash_reset_continue_read(p_flash_cfg); + bflb_sflash_disable_burst_wrap(p_flash_cfg); + jedec_id = 0; + bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id); + bflb_sflash_disable_burst_wrap(p_flash_cfg); + jedec_id = jedec_id & 0xffffff; + flash_pin++; + } while ((jedec_id & 0x00ffff) == 0 || (jedec_id & 0xffff00) == 0 || (jedec_id & 0x00ffff) == 0xffff || (jedec_id & 0xffff00) == 0xffff00); + } else { + /* select media gpio */ +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE + if (bank == SF_CTRL_FLASH_BANK1) { + bflb_sf_cfg_init_flash2_gpio(!((flash_pin >> 5) & 1)); + } else { + bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default); + } +#else + bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default); +#endif + bflb_sflash_release_powerdown(p_flash_cfg); + bflb_sflash_reset_continue_read(p_flash_cfg); + bflb_sflash_disable_burst_wrap(p_flash_cfg); + bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id); + bflb_sflash_disable_burst_wrap(p_flash_cfg); + jedec_id = jedec_id & 0xffffff; + } + + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == jedec_id) { + arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); + break; + } + } + + if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) { + if (call_from_flash == 1) { + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + return jedec_id; + } else { + if (call_from_flash == 1) { + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + return (jedec_id | BFLB_FLASH_ID_VALID_FLAG); + } +} + +#if defined(BL616) || defined(BL606P) || defined(BL808) +/****************************************************************************/ /** + * @brief Identify one flash patch + * + * @param call_from_flash: code run at flash or ram + * @param flash_pin_cfg: Bit 7: auto_scan, Bit6-0: flash GPIO config + * @param restore_default: Wether restore default flash GPIO config + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return Flash ID + * +*******************************************************************************/ +__WEAK +uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, + uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) +{ + return bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank); +} +#endif + +#if defined(BL628) || defined(BL616) +/****************************************************************************/ /** + * @brief SF Cfg flash init + * + * @param sel: SF pin select + * @param p_sf_ctrl_cfg: Serial flash controller configuration pointer + * @param p_bank2_cfg: Serial flash2 controller configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, + const struct sf_ctrl_bank2_cfg *p_bank2_cfg) +{ + uint8_t sel_embedded = 0; + uint8_t swap_io2_cs = 0; + uint8_t swap_io3_io0 = 0; + + if (sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) { + return -1; + } + + if (sel & (1 << 2)) { + bflb_sf_cfg_init_flash2_gpio(!((sel >> 5) & 1)); + sel_embedded = 0; + } else if (sel & (1 << 3)) { + bflb_sf_cfg_init_ext_flash_gpio(1); + sel_embedded = 0; + } else { + sel_embedded = 1; + } + /* If pin select dual flash, embedded is default */ + if ((sel & (1 << 4))) { + sel_embedded = 1; + } + + swap_io3_io0 = ((sel >> 1) & 1); + swap_io3_io0 = (!swap_io3_io0); + swap_io2_cs = ((sel >> 0) & 1); +#if defined(BL628) + bflb_glb_set_sflash_io_parm(sel_embedded, swap_io3_io0, swap_io2_cs); +#else + GLB_Set_SFlash_IO_PARM(sel_embedded, swap_io3_io0, swap_io2_cs); +#endif + bflb_sf_ctrl_select_pad(sel); + + if (sel <= SF_IO_EMB_SWAP_IO2CS) { + /* Embedded pad1 io delay set */ + if (p_sf_ctrl_cfg != NULL) { + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay); + } + } else if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) { + /* Pad2 or pad3 io delay set */ + if (p_sf_ctrl_cfg != NULL) { + bflb_sf_ctrl_set_io_delay(((sel&0xf) >> 2), p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay); + } + } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) + ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { + /* Dual flash mode, embedded pad1 and pad2 io delay set */ + if (p_sf_ctrl_cfg != NULL) { + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay); + } + if (p_bank2_cfg != NULL) { + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay); + } + } + + if (p_bank2_cfg != NULL) { + if (p_bank2_cfg->sbus2_select) { + if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) + ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { + /* Default sbus2 replace opt flash2 */ + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + } + } + } + + bflb_sflash_init(p_sf_ctrl_cfg, p_bank2_cfg); + + return 0; +} + +/****************************************************************************/ /** + * @brief SF Cfg system bus 2 flash init + * + * @param sel: SF pin select + * @param p_bank2_cfg: Serial flash2 controller configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg) +{ + if (sel < SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 || sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) { + return -1; + } + + /* Init flash2 gpio */ + if (sel & (1 << 2)) { + bflb_sf_cfg_init_flash2_gpio(!((sel >> 5) & 1)); + } + + /* Set remap for flash2 xip mode */ + bflb_sf_ctrl_remap_set(p_bank2_cfg->remap, p_bank2_cfg->remap_lock); + + if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) + ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { + /* Dual flash mode, pad2 io delay set */ + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay); + } + if (p_bank2_cfg->sbus2_select) { + if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) + ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { + /* Default sbus2 replace opt flash2 */ + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + } + } + + bflb_sflash_init(NULL, p_bank2_cfg); + + return 0; +} +#elif defined(BL808) || defined(BL606P) +/****************************************************************************/ /** + * @brief SF Cfg flash init + * + * @param sel: SF pin select + * @param p_sf_ctrl_cfg: Serial flash controller configuration pointer + * @param p_bank2_cfg: Serial flash2 controller configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, + const struct sf_ctrl_bank2_cfg *p_bank2_cfg) +{ + uint8_t sel_embedded = 0; + uint8_t swap = 0; + + if ((sel&(1<<3)) > 0) { + return ERROR; + } + + if (sel & (1 << 2)) { + bflb_sf_cfg_init_ext_flash_gpio(0); + sel_embedded = 0; + } else { + sel_embedded = 1; + } + /* If pin select dual flash, embedded is default */ + if ((sel & (1 << 4))) { + sel_embedded = 1; + } + + swap = ((sel >> 1) & 1); + swap = (!swap); + GLB_Set_Flash_IO_PARM(sel_embedded, swap); + bflb_sf_ctrl_select_pad(sel); + + if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { + /* Embedded pad1 io delay set */ + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay); + } else if (sel <= SF_IO_EXT_SF2) { + /* Pad2 or pad3 io delay set */ + bflb_sf_ctrl_set_io_delay((sel >> 2), p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay); + } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { + /* Dual flash mode, embedded pad1 and pad2 io delay set */ + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay); + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay); + } + + if (p_bank2_cfg != NULL) { + if (p_bank2_cfg->sbus2_select) { + if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { + /* Default sbus2 replace opt flash2 */ + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + } + } + } + + bflb_sflash_init(p_sf_ctrl_cfg, p_bank2_cfg); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief SF Cfg system bus 2 flash init + * + * @param sel: SF pin select + * @param p_bank2_cfg: Serial flash2 controller configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg) +{ + if (sel < SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 || sel > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { + return ERROR; + } + + /* Init flash2 gpio */ + if (sel & (1 << 2)) { + bflb_sf_cfg_init_ext_flash_gpio(0); + } + + /* Set remap for flash2 xip mode */ + bflb_sf_ctrl_remap_set(p_bank2_cfg->remap, p_bank2_cfg->remap_lock); + + /* Dual flash mode, pad2 io delay set */ + bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay); + + if (p_bank2_cfg->sbus2_select) { + /* Default sbus2 replace opt flash2 */ + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + } + + bflb_sflash_init(NULL, p_bank2_cfg); + + return SUCCESS; +} +#endif + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL628_Peripheral_Driver */ diff --git a/drivers/lhal/src/flash/bflb_sf_cfg.h b/drivers/lhal/src/flash/bflb_sf_cfg.h new file mode 100644 index 00000000..7b984cf0 --- /dev/null +++ b/drivers/lhal/src/flash/bflb_sf_cfg.h @@ -0,0 +1,215 @@ +/** + ****************************************************************************** + * @file bflb_sf_cfg.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL628_SF_CFG_H__ +#define __BL628_SF_CFG_H__ + +#include "bflb_gpio.h" +#include "bflb_sflash.h" + +/** @addtogroup BL628_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CFG + * @{ + */ + +/** @defgroup SF_CFG_Public_Types + * @{ + */ + +/*@} end of group SF_CFG_Public_Types */ + +/** @defgroup SF_CFG_Public_Constants + * @{ + */ + +/*@} end of group SF_CFG_Public_Constants */ + +/** @defgroup SF_CFG_Public_Macros + * @{ + */ +#define BFLB_GPIO_FUNC_SF 2 +#if defined(BL628) || defined(BL616) +/* Flash option sf2 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_8 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_4 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_7 +#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_5 +#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_6 +#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_9 +/* Flash option sf3 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_15 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_20 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_16 +#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_19 +#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_18 +#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_14 +#elif defined(BL808) || defined(BL606P) +/* Flash option sf2 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_34 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_35 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_36 +#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_37 +#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_38 +#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_39 +#elif defined(BL702L) +/* Flash option */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_27 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_26 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_23 +#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_25 +#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_24 +#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_28 +#elif defined(BL702) +/* Flash option 0 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_21 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_19 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_17 +#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_18 +#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_22 +#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_20 +/* Flash option 1 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_27 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_25 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_28 +#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_24 +#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_23 +#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_26 +/* Flash option 2 */ +/* Flash CLK */ +#define BFLB_EXTFLASH_CLK2_GPIO GPIO_PIN_36 +/* FLASH CS */ +#define BFLB_EXTFLASH_CS2_GPIO GPIO_PIN_35 +/* FLASH DATA */ +#define BFLB_EXTFLASH_DATA02_GPIO GPIO_PIN_32 +#define BFLB_EXTFLASH_DATA12_GPIO GPIO_PIN_34 +#define BFLB_EXTFLASH_DATA22_GPIO GPIO_PIN_33 +#define BFLB_EXTFLASH_DATA32_GPIO GPIO_PIN_37 +#define BFLB_FLASH_CFG_SF2_EXT_23_28 0 +#define BFLB_FLASH_CFG_SF2_INT_512K 1 +#define BFLB_FLASH_CFG_SF2_INT_1M 2 +#define BFLB_FLASH_CFG_SF1_EXT_17_22 3 +#define BFLB_SF2_SWAP_NONE 0 +#define BFLB_SF2_SWAP_CS_IO2 1 +#define BFLB_SF2_SWAP_IO0_IO3 2 +#define BFLB_SF2_SWAP_BOTH 3 +#elif defined(BL602) +/*Flash option 0*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK0_GPIO GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS0_GPIO GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA00_GPIO GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA10_GPIO GPIO_PIN_19 +#define BFLB_EXTFLASH_DATA20_GPIO GPIO_PIN_18 +#define BFLB_EXTFLASH_DATA30_GPIO GPIO_PIN_17 +/*Flash option 1*/ +/*Flash CLK*/ +#define BFLB_EXTFLASH_CLK1_GPIO GPIO_PIN_22 +/*FLASH CS*/ +#define BFLB_EXTFLASH_CS1_GPIO GPIO_PIN_21 +/*FLASH DATA*/ +#define BFLB_EXTFLASH_DATA01_GPIO GPIO_PIN_20 +#define BFLB_EXTFLASH_DATA11_GPIO GPIO_PIN_0 +#define BFLB_EXTFLASH_DATA21_GPIO GPIO_PIN_1 +#define BFLB_EXTFLASH_DATA31_GPIO GPIO_PIN_2 +#define BFLB_FLASH_CFG_DESWAP 1 +#define BFLB_FLASH_CFG_EXT0_17_22 2 +#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3 +#endif +#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 +#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF + +/*@} end of group SF_CFG_Public_Macros */ + +/** @defgroup SF_CFG_Public_Functions + * @{ + */ +int bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank); +int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank); +#if defined(BL702L) || defined(BL702) +void bflb_sf_cfg_init_internal_flash_gpio(void); +#endif +#if defined(BL602) +void bflb_sf_cfg_restore_gpio17_fun(uint8_t fun); +#endif +int bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default); +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +int bflb_sf_cfg_init_flash2_gpio(uint8_t swap); +#endif +int bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin); +int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin); +uint32_t bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, + spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank); +uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t callfromflash, uint8_t flash_pin_cfg, uint8_t restore_default, + spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank); +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg, + const struct sf_ctrl_bank2_cfg *p_bank2_cfg); +int bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg); +#else +int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg); +#endif + +/*@} end of group SF_CFG_Public_Functions */ + +/*@} end of group SF_CFG */ + +/*@} end of group BL628_Peripheral_Driver */ + +#endif /* __BL628_SF_CFG_H__ */ diff --git a/drivers/lhal/src/flash/bflb_sf_ctrl.c b/drivers/lhal/src/flash/bflb_sf_ctrl.c new file mode 100644 index 00000000..2996a656 --- /dev/null +++ b/drivers/lhal/src/flash/bflb_sf_ctrl.c @@ -0,0 +1,2244 @@ +/** + ****************************************************************************** + * @file bl628_sf_ctrl.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bflb_sf_ctrl.h" +#include "hardware/sf_ctrl_reg.h" +#if defined(BL602) || defined(BL702) || defined(BL702L) +#include +#else +#include +#endif + +/** @addtogroup BL628_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Private_Macros + * @{ + */ + +/*@} end of group SF_CTRL_Private_Macros */ + +/** @defgroup SF_CTRL_Private_Types + * @{ + */ + +/*@} end of group SF_CTRL_Private_Types */ + +/** @defgroup SF_CTRL_Private_Variables + * @{ + */ + +#if defined(BL702) || defined(BL702L) +#define bflb_sf_ctrl_get_aes_region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100) +#else +#define bflb_sf_ctrl_get_aes_region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80) +#endif +#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) + +/*@} end of group SF_CTRL_Private_Variables */ + +/** @defgroup SF_CTRL_Global_Variables + * @{ + */ + +/*@} end of group SF_CTRL_Global_Variables */ + +/** @defgroup SF_CTRL_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SF_CTRL_Private_Fun_Declaration */ + +/** @defgroup SF_CTRL_Private_Functions + * @{ + */ + +/*@} end of group SF_CTRL_Private_Functions */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ + +#if defined(BL702L) || defined(BL702) || defined(BL602) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + //return __builtin_bswap32(value); + uint32_t res = 0; + + res = (value << 24) | (value >> 24); + res &= 0xFF0000FF; /* only for sure */ + res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000); + + return res; +} +#endif + +/****************************************************************************/ /** + * @brief Enable serail flash controller + * + * @param cfg: serial flash controller config + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + uint32_t time_out = 0; + + if (cfg == NULL) { + return; + } + + reg_base = BFLB_SF_CTRL_BASE; + time_out = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + time_out--; + + if (time_out == 0) { + return; + } + } + + regval = getreg32(reg_base + SF_CTRL_0_OFFSET); +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE + if (cfg->en32b_addr) { + regval |= SF_CTRL_SF_IF_32B_ADR_EN; + } else { + regval &= ~SF_CTRL_SF_IF_32B_ADR_EN; + } +#endif + + if (cfg->clk_delay > 0) { + regval |= SF_CTRL_SF_IF_READ_DLY_EN; + regval &= ~SF_CTRL_SF_IF_READ_DLY_N_MASK; + regval |= ((cfg->clk_delay-1) << SF_CTRL_SF_IF_READ_DLY_N_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_READ_DLY_EN; + } + + /* Serail out inverted, so sf ctrl send on negative edge */ + if (cfg->clk_invert) { + regval |= SF_CTRL_SF_CLK_OUT_INV_SEL; + } else { + regval &= ~SF_CTRL_SF_CLK_OUT_INV_SEL; + } + if (cfg->rx_clk_invert) { + regval |= SF_CTRL_SF_CLK_SF_RX_INV_SEL; + } else { + regval &= ~SF_CTRL_SF_CLK_SF_RX_INV_SEL; + } + putreg32(regval, reg_base+SF_CTRL_0_OFFSET); + +#if defined(BL602) ||defined(BL702) || defined(BL702L) + bflb_sf_ctrl_set_io_delay(0, cfg->do_delay, cfg->di_delay, cfg->oe_delay); + bflb_sf_ctrl_set_io_delay(1, cfg->do_delay, cfg->di_delay, cfg->oe_delay); + bflb_sf_ctrl_set_io_delay(2, cfg->do_delay, cfg->di_delay, cfg->oe_delay); +#endif + + /* Enable AHB access sram buffer and enable sf interface */ + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + regval |= SF_CTRL_SF_AHB2SRAM_EN; + regval |= SF_CTRL_SF_IF_EN; + putreg32(regval, reg_base+SF_CTRL_1_OFFSET); + + bflb_sf_ctrl_set_owner(cfg->owner); +} + +/****************************************************************************/ /** + * @brief SF Ctrl set io delay + * + * @param pad: Pad select + * @param do_delay: DO delay select + * @param di_delay: DI delay select + * @param oe_delay: OE delay select + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t do_delay, uint8_t di_delay, uint8_t oe_delay) +{ + uint32_t offset = 0; + uint32_t regval = 0; + + if (pad == SF_CTRL_PAD1) { + offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET; + } else if (pad == SF_CTRL_PAD2) { + offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET; + } else { + offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET; + } + + /* Set do di and oe delay */ + regval = getreg32(offset + SF_CTRL_IO_DLY_1_OFFSET); + regval &= ~SF_CTRL_IO_0_DO_DLY_SEL_MASK; + regval |= (do_delay << SF_CTRL_IO_0_DO_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_0_DI_DLY_SEL_MASK; + regval |= (di_delay << SF_CTRL_IO_0_DI_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_0_OE_DLY_SEL_MASK; + regval |= (oe_delay << SF_CTRL_IO_0_OE_DLY_SEL_SHIFT); + putreg32(regval, offset + SF_CTRL_IO_DLY_1_OFFSET); + + regval = getreg32(offset + SF_CTRL_IO_DLY_2_OFFSET); + regval &= ~SF_CTRL_IO_1_DO_DLY_SEL_MASK; + regval |= (do_delay << SF_CTRL_IO_1_DO_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_1_DI_DLY_SEL_MASK; + regval |= (di_delay << SF_CTRL_IO_1_DI_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_1_OE_DLY_SEL_MASK; + regval |= (oe_delay << SF_CTRL_IO_1_OE_DLY_SEL_SHIFT); + putreg32(regval, offset + SF_CTRL_IO_DLY_2_OFFSET); + + regval = getreg32(offset + SF_CTRL_IO_DLY_3_OFFSET); + regval &= ~SF_CTRL_IO_2_DO_DLY_SEL_MASK; + regval |= (do_delay << SF_CTRL_IO_2_DO_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_2_DI_DLY_SEL_MASK; + regval |= (di_delay << SF_CTRL_IO_2_DI_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_2_OE_DLY_SEL_MASK; + regval |= (oe_delay << SF_CTRL_IO_2_OE_DLY_SEL_SHIFT); + putreg32(regval, offset + SF_CTRL_IO_DLY_3_OFFSET); + + regval = getreg32(offset + SF_CTRL_IO_DLY_4_OFFSET); + regval &= ~SF_CTRL_IO_3_DO_DLY_SEL_MASK; + regval |= (do_delay << SF_CTRL_IO_3_DO_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_3_DI_DLY_SEL_MASK; + regval |= (di_delay << SF_CTRL_IO_3_DI_DLY_SEL_SHIFT); + regval &= ~SF_CTRL_IO_3_OE_DLY_SEL_MASK; + regval |= (oe_delay << SF_CTRL_IO_3_OE_DLY_SEL_SHIFT); + putreg32(regval, offset + SF_CTRL_IO_DLY_4_OFFSET); +} + +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +/****************************************************************************/ /** + * @brief Enable serail bank2 controller + * + * @param bank2_cfg: serial bank2 controller config + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2_cfg) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + if (bank2_cfg == NULL) { + return; + } + + reg_base = BFLB_SF_CTRL_BASE; + + /* Select if1 bank2 clock delay */ + regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_12_OFFSET); + if (bank2_cfg->bank2_rx_clk_invert_src) { + regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SRC; + + if (bank2_cfg->bank2_rx_clk_invert_sel) { + regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SEL; + } else { + regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SEL; + } + } else { + regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SRC; + } + + if (bank2_cfg->bank2_delay_src) { + regval |= SF_CTRL_SF2_IF_READ_DLY_SRC; + + if (bank2_cfg->bank2_clk_delay > 0) { + regval |= SF_CTRL_SF2_IF_READ_DLY_EN; + regval &= ~SF_CTRL_SF2_IF_READ_DLY_N_MASK; + regval |= ((bank2_cfg->bank2_clk_delay - 1) << SF_CTRL_SF2_IF_READ_DLY_N_SHIFT); + } else { + regval &= ~SF_CTRL_SF2_IF_READ_DLY_EN; + } + } else { + regval &= ~SF_CTRL_SF2_IF_READ_DLY_SRC; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_12_OFFSET); + + /* Select sbus2 clock delay */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET); + if (bank2_cfg->bank2_rx_clk_invert_sel) { + regval |= SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL; + } else { + regval &= ~SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL; + } + + if (bank2_cfg->bank2_clk_delay > 0) { + regval |= SF_CTRL_SF_IF2_READ_DLY_EN; + regval &= ~SF_CTRL_SF_IF2_READ_DLY_N_MASK; + regval |= ((bank2_cfg->bank2_clk_delay - 1) << SF_CTRL_SF_IF2_READ_DLY_N_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF2_READ_DLY_EN; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET); + + /* Dual flash mode, enable bank2, select pad1 and pad2 */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET); + regval |= SF_CTRL_SF_IF_BK2_EN; + regval |= SF_CTRL_SF_IF_BK2_MODE; + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + putreg32(regval, reg_base+SF_CTRL_2_OFFSET); +} + +/****************************************************************************/ /** + * @brief Flash controller sbus2 hold sram + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_hold_sram(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + /* Sbus2 hold sram */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET); + regval |= SF_CTRL_SF_IF2_FN_SEL; + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET); +} + +/****************************************************************************/ /** + * @brief Flash controller sbus2 release sram + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_release_sram(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + /* Sbus2 release sram */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET); + regval &= ~SF_CTRL_SF_IF2_FN_SEL; + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET); +} + +/****************************************************************************/ /** + * @brief Get flash controller sbus2 status + * + * @param None + * + * @return Wether if2 is enable + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_is_sbus2_enable(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET); + if (regval & SF_CTRL_SF_IF2_EN) { + if (regval & SF_CTRL_SF_IF2_FN_SEL) { + return 1; + } else { + return 0; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief SF Ctrl set sbus2 repalce + * + * @param pad: SF pad to replace + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_replace(uint8_t pad) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + /* Sbus2 enable */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET); + regval |= SF_CTRL_SF_IF2_EN; + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET); + + bflb_sf_ctrl_sbus2_hold_sram(); + + /* Sbus2 repalce pad */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET); + regval &= ~SF_CTRL_SF_IF2_REPLACE_SF1; + regval &= ~SF_CTRL_SF_IF2_REPLACE_SF2; + regval &= ~SF_CTRL_SF_IF2_REPLACE_SF3; + + if (pad == SF_CTRL_PAD1) { + regval |= SF_CTRL_SF_IF2_REPLACE_SF1; + } else if (pad == SF_CTRL_PAD2) { + regval |= SF_CTRL_SF_IF2_REPLACE_SF2; + } else { + regval |= SF_CTRL_SF_IF2_REPLACE_SF3; + } + + regval &= ~SF_CTRL_SF_IF2_PAD_SEL_MASK; + regval |= (pad << SF_CTRL_SF_IF2_PAD_SEL_SHIFT); + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET); +} + +/****************************************************************************/ /** + * @brief SF Ctrl sbus2 revoke replace + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_revoke_replace(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + bflb_sf_ctrl_sbus2_release_sram(); + + /* Sbus2 clear repalce pad */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET); + regval &= ~SF_CTRL_SF_IF2_REPLACE_SF1; + regval &= ~SF_CTRL_SF_IF2_REPLACE_SF2; + regval &= ~SF_CTRL_SF_IF2_REPLACE_SF3; + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET); + + /* Sbus2 disable */ + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET); + regval &= ~SF_CTRL_SF_IF2_EN; + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET); +} + +/****************************************************************************/ /** + * @brief SF Ctrl set sbus2 clock delay + * + * @param clk_delay: Sbus2 clock delay + * @param rx_clk_invert: Sbus2 rx clock invert + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET); + + if (clk_delay > 0) { + regval |= SF_CTRL_SF_IF2_READ_DLY_EN; + regval &= ~SF_CTRL_SF_IF2_READ_DLY_N_MASK; + regval |= ((clk_delay-1) << SF_CTRL_SF_IF2_READ_DLY_N_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF2_READ_DLY_EN; + } + + if (rx_clk_invert) { + regval |= SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL; + } else { + regval &= ~SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET); +} + +/****************************************************************************/ /** + * @brief SF Ctrl dual flash memory remap set + * + * @param remap: Memory remap set type + * @param lock: Memory remap lock + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_2_OFFSET); + regval &= ~SF_CTRL_SF_AHB2SIF_REMAP_MASK; + regval |= (remap << SF_CTRL_SF_AHB2SIF_REMAP_SHIFT); + putreg32(regval, reg_base+SF_CTRL_2_OFFSET); + + regval = getreg32(reg_base + SF_CTRL_2_OFFSET); + if (lock) { + regval |= SF_CTRL_SF_AHB2SIF_REMAP_LOCK; + } else { + regval &= ~SF_CTRL_SF_AHB2SIF_REMAP_LOCK; + } + putreg32(regval, reg_base+SF_CTRL_2_OFFSET); +} +#endif + +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE +/****************************************************************************/ /** + * @brief Get flash controller clock delay value + * + * @param en32_bits_addr: Serial flash enable or disable 32-bits addr + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_32bits_addr_en(uint8_t en32_bits_addr) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_0_OFFSET); + if (en32_bits_addr) { + regval |= SF_CTRL_SF_IF_32B_ADR_EN; + } else { + regval &= ~SF_CTRL_SF_IF_32B_ADR_EN; + } + putreg32(regval, reg_base+SF_CTRL_0_OFFSET); +} +#endif + +#ifdef BFLB_SF_CTRL_PSRAM_ENABLE +/****************************************************************************/ /** + * @brief Enable serail psram controller + * + * @param psram_cfg: serial psram controller config + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + +#if defined(BL702L) + /* Enable psram dual bank mode */ + regval = getreg32(reg_base + SF_CTRL_2_OFFSET); + regval |= SF_CTRL_SF_IF_BK2_EN; + regval |= SF_CTRL_SF_IF_BK2_MODE; + putreg32(regval, reg_base+SF_CTRL_2_OFFSET); +#endif + + /* Select psram clock delay */ + regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_12_OFFSET); + if (psram_cfg->psram_rx_clk_invert_src) { + regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SRC; + + if (psram_cfg->psram_rx_clk_invert_sel) { + regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SEL; + } else { + regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SEL; + } + } else { + regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SRC; + } + + if (psram_cfg->psram_delay_src) { + regval |= SF_CTRL_SF2_IF_READ_DLY_SRC; + + if (psram_cfg->psram_clk_delay > 0) { + regval |= SF_CTRL_SF2_IF_READ_DLY_EN; + regval &= ~SF_CTRL_SF2_IF_READ_DLY_N_MASK; + regval |= ((psram_cfg->psram_clk_delay - 1) << SF_CTRL_SF2_IF_READ_DLY_N_SHIFT); + } else { + regval &= ~SF_CTRL_SF2_IF_READ_DLY_EN; + } + } else { + regval &= ~SF_CTRL_SF2_IF_READ_DLY_SRC; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_12_OFFSET); + + /* Enable AHB access sram buffer and enable sf interface */ + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + regval |= SF_CTRL_SF_AHB2SRAM_EN; + regval |= SF_CTRL_SF_IF_EN; + putreg32(regval, reg_base+SF_CTRL_1_OFFSET); + + bflb_sf_ctrl_set_owner(psram_cfg->owner); +} +#endif + +/****************************************************************************/ /** + * @brief Get flash controller clock delay value + * + * @param None + * + * @return Clock delay value + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_clock_delay(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_0_OFFSET); + if ((regval&SF_CTRL_SF_IF_READ_DLY_EN) == 0) { + return 0; + } + + return ((regval&SF_CTRL_SF_IF_READ_DLY_N_MASK)>>SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1; +} + +/****************************************************************************/ /** + * @brief Set flash controller clock delay value + * + * @param delay: Clock delay value + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_set_clock_delay(uint8_t delay) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_0_OFFSET); + if (delay > 0) { + regval |= SF_CTRL_SF_IF_READ_DLY_EN; + regval &= ~SF_CTRL_SF_IF_READ_DLY_N_MASK; + regval |= ((delay-1) << SF_CTRL_SF_IF_READ_DLY_N_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_READ_DLY_EN; + } + putreg32(regval, reg_base+SF_CTRL_0_OFFSET); +} + +/****************************************************************************/ /** + * @brief SF Ctrl get wrap queue value + * + * @param None + * + * @return Wrap queue value + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_wrap_queue_value(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_3_OFFSET); + return (regval&SF_CTRL_SF_CMDS_2_WRAP_Q) ? 1:0; +} + +#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P) +/****************************************************************************/ /** + * @brief SF Ctrl set cmds config + * + * @param cmds_cfg: SF Ctrl cmds config + * @param bank: bank select type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t bank) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_3_OFFSET); + regval &= ~SF_CTRL_SF_IF_1_ACK_LAT_MASK; + regval |= ((cmds_cfg->ack_latency) << SF_CTRL_SF_IF_1_ACK_LAT_SHIFT); + + if (cmds_cfg->cmds_core_en) { + regval |= SF_CTRL_SF_CMDS_CORE_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_CORE_EN; + } + + if (bank == SF_CTRL_FLASH_BANK1) { + if (cmds_cfg->cmds_en) { + regval |= SF_CTRL_SF_CMDS_2_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_2_EN; + } + + regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK; + regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT); + regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK; + regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT); + } else { + if (cmds_cfg->cmds_en) { + regval |= SF_CTRL_SF_CMDS_1_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_1_EN; + } + + regval &= ~SF_CTRL_SF_CMDS_1_WRAP_MODE_MASK; + regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT); + regval &= ~SF_CTRL_SF_CMDS_1_WRAP_LEN_MASK; + regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT); + } + putreg32(regval, reg_base+SF_CTRL_3_OFFSET); +} +#elif defined(BL702L) +/****************************************************************************/ /** + * @brief SF Ctrl set cmds config + * + * @param cmds_cfg: SF Ctrl cmds config + * @param sel: select set flash or psram cmds + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_3_OFFSET); + if (sel == SF_CTRL_SEL_FLASH) { + if (cmds_cfg->cmds_en) { + regval |= SF_CTRL_SF_CMDS_1_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_1_EN; + } + regval &= ~SF_CTRL_SF_CMDS_1_WRAP_MODE_MASK; + regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT); + regval &= ~SF_CTRL_SF_CMDS_1_WRAP_LEN_MASK; + regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT); + } else { + if (cmds_cfg->cmds_en) { + regval |= SF_CTRL_SF_CMDS_2_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_2_EN; + } + regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK; + regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT); + regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK; + regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT); + } + putreg32(regval, reg_base+SF_CTRL_3_OFFSET); +} + +/****************************************************************************/ /** + * @brief SF Ctrl burst toggle select + * + * @param burst_toggle_en: burst toggle enable or not + * @param mode: SPI or QPI mode + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_3_OFFSET); + if (burst_toggle_en) { + regval |= SF_CTRL_SF_CMDS_2_BT_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_2_BT_EN; + } + putreg32(regval, reg_base+SF_CTRL_3_OFFSET); + + regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_6_OFFSET); + if (mode) { + regval |= SF_CTRL_SF_IF_3_QPI_MODE_EN; + } else { + regval &= ~SF_CTRL_SF_IF_3_QPI_MODE_EN; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_6_OFFSET); +} +#elif defined(BL702) || defined(BL602) +/****************************************************************************/ /** + * @brief SF Ctrl set cmds config + * + * @param cmds_cfg: SF Ctrl cmds config + * @param sel: select bank0 or bank1 + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_3_OFFSET); + + if (cmds_cfg->cmds_en) { + regval |= SF_CTRL_SF_CMDS_2_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_2_EN; + } + +#if defined(BL702) + if (cmds_cfg->burst_toggle_en) { + regval |= SF_CTRL_SF_CMDS_2_BT_EN; + } else { + regval &= ~SF_CTRL_SF_CMDS_2_BT_EN; + } +#endif + + regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK; + regval |= (cmds_cfg->cmds_wrap_mode << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT); + + regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK; + regval |= (cmds_cfg->cmds_wrap_len << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT); + putreg32(regval, reg_base+SF_CTRL_3_OFFSET); +} +#endif + +/****************************************************************************/ /** + * @brief SF Ctrl pad select + * + * @param sel: Pin select type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_select_pad(uint8_t sel) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_2_OFFSET); +#if defined(BL628) || defined(BL616) + if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) { + /* Single flash mode, disable bank2 */ + regval &= ~SF_CTRL_SF_IF_BK2_EN; + + if (sel <= SF_IO_EMB_SWAP_IO2CS) { + /* Select embedded pad1 */ + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + } else { + /* Select pad2 or pad3 */ + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + regval |= (((sel&0xf) >> 2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT); + } + } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) + ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { + /* Dual flash mode, enable bank2, select pad1 and pad2 */ + regval |= SF_CTRL_SF_IF_BK2_EN; + regval |= SF_CTRL_SF_IF_BK2_MODE; + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + } +#elif defined(BL808) || defined(BL606P) + if (sel <= SF_IO_EXT_SF2) { + /* Single flash mode, disable bank2 */ + regval &= ~SF_CTRL_SF_IF_BK2_EN; + + if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { + /* Select embedded pad1 */ + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + } else { + /* Select pad2 or pad3 */ + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + regval |= (((sel&0xf) >> 2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT); + } + } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { + /* Dual flash mode, enable bank2, select pad1 and pad2 */ + regval |= SF_CTRL_SF_IF_BK2_EN; + regval |= SF_CTRL_SF_IF_BK2_MODE; + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + } +#elif defined(BL702) + if (sel <= SF_CTRL_SEL_SF3) { + regval &= ~SF_CTRL_SF_IF_BK2_EN; + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + regval |= (sel << SF_CTRL_SF_IF_PAD_SEL_SHIFT); + } else if (sel >= SF_CTRL_SEL_DUAL_BANK_SF1_SF2 && sel <= SF_CTRL_SEL_DUAL_BANK_SF3_SF1) { + regval |= SF_CTRL_SF_IF_BK2_EN; + regval |= SF_CTRL_SF_IF_BK2_MODE; + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + regval |= ((sel - SF_CTRL_SEL_DUAL_BANK_SF1_SF2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT); + } else if (sel == SF_CTRL_SEL_DUAL_CS_SF2) { + regval |= SF_CTRL_SF_IF_BK2_EN; + regval &= ~SF_CTRL_SF_IF_BK2_MODE; + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + regval |= (1 << SF_CTRL_SF_IF_PAD_SEL_SHIFT); + } else if (sel == SF_CTRL_SEL_DUAL_CS_SF3) { + regval |= SF_CTRL_SF_IF_BK2_EN; + regval &= ~SF_CTRL_SF_IF_BK2_MODE; + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + regval |= (2 << SF_CTRL_SF_IF_PAD_SEL_SHIFT); + } +#else + regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK; + regval |= (sel << SF_CTRL_SF_IF_PAD_SEL_SHIFT); +#endif + putreg32(regval, reg_base+SF_CTRL_2_OFFSET); +} + +/****************************************************************************/ /** + * @brief SF Ctrl select bank on system bus + * + * @param bank: bank select type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_sbus_select_bank(uint8_t bank) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_2_OFFSET); + if (bank) { + regval |= SF_CTRL_SF_IF_0_BK_SEL; + } else { + regval &= ~SF_CTRL_SF_IF_0_BK_SEL; + } + putreg32(regval, reg_base+SF_CTRL_2_OFFSET); +} + +/****************************************************************************/ /** + * @brief Set flash controller owner:I/D AHB or system AHB + * + * @param owner: owner type + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_set_owner(uint8_t owner) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + uint32_t time_out = 0; + + reg_base = BFLB_SF_CTRL_BASE; + time_out = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + time_out--; + + if (time_out == 0) { + return; + } + } + + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + /* Set owner */ + if (owner) { + regval |= SF_CTRL_SF_IF_FN_SEL; + } else { + regval &= ~SF_CTRL_SF_IF_FN_SEL; + } + + /* Set iahb to flash interface */ + if (owner == SF_CTRL_OWNER_IAHB) { + regval |= SF_CTRL_SF_AHB2SIF_EN; + } else { + regval &= ~SF_CTRL_SF_AHB2SIF_EN; + } + putreg32(regval, reg_base+SF_CTRL_1_OFFSET); +} + +/****************************************************************************/ /** + * @brief Disable flash controller + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_disable(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + regval &= ~SF_CTRL_SF_IF_EN; + putreg32(regval, reg_base+SF_CTRL_1_OFFSET); +} + +/****************************************************************************/ /** + * @brief Enable flash controller AES with big indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_be(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_0_OFFSET); + regval |= SF_CTRL_SF_AES_KEY_ENDIAN; + regval |= SF_CTRL_SF_AES_IV_ENDIAN; + regval |= SF_CTRL_SF_AES_DIN_ENDIAN; + regval |= SF_CTRL_SF_AES_DOUT_ENDIAN; + putreg32(regval, reg_base+SF_CTRL_0_OFFSET); +} + +/****************************************************************************/ /** + * @brief Enable flash controller AES with little indian + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_le(void) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_0_OFFSET); + regval &= ~SF_CTRL_SF_AES_KEY_ENDIAN; + regval &= ~SF_CTRL_SF_AES_IV_ENDIAN; + regval &= ~SF_CTRL_SF_AES_DIN_ENDIAN; + regval &= ~SF_CTRL_SF_AES_DOUT_ENDIAN; + putreg32(regval, reg_base+SF_CTRL_0_OFFSET); +} + +/****************************************************************************/ /** + * @brief Serial flash controller set AES region + * + * @param region: region number + * @param enable: enable or not + * @param hw_key: hardware key or software key + * @param start_addr: region start address + * @param end_addr: region end address + * @param locked: lock this region or not + * + * @return None + * +*******************************************************************************/ +__WEAK +#if defined (BL702) || defined(BL602) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hw_key, + uint32_t start_addr, uint32_t end_addr, uint8_t locked) +{ + /* 0x30 : sf_aes_cfg */ + #define SF_CTRL_SF_AES_REGION_CFG_END_SHIFT (0U) + #define SF_CTRL_SF_AES_REGION_CFG_END_MASK (0x3fff<cmd_buf[0], cmd_offset+SF_CTRL_IF_SAHB_1_OFFSET); + putreg32(cfg->cmd_buf[1], cmd_offset+SF_CTRL_IF_SAHB_2_OFFSET); + + regval = getreg32(cmd_offset + SF_CTRL_IF_SAHB_0_OFFSET); + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) { + regval &= ~SF_CTRL_IF_0_QPI_MODE_EN; + } else { + regval |= SF_CTRL_IF_0_QPI_MODE_EN; + } + + regval &= ~SF_CTRL_IF_0_SPI_MODE_MASK; + if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) { + if (SF_CTRL_DATA_1_LINE == cfg->data_mode) { + regval |= (SF_CTRL_NIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) { + regval |= (SF_CTRL_DO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) { + regval |= (SF_CTRL_QO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_DIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_QIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT); + } + + /* Configure cmd */ + regval |= SF_CTRL_IF_0_CMD_EN; + regval &= ~SF_CTRL_IF_0_CMD_BYTE_MASK; + + /* Configure address */ + regval &= ~SF_CTRL_IF_0_ADR_BYTE_MASK; + if (cfg->addr_size != 0) { + regval |= SF_CTRL_IF_0_ADR_EN; + regval |= ((cfg->addr_size-1) << SF_CTRL_IF_0_ADR_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_IF_0_ADR_EN; + } + + /* Configure dummy */ + regval &= ~SF_CTRL_IF_0_DMY_BYTE_MASK; + if (cfg->dummy_clks != 0) { + regval |= SF_CTRL_IF_0_DMY_EN; + regval |= ((cfg->dummy_clks-1) << SF_CTRL_IF_0_DMY_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_IF_0_DMY_EN; + } + + /* Configure data */ + regval &= ~SF_CTRL_IF_0_DAT_BYTE_MASK; + if (cfg->nb_data != 0) { + regval |= SF_CTRL_IF_0_DAT_EN; + regval |= ((cfg->nb_data-1) << SF_CTRL_IF_0_DAT_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_IF_0_DAT_EN; + } + + /* Set read write flag */ + if (cfg->rw_flag) { + regval |= SF_CTRL_IF_0_DAT_RW; + } else { + regval &= ~SF_CTRL_IF_0_DAT_RW; + } + putreg32(regval, cmd_offset+SF_CTRL_IF_SAHB_0_OFFSET); + + //switch sf_clk_sahb_sram_sel = 0 + bflb_sf_ctrl_select_clock(1); + + /* Trigger */ + regval |= SF_CTRL_IF_0_TRIG; + putreg32(regval, cmd_offset+SF_CTRL_IF_SAHB_0_OFFSET); + + time_out = SF_CTRL_BUSY_STATE_TIMEOUT; + while (bflb_sf_ctrl_get_busy_state()) { + time_out--; + + if (time_out == 0) { + bflb_sf_ctrl_select_clock(0); + return; + } + } + + //switch sf_clk_sahb_sram_sel = 0 + bflb_sf_ctrl_select_clock(0); +} + +/****************************************************************************/ /** + * @brief SF Ctrl disable iahb to flash wrap access for XTS mode + * + * @param disable: Disable for 1 and enable for 0 + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_disable_wrap_access(uint8_t disable) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + + reg_base = BFLB_SF_CTRL_BASE; + + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + if (disable) { + regval &= ~SF_CTRL_SF_AHB2SIF_DISWRAP; + } else { + regval |= SF_CTRL_SF_AHB2SIF_DISWRAP; + } + putreg32(regval, reg_base+SF_CTRL_1_OFFSET); +} + +/****************************************************************************/ /** + * @brief Config SF controller for xip read + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmd_valid: command valid or not, for continous read, cache may need no command + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + uint32_t time_out = 0; + + reg_base = BFLB_SF_CTRL_BASE; + time_out = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + time_out--; + + if (time_out == 0) { + return; + } + } + + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) { + return; + } + + /* Copy command buffer */ + putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_1_OFFSET); + putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_2_OFFSET); + + regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_0_OFFSET); + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) { + regval &= ~SF_CTRL_SF_IF_1_QPI_MODE_EN; + } else { + regval |= SF_CTRL_SF_IF_1_QPI_MODE_EN; + } + + regval &= ~SF_CTRL_SF_IF_1_SPI_MODE_MASK; + if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) { + if (SF_CTRL_DATA_1_LINE == cfg->data_mode) { + regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) { + regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) { + regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT); + } + + regval &= ~SF_CTRL_SF_IF_1_CMD_BYTE_MASK; + if (cmd_valid) { + regval |= SF_CTRL_SF_IF_1_CMD_EN; + } else { + regval &= ~SF_CTRL_SF_IF_1_CMD_EN; + } + + /* Configure address */ + regval &= ~SF_CTRL_SF_IF_1_ADR_BYTE_MASK; + if (cfg->addr_size != 0) { + regval |= SF_CTRL_SF_IF_1_ADR_EN; + regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_1_ADR_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_1_ADR_EN; + } + + /* configure dummy */ + regval &= ~SF_CTRL_SF_IF_1_DMY_BYTE_MASK; + if (cfg->dummy_clks != 0) { + regval |= SF_CTRL_SF_IF_1_DMY_EN; + regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_1_DMY_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_1_DMY_EN; + } + + /* Configure data */ + if (cfg->nb_data != 0) { + regval |= SF_CTRL_SF_IF_1_DAT_EN; + } else { + regval &= ~SF_CTRL_SF_IF_1_DAT_EN; + } + + /* Set read write flag */ + if (cfg->rw_flag) { + regval |= SF_CTRL_SF_IF_1_DAT_RW; + } else { + regval &= ~SF_CTRL_SF_IF_1_DAT_RW; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_0_OFFSET); +} + +#ifdef BFLB_SF_CTRL_PSRAM_ENABLE +/****************************************************************************/ /** + * @brief Config psram controller for psram I/D cache write + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmd_valid: command valid or not, cache may need no command + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + uint32_t time_out = 0; + + reg_base = BFLB_SF_CTRL_BASE; + time_out = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + time_out--; + + if (time_out == 0) { + return; + } + } + + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) { + return; + } + + /* Copy command buffer */ + putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_4_OFFSET); + putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_5_OFFSET); + + getreg32(reg_base + SF_CTRL_SF_IF_IAHB_3_OFFSET); + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) { + regval &= ~SF_CTRL_SF_IF_2_QPI_MODE_EN; + } else { + regval |= SF_CTRL_SF_IF_2_QPI_MODE_EN; + } + + regval &= ~SF_CTRL_SF_IF_2_SPI_MODE_MASK; + if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) { + if (SF_CTRL_DATA_1_LINE == cfg->data_mode) { + regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) { + regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) { + regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT); + } + + regval &= ~SF_CTRL_SF_IF_2_CMD_BYTE_MASK; + if (cmd_valid) { + regval |= SF_CTRL_SF_IF_2_CMD_EN; + } else { + regval &= ~SF_CTRL_SF_IF_2_CMD_EN; + } + + /* Configure address */ + regval &= ~SF_CTRL_SF_IF_2_ADR_BYTE_MASK; + if (cfg->addr_size != 0) { + regval |= SF_CTRL_SF_IF_2_ADR_EN; + regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_2_ADR_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_2_ADR_EN; + } + + /* configure dummy */ + regval &= ~SF_CTRL_SF_IF_2_DMY_BYTE_MASK; + if (cfg->dummy_clks != 0) { + regval |= SF_CTRL_SF_IF_2_DMY_EN; + regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_2_DMY_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_2_DMY_EN; + } + + /* Configure data */ + if (cfg->nb_data != 0) { + regval |= SF_CTRL_SF_IF_2_DAT_EN; + } else { + regval &= ~SF_CTRL_SF_IF_2_DAT_EN; + } + + /* Set read write flag */ + if (cfg->rw_flag) { + regval |= SF_CTRL_SF_IF_2_DAT_RW; + } else { + regval &= ~SF_CTRL_SF_IF_2_DAT_RW; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_3_OFFSET); +} +#endif + +/****************************************************************************/ /** + * @brief Config bank2 controller for flash2 I/D cache read + * + * @param cfg: Serial flash controller command configuration pointer + * @param cmd_valid: command valid or not, for continous read, cache may need no command + * + * @return None + * +*******************************************************************************/ +__WEAK +#ifdef BFLB_SF_CTRL_PSRAM_ENABLE +void ATTR_TCM_SECTION bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) +#else +void ATTR_TCM_SECTION bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) +#endif +{ + uint32_t reg_base = 0; + uint32_t regval = 0; + uint32_t time_out = 0; + + reg_base = BFLB_SF_CTRL_BASE; + time_out = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + time_out--; + + if (time_out == 0) { + return; + } + } + + regval = getreg32(reg_base + SF_CTRL_1_OFFSET); + if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) { + return; + } + + /* Copy command buffer */ + putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_10_OFFSET); + putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_11_OFFSET); + + regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_9_OFFSET); + /* Configure SPI and IO mode*/ + if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) { + regval &= ~SF_CTRL_SF_IF_4_QPI_MODE_EN; + } else { + regval |= SF_CTRL_SF_IF_4_QPI_MODE_EN; + } + + regval &= ~SF_CTRL_SF_IF_4_SPI_MODE_MASK; + if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) { + if (SF_CTRL_DATA_1_LINE == cfg->data_mode) { + regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) { + regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT); + } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) { + regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT); + } + } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT); + } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) { + regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT); + } + + regval &= ~SF_CTRL_SF_IF_4_CMD_BYTE_MASK; + if (cmd_valid) { + regval |= SF_CTRL_SF_IF_4_CMD_EN; + } else { + regval &= ~SF_CTRL_SF_IF_4_CMD_EN; + } + + /* Configure address */ + regval &= ~SF_CTRL_SF_IF_4_ADR_BYTE_MASK; + if (cfg->addr_size != 0) { + regval |= SF_CTRL_SF_IF_4_ADR_EN; + regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_4_ADR_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_4_ADR_EN; + } + + /* configure dummy */ + regval &= ~SF_CTRL_SF_IF_4_DMY_BYTE_MASK; + if (cfg->dummy_clks != 0) { + regval |= SF_CTRL_SF_IF_4_DMY_EN; + regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_4_DMY_BYTE_SHIFT); + } else { + regval &= ~SF_CTRL_SF_IF_4_DMY_EN; + } + + /* Configure data */ + if (cfg->nb_data != 0) { + regval |= SF_CTRL_SF_IF_4_DAT_EN; + } else { + regval &= ~SF_CTRL_SF_IF_4_DAT_EN; + } + + /* Set read write flag */ + if (cfg->rw_flag) { + regval |= SF_CTRL_SF_IF_4_DAT_RW; + } else { + regval &= ~SF_CTRL_SF_IF_4_DAT_RW; + } + putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_9_OFFSET); +} + +/****************************************************************************/ /** + * @brief Get SF Ctrl busy state + * + * @param None + * + * @return 1 means SF ctrl busy or 0 means SF ctrl not busy + * +*******************************************************************************/ +__WEAK +uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_busy_state(void) +{ + uint32_t regval = 0; + uint32_t cmd_offset = 0; + +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE + if (bflb_sf_ctrl_is_sbus2_enable() == 0) { + cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; + } else { + cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; + } +#else + cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; +#endif + + regval = getreg32(cmd_offset + SF_CTRL_IF_SAHB_0_OFFSET); + if (regval & SF_CTRL_IF_BUSY) { + return 1; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief SF Controller interrupt handler + * + * @param None + * + * @return None + * +*******************************************************************************/ +void bflb_sf_ctrl_irqhandler(void) +{ + /* TODO: Not implemented */ +} + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL628_Peripheral_Driver */ diff --git a/drivers/lhal/src/flash/bflb_sf_ctrl.h b/drivers/lhal/src/flash/bflb_sf_ctrl.h new file mode 100644 index 00000000..de58709e --- /dev/null +++ b/drivers/lhal/src/flash/bflb_sf_ctrl.h @@ -0,0 +1,482 @@ +/** + ****************************************************************************** + * @file bflb_sf_ctrl.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL628_SF_CTRL_H__ +#define __BL628_SF_CTRL_H__ + +#include "bflb_core.h" + +/** @addtogroup BL628_Peripheral_Driver + * @{ + */ + +/** @addtogroup SF_CTRL + * @{ + */ + +/** @defgroup SF_CTRL_Public_Types + * @{ + */ + +#if defined(BL602) || defined(BL702) || defined(BL702L) +#define BFLB_SF_CTRL_BASE ((uint32_t)0x4000B000) +#elif defined(BL606P) || defined(BL808) || defined(BL616) +#define BFLB_SF_CTRL_BASE ((uint32_t)0x2000b000) +#elif defined(BL628) +#define BFLB_SF_CTRL_BASE ((uint32_t)0x20082000) +#endif + +#if defined(BL602) || defined(BL702) || defined(BL702L) +#define BFLB_FLASH_XIP_BASE (0x23000000) +#define BFLB_FLASH_XIP_END (0x23000000 + 16 * 1024 * 1024) +#elif defined(BL606P) || defined(BL808) +#define BFLB_FLASH_XIP_BASE (0x58000000) +#define BFLB_FLASH_XIP_END (0x58000000 + 64 * 1024 * 1024) +#elif defined(BL616) +#define BFLB_FLASH_XIP_BASE (0xA0000000) +#define BFLB_FLASH_XIP_END (0xA0000000 + 64 * 1024 * 1024) +#elif defined(BL628) +#define BFLB_FLASH_XIP_BASE (0x80000000) +#define BFLB_FLASH_XIP_END (0x80000000 + 64 * 1024 * 1024) +#endif + +#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P) +#define BFLB_SF_CTRL_SBUS2_ENABLE +#define BFLB_SF_CTRL_32BITS_ADDR_ENABLE +#define BFLB_SF_CTRL_AES_XTS_ENABLE +#endif +#if defined(BL702) || defined(BL702L) +#define BFLB_SF_CTRL_PSRAM_ENABLE +#endif + +/** + * @brief Serial flash pad type definition + */ +#define SF_CTRL_PAD1 0 /*!< SF Ctrl pad 1 */ +#define SF_CTRL_PAD2 1 /*!< SF Ctrl pad 2 */ +#define SF_CTRL_PAD3 2 /*!< SF Ctrl pad 3 */ + +/** + * @brief Serial flash config pin select type definition + */ +#if defined(BL628) || defined(BL616) +#define SF_IO_EMB_SWAP_IO3IO0 0x0 /*!< SF select embedded flash swap io3 with io0 */ +#define SF_IO_EMB_SWAP_IO3IO0_IO2CS 0x1 /*!< SF select embedded flash swap io3 with io0 and io2 with cs */ +#define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */ +#define SF_IO_EMB_SWAP_IO2CS 0x3 /*!< SF select embedded flash swap io2 with cs */ +#define SF_IO_EXT_SF2_SWAP_IO3IO0 0x4 /*!< SF select external flash SF2 use gpio4-9 and SF2 swap io3 with io0 */ +#define SF_IO_EXT_SF3 0x8 /*!< SF select external flash SF3 use gpio10-15 */ +#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 0x14 /*!< SF select embedded flash swap io3 with io0 and SF2 swap io3 with io0*/ +#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0 0x15 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 swap io3 with io0 */ +#define SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0 0x16 /*!< SF select embedded flash no swap and SF2 swap io3 with io0 */ +#define SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0 0x17 /*!< SF select embedded flash swap io2 with cs, and SF2 swap io3 with io0 */ +#define SF_IO_EXT_SF2 0x24 /*!< SF select external flash SF2 use gpio4-9 */ +#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2 0x34 /*!< SF select embedded flash swap io3 with io0 and SF2 use gpio4-9 */ +#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2 0x35 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 use gpio4-9 */ +#define SF_IO_EMB_SWAP_NONE_AND_SF2 0x36 /*!< SF select embedded flash no swap and SF2 use gpio4-9 */ +#define SF_IO_EMB_SWAP_IO2CS_AND_SF2 0x37 /*!< SF select embedded flash swap io2 with cs and SF2 use gpio4-9 */ +#elif defined(BL808) || defined(BL606P) +#define SF_IO_EMB_SWAP_IO0_IO3 0x0 /*!< SF select embedded flash swap io0 with io3 */ +#define SF_IO_EMB_SWAP_DUAL_IO0_IO3 0x1 /*!< SF select embedded flash swap dual io0 with io3 */ +#define SF_IO_EMB_SWAP_NONE 0x2 /*!< SF select embedded flash no swap */ +#define SF_IO_EMB_SWAP_NONE_DUAL_IO0 0x3 /*!< SF select embedded flash no swap and use dual io0 */ +#define SF_IO_EXT_SF2 0x4 /*!< SF select external flash SF2 use gpio34-39 */ +#define SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 0x14 /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */ +#define SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 0x15 /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */ +#define SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 0x16 /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */ +#define SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 0x17 /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */ +#elif defined(BL702L) +#define SF_CTRL_SEL_EXTERNAL_FLASH 0x0 /*!< SF select sf2, flash use GPIO 23-28, external flash */ +#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE 0x1 /*!< SF select sf1, embedded flash do not swap */ +#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2 0x2 /*!< SF select sf1, embedded flash swap cs/io2 */ +#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3 0x3 /*!< SF select sf1, embedded flash swap io0/io3 */ +#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH 0x4 /*!< SF select sf1, embedded flash swap cs/io2 and io0/io3 */ +#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE 0x5 /*!< SF select sf1, embedded flash interface reverse and do not swap */ +#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2 0x6 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 */ +#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3 0x7 /*!< SF select sf1, embedded flash interface reverse and swap io0/io3 */ +#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH 0x8 /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 and io0/io3 */ +#elif defined(BL702) +#define SF_CTRL_SEL_SF1 0x0 /*!< SF Ctrl select sf1, flash use GPIO 17-22, no psram */ +#define SF_CTRL_SEL_SF2 0x1 /*!< SF Ctrl select sf2, flash use GPIO 23-28, no psram, embedded flash */ +#define SF_CTRL_SEL_SF3 0x2 /*!< SF Ctrl select sf3, flash use GPIO 32-37, no psram */ +#define SF_CTRL_SEL_DUAL_BANK_SF1_SF2 0x3 /*!< SF Ctrl select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */ +#define SF_CTRL_SEL_DUAL_BANK_SF2_SF3 0x4 /*!< SF Ctrl select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */ +#define SF_CTRL_SEL_DUAL_BANK_SF3_SF1 0x5 /*!< SF Ctrl select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */ +#define SF_CTRL_SEL_DUAL_CS_SF2 0x6 /*!< SF Ctrl select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */ +#define SF_CTRL_SEL_DUAL_CS_SF3 0x7 /*!< SF Ctrl select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */ +#elif defined(BL602) +#define SF_CTRL_EMBEDDED_SEL 0x0 /*!< Embedded flash select */ +#define SF_CTRL_EXTERNAL_17TO22_SEL 0x1 /*!< External flash select gpio 17-22 */ +#define SF_CTRL_EXTERNAL_0TO2_20TO22_SEL 0x2 /*!< External flash select gpio 0-2 and 20-22 */ +#endif + + +/** + * @brief Serial flash select bank control type definition + */ +#if defined(BL702) || defined(BL702L) +#define SF_CTRL_SEL_FLASH 0 /*!< SF Ctrl system bus control flash */ +#define SF_CTRL_SEL_PSRAM 1 /*!< SF Ctrl system bus control psram */ +#else +#define SF_CTRL_FLASH_BANK0 0 /*!< SF Ctrl select flash bank0 */ +#define SF_CTRL_FLASH_BANK1 1 /*!< SF Ctrl select flash bank1 */ +#endif + +/** + * @brief Serial flash controller wrap mode type definition + */ +#define SF_CTRL_WRAP_MODE_0 0 /*!< Cmds bypass wrap commands to macro, original mode */ +#define SF_CTRL_WRAP_MODE_1 1 /*!< Cmds handle wrap commands, original mode */ +#define SF_CTRL_WRAP_MODE_2 2 /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */ +#define SF_CTRL_WRAP_MODE_3 3 /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */ + +/** + * @brief Serail flash controller wrap mode len type definition + */ +#define SF_CTRL_WRAP_LEN_8 0 /*!< SF Ctrl wrap length: 8 */ +#define SF_CTRL_WRAP_LEN_16 1 /*!< SF Ctrl wrap length: 16 */ +#define SF_CTRL_WRAP_LEN_32 2 /*!< SF Ctrl wrap length: 32 */ +#define SF_CTRL_WRAP_LEN_64 3 /*!< SF Ctrl wrap length: 64 */ +#define SF_CTRL_WRAP_LEN_128 4 /*!< SF Ctrl wrap length: 128 */ +#define SF_CTRL_WRAP_LEN_256 5 /*!< SF Ctrl wrap length: 256 */ +#define SF_CTRL_WRAP_LEN_512 6 /*!< SF Ctrl wrap length: 512 */ +#define SF_CTRL_WRAP_LEN_1024 7 /*!< SF Ctrl wrap length: 1024 */ +#define SF_CTRL_WRAP_LEN_2048 8 /*!< SF Ctrl wrap length: 2048 */ +#define SF_CTRL_WRAP_LEN_4096 9 /*!< SF Ctrl wrap length: 4096 */ + +/** + * @brief Serail flash controller memory remap type define + */ +#define SF_CTRL_ORIGINAL_MEMORY_MAP 0 /*!< Remap none, use two addr map when use dual flash */ +#define SF_CTRL_REMAP_16MB 1 /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */ +#define SF_CTRL_REMAP_8MB 2 /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */ +#define SF_CTRL_REMAP_4MB 3 /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */ + +/** + * @brief Serial flash controller select clock type definition + */ +#define SF_CTRL_OWNER_SAHB 0 /*!< System AHB bus control serial flash controller */ +#define SF_CTRL_OWNER_IAHB 1 /*!< I-Code AHB bus control serial flash controller */ + +/** + * @brief Serial flash controller select clock type definition + */ +#define SF_CTRL_SAHB_CLOCK 0 /*!< Serial flash controller select default sahb clock */ +#define SF_CTRL_FLASH_CLOCK 1 /*!< Serial flash controller select flash clock */ + +/** + * @brief Read and write type definition + */ +#define SF_CTRL_READ 0 /*!< Serail flash read command flag */ +#define SF_CTRL_WRITE 1 /*!< Serail flash write command flag */ + +/** + * @brief Serail flash interface IO type definition + */ +#define SF_CTRL_NIO_MODE 0 /*!< Normal IO mode define */ +#define SF_CTRL_DO_MODE 1 /*!< Dual Output mode define */ +#define SF_CTRL_QO_MODE 2 /*!< Quad Output mode define */ +#define SF_CTRL_DIO_MODE 3 /*!< Dual IO mode define */ +#define SF_CTRL_QIO_MODE 4 /*!< Quad IO mode define */ + +/** + * @brief Serail flash controller interface mode type definition + */ +#define SF_CTRL_SPI_MODE 0 /*!< SPI mode define */ +#define SF_CTRL_QPI_MODE 1 /*!< QPI mode define */ + +/** + * @brief Serail flash controller command mode type definition + */ +#define SF_CTRL_CMD_1_LINE 0 /*!< Command in one line mode */ +#define SF_CTRL_CMD_4_LINES 1 /*!< Command in four lines mode */ + +/** + * @brief Serail flash controller address mode type definition + */ +#define SF_CTRL_ADDR_1_LINE 0 /*!< Address in one line mode */ +#define SF_CTRL_ADDR_2_LINES 1 /*!< Address in two lines mode */ +#define SF_CTRL_ADDR_4_LINES 2 /*!< Address in four lines mode */ + +/** + * @brief Serail flash controller dummy mode type definition + */ +#define SF_CTRL_DUMMY_1_LINE 0 /*!< Dummy in one line mode */ +#define SF_CTRL_DUMMY_2_LINES 1 /*!< Dummy in two lines mode */ +#define SF_CTRL_DUMMY_4_LINES 2 /*!< Dummy in four lines mode */ + +/** + * @brief Serail flash controller data mode type definition + */ +#define SF_CTRL_DATA_1_LINE 0 /*!< Data in one line mode */ +#define SF_CTRL_DATA_2_LINES 1 /*!< Data in two lines mode */ +#define SF_CTRL_DATA_4_LINES 2 /*!< Data in four lines mode */ + +/** + * @brief Serail flash controller AES mode type definition + */ +#define SF_CTRL_AES_CTR_MODE 0 /*!< Serail flash AES CTR mode */ +#define SF_CTRL_AES_XTS_MODE 1 /*!< Serail flash AES XTS mode */ + +/** + * @brief Serail flash controller AES key len type definition + */ +#define SF_CTRL_AES_128BITS 0 /*!< Serail flash AES key 128 bits length */ +#define SF_CTRL_AES_256BITS 1 /*!< Serail flash AES key 256 bits length */ +#define SF_CTRL_AES_192BITS 2 /*!< Serail flash AES key 192 bits length */ +#define SF_CTRL_AES_128BITS_DOUBLE_KEY 3 /*!< Serail flash AES key 128 bits length double key */ + +/** + * @brief Serail flash controller configuration structure type definition + */ +struct sf_ctrl_cfg_type { + uint8_t owner; /*!< Sflash interface bus owner */ +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE + uint8_t en32b_addr; /*!< Sflash enable 32-bits address */ +#endif + uint8_t clk_delay; /*!< Clock count for read due to pad delay */ + uint8_t clk_invert; /*!< Clock invert */ + uint8_t rx_clk_invert; /*!< RX clock invert */ + uint8_t do_delay; /*!< Data out delay */ + uint8_t di_delay; /*!< Data in delay */ + uint8_t oe_delay; /*!< Output enable delay */ +}; + +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +/** + * @brief SF Ctrl bank2 controller configuration structure type definition + */ +struct sf_ctrl_bank2_cfg { + uint8_t sbus2_select; /*!< Select sbus2 as 2nd flash controller */ + uint8_t bank2_rx_clk_invert_src; /*!< Select bank2 rx clock invert source */ + uint8_t bank2_rx_clk_invert_sel; /*!< Select inveted bank2 rx clock */ + uint8_t bank2_delay_src; /*!< Select bank2 read delay source */ + uint8_t bank2_clk_delay; /*!< Bank2 read delay cycle = n + 1 */ + uint8_t do_delay; /*!< Data out delay */ + uint8_t di_delay; /*!< Data in delay */ + uint8_t oe_delay; /*!< Output enable delay */ + uint8_t remap; /*!< Select dual flash memory remap set */ + uint8_t remap_lock; /*!< Select memory remap lock */ +}; +#endif + +#ifdef BFLB_SF_CTRL_PSRAM_ENABLE +/** + * @brief SF Ctrl psram controller configuration structure type definition + */ +struct sf_ctrl_psram_cfg { + uint8_t owner; /*!< Psram interface bus owner */ + uint8_t pad_sel; /*!< SF Ctrl pad select */ + uint8_t bank_sel; /*!< SF Ctrl bank select */ + uint8_t psram_rx_clk_invert_src; /*!< Select psram rx clock invert source */ + uint8_t psram_rx_clk_invert_sel; /*!< Select inveted psram rx clock */ + uint8_t psram_delay_src; /*!< Select psram read delay source */ + uint8_t psram_clk_delay; /*!< Psram read delay cycle = n + 1 */ +} ; +#endif + +/** + * @brief SF Ctrl cmds configuration structure type definition + */ +struct sf_ctrl_cmds_cfg { + uint8_t ack_latency; /*!< SF Ctrl ack latency cycles */ + uint8_t cmds_core_en; /*!< SF Ctrl cmds core enable */ +#if defined(BL702) + uint8_t burst_toggle_en; /*!< SF Ctrl burst toggle mode enable */ +#endif + uint8_t cmds_en; /*!< SF Ctrl cmds enable */ + uint8_t cmds_wrap_mode; /*!< SF Ctrl cmds wrap mode */ + uint8_t cmds_wrap_len; /*!< SF Ctrl cmds wrap length */ +}; + +/** + * @brief Serail flash command configuration structure type definition + */ +struct sf_ctrl_cmd_cfg_type { + uint8_t rw_flag; /*!< Read write flag */ + uint8_t cmd_mode; /*!< Command mode */ + uint8_t addr_mode; /*!< Address mode */ + uint8_t addr_size; /*!< Address size */ + uint8_t dummy_clks; /*!< Dummy clocks */ + uint8_t dummy_mode; /*!< Dummy mode */ + uint8_t data_mode; /*!< Data mode */ + uint8_t rsv[1]; /*!< Reserved */ + uint32_t nb_data; /*!< Transfer number of bytes */ + uint32_t cmd_buf[2]; /*!< Command buffer */ +}; + +/*@} end of group SF_CTRL_Public_Types */ + +/** @defgroup SF_CTRL_Public_Macros + * @{ + */ +#if defined(BL602) || defined(BL702) || defined(BL702L) +#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) +#else +#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) +#endif +#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF +#define NOR_FLASH_CTRL_BUF_SIZE 256 +#define NAND_FLASH_CTRL_BUF_SIZE 512 + +#if defined(BL628) || defined(BL616) +#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO3IO0) || \ + ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS) || \ + ((type) == SF_IO_EMB_SWAP_NONE) || \ + ((type) == SF_IO_EMB_SWAP_IO2CS) || \ + ((type) == SF_IO_EXT_SF2_SWAP_IO3IO0) || \ + ((type) == SF_IO_EXT_SF3) || \ + ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0) || \ + ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0) || \ + ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0) || \ + ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) || \ + ((type) == SF_IO_EXT_SF2) || \ + ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2) || \ + ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2) || \ + ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2) || \ + ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2)) +#elif defined(BL808) || defined(BL606P) +#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \ + ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \ + ((type) == SF_IO_EMB_SWAP_NONE) || \ + ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \ + ((type) == SF_IO_EXT_SF2) || \ + ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \ + ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \ + ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \ + ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2)) +#elif defined(BL702L) +#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_EXTERNAL_FLASH) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) || \ + ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH)) +#elif defined(BL702) +#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_SF1) || \ + ((type) == SF_CTRL_SEL_SF2) || \ + ((type) == SF_CTRL_SEL_SF3) || \ + ((type) == SF_CTRL_SEL_DUAL_BANK_SF1_SF2) || \ + ((type) == SF_CTRL_SEL_DUAL_BANK_SF2_SF3) || \ + ((type) == SF_CTRL_SEL_DUAL_BANK_SF3_SF1) || \ + ((type) == SF_CTRL_SEL_DUAL_CS_SF2) || \ + ((type) == SF_CTRL_SEL_DUAL_CS_SF3)) +#elif defined(BL602) +#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \ + ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL)) +#endif + +/*@} end of group SF_CTRL_Public_Macros */ + +/** @defgroup SF_CTRL_Public_Functions + * @{ + */ +void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg); +void bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t dodelay, uint8_t didelay, uint8_t oedelay); +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +void bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2cfg); +void bflb_sf_ctrl_sbus2_hold_sram(void); +void bflb_sf_ctrl_sbus2_release_sram(void); +uint8_t sf_ctrl_is_sbus2_enable(void); +void bflb_sf_ctrl_sbus2_replace(uint8_t pad); +void bflb_sf_ctrl_sbus2_revoke_replace(void); +void bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert); +void bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock); +#endif +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE +void bflb_sf_ctrl_32bits_addr_en(uint8_t en_32bit_saddr); +#endif +#ifdef BFLB_SF_CTRL_PSRAM_ENABLE +void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg); +#endif +uint8_t bflb_sf_ctrl_get_clock_delay(void); +void bflb_sf_ctrl_set_clock_delay(uint8_t delay); +uint8_t bflb_sf_ctrl_get_wrap_queue_value(void); +void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel); +#if defined(BL702L) +void bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode); +#endif +void bflb_sf_ctrl_select_pad(uint8_t sel); +void bflb_sf_ctrl_sbus_select_bank(uint8_t bank); +void bflb_sf_ctrl_set_owner(uint8_t owner); +void bflb_sf_ctrl_disable(void); +void bflb_sf_ctrl_aes_enable_be(void); +void bflb_sf_ctrl_aes_enable_le(void); +void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwkey, + uint32_t start_addr, uint32_t end_addr, uint8_t locked); +void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type); +void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type); +void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset); +void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset); +#ifdef BFLB_SF_CTRL_AES_XTS_ENABLE +void bflb_sf_ctrl_aes_xts_set_key(uint8_t region, uint8_t *key, uint8_t key_type); +void bflb_sf_ctrl_aes_xts_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type); +void bflb_sf_ctrl_aes_xts_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset); +void bflb_sf_ctrl_aes_xts_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset); +#endif +void bflb_sf_ctrl_aes_set_mode(uint8_t mode); +void bflb_sf_ctrl_aes_enable(void); +void bflb_sf_ctrl_aes_disable(void); +uint8_t bflb_sf_ctrl_is_aes_enable(void); +void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank); +uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank); +void bflb_sf_ctrl_lock_flash_image_offset(uint8_t lock); +void bflb_sf_ctrl_select_clock(uint8_t sahb_sram_sel); +void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg); +void bflb_sf_ctrl_disable_wrap_access(uint8_t disable); +void bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +void bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); +#endif +#ifdef BFLB_SF_CTRL_PSRAM_ENABLE +void bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); +void bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid); +#endif +uint8_t bflb_sf_ctrl_get_busy_state(void); +#ifndef BFLB_USE_HAL_DRIVER +void bflb_sf_ctrl_irqhandler(void); +#endif + +/*@} end of group SF_CTRL_Public_Functions */ + +/*@} end of group SF_CTRL */ + +/*@} end of group BL628_Peripheral_Driver */ + +#endif /* __BL628_SF_CTRL_H__ */ diff --git a/drivers/lhal/src/flash/bflb_sflash.c b/drivers/lhal/src/flash/bflb_sflash.c new file mode 100644 index 00000000..a97f9de4 --- /dev/null +++ b/drivers/lhal/src/flash/bflb_sflash.c @@ -0,0 +1,2182 @@ +/** + ****************************************************************************** + * @file bflb_sflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#include "bflb_sf_ctrl.h" +#include "bflb_sflash.h" +//#include "bl628_l1c.h" + +/** @addtogroup BL628_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLASH + * @{ + */ + +/** @defgroup SFLASH_Private_Macros + * @{ + */ + +#if defined(BL602) || defined(BL702) +#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x4000B700) +#elif defined(BL702L) +#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x4000B600) +#elif defined(BL606P) || defined(BL808) || defined(BL616) +#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x2000b600) +#elif defined(BL628) +#define BFLB_SF_CTRL_BUF_BASE ((uint32_t)0x20082600) +#endif + +/*@} end of group SFLASH_Private_Macros */ + +/** @defgroup SFLASH_Private_Types + * @{ + */ + +/*@} end of group SFLASH_Private_Types */ + +/** @defgroup SFLASH_Private_Variables + * @{ + */ + +/*@} end of group SFLASH_Private_Variables */ + +/** @defgroup SFLASH_Global_Variables + * @{ + */ + +/*@} end of group SFLASH_Global_Variables */ + +/** @defgroup SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group SFLASH_Private_Fun_Declaration */ + +/** @defgroup SFLASH_Private_Functions + * @{ + */ + +/*@} end of group SFLASH_Private_Functions */ + +/** @defgroup SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Init serial flash control interface + * + * @param p_sf_ctrl_cfg: Serial flash controller configuration pointer + * @param p_bank2_cfg: Serial flash2 controller configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, + const struct sf_ctrl_bank2_cfg *p_bank2_cfg) +{ + uint8_t clk_delay = 0; + uint8_t rx_clk_invert = 0; + + if (p_bank2_cfg != NULL) { + if (p_bank2_cfg->sbus2_select) { + if (p_bank2_cfg->bank2_delay_src) { + clk_delay = p_bank2_cfg->bank2_clk_delay; + } else { + if (p_sf_ctrl_cfg != NULL) { + clk_delay = p_sf_ctrl_cfg->clk_delay; + } else { + clk_delay = 1; + } + } + + if (p_bank2_cfg->bank2_rx_clk_invert_src) { + rx_clk_invert = p_bank2_cfg->bank2_rx_clk_invert_sel; + } else { + if (p_sf_ctrl_cfg != NULL) { + rx_clk_invert = p_sf_ctrl_cfg->rx_clk_invert; + } else { + rx_clk_invert = 0; + } + } + + bflb_sf_ctrl_sbus2_set_delay(clk_delay, rx_clk_invert); + } else { + bflb_sf_ctrl_sbus2_revoke_replace(); + } + + bflb_sf_ctrl_bank2_enable(p_bank2_cfg); + } else { + bflb_sf_ctrl_sbus2_revoke_replace(); + } +#else +void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg) +{ +#endif + + if (p_sf_ctrl_cfg != NULL) { + bflb_sf_ctrl_enable(p_sf_ctrl_cfg); + } +} + +/****************************************************************************/ /** + * @brief Set serial flash control interface SPI or QPI mode + * + * @param mode: Serial flash interface mode + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_set_spi_mode(uint8_t mode) +{ + int stat = 0; + + return stat; +} + +/****************************************************************************/ /** + * @brief Read flash register + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param reg_index: register index + * @param reg_value: register value pointer to store data + * @param reg_len: register value length + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, + uint8_t *reg_value, uint8_t reg_len) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint32_t cnt = 0; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (flash_cfg->read_reg_cmd[reg_index]) << 24; + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.nb_data = reg_len; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + while (bflb_sf_ctrl_get_busy_state()) { + arch_delay_us(1); + cnt++; + + if (cnt > 1000) { + return -1; + } + } + + arch_memcpy(reg_value, flash_ctrl_buf, reg_len); + return 0; +} + +/****************************************************************************/ /** + * @brief Write flash register + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param reg_index: register index + * @param reg_value: register value pointer storing data + * @param reg_len: register value length + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, + uint8_t *reg_value, uint8_t reg_len) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint32_t cnt = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + arch_memcpy(flash_ctrl_buf, reg_value, reg_len); + + flash_cmd.cmd_buf[0] = (flash_cfg->write_reg_cmd[reg_index]) << 24; + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.nb_data = reg_len; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + /* take 40ms for tw(write status register) as default */ + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(100); + cnt++; + + if (cnt > 400) { + return -1; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Read flash register with read command + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param read_reg_cmd: read command + * @param reg_value: register value pointer to store data + * @param reg_len: register value length + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, + uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint32_t cnt = 0; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = read_reg_cmd << 24; + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.nb_data = reg_len; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + while (bflb_sf_ctrl_get_busy_state()) { + arch_delay_us(1); + cnt++; + + if (cnt > 1000) { + return -1; + } + } + + arch_memcpy(reg_value, flash_ctrl_buf, reg_len); + return 0; +} + +/****************************************************************************/ /** + * @brief Write flash register with write command + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param write_reg_cmd: write command + * @param reg_value: register value pointer storing data + * @param reg_len: register value length + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, + uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint32_t cnt = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + arch_memcpy(flash_ctrl_buf, reg_value, reg_len); + + flash_cmd.cmd_buf[0] = write_reg_cmd << 24; + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.nb_data = reg_len; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + /* take 40ms for tw(write status register) as default */ + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(100); + cnt++; + + if (cnt > 400) { + return -1; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Check flash busy status + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return 1 means busy or 0 means not busy + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_busy(spi_flash_cfg_type *flash_cfg) +{ + uint32_t stat = 0; + bflb_sflash_read_reg(flash_cfg, flash_cfg->busy_index, (uint8_t *)&stat, flash_cfg->busy_read_reg_len); + + if ((stat & (1 << flash_cfg->busy_bit)) == 0) { + return 0; + } + + return 1; +} + +/****************************************************************************/ /** + * @brief Enable flash write function + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg) +{ + uint32_t stat = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + /* Write enable*/ + flash_cmd.cmd_buf[0] = (flash_cfg->write_enable_cmd) << 24; + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + bflb_sflash_read_reg(flash_cfg, flash_cfg->wr_enable_index, (uint8_t *)&stat, flash_cfg->wr_enable_read_reg_len); + + if ((stat & (1 << flash_cfg->wr_enable_bit)) != 0) { + return 0; + } + + return -1; +} + +/****************************************************************************/ /** + * @brief Enable flash flash controller QSPI interface + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg) +{ + uint32_t stat = 0, ret = 0; + + if (flash_cfg->qe_read_reg_len == 0) { + ret = bflb_sflash_write_enable(flash_cfg); + + if (0 != ret) { + return -1; + } + + bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len); + return 0; + } + + bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len); + + if (flash_cfg->qe_data == 0) { + if ((stat & (1 << flash_cfg->qe_bit)) != 0) { + return 0; + } + } else { + if (((stat >> (flash_cfg->qe_bit & 0x08)) & 0xff) == flash_cfg->qe_data) { + return 0; + } + } + + if (flash_cfg->qe_write_reg_len != 1) { + /* This is read r0,read r1 write r0,r1 case*/ + bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1); + bflb_sflash_read_reg(flash_cfg, 1, ((uint8_t *)&stat) + 1, 1); + + if (flash_cfg->qe_data == 0) { + stat |= (1 << (flash_cfg->qe_bit + 8 * flash_cfg->qe_index)); + } else { + stat = stat & (~(0xff << (8 * flash_cfg->qe_index))); + stat |= (flash_cfg->qe_data << (8 * flash_cfg->qe_index)); + } + } else { + if (flash_cfg->qe_data == 0) { + stat |= (1 << (flash_cfg->qe_bit % 8)); + } else { + stat = flash_cfg->qe_data; + } + } + + ret = bflb_sflash_write_enable(flash_cfg); + + if (0 != ret) { + return -1; + } + + bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len); + bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len); + + if (flash_cfg->qe_data == 0) { + if ((stat & (1 << flash_cfg->qe_bit)) != 0) { + return 0; + } + } else { + if (((stat >> (flash_cfg->qe_bit & 0x08)) & 0xff) == flash_cfg->qe_data) { + return 0; + } + } + + return -1; +} + +/****************************************************************************/ /** + * @brief Disable flash flash controller QSPI interface + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg) +{ + uint32_t stat = 0, ret = 0; + + if (flash_cfg->qe_read_reg_len == 0) { + ret = bflb_sflash_write_enable(flash_cfg); + + if (0 != ret) { + return -1; + } + + bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len); + return 0; + } + + bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len); + + if ((stat & (1 << flash_cfg->qe_bit)) == 0) { + return 0; + } + + if (flash_cfg->qe_write_reg_len != 1) { + /* This is read r0,read r1 write r0,r1 case*/ + bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1); + bflb_sflash_read_reg(flash_cfg, 1, ((uint8_t *)&stat) + 1, 1); + stat &= (~(1 << (flash_cfg->qe_bit + 8 * flash_cfg->qe_index))); + } else { + stat &= (~(1 << (flash_cfg->qe_bit % 8))); + } + + ret = bflb_sflash_write_enable(flash_cfg); + + if (0 != ret) { + return -1; + } + + bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len); + bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len); + + if ((stat & (1 << flash_cfg->qe_bit)) == 0) { + return 0; + } + + return -1; +} + +/****************************************************************************/ /** + * @brief Enable flash volatile register write enable + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg) +{ + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (flash_cfg->write_vreg_enable_cmd) << 24; + flash_cmd.rw_flag = SF_CTRL_WRITE; + + bflb_sf_ctrl_sendcmd(&flash_cmd); +} + +/****************************************************************************/ /** + * @brief Erase flash whole chip + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg) +{ + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint32_t cnt = 0; + uint32_t timeout = 0; + int stat = bflb_sflash_write_enable(flash_cfg); + + if (stat != 0) { + return stat; + } + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (flash_cfg->chip_erase_cmd) << 24; + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = flash_cfg->time_ce; + + if ((timeout >> 15) > 0) { + timeout = (timeout & 0x7FFF) * 1000; + } + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(500); + cnt++; + + if (cnt > timeout * 3) { + return -1; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Erase flash one sector + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param sector_num: flash sector number + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num) +{ + uint32_t cnt = 0; + uint8_t is_32bits_addr = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + int stat = bflb_sflash_write_enable(flash_cfg); + + if (stat != 0) { + return stat; + } + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + is_32bits_addr = (flash_cfg->io_mode & 0x20); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + + if (is_32bits_addr > 0) { + flash_cmd.addr_size++; + flash_cmd.cmd_buf[0] = (flash_cfg->sector_erase_cmd << 24) | ((flash_cfg->sector_size * 1024 * sector_num) >> 8); + flash_cmd.cmd_buf[1] = ((flash_cfg->sector_size * 1024 * sector_num) << 24); + } else { + flash_cmd.cmd_buf[0] = (flash_cfg->sector_erase_cmd << 24) | (flash_cfg->sector_size * 1024 * sector_num); + } + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(500); + cnt++; + + if (cnt > flash_cfg->time_e_sector * 3) { + return -1; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Erase flash one 32K block + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param blk_num: flash 32K block number + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num) +{ + uint32_t cnt = 0; + uint8_t is_32bits_addr = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + int stat = bflb_sflash_write_enable(flash_cfg); + + if (stat != 0) { + return stat; + } + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + is_32bits_addr = (flash_cfg->io_mode & 0x20); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + + if (is_32bits_addr > 0) { + flash_cmd.addr_size++; + flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) >> 8); + flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) << 24); + } else { + flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blk_num); + } + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(500); + cnt++; + + if (cnt > flash_cfg->time_e_32k * 3) { + return -1; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Erase flash one 64K block + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param blk_num: flash 64K block number + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num) +{ + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint32_t cnt = 0; + uint8_t is_32bits_addr = 0; + int stat = bflb_sflash_write_enable(flash_cfg); + + if (stat != 0) { + return stat; + } + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + is_32bits_addr = (flash_cfg->io_mode & 0x20); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + + if (is_32bits_addr > 0) { + flash_cmd.addr_size++; + flash_cmd.cmd_buf[0] = (flash_cfg->blk64_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blk_num) >> 8); + flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blk_num) << 24); + } else { + flash_cmd.cmd_buf[0] = (flash_cfg->blk64_erase_cmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blk_num); + } + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(500); + cnt++; + + if (cnt > flash_cfg->time_e_64k * 3) { + return -1; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Erase flash one region + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param start_addr: start address to erase + * @param end_addr: end address(include this address) to erase + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr) +{ + uint32_t len = 0; + uint32_t erase_len = 0; + uint8_t ret = 0; + + if (start_addr > end_addr) { + return -1; + } + + while (start_addr <= end_addr) { + len = end_addr - start_addr + 1; + + if (flash_cfg->blk64_erase_cmd != BFLB_SPIFLASH_CMD_INVALID && + (start_addr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK64K_SIZE - flash_cfg->sector_size * 1024)) { + /* 64K margin address,and length > 64K-sector size, erase one first */ + ret = bflb_sflash_blk64_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK64K_SIZE); + erase_len = BFLB_SPIFLASH_BLK64K_SIZE; + } else if (flash_cfg->blk32_erase_cmd != BFLB_SPIFLASH_CMD_INVALID && + (start_addr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK32K_SIZE - flash_cfg->sector_size * 1024)) { + /* 32K margin address,and length > 32K-sector size, erase one first */ + ret = bflb_sflash_blk32_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK32K_SIZE); + erase_len = BFLB_SPIFLASH_BLK32K_SIZE; + } else { + /* Sector erase */ + start_addr = ((start_addr) & (~(flash_cfg->sector_size * 1024 - 1))); + ret = bflb_sflash_sector_erase(flash_cfg, start_addr / flash_cfg->sector_size / 1024); + erase_len = flash_cfg->sector_size * 1024; + } + + start_addr += erase_len; + + if (ret != 0) { + return -1; + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Get flash unique ID + * + * @param data: data pointer to store read data + * @param id_len: unique ID len + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint8_t cmd = 0, dummy_clks = 0; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + dummy_clks = 4; + cmd = 0x4B; + flash_cmd.cmd_buf[0] = (cmd << 24); + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.dummy_clks = dummy_clks; + flash_cmd.nb_data = id_len; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return; + } + } + + arch_memcpy(data, flash_ctrl_buf, id_len); +} + +/****************************************************************************/ /** + * @brief Get flash jedec ID + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param data: data pointer to store read data + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint8_t cmd = 0, dummy_clks = 0; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + dummy_clks = flash_cfg->jedec_id_cmd_dmy_clk; + cmd = flash_cfg->jedec_id_cmd; + flash_cmd.cmd_buf[0] = (cmd << 24); + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.dummy_clks = dummy_clks; + flash_cmd.nb_data = 3; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return; + } + } + + arch_memcpy(data, flash_ctrl_buf, 3); +} + +/****************************************************************************/ /** + * @brief Get flash device ID + * + * @param data: data pointer to store read data + * @param is_32bits_addr: Is flash addr mode in 32-bits + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint8_t cmd = 0, dummy_clks = 0; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint32_t addr = 0x00000001; + uint8_t read_mode = 0xFF; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + flash_cmd.data_mode = SF_CTRL_DATA_4_LINES; + dummy_clks = 2; + cmd = 0x94; + flash_cmd.addr_size = 4; + + if (is_32bits_addr) { + flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8); + flash_cmd.cmd_buf[1] = (addr << 24) | (read_mode << 16); + flash_cmd.addr_size++; + } else { + flash_cmd.cmd_buf[0] = (cmd << 24) | (addr); + flash_cmd.cmd_buf[1] = (read_mode << 24); + } + + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.dummy_clks = dummy_clks; + flash_cmd.nb_data = 2; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return; + } + } + + arch_memcpy(data, flash_ctrl_buf, 2); +} + +/****************************************************************************/ /** + * @brief Set flash power down + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_powerdown(void) +{ + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint8_t cmd = 0; + uint32_t timeout = 0; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + cmd = 0xB9; + flash_cmd.cmd_buf[0] = (cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return; + } + } +} + +/****************************************************************************/ /** + * @brief Release flash power down for wake up + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg) +{ + uint8_t cmd = 0; + uint32_t timeout = 0; + + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + cmd = flash_cfg->release_powerdown; + flash_cmd.cmd_buf[0] = (cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return; + } + } +} + +/****************************************************************************/ /** + * @brief Sflash restore from power down + * + * @param flash_cfg: Flash configuration pointer + * @param flash_cont_read: Whether enable continuous read + * @param bank: bank select type + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, + uint8_t flash_cont_read, uint8_t bank) +{ + int stat = 0; + uint32_t jedecid = 0; + uint8_t tmp[8]; + uint8_t io_mode = flash_cfg->io_mode & 0xf; + + /* Wake flash up from power down */ + bflb_sflash_release_powerdown(flash_cfg); + arch_delay_us(120); + + bflb_sflash_get_jedecid(flash_cfg, (uint8_t *)&jedecid); + + if (SF_CTRL_QO_MODE == io_mode || SF_CTRL_QIO_MODE == io_mode) { + bflb_sflash_qspi_enable(flash_cfg); + } + + if (((flash_cfg->io_mode >> 4) & 0x01) == 1) { + /* unwrap */ + //L1C_Set_Wrap(0); + } else { + /* burst wrap */ + //L1C_Set_Wrap(1); + /* For command that is setting register instead of send command, we need write enable */ + bflb_sflash_write_enable(flash_cfg); + bflb_sflash_set_burst_wrap(flash_cfg); + } + + if (flash_cont_read) { + stat = bflb_sflash_read(flash_cfg, io_mode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, 1, 0, 32, bank); + } else { + stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, 0, 0, 32, bank); + } + + return stat; +} + +/****************************************************************************/ /** + * @brief Set flash burst wrap config + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint8_t cmd = 0, dummy_clks = 0; + uint32_t wrap_data = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((flash_cfg->io_mode >> 4) & 0x01) == 1) { + /* Disable burst wrap ,just return */ + return; + } + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.addr_mode = flash_cfg->burst_wrap_data_mode; + flash_cmd.data_mode = flash_cfg->burst_wrap_data_mode; + dummy_clks = flash_cfg->burst_wrap_cmd_dmy_clk; + cmd = flash_cfg->burst_wrap_cmd; + wrap_data = flash_cfg->burst_wrap_data; + arch_memcpy4((uint32_t *)flash_ctrl_buf, &wrap_data, 4); + flash_cmd.cmd_buf[0] = (cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.dummy_clks = dummy_clks; + flash_cmd.nb_data = 1; + + bflb_sf_ctrl_sendcmd(&flash_cmd); +} + +/****************************************************************************/ /** + * @brief Disable flash burst wrap config + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint8_t cmd = 0, dummy_clks = 0; + uint32_t wrap_data = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.addr_mode = flash_cfg->de_burst_wrap_data_mode; + flash_cmd.data_mode = flash_cfg->de_burst_wrap_data_mode; + dummy_clks = flash_cfg->de_burst_wrap_cmd_dmy_clk; + cmd = flash_cfg->de_burst_wrap_cmd; + wrap_data = flash_cfg->de_burst_wrap_data; + arch_memcpy4((uint32_t *)flash_ctrl_buf, &wrap_data, 4); + flash_cmd.cmd_buf[0] = (cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.dummy_clks = dummy_clks; + flash_cmd.nb_data = 1; + + bflb_sf_ctrl_sendcmd(&flash_cmd); +} + +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE +/****************************************************************************/ /** + * @brief Set flash 24-bits or 32-bits addr mode + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param en_32bits_addr: Serial flash enable or disable 32-bits addr + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, + uint8_t en_32bits_addr) +{ + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint8_t cmd = 0; + + if ((flash_cfg->io_mode & 0x20) == 0) { + return -1; + } + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + bflb_sf_ctrl_32bits_addr_en(en_32bits_addr); + + if (en_32bits_addr) { + cmd = flash_cfg->enter_32bits_addr_cmd; + } else { + cmd = flash_cfg->exit_32bits_addr_cmd; + } + + flash_cmd.cmd_buf[0] = (cmd << 24); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + return 0; +} +#endif + +/****************************************************************************/ /** + * @brief Software reset flash + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg) +{ + uint16_t cnt = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + /* Reset enable */ + flash_cmd.cmd_buf[0] = (flash_cfg->reset_en_cmd) << 24; + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + + /* Wait for write done */ + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(100); + cnt++; + + if (cnt > 20) { + return -1; + } + } + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + /* Reset */ + flash_cmd.cmd_buf[0] = (flash_cfg->reset_cmd) << 24; + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + arch_delay_us(50); + + return 0; +} + +/****************************************************************************/ /** + * @brief Reset flash continous read mode + * + * @param flash_cfg: Serial flash parameter configuration pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg) +{ + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + /* Reset continous read */ + arch_memset(&flash_cmd.cmd_buf[0], flash_cfg->reset_c_read_cmd, 4); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = flash_cfg->reset_c_read_cmd_size; + bflb_sf_ctrl_sendcmd(&flash_cmd); +} + +/****************************************************************************/ /** + * @brief Set xip read flash configuration in flash controller + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param io_mode: flash controller interface mode + * @param cont_read: Wether enable cont read mode + * @param addr: address to read/write + * @param len: data length to read/write + * @param bank: bank select type + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, + uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank) +{ + uint8_t cmd = 0, dummy_clks = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint8_t cmd_valid = 1; + uint8_t no_read_mode_cfg = 0; + uint8_t c_read_support = 0; + uint8_t is_32bits_addr = 0; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB); + + if (SF_CTRL_NIO_MODE == io_mode) { + cmd = flash_cfg->fast_read_cmd; + dummy_clks = flash_cfg->fr_dmy_clk; + } else if (SF_CTRL_DO_MODE == io_mode) { + flash_cmd.data_mode = SF_CTRL_DATA_2_LINES; + cmd = flash_cfg->fast_read_do_cmd; + dummy_clks = flash_cfg->fr_do_dmy_clk; + } else if (SF_CTRL_DIO_MODE == io_mode) { + flash_cmd.addr_mode = SF_CTRL_ADDR_2_LINES; + flash_cmd.data_mode = SF_CTRL_DATA_2_LINES; + cmd = flash_cfg->fast_read_dio_cmd; + dummy_clks = flash_cfg->fr_dio_dmy_clk; + } else if (SF_CTRL_QO_MODE == io_mode) { + flash_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = flash_cfg->fast_read_qo_cmd; + dummy_clks = flash_cfg->fr_qo_dmy_clk; + } else if (SF_CTRL_QIO_MODE == io_mode) { + flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + flash_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = flash_cfg->fast_read_qio_cmd; + dummy_clks = flash_cfg->fr_qio_dmy_clk; + } else { + return -1; + } + + is_32bits_addr = (flash_cfg->io_mode & 0x20); + /*prepare command**/ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + + if (is_32bits_addr > 0) { + flash_cmd.addr_size++; + flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8); + flash_cmd.cmd_buf[1] = (addr << 24); + } else { + flash_cmd.cmd_buf[0] = (cmd << 24) | addr; + } + + if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) { + no_read_mode_cfg = flash_cfg->c_read_support & 0x02; + c_read_support = flash_cfg->c_read_support & 0x01; + + if (no_read_mode_cfg == 0) { + /* Read mode must be set*/ + if (c_read_support == 0) { + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16); + } else { + flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24); + } + } else { + /* Flash support cont read, setting depend on user parameter */ + if (cont_read) { + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[0] = addr; + flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24); + } else { + flash_cmd.cmd_buf[0] = (addr << 8) | flash_cfg->c_read_mode; + } + + cmd_valid = 0; + } else { + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[1] |= ((!flash_cfg->c_read_mode) << 16); + } else { + flash_cmd.cmd_buf[1] = ((!flash_cfg->c_read_mode) << 24); + } + } + } + + flash_cmd.addr_size++; + } + } + + flash_cmd.dummy_clks = dummy_clks; + flash_cmd.nb_data = len; +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE + if (bank == SF_CTRL_FLASH_BANK0) { + bflb_sf_ctrl_xip_set(&flash_cmd, cmd_valid); + } else { + bflb_sf_ctrl_xip2_set(&flash_cmd, cmd_valid); + } +#else + bflb_sf_ctrl_xip_set(&flash_cmd, cmd_valid); +#endif + + return 0; +} + +/****************************************************************************/ /** + * @brief Enable xip read from flash + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param io_mode: flash controller interface mode + * @param cont_read: Wether enable cont read mode + * @param bank: bank select type + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg, + uint8_t io_mode, uint8_t cont_read, uint8_t bank) +{ + int stat = 0; + + stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, cont_read, 0, 32, bank); + if (0 != stat) { + return stat; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Disable read from flash with xip + * + * @param None + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_sflash_xip_read_disable(void) +{ + +} + +/****************************************************************************/ /** + * @brief Sflash enable RCV mode to recovery for erase while power drop + * + * @param flash_cfg: Flash configuration pointer + * @param r_cmd: Read RCV register cmd + * @param w_cmd: Write RCV register cmd + * @param bit_pos: RCV register bit pos + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, + uint8_t w_cmd, uint8_t bit_pos) +{ + int stat = 0; + uint32_t cnt = 0; + uint32_t temp_val = 0; + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(500); + cnt++; + + if (cnt > 20000 * 3) { + return -1; + } + } + + stat = bflb_sflash_read_reg_with_cmd(flash_cfg, r_cmd, (uint8_t *)&temp_val, 1); + if (0 != stat) { + stat = -1; + } + + if (((temp_val >> bit_pos) & 0x01) > 0) { + return 0; + } + + temp_val |= (uint32_t)(1 << bit_pos); + stat = bflb_sflash_write_enable(flash_cfg); + if (0 != stat) { + stat = -1; + } + + stat = bflb_sflash_write_reg_with_cmd(flash_cfg, w_cmd, (uint8_t *)&temp_val, 1); + if (0 != stat) { + return stat; + } + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(500); + cnt++; + + if (cnt > 20000 * 3) { + return -1; + } + } + + stat = bflb_sflash_read_reg_with_cmd(flash_cfg, r_cmd, (uint8_t *)&temp_val, 1); + if (0 != stat) { + stat = -1; + } + + if (((temp_val >> bit_pos) & 0x01) <= 0) { + return -1; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Erase flash security register one block + * + * @param flash_cfg: Flash configuration pointer + * @param p_sec_reg_cfg: Security register configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, + struct sflash_sec_reg_cfg *p_sec_reg_cfg) +{ + int stat = 0; + uint32_t cnt = 0; + uint8_t cmd = 0; + uint8_t sec_opt_mode = 0; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) { + sec_opt_mode = 1; + + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + } + + stat = bflb_sflash_write_enable(flash_cfg); + if (stat != 0) { + return stat; + } + + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + cmd = p_sec_reg_cfg->erase_cmd; + flash_cmd.cmd_buf[0] = (cmd << 24) | (p_sec_reg_cfg->block_num << 12); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(500); + cnt++; + + if (cnt > flash_cfg->time_e_sector * 3) { + return -1; + } + } + + if (sec_opt_mode > 0) { + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Program flash security register one block + * + * @param flash_cfg: Flash configuration pointer + * @param p_sec_reg_cfg: Security register configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, + struct sflash_sec_reg_cfg *p_sec_reg_cfg) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint32_t i = 0, cur_len = 0; + uint32_t cnt = 0; + int stat = 0; + uint8_t cmd = 0; + uint8_t sec_opt_mode = 0; + uint8_t *data = p_sec_reg_cfg->data; + uint32_t addr = p_sec_reg_cfg->addr; + uint32_t len = p_sec_reg_cfg->len; + uint32_t current_addr = 0; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) { + sec_opt_mode = 1; + + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + } + + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + /* Prepare command */ + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.addr_size = 3; + cmd = p_sec_reg_cfg->program_cmd; + + for (i = 0; i < len;) { + /* Write enable is needed for every program */ + stat = bflb_sflash_write_enable(flash_cfg); + + if (stat != 0) { + return stat; + } + + /* Get current programmed length within page size */ + cur_len = 256 - addr % 256; + + if (cur_len > len - i) { + cur_len = len - i; + } + + current_addr = (p_sec_reg_cfg->block_num << 12) | addr; + + /* Prepare command */ + arch_memcpy_fast(flash_ctrl_buf, data, cur_len); + flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr); + flash_cmd.nb_data = cur_len; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + /* Adjust address and programmed length */ + addr += cur_len; + i += cur_len; + data += cur_len; + + /* Wait for write done */ + cnt = 0; + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(100); + cnt++; + + if (cnt > flash_cfg->time_page_pgm * 20) { + return -1; + } + } + } + + if (sec_opt_mode > 0) { + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Read data from flash security register one block + * + * @param p_sec_reg_cfg: Security register configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint32_t cur_len = 0, i = 0; + uint8_t cmd = 0; + uint8_t sec_opt_mode = 0; + uint8_t *data = p_sec_reg_cfg->data; + uint32_t addr = p_sec_reg_cfg->addr; + uint32_t len = p_sec_reg_cfg->len; + uint32_t current_addr = 0; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) { + sec_opt_mode = 1; + + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + } + + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + /* Prepare command */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + flash_cmd.dummy_clks = 1; + cmd = p_sec_reg_cfg->read_cmd; + + /* Read data */ + for (i = 0; i < len;) { + current_addr = (p_sec_reg_cfg->block_num << 12) | addr; + /* Prepare command */ + flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr); + cur_len = len - i; + + if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) { + cur_len = NOR_FLASH_CTRL_BUF_SIZE; + flash_cmd.nb_data = cur_len; + } else { + /* Make sf_ctrl word read */ + flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2; + } + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + arch_memcpy_fast(data, flash_ctrl_buf, cur_len); + + addr += cur_len; + i += cur_len; + data += cur_len; + } + + if (sec_opt_mode > 0) { + if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + } + + return 0; +} + +/****************************************************************************//** + * @brief Clear flash status register + * + * @param flash_cfg: Flash configuration pointer + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg) +{ + uint32_t ret = 0; + uint32_t qe_value = 0; + uint32_t reg_value = 0; + uint32_t read_value = 0; + uint8_t read_reg_value0 = 0; + uint8_t read_reg_value1 = 0; + + if ((flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE) { + qe_value = 1; + } + + bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&read_reg_value0, 1); + bflb_sflash_read_reg(flash_cfg, 1, (uint8_t *)&read_reg_value1, 1); + read_value = (read_reg_value0|(read_reg_value1<<8)); + if ((read_value & (~((1<<(flash_cfg->qe_index*8+flash_cfg->qe_bit)) | + (1<<(flash_cfg->busy_index*8+flash_cfg->busy_bit)) | + (1<<(flash_cfg->wr_enable_index*8+flash_cfg->wr_enable_bit))))) == 0) { + return 0; + } + + ret = bflb_sflash_write_enable(flash_cfg); + if (0 != ret) { + return ret; + } + if (flash_cfg->qe_write_reg_len == 2) { + reg_value = (qe_value<<(flash_cfg->qe_index*8+flash_cfg->qe_bit)); + bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 2); + } else { + if (flash_cfg->qe_index == 0) { + reg_value = (qe_value<qe_bit); + } else { + reg_value = 0; + } + bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 1); + ret = bflb_sflash_write_enable(flash_cfg); + if (0 != ret) { + return ret; + } + if (flash_cfg->qe_index == 1) { + reg_value = (qe_value<qe_bit); + } else { + reg_value = 0; + } + bflb_sflash_write_reg(flash_cfg, 1, (uint8_t *)®_value, 1); + } + return 0; +} + +/****************************************************************************/ /** + * @brief Read data from flash + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param io_mode: flash controller interface mode + * @param cont_read: Wether enable cont read mode + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, + uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint32_t cur_len = 0, i = 0; + uint8_t cmd = 0, dummy_clks = 0; + uint32_t timeout = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + uint8_t no_read_mode_cfg = 0; + uint8_t c_read_support = 0; + uint8_t is_32bits_addr = 0; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + if (SF_CTRL_NIO_MODE == io_mode) { + cmd = flash_cfg->fast_read_cmd; + dummy_clks = flash_cfg->fr_dmy_clk; + } else if (SF_CTRL_DO_MODE == io_mode) { + flash_cmd.data_mode = SF_CTRL_DATA_2_LINES; + cmd = flash_cfg->fast_read_do_cmd; + dummy_clks = flash_cfg->fr_do_dmy_clk; + } else if (SF_CTRL_DIO_MODE == io_mode) { + flash_cmd.addr_mode = SF_CTRL_ADDR_2_LINES; + flash_cmd.data_mode = SF_CTRL_DATA_2_LINES; + cmd = flash_cfg->fast_read_dio_cmd; + dummy_clks = flash_cfg->fr_dio_dmy_clk; + } else if (SF_CTRL_QO_MODE == io_mode) { + flash_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = flash_cfg->fast_read_qo_cmd; + dummy_clks = flash_cfg->fr_qo_dmy_clk; + } else if (SF_CTRL_QIO_MODE == io_mode) { + flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES; + flash_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = flash_cfg->fast_read_qio_cmd; + dummy_clks = flash_cfg->fr_qio_dmy_clk; + } else { + return -1; + } + + is_32bits_addr = (flash_cfg->io_mode & 0x20); + /* Prepare command */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + + if (is_32bits_addr > 0) { + flash_cmd.addr_size++; + } + + if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) { + no_read_mode_cfg = flash_cfg->c_read_support & 0x02; + c_read_support = flash_cfg->c_read_support & 0x01; + + if (no_read_mode_cfg == 0) { + /* Read mode must be set*/ + if (c_read_support == 0) { + /* Not support cont read,but we still need set read mode(winbond 80dv)*/ + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16); + } else { + flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24); + } + } else { + /* Flash support cont read, setting depend on user parameter */ + if (cont_read) { + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16); + } else { + flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24); + } + } else { + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[1] |= ((!flash_cfg->c_read_mode) << 16); + } else { + flash_cmd.cmd_buf[1] = ((!flash_cfg->c_read_mode) << 24); + } + } + } + + flash_cmd.addr_size++; + } + } + + flash_cmd.dummy_clks = dummy_clks; + + /* Read data */ + for (i = 0; i < len;) { + /* Prepare command */ + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8); + flash_cmd.cmd_buf[1] |= (addr << 24); + } else { + flash_cmd.cmd_buf[0] = (cmd << 24) | (addr); + } + + cur_len = len - i; + + if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) { + cur_len = NOR_FLASH_CTRL_BUF_SIZE; + flash_cmd.nb_data = cur_len; + } else { + /* Make sf_ctrl word read */ + flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2; + } + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + timeout = SF_CTRL_BUSY_STATE_TIMEOUT; + + while (bflb_sf_ctrl_get_busy_state()) { + timeout--; + + if (timeout == 0) { + return -2; + } + } + + arch_memcpy_fast(data, flash_ctrl_buf, cur_len); + + addr += cur_len; + i += cur_len; + data += cur_len; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief Program flash one region + * + * @param flash_cfg: Serial flash parameter configuration pointer + * @param io_mode: progran mode:SPI mode or QPI mode + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, + uint32_t addr, uint8_t *data, uint32_t len) +{ + uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE; + uint32_t i = 0, cur_len = 0; + uint32_t cnt = 0; + int stat = 0; + uint8_t is_32bits_addr = 0; + uint8_t cmd = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + + if (((uintptr_t)&flash_cmd) % 4 == 0) { + arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); + } else { + arch_memset(&flash_cmd, 0, sizeof(flash_cmd)); + } + + if (SF_CTRL_NIO_MODE == io_mode || SF_CTRL_DO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) { + cmd = flash_cfg->page_program_cmd; + } else if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_QO_MODE == io_mode) { + flash_cmd.addr_mode = flash_cfg->qpp_addr_mode; + flash_cmd.data_mode = SF_CTRL_DATA_4_LINES; + cmd = flash_cfg->qpage_program_cmd; + } else { + return -1; + } + + is_32bits_addr = (flash_cfg->io_mode & 0x20); + /* Prepare command */ + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.addr_size = 3; + + if (is_32bits_addr > 0) { + flash_cmd.addr_size++; + } + + for (i = 0; i < len;) { + /* Write enable is needed for every program */ + stat = bflb_sflash_write_enable(flash_cfg); + + if (stat != 0) { + return stat; + } + + /* Get current programmed length within page size */ + cur_len = flash_cfg->page_size - addr % flash_cfg->page_size; + + if (cur_len > len - i) { + cur_len = len - i; + } + + /* Prepare command */ + arch_memcpy_fast(flash_ctrl_buf, data, cur_len); + + if (is_32bits_addr > 0) { + flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8); + flash_cmd.cmd_buf[1] = (addr << 24); + } else { + flash_cmd.cmd_buf[0] = (cmd << 24) | (addr); + } + + flash_cmd.nb_data = cur_len; + + bflb_sf_ctrl_sendcmd(&flash_cmd); + + /* Adjust address and programmed length */ + addr += cur_len; + i += cur_len; + data += cur_len; + + /* Wait for write done */ + cnt = 0; + + while (bflb_sflash_busy(flash_cfg)) { + arch_delay_us(100); + cnt++; + + if (cnt > flash_cfg->time_page_pgm * 20) { + return -1; + } + } + } + + return 0; +} + +/*@} end of group SFLASH_Public_Functions */ + +/*@} end of group SFLASH */ + +/*@} end of group BL628_Peripheral_Driver */ diff --git a/drivers/lhal/src/flash/bflb_sflash.h b/drivers/lhal/src/flash/bflb_sflash.h new file mode 100644 index 00000000..339f3790 --- /dev/null +++ b/drivers/lhal/src/flash/bflb_sflash.h @@ -0,0 +1,226 @@ +/** + ****************************************************************************** + * @file bl628_sflah.h + * @version V1.0 + * @date + * @brief This file is the standard driver header file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __BL628_SFLAH_H__ +#define __BL628_SFLAH_H__ + +#include "bflb_sf_ctrl.h" + +/** @addtogroup BL628_Peripheral_Driver + * @{ + */ + +/** @addtogroup SFLAH + * @{ + */ + +/** @defgroup SFLAH_Public_Types + * @{ + */ + +/** + * @brief Serial flash configuration structure type definition + */ +typedef struct +{ + uint8_t io_mode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */ + uint8_t c_read_support; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ + uint8_t clk_delay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ + uint8_t clk_invert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ + uint8_t reset_en_cmd; /*!< Flash enable reset command */ + uint8_t reset_cmd; /*!< Flash reset command */ + uint8_t reset_c_read_cmd; /*!< Flash reset continuous read command */ + uint8_t reset_c_read_cmd_size; /*!< Flash reset continuous read command size */ + uint8_t jedec_id_cmd; /*!< JEDEC ID command */ + uint8_t jedec_id_cmd_dmy_clk; /*!< JEDEC ID command dummy clock */ +#if defined(BL702L) || defined(BL702) || defined(BL602) + uint8_t qpi_jedec_id_cmd; /*!< QPI JEDEC ID comamnd */ + uint8_t qpi_jedec_id_cmd_dmy_clk; /*!< QPI JEDEC ID command dummy clock */ +#else + uint8_t enter_32bits_addr_cmd; /*!< Enter 32-bits addr command */ + uint8_t exit_32bits_addr_cmd; /*!< Exit 32-bits addr command */ +#endif + uint8_t sector_size; /*!< *1024bytes */ + uint8_t mid; /*!< Manufacturer ID */ + uint16_t page_size; /*!< Page size */ + uint8_t chip_erase_cmd; /*!< Chip erase cmd */ + uint8_t sector_erase_cmd; /*!< Sector erase command */ + uint8_t blk32_erase_cmd; /*!< Block 32K erase command,some Micron not support */ + uint8_t blk64_erase_cmd; /*!< Block 64K erase command */ + uint8_t write_enable_cmd; /*!< Need before every erase or program */ + uint8_t page_program_cmd; /*!< Page program cmd */ + uint8_t qpage_program_cmd; /*!< QIO page program cmd */ + uint8_t qpp_addr_mode; /*!< QIO page program address mode */ + uint8_t fast_read_cmd; /*!< Fast read command */ + uint8_t fr_dmy_clk; /*!< Fast read command dummy clock */ + uint8_t qpi_fast_read_cmd; /*!< QPI fast read command */ + uint8_t qpi_fr_dmy_clk; /*!< QPI fast read command dummy clock */ + uint8_t fast_read_do_cmd; /*!< Fast read dual output command */ + uint8_t fr_do_dmy_clk; /*!< Fast read dual output command dummy clock */ + uint8_t fast_read_dio_cmd; /*!< Fast read dual io comamnd */ + uint8_t fr_dio_dmy_clk; /*!< Fast read dual io command dummy clock */ + uint8_t fast_read_qo_cmd; /*!< Fast read quad output comamnd */ + uint8_t fr_qo_dmy_clk; /*!< Fast read quad output comamnd dummy clock */ + uint8_t fast_read_qio_cmd; /*!< Fast read quad io comamnd */ + uint8_t fr_qio_dmy_clk; /*!< Fast read quad io comamnd dummy clock */ + uint8_t qpi_fast_read_qio_cmd; /*!< QPI fast read quad io comamnd */ + uint8_t qpi_fr_qio_dmy_clk; /*!< QPI fast read QIO dummy clock */ + uint8_t qpi_page_program_cmd; /*!< QPI program command */ + uint8_t write_vreg_enable_cmd; /*!< Enable write reg */ + uint8_t wr_enable_index; /*!< Write enable register index */ + uint8_t qe_index; /*!< Quad mode enable register index */ + uint8_t busy_index; /*!< Busy status register index */ + uint8_t wr_enable_bit; /*!< Write enable bit pos */ + uint8_t qe_bit; /*!< Quad enable bit pos */ + uint8_t busy_bit; /*!< Busy status bit pos */ + uint8_t wr_enable_write_reg_len; /*!< Register length of write enable */ + uint8_t wr_enable_read_reg_len; /*!< Register length of write enable status */ + uint8_t qe_write_reg_len; /*!< Register length of contain quad enable */ + uint8_t qe_read_reg_len; /*!< Register length of contain quad enable status */ + uint8_t release_powerdown; /*!< Release power down command */ + uint8_t busy_read_reg_len; /*!< Register length of contain busy status */ + uint8_t read_reg_cmd[4]; /*!< Read register command buffer */ + uint8_t write_reg_cmd[4]; /*!< Write register command buffer */ + uint8_t enter_qpi; /*!< Enter qpi command */ + uint8_t exit_qpi; /*!< Exit qpi command */ + uint8_t c_read_mode; /*!< Config data for continuous read mode */ + uint8_t c_rexit; /*!< Config data for exit continuous read mode */ + uint8_t burst_wrap_cmd; /*!< Enable burst wrap command */ + uint8_t burst_wrap_cmd_dmy_clk; /*!< Enable burst wrap command dummy clock */ + uint8_t burst_wrap_data_mode; /*!< Data and address mode for this command */ + uint8_t burst_wrap_data; /*!< Data to enable burst wrap */ + uint8_t de_burst_wrap_cmd; /*!< Disable burst wrap command */ + uint8_t de_burst_wrap_cmd_dmy_clk; /*!< Disable burst wrap command dummy clock */ + uint8_t de_burst_wrap_data_mode; /*!< Data and address mode for this command */ + uint8_t de_burst_wrap_data; /*!< Data to disable burst wrap */ + uint16_t time_e_sector; /*!< 4K erase time */ + uint16_t time_e_32k; /*!< 32K erase time */ + uint16_t time_e_64k; /*!< 64K erase time */ + uint16_t time_page_pgm; /*!< Page program time */ + uint16_t time_ce; /*!< Chip erase time in ms */ + uint8_t pd_delay; /*!< Release power down command delay time for wake up */ + uint8_t qe_data; /*!< QE set data */ +} __attribute__((packed)) spi_flash_cfg_type; + +/** + * @brief Serial flash security register configuration + */ +struct sflash_sec_reg_cfg +{ + uint8_t erase_cmd; /*!< Erase security register command */ + uint8_t program_cmd; /*!< Program security register command */ + uint8_t read_cmd; /*!< Read security register command */ + uint8_t enter_sec_opt_cmd; /*!< Enter security register option mode command */ + uint8_t exit_sec_opt_cmd; /*!< Exit security register option mode command */ + uint8_t block_num; /*!< Security register block number */ + uint8_t *data; /*!< Data pointer to be program/read */ + uint32_t addr; /*!< Start address to be program/read */ + uint32_t len; /*!< Data length to be program/read */ +}; +/*@} end of group SFLAH_Public_Types */ + +/** @defgroup SFLAH_Public_Constants + * @{ + */ + +/*@} end of group SFLAH_Public_Constants */ + +/** @defgroup SFLAH_Public_Macros + * @{ + */ +#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) +#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) +#define BFLB_SPIFLASH_CMD_INVALID 0xff + +/*@} end of group SFLAH_Public_Macros */ + +/** @defgroup SFLAH_Public_Functions + * @{ + */ +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE +void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg); +#else +void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg); +#endif +int bflb_sflash_set_spi_mode(uint8_t mode); +int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len); +int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len); +int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, + uint8_t reg_len); +int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, + uint8_t reg_len); +int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg); +void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num); +int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num); +int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num); +int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr); +void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len); +void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data); +void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr); +void bflb_sflash_powerdown(void); +void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, uint8_t flash_cont_read, uint8_t bank); +void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg); +void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg); +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE +int bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, uint8_t en_32bits_addr); +#endif +int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg); +void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, + uint32_t len, uint8_t bank); +int bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank); +void bflb_sflash_xip_read_disable(void); +int bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos); +int bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg); +int bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg); +int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg); +int bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg); +int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, + uint32_t len); +int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len); + +/*@} end of group SFLAH_Public_Functions */ + +/*@} end of group SFLAH */ + +/*@} end of group BL628_Peripheral_Driver */ + +#endif /* __BL628_SFLAH_H__ */ diff --git a/drivers/lhal/src/flash/bflb_xip_sflash.c b/drivers/lhal/src/flash/bflb_xip_sflash.c new file mode 100644 index 00000000..4d4a5943 --- /dev/null +++ b/drivers/lhal/src/flash/bflb_xip_sflash.c @@ -0,0 +1,495 @@ +/** + ****************************************************************************** + * @file bflb_xip_sflash.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bflb_common.h" +#include "bflb_xip_sflash.h" + +/** @addtogroup BL628_Peripheral_Driver + * @{ + */ + +/** @addtogroup XIP_SFLASH + * @{ + */ + +/** @defgroup XIP_SFLASH_Private_Macros + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Macros */ + +/** @defgroup XIP_SFLASH_Private_Types + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Types */ + +/** @defgroup XIP_SFLASH_Private_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Variables */ + +/** @defgroup XIP_SFLASH_Global_Variables + * @{ + */ + +/*@} end of group XIP_SFLASH_Global_Variables */ + +/** @defgroup XIP_SFLASH_Private_Fun_Declaration + * @{ + */ + +/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ + +/** @defgroup XIP_SFLASH_Private_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Save flash controller state + * + * @param p_flash_cfg: Flash config pointer + * @param offset: CPU XIP flash offset pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, + uint8_t group, uint8_t bank) +{ + /* XIP_SFlash_Delay */ + volatile uint32_t i = 32 * 2; + + while (i--) + ; + +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE + if (bank == SF_CTRL_FLASH_BANK1) { + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); + } +#endif + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + /* Exit form continous read for accepting command */ + bflb_sflash_reset_continue_read(p_flash_cfg); + /* For disable command that is setting register instaed of send command, we need write enable */ + bflb_sflash_disable_burst_wrap(p_flash_cfg); +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE + /* Enable 32Bits addr mode again in case reset command make it reset */ + bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1); +#endif + if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) { + /* Enable QE again in case reset command make it reset */ + bflb_sflash_qspi_enable(p_flash_cfg); + } + /* Deburst again to make sure */ + bflb_sflash_disable_burst_wrap(p_flash_cfg); + + /* Clear offset setting*/ + *offset = bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); + + return 0; +} + +/****************************************************************************/ /** + * @brief Restore flash controller state + * + * @param p_flash_cfg: Flash config pointer + * @param offset: CPU XIP flash offset + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, + uint8_t group, uint8_t bank) +{ + uint32_t tmp[1]; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_sf_ctrl_set_flash_image_offset(offset, group, bank); + + if(((p_flash_cfg->io_mode>>4)&0x01) == 0) { + if((p_flash_cfg->io_mode&0x0f)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0x0f)==SF_CTRL_QIO_MODE) { + bflb_sflash_set_burst_wrap(p_flash_cfg); + } + } +#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE + bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1); +#endif + bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); +#ifdef BFLB_SF_CTRL_SBUS2_ENABLE + if (bank == SF_CTRL_FLASH_BANK1) { + bflb_sf_ctrl_sbus2_revoke_replace(); + } +#endif + + return 0; +} + +/*@} end of group XIP_SFLASH_Private_Functions */ + +/** @defgroup XIP_SFLASH_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief Erase flash one region + * + * @param p_flash_cfg: Flash config pointer + * @param start_addr: start address to erase + * @param len: data length to erase + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr, + int len, uint8_t group, uint8_t bank) +{ + int stat = 0; + uint32_t offset = 0; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); + } else { + stat = bflb_sflash_erase(p_flash_cfg, start_addr, start_addr + len - 1); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + bflb_xip_sflash_opt_exit(aes_enable); + + return stat; +} + +/****************************************************************************/ /** + * @brief Program flash one region + * + * @param p_flash_cfg: Flash config pointer + * @param addr: start address to be programed + * @param data: data pointer to be programed + * @param len: data length to be programed + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, + uint32_t len, uint8_t group, uint8_t bank) +{ + int stat = 0; + uint32_t offset = 0; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); + } else { + stat = bflb_sflash_program(p_flash_cfg, io_mode, addr, data, len); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + bflb_xip_sflash_opt_exit(aes_enable); + + return stat; +} + +/****************************************************************************/ /** + * @brief Read data from flash + * + * @param p_flash_cfg: Flash config pointer + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, + uint32_t len, uint8_t group, uint8_t bank) +{ + int stat = 0; + uint32_t offset = 0; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); + } else { + stat = bflb_sflash_read(p_flash_cfg, io_mode, 0, addr, data, len); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + bflb_xip_sflash_opt_exit(aes_enable); + + return stat; +} + +/****************************************************************************/ /** + * @brief Get Flash Jedec ID + * + * @param p_flash_cfg: Flash config pointer + * @param data: data pointer to store Jedec ID Read from flash + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t group, uint8_t bank) +{ + int stat = 0; + uint32_t offset = 0; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); + } else { + bflb_sflash_get_jedecid(p_flash_cfg, data); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + bflb_xip_sflash_opt_exit(aes_enable); + + return 0; +} + +/****************************************************************************/ /** + * @brief Get Flash Device ID + * + * @param p_flash_cfg: Flash config pointer + * @param is_32bits_addr: Is flash addr mode in 32-bits + * @param data: data pointer to store Device ID Read from flash + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, + uint8_t *data, uint8_t group, uint8_t bank) +{ + int stat = 0; + uint32_t offset = 0; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); + } else { + bflb_sflash_get_deviceid(data, is_32bits_addr); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + bflb_xip_sflash_opt_exit(aes_enable); + + return 0; +} + +/****************************************************************************/ /** + * @brief Get Flash Unique ID + * + * @param p_flash_cfg: Flash config pointer + * @param data: data pointer to store Device ID Read from flash + * @param id_len: Unique id len + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t id_len, uint8_t group, uint8_t bank) +{ + int stat = 0; + uint32_t offset = 0; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); + } else { + bflb_sflash_get_uniqueid(data, id_len); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + bflb_xip_sflash_opt_exit(aes_enable); + + return 0; +} + +/****************************************************************************//** + * @brief Clear flash status register need lock + * + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) +{ + int stat = 0; + uint32_t offset = 0; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); + } else { + stat = bflb_sflash_clear_status_register(p_flash_cfg); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); + } + + bflb_xip_sflash_opt_exit(aes_enable); + + return 0; +} + +/****************************************************************************/ /** + * @brief Read data from flash via XIP + * + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, + uint8_t group, uint8_t bank) +{ + uint32_t offset = 0; + + addr = addr & (BFLB_FLASH_XIP_END-BFLB_FLASH_XIP_BASE-1); + addr |= BFLB_FLASH_XIP_BASE; + + offset = bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); + /* Flash read */ + arch_memcpy_fast(data, (void *)(uintptr_t)(addr - bflb_sf_ctrl_get_flash_image_offset(group, bank)), len); + bflb_sf_ctrl_set_flash_image_offset(offset, group, bank); + + return 0; +} + +/****************************************************************************/ /** + * @brief XIP SFlash option save + * + * @param aes_enable: AES enable status pointer + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable) +{ + *aes_enable = bflb_sf_ctrl_is_aes_enable(); + + if (*aes_enable) { + bflb_sf_ctrl_aes_disable(); + } +} + +/****************************************************************************/ /** + * @brief XIP SFlash option restore + * + * @param aes_enable: AES enable status + * + * @return None + * +*******************************************************************************/ +__WEAK +void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable) +{ + if (aes_enable) { + bflb_sf_ctrl_aes_enable(); + } +} + +/*@} end of group XIP_SFLASH_Public_Functions */ + +/*@} end of group XIP_SFLASH */ + +/*@} end of group BL628_Peripheral_Driver */ diff --git a/drivers/soc/bl702/std/include/bl702_xip_sflash.h b/drivers/lhal/src/flash/bflb_xip_sflash.h similarity index 55% rename from drivers/soc/bl702/std/include/bl702_xip_sflash.h rename to drivers/lhal/src/flash/bflb_xip_sflash.h index 4b749817..ab4cf7d7 100644 --- a/drivers/soc/bl702/std/include/bl702_xip_sflash.h +++ b/drivers/lhal/src/flash/bflb_xip_sflash.h @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file bl702_xip_sflash.h + * @file bflb_xip_sflash.h * @version V1.0 * @date * @brief This file is the standard driver header file @@ -33,13 +33,12 @@ * ****************************************************************************** */ -#ifndef __BL702_XIP_SFLASH_H__ -#define __BL702_XIP_SFLASH_H__ +#ifndef __BL628_XIP_SFLASH_H__ +#define __BL628_XIP_SFLASH_H__ -#include "bl702_common.h" -#include "bl702_sflash.h" +#include "bflb_sflash.h" -/** @addtogroup BL702_Peripheral_Driver +/** @addtogroup BL628_Peripheral_Driver * @{ */ @@ -68,28 +67,33 @@ /** @defgroup XIP_SFLASH_Public_Functions * @{ */ -void XIP_SFlash_Opt_Enter(void); -void XIP_SFlash_Opt_Exit(void); -BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset); -BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset); -BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, - uint32_t startaddr, uint32_t endaddr); -BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, - uint8_t *data, uint32_t len); -BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, - uint8_t *data, uint32_t len); -BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, - uint8_t *data); -BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, - uint8_t *data); -BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, - uint8_t *data, uint8_t idLen); -BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len); +int bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, + uint8_t group, uint8_t bank); +int bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, + uint8_t group, uint8_t bank); +int bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr, + int len, uint8_t group, uint8_t bank); +int bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, + uint8_t *data, uint32_t len, uint8_t group, uint8_t bank); +int bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, + uint8_t *data, uint32_t len, uint8_t group, uint8_t bank); +int bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t group, uint8_t bank); +int bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, + uint8_t *data, uint8_t group, uint8_t bank); +int bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t idlen, uint8_t group, uint8_t bank); +int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_Flash_Cfg, + uint8_t group, uint8_t bank); +int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, + uint8_t group, uint8_t bank); +void bflb_xip_sflash_opt_enter(uint8_t *aes_enable); +void bflb_xip_sflash_opt_exit(uint8_t aes_enable); /*@} end of group XIP_SFLASH_Public_Functions */ /*@} end of group XIP_SFLASH */ -/*@} end of group BL702_Peripheral_Driver */ +/*@} end of group BL628_Peripheral_Driver */ -#endif /* __BL702_XIP_SFLASH_H__ */ +#endif /* __BL628_XIP_SFLASH_H__ */ diff --git a/drivers/lhal/src/pka/libpka.a b/drivers/lhal/src/pka/libpka.a index 32ba3696..893de7c3 100644 Binary files a/drivers/lhal/src/pka/libpka.a and b/drivers/lhal/src/pka/libpka.a differ diff --git a/drivers/soc/bl602/std/CMakeLists.txt b/drivers/soc/bl602/std/CMakeLists.txt index 1b1ed52b..04f7caf1 100644 --- a/drivers/soc/bl602/std/CMakeLists.txt +++ b/drivers/soc/bl602/std/CMakeLists.txt @@ -20,16 +20,11 @@ sdk_library_add_sources(src/bl602_l1c.c) sdk_library_add_sources(src/bl602_pds.c) sdk_library_add_sources(src/bl602_tzc_sec.c) -sdk_library_add_sources(src/bl602_sf_cfg.c) -sdk_library_add_sources(src/bl602_sf_cfg_ext.c) -sdk_library_add_sources(src/bl602_sf_ctrl.c) -sdk_library_add_sources(src/bl602_sflash.c) sdk_library_add_sources(src/bl602_sflash_ext.c) -sdk_library_add_sources(src/bl602_xip_sflash.c) sdk_library_add_sources(src/bl602_xip_sflash_ext.c) +sdk_library_add_sources(src/bl602_sf_cfg_ext.c) sdk_library_add_sources(port/bl602_clock.c) -sdk_library_add_sources(port/bl602_flash.c) sdk_add_include_directories( include diff --git a/drivers/soc/bl602/std/include/bl602_glb.h b/drivers/soc/bl602/std/include/bl602_glb.h index e4e59ce0..8ba8c891 100644 --- a/drivers/soc/bl602/std/include/bl602_glb.h +++ b/drivers/soc/bl602/std/include/bl602_glb.h @@ -41,11 +41,11 @@ #include "bl602_gpio.h" #include "bl602_l1c.h" #include "bl602_hbn.h" -#include "bl602_sf_ctrl.h" -#include "bl602_sf_cfg.h" #include "bl602_aon.h" #include "bl602_pds.h" #include "bl602_common.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" /** @addtogroup BL602_Peripheral_Driver * @{ diff --git a/drivers/soc/bl602/std/include/bl602_hbn.h b/drivers/soc/bl602/std/include/bl602_hbn.h index 8b31dad4..07e68742 100644 --- a/drivers/soc/bl602/std/include/bl602_hbn.h +++ b/drivers/soc/bl602/std/include/bl602_hbn.h @@ -38,7 +38,7 @@ #include "hbn_reg.h" #include "bl602_aon.h" -#include "bl602_sflash.h" +#include "bflb_sflash.h" #include "bl602_common.h" /** @addtogroup BL602_Peripheral_Driver @@ -243,7 +243,7 @@ typedef struct uint32_t sleepTime; /*!< HBN sleep time */ uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ HBN_LEVEL_Type hbnLevel; /*!< HBN level */ HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ } HBN_APP_CFG_Type; @@ -411,7 +411,7 @@ void HBN_OUT1_IRQHandler(void); #endif /*----------*/ void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg); -void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg); void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); BL_Err_Type HBN_Reset(void); BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); diff --git a/drivers/soc/bl602/std/include/bl602_pds.h b/drivers/soc/bl602/std/include/bl602_pds.h index af5f22b0..6217f6f6 100644 --- a/drivers/soc/bl602/std/include/bl602_pds.h +++ b/drivers/soc/bl602/std/include/bl602_pds.h @@ -39,8 +39,8 @@ #include "pds_reg.h" #include "bl602_aon.h" #include "bl602_hbn.h" -#include "bl602_sflash.h" #include "bl602_common.h" +#include "bflb_sflash.h" /** @addtogroup BL602_Peripheral_Driver * @{ @@ -321,7 +321,7 @@ typedef struct uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ uint8_t flashContRead; /*!< Whether enable flash continue read */ uint32_t sleepTime; /*!< PDS sleep time */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ void (*preCbFun)(void); /*!< Pre callback function */ void (*postCbFun)(void); /*!< Post callback function */ diff --git a/drivers/soc/bl602/std/include/bl602_romdriver.h b/drivers/soc/bl602/std/include/bl602_romdriver.h index 6058b2ab..5b263a2f 100644 --- a/drivers/soc/bl602/std/include/bl602_romdriver.h +++ b/drivers/soc/bl602/std/include/bl602_romdriver.h @@ -40,11 +40,11 @@ #include "bl602_aon.h" #include "bl602_glb.h" #include "bl602_hbn.h" -#include "bl602_xip_sflash.h" -#include "bl602_sflash.h" -#include "bl602_sf_ctrl.h" #include "bl602_ef_ctrl.h" // #include "bl602_sec_eng.h" +#include "bflb_xip_sflash.h" +#include "bflb_sflash.h" +#include "bflb_sf_ctrl.h" // #include "softcrc.h" /** @addtogroup BL602_Peripheral_Driver @@ -446,7 +446,7 @@ typedef enum { ((void (*)(HBN_APP_CFG_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter]) #define RomDriver_HBN_Power_Down_Flash \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) #define RomDriver_HBN_Enable \ ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable]) @@ -554,52 +554,52 @@ typedef enum { ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring]) #define RomDriver_SFlash_Init \ - ((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) + ((void (*)(const struct sf_ctrl_cfg_type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) #define RomDriver_SFlash_SetSPIMode \ - ((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) + ((int(*)(uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) #define RomDriver_SFlash_Read_Reg \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) #define RomDriver_SFlash_Write_Reg \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) #define RomDriver_SFlash_Busy \ - ((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) #define RomDriver_SFlash_Write_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) #define RomDriver_SFlash_Qspi_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) #define RomDriver_SFlash_Volatile_Reg_Write_Enable \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) #define RomDriver_SFlash_Chip_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) #define RomDriver_SFlash_Sector_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) #define RomDriver_SFlash_Blk32_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) #define RomDriver_SFlash_Blk64_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) #define RomDriver_SFlash_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) #define RomDriver_SFlash_Program \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) #define RomDriver_SFlash_GetUniqueId \ ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) #define RomDriver_SFlash_GetJedecId \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) + ((void (*)(spi_flash_cfg_type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) #define RomDriver_SFlash_GetDeviceId \ ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) @@ -608,34 +608,34 @@ typedef enum { ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) #define RomDriver_SFlash_Releae_Powerdown \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) #define RomDriver_SFlash_SetBurstWrap \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) #define RomDriver_SFlash_DisableBurstWrap \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) #define RomDriver_SFlash_Software_Reset \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) #define RomDriver_SFlash_Reset_Continue_Read \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) #define RomDriver_SFlash_Set_IDbus_Cfg \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) #define RomDriver_SFlash_IDbus_Read_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) #define RomDriver_SFlash_Cache_Enable_Set \ - ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set]) + ((int(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set]) #define RomDriver_SFlash_Cache_Flush \ - ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush]) + ((int(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush]) #define RomDriver_SFlash_Cache_Read_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) #define RomDriver_SFlash_Cache_Hit_Count_Get \ ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get]) @@ -647,46 +647,46 @@ typedef enum { ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable]) #define RomDriver_SFlash_Read \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) #define RomDriver_SFlash_Read_Reg_With_Cmd \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) #define RomDriver_SFlash_Write_Reg_With_Cmd \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) #define RomDriver_SFlash_Restore_From_Powerdown \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) #define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ - ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) + ((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) #define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \ ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio]) #define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ - ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) + ((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) #define RomDriver_SF_Cfg_Restore_GPIO17_Fun \ ((void (*)(uint8_t fun))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun]) #define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ - ((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) + ((int(*)(uint32_t flashID, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) #define RomDriver_SF_Cfg_Init_Flash_Gpio \ - ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) + ((int (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) #define RomDriver_SF_Cfg_Flash_Identify \ - ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) #define RomDriver_SF_Ctrl_Enable \ - ((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) + ((void (*)(const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) #define RomDriver_SF_Ctrl_Select_Pad \ - ((void (*)(SF_Ctrl_Pad_Sel sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) + ((void (*)(uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) #define RomDriver_SF_Ctrl_Set_Owner \ - ((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) + ((void (*)(uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) #define RomDriver_SF_Ctrl_Disable \ ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) @@ -701,10 +701,10 @@ typedef enum { ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) #define RomDriver_SF_Ctrl_AES_Set_Key \ - ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) + ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) #define RomDriver_SF_Ctrl_AES_Set_Key_BE \ - ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) + ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) #define RomDriver_SF_Ctrl_AES_Set_IV \ ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV]) @@ -725,19 +725,19 @@ typedef enum { ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) #define RomDriver_SF_Ctrl_Select_Clock \ - ((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) + ((void (*)(uint8_t sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) #define RomDriver_SF_Ctrl_SendCmd \ - ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) + ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) #define RomDriver_SF_Ctrl_Icache_Set \ - ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set]) + ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set]) #define RomDriver_SF_Ctrl_Icache2_Set \ - ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set]) + ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set]) #define RomDriver_SF_Ctrl_GetBusyState \ - ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) + ((int(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) #define RomDriver_SF_Ctrl_Is_AES_Enable \ ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) @@ -749,31 +749,31 @@ typedef enum { ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) #define RomDriver_XIP_SFlash_State_Save \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) #define RomDriver_XIP_SFlash_State_Restore \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) #define RomDriver_XIP_SFlash_Erase_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) #define RomDriver_XIP_SFlash_Write_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) #define RomDriver_XIP_SFlash_Read_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) #define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) #define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) #define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) #define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ - ((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) + ((int(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) #define RomDriver_XIP_SFlash_Opt_Enter \ ((void (*)(uint8_t * aesEnable)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter]) diff --git a/drivers/soc/bl602/std/include/bl602_sf_cfg.h b/drivers/soc/bl602/std/include/bl602_sf_cfg.h deleted file mode 100644 index cb2cd503..00000000 --- a/drivers/soc/bl602/std/include/bl602_sf_cfg.h +++ /dev/null @@ -1,112 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_sf_cfg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL602_SF_CFG_H__ -#define __BL602_SF_CFG_H__ - -#include "string.h" -#include "bl602_sflash.h" -#include "bl602_sf_ctrl.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Public_Types - * @{ - */ - -/*@} end of group SF_CFG_Public_Types */ - -/** @defgroup SF_CFG_Public_Constants - * @{ - */ - -/*@} end of group SF_CFG_Public_Constants */ - -/** @defgroup SF_CFG_Public_Macros - * @{ - */ -/*Flash option 0*/ -/*Flash CLK*/ -#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_22 -/*FLASH CS*/ -#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_21 -/*FLASH DATA*/ -#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_20 -#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_19 -#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_18 -#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_17 -/*Flash option 1*/ -/*Flash CLK*/ -#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_22 -/*FLASH CS*/ -#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_21 -/*FLASH DATA*/ -#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_20 -#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_0 -#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_1 -#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_2 -#define BFLB_FLASH_CFG_DESWAP 1 -#define BFLB_FLASH_CFG_EXT0_17_22 2 -#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3 -#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 -#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF - -/*@} end of group SF_CFG_Public_Macros */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); -void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault); -void SF_Cfg_Restore_GPIO17_Fun(uint8_t fun); -uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg); -void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); -void SF_Cfg_Init_Internal_Flash_Gpio(void); -void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL602_Peripheral_Driver */ - -#endif /* __BL602_SF_CFG_H__ */ diff --git a/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h b/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h index f3fbdfcb..b2090baa 100644 --- a/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h +++ b/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h @@ -37,8 +37,8 @@ #define __BL602_SF_CFG_EXT_H__ #include "string.h" -#include "bl602_sflash.h" -#include "bl602_sf_ctrl.h" +#include "bflb_sflash.h" +#include "bflb_sf_ctrl.h" /** @addtogroup BL602_Peripheral_Driver * @{ @@ -69,9 +69,10 @@ /** @defgroup SF_CFG_EXT_Public_Functions * @{ */ -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); -uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg); +int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank); +uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, + spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank); /*@} end of group SF_CFG_EXT_Public_Functions */ diff --git a/drivers/soc/bl602/std/include/bl602_sf_ctrl.h b/drivers/soc/bl602/std/include/bl602_sf_ctrl.h deleted file mode 100644 index b5b882ea..00000000 --- a/drivers/soc/bl602/std/include/bl602_sf_ctrl.h +++ /dev/null @@ -1,327 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_sf_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL602_SF_CTRL_H__ -#define __BL602_SF_CTRL_H__ - -#include "sf_ctrl_reg.h" -#include "bl602_common.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Serial flash pad select type definition - */ -typedef enum { - SF_CTRL_EMBEDDED_SEL, /*!< Embedded flash select */ - SF_CTRL_EXTERNAL_17TO22_SEL, /*!< External flash select gpio 17-22 */ - SF_CTRL_EXTERNAL_0TO2_20TO22_SEL, /*!< External flash select gpio 0-2 and 20-22 */ -} SF_Ctrl_Pad_Sel; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ - SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ -} SF_Ctrl_Owner_Type; - -/** - * @brief Serial flash controller select clock type definition - */ -typedef enum { - SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */ - SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */ -} SF_Ctrl_Sahb_Type; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */ - REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */ -} SF_Ctrl_Ahb2sif_Type; - -/** - * @brief Read and write type definition - */ -typedef enum { - SF_CTRL_READ, /*!< Serail flash read command flag */ - SF_CTRL_WRITE, /*!< Serail flash write command flag */ -} SF_Ctrl_RW_Type; - -/** - * @brief Serail flash interface IO type definition - */ -typedef enum { - SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ - SF_CTRL_DO_MODE, /*!< Dual Output mode define */ - SF_CTRL_QO_MODE, /*!< Quad Output mode define */ - SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ - SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ -} SF_Ctrl_IO_Type; - -/** - * @brief Serail flash controller interface mode type definition - */ -typedef enum { - SF_CTRL_SPI_MODE, /*!< SPI mode define */ - SF_CTRL_QPI_MODE, /*!< QPI mode define */ -} SF_Ctrl_Mode_Type; - -/** - * @brief Serail flash controller command mode type definition - */ -typedef enum { - SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ - SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ -} SF_Ctrl_Cmd_Mode_Type; - -/** - * @brief Serail flash controller address mode type definition - */ -typedef enum { - SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ - SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ - SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ -} SF_Ctrl_Addr_Mode_Type; - -/** - * @brief Serail flash controller dummy mode type definition - */ -typedef enum { - SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ - SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ - SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ -} SF_Ctrl_Dmy_Mode_Type; - -/** - * @brief Serail flash controller data mode type definition - */ -typedef enum { - SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ - SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ - SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ -} SF_Ctrl_Data_Mode_Type; - -/** - * @brief Serail flash controller AES type definition - */ -typedef enum { - SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ - SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ - SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ - SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ -} SF_Ctrl_AES_Key_Type; - -/** - * @brief Serail flash controller configuration structure type definition - */ -typedef struct -{ - SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ - SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */ - SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */ - uint8_t clkDelay; /*!< Clock count for read due to pad delay */ - uint8_t clkInvert; /*!< Clock invert */ - uint8_t rxClkInvert; /*!< RX clock invert */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ -} SF_Ctrl_Cfg_Type; - -/** - * @brief Serail flash command configuration structure type definition - */ -typedef struct -{ - uint8_t rwFlag; /*!< Read write flag */ - SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ - SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ - uint8_t addrSize; /*!< Address size */ - uint8_t dummyClks; /*!< Dummy clocks */ - SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ - SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ - uint8_t rsv[1]; /*!< */ - uint32_t nbData; /*!< Transfer number of bytes */ - uint32_t cmdBuf[2]; /*!< Command buffer */ -} SF_Ctrl_Cmd_Cfg_Type; - -/*@} end of group SF_CTRL_Public_Types */ - -/** @defgroup SF_CTRL_Public_Constants - * @{ - */ - -/** @defgroup SF_CTRL_PAD_SEL - * @{ - */ -#define IS_SF_CTRL_PAD_SEL(type) (((type) == SF_CTRL_EMBEDDED_SEL) || \ - ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) || \ - ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL)) - -/** @defgroup SF_CTRL_OWNER_TYPE - * @{ - */ -#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ - ((type) == SF_CTRL_OWNER_IAHB)) - -/** @defgroup SF_CTRL_SAHB_TYPE - * @{ - */ -#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \ - ((type) == SF_CTRL_FLASH_CLOCK)) - -/** @defgroup SF_CTRL_AHB2SIF_TYPE - * @{ - */ -#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \ - ((type) == REMOVE_CLOCK_CONSTRAIN)) - -/** @defgroup SF_CTRL_RW_TYPE - * @{ - */ -#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ - ((type) == SF_CTRL_WRITE)) - -/** @defgroup SF_CTRL_IO_TYPE - * @{ - */ -#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ - ((type) == SF_CTRL_DO_MODE) || \ - ((type) == SF_CTRL_QO_MODE) || \ - ((type) == SF_CTRL_DIO_MODE) || \ - ((type) == SF_CTRL_QIO_MODE)) - -/** @defgroup SF_CTRL_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ - ((type) == SF_CTRL_QPI_MODE)) - -/** @defgroup SF_CTRL_CMD_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ - ((type) == SF_CTRL_CMD_4_LINES)) - -/** @defgroup SF_CTRL_ADDR_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ - ((type) == SF_CTRL_ADDR_2_LINES) || \ - ((type) == SF_CTRL_ADDR_4_LINES)) - -/** @defgroup SF_CTRL_DMY_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ - ((type) == SF_CTRL_DUMMY_2_LINES) || \ - ((type) == SF_CTRL_DUMMY_4_LINES)) - -/** @defgroup SF_CTRL_DATA_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ - ((type) == SF_CTRL_DATA_2_LINES) || \ - ((type) == SF_CTRL_DATA_4_LINES)) - -/** @defgroup SF_CTRL_AES_KEY_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ - ((type) == SF_CTRL_AES_256BITS) || \ - ((type) == SF_CTRL_AES_192BITS) || \ - ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) - -/*@} end of group SF_CTRL_Public_Constants */ - -/** @defgroup SF_CTRL_Public_Macros - * @{ - */ -#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF -#define FLASH_CTRL_BUF_SIZE 256 - -/*@} end of group SF_CTRL_Public_Macros */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void); -#endif -void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); -void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); -void SF_Ctrl_Disable(void); -void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel); -void SF_Ctrl_AES_Enable_BE(void); -void SF_Ctrl_AES_Enable_LE(void); -void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, - uint32_t endAddr, - uint8_t locked); -void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Enable(void); -void SF_Ctrl_AES_Disable(void); -void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset); -uint32_t SF_Ctrl_Get_Flash_Image_Offset(void); -void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType); -void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); -void SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -void SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -BL_Sts_Type SF_Ctrl_GetBusyState(void); -uint8_t SF_Ctrl_Is_AES_Enable(void); -uint8_t SF_Ctrl_Get_Clock_Delay(void); -void SF_Ctrl_Set_Clock_Delay(uint8_t delay); - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL602_Peripheral_Driver */ - -#endif /* __BL602_SF_CTRL_H__ */ diff --git a/drivers/soc/bl602/std/include/bl602_sflash.h b/drivers/soc/bl602/std/include/bl602_sflash.h deleted file mode 100644 index ec5bd82d..00000000 --- a/drivers/soc/bl602/std/include/bl602_sflash.h +++ /dev/null @@ -1,199 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_sflah.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL602_SFLAH_H__ -#define __BL602_SFLAH_H__ - -#include "bl602_common.h" -#include "bl602_sf_ctrl.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLAH - * @{ - */ - -/** @defgroup SFLAH_Public_Types - * @{ - */ - -/** - * @brief Serial flash configuration structure type definition - */ -typedef struct -{ - uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ - uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - uint8_t resetEnCmd; /*!< Flash enable reset command */ - uint8_t resetCmd; /*!< Flash reset command */ - uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ - uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ - uint8_t jedecIdCmd; /*!< JEDEC ID command */ - uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ - uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */ - uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */ - uint8_t sectorSize; /*!< *1024bytes */ - uint8_t mid; /*!< Manufacturer ID */ - uint16_t pageSize; /*!< Page size */ - uint8_t chipEraseCmd; /*!< Chip erase cmd */ - uint8_t sectorEraseCmd; /*!< Sector erase command */ - uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ - uint8_t blk64EraseCmd; /*!< Block 64K erase command */ - uint8_t writeEnableCmd; /*!< Need before every erase or program */ - uint8_t pageProgramCmd; /*!< Page program cmd */ - uint8_t qpageProgramCmd; /*!< QIO page program cmd */ - uint8_t qppAddrMode; /*!< QIO page program address mode */ - uint8_t fastReadCmd; /*!< Fast read command */ - uint8_t frDmyClk; /*!< Fast read command dummy clock */ - uint8_t qpiFastReadCmd; /*!< QPI fast read command */ - uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ - uint8_t fastReadDoCmd; /*!< Fast read dual output command */ - uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ - uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ - uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ - uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ - uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ - uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ - uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ - uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ - uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ - uint8_t qpiPageProgramCmd; /*!< QPI program command */ - uint8_t writeVregEnableCmd; /*!< Enable write reg */ - uint8_t wrEnableIndex; /*!< Write enable register index */ - uint8_t qeIndex; /*!< Quad mode enable register index */ - uint8_t busyIndex; /*!< Busy status register index */ - uint8_t wrEnableBit; /*!< Write enable bit pos */ - uint8_t qeBit; /*!< Quad enable bit pos */ - uint8_t busyBit; /*!< Busy status bit pos */ - uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ - uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ - uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ - uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ - uint8_t releasePowerDown; /*!< Release power down command */ - uint8_t busyReadRegLen; /*!< Register length of contain busy status */ - uint8_t readRegCmd[4]; /*!< Read register command buffer */ - uint8_t writeRegCmd[4]; /*!< Write register command buffer */ - uint8_t enterQpi; /*!< Enter qpi command */ - uint8_t exitQpi; /*!< Exit qpi command */ - uint8_t cReadMode; /*!< Config data for continuous read mode */ - uint8_t cRExit; /*!< Config data for exit continuous read mode */ - uint8_t burstWrapCmd; /*!< Enable burst wrap command */ - uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ - uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t burstWrapData; /*!< Data to enable burst wrap */ - uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ - uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ - uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ - uint16_t timeEsector; /*!< 4K erase time */ - uint16_t timeE32k; /*!< 32K erase time */ - uint16_t timeE64k; /*!< 64K erase time */ - uint16_t timePagePgm; /*!< Page program time */ - uint16_t timeCe; /*!< Chip erase time in ms */ - uint8_t pdDelay; /*!< Release power down command delay time for wake up */ - uint8_t qeData; /*!< QE set data */ -} __attribute__((packed)) SPI_Flash_Cfg_Type; - -/*@} end of group SFLAH_Public_Types */ - -/** @defgroup SFLAH_Public_Constants - * @{ - */ - -/*@} end of group SFLAH_Public_Constants */ - -/** @defgroup SFLAH_Public_Macros - * @{ - */ -#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) -#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) -#define BFLB_SPIFLASH_CMD_INVALID 0xff - -/*@} end of group SFLAH_Public_Macros */ - -/** @defgroup SFLAH_Public_Functions - * @{ - */ -void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg); -BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); -BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum); -BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr); -BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); -void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen); -void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data); -void SFlash_GetDeviceId(uint8_t *data); -void SFlash_Powerdown(void); -void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, - uint32_t len); -BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead); -BL_Err_Type SFlash_Cache_Enable_Set(uint8_t wayDisable); -BL_Err_Type SFlash_Cache_Flush(void); -BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - uint8_t wayDisable); -void SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh); -uint32_t SFlash_Cache_Miss_Count_Get(void); -void SFlash_Cache_Read_Disable(void); -BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, - uint32_t len); -BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, - uint8_t regLen); - -/*@} end of group SFLAH_Public_Functions */ - -/*@} end of group SFLAH */ - -/*@} end of group BL602_Peripheral_Driver */ - -#endif /* __BL602_SFLAH_H__ */ diff --git a/drivers/soc/bl602/std/include/bl602_sflash_ext.h b/drivers/soc/bl602/std/include/bl602_sflash_ext.h index 817e9260..a706e06d 100644 --- a/drivers/soc/bl602/std/include/bl602_sflash_ext.h +++ b/drivers/soc/bl602/std/include/bl602_sflash_ext.h @@ -36,7 +36,7 @@ #ifndef __BL602_SFLAH_EXT_H__ #define __BL602_SFLAH_EXT_H__ -#include "bl602_sflash.h" +#include "bflb_sflash.h" #include "bl602_common.h" /** @addtogroup BL602_Peripheral_Driver @@ -51,22 +51,6 @@ * @{ */ -/** - * @brief Serial flash security register configuration - */ -typedef struct -{ - uint8_t eraseCmd; /*!< Erase security register command */ - uint8_t programCmd; /*!< Program security register command */ - uint8_t readCmd; /*!< Read security register command */ - uint8_t enterSecOptCmd; /*!< Enter security register option mode command */ - uint8_t exitSecOptCmd; /*!< Exit security register option mode command */ - uint8_t blockNum; /*!< Security register block number */ - uint8_t *data; /*!< Data pointer to be program/read */ - uint32_t addr; /*!< Start address to be program/read */ - uint32_t len; /*!< Data length to be program/read */ -} SFlash_Sec_Reg_Cfg; - /*@} end of group SFLAH_EXT_Public_Types */ /** @defgroup SFLAH_EXT_Public_Constants @@ -84,13 +68,15 @@ typedef struct /** @defgroup SFLAH_EXT_Public_Functions * @{ */ -BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead); -BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos); -BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, - SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg); +int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flash_cont_read, uint8_t bank); +int bflb_sflash_rcv_enable(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos); +int bflb_sflash_erase_security_register(spi_flash_cfg_type *p_flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg); +int bflb_sflash_program_security_register(spi_flash_cfg_type *p_flash_cfg, + struct sflash_sec_reg_cfg *p_sec_reg_cfg); +int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg); +int bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg); +int bflb_sflash_cache_enable_set(uint8_t way_disable); +int bflb_sflash_cache_flush(void); /*@} end of group SFLAH_EXT_Public_Functions */ diff --git a/drivers/soc/bl602/std/include/bl602_xip_sflash.h b/drivers/soc/bl602/std/include/bl602_xip_sflash.h deleted file mode 100644 index aa3d2b56..00000000 --- a/drivers/soc/bl602/std/include/bl602_xip_sflash.h +++ /dev/null @@ -1,90 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_xip_sflash.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL602_XIP_SFLASH_H__ -#define __BL602_XIP_SFLASH_H__ - -#include "bl602_common.h" -#include "bl602_sflash.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Public_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Types */ - -/** @defgroup XIP_SFLASH_Public_Constants - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Constants */ - -/** @defgroup XIP_SFLASH_Public_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Macros */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ -BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset); -BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset); -BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr); -BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, - uint32_t len); -BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data); -BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data); -BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen); -BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len); -void XIP_SFlash_Opt_Enter(uint8_t *aesEnable); -void XIP_SFlash_Opt_Exit(uint8_t aesEnable); - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL602_Peripheral_Driver */ - -#endif /* __BL602_XIP_SFLASH_H__ */ diff --git a/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h b/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h index d73bf5c5..1bf26e49 100644 --- a/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h +++ b/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h @@ -37,9 +37,9 @@ #define __BL602_XIP_SFLASH_EXT_H__ #include "bl602_common.h" -#include "bl602_sflash.h" #include "bl602_sflash_ext.h" -#include "bl602_xip_sflash.h" +#include "bflb_sflash.h" +#include "bflb_xip_sflash.h" /** @addtogroup BL602_Peripheral_Driver * @{ @@ -70,21 +70,23 @@ /** @defgroup XIP_SFLASH_EXT_Public_Functions * @{ */ -BL_Err_Type XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t offset); -BL_Err_Type XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t startaddr, - uint32_t endaddr); -BL_Err_Type XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, - uint32_t len); -BL_Err_Type XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr,uint8_t *data, - uint32_t len); -BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg); -BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); -BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data); -BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint8_t *data, - uint8_t idLen); -BL_Err_Type XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, - uint8_t bitPos); -BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg); +int bflb_xip_sflash_state_restore_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank); +int bflb_xip_sflash_erase_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, + uint32_t endaddr, uint8_t group, uint8_t bank); +int bflb_xip_sflash_write_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, + uint32_t len, uint8_t group, uint8_t bank); +int bflb_xip_sflash_read_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, + uint32_t len, uint8_t group, uint8_t bank); +int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank); +int bflb_xip_sflash_get_jedecid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t group, uint8_t bank); +int bflb_xip_sflash_get_deviceid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, + uint8_t *data, uint8_t group, uint8_t bank); +int bflb_xip_sflash_get_uniqueid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint8_t *data, + uint8_t idLen, uint8_t group, uint8_t bank); +int bflb_xip_sflash_rcv_enable_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t rCmd, uint8_t wCmd, + uint8_t bitPos, uint8_t group, uint8_t bank); +int bflb_xip_sflash_init(spi_flash_cfg_type *p_flash_cfg); /*@} end of group XIP_SFLASH_EXT_Public_Functions */ diff --git a/drivers/soc/bl602/std/include/hardware/ef_data_0_reg.h b/drivers/soc/bl602/std/include/hardware/ef_data_0_reg.h deleted file mode 100644 index 2322c740..00000000 --- a/drivers/soc/bl602/std/include/hardware/ef_data_0_reg.h +++ /dev/null @@ -1,762 +0,0 @@ -/** - ****************************************************************************** - * @file ef_data_0_reg.h - * @version V1.2 - * @date 2019-11-22 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __EF_DATA_0_REG_H__ -#define __EF_DATA_0_REG_H__ - -#include "bl602.h" - -/* 0x0 : ef_cfg_0 */ -#define EF_DATA_0_EF_CFG_0_OFFSET (0x0) -#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE -#define EF_DATA_0_EF_SF_AES_MODE_POS (0U) -#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U) -#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS) -#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)) -#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN -#define EF_DATA_0_EF_SBOOT_EN_POS (4U) -#define EF_DATA_0_EF_SBOOT_EN_LEN (2U) -#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS) -#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)) -#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN -#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U) -#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U) -#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS) -#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)) -#define EF_DATA_0_EF_TRIM_EN EF_DATA_0_EF_TRIM_EN -#define EF_DATA_0_EF_TRIM_EN_POS (12U) -#define EF_DATA_0_EF_TRIM_EN_LEN (1U) -#define EF_DATA_0_EF_TRIM_EN_MSK (((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS) -#define EF_DATA_0_EF_TRIM_EN_UMSK (~(((1U << EF_DATA_0_EF_TRIM_EN_LEN) - 1) << EF_DATA_0_EF_TRIM_EN_POS)) -#define EF_DATA_0_EF_NO_HD_BOOT_EN EF_DATA_0_EF_NO_HD_BOOT_EN -#define EF_DATA_0_EF_NO_HD_BOOT_EN_POS (13U) -#define EF_DATA_0_EF_NO_HD_BOOT_EN_LEN (1U) -#define EF_DATA_0_EF_NO_HD_BOOT_EN_MSK (((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS) -#define EF_DATA_0_EF_NO_HD_BOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_0_EF_NO_HD_BOOT_EN_POS)) -#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN -#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U) -#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U) -#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS) -#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)) -#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE -#define EF_DATA_0_EF_DBG_MODE_POS (28U) -#define EF_DATA_0_EF_DBG_MODE_LEN (4U) -#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS) -#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)) - -/* 0x4 : ef_dbg_pwd_low */ -#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4) -#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW -#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U) -#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U) -#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS) -#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)) - -/* 0x8 : ef_dbg_pwd_high */ -#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8) -#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH -#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U) -#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U) -#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS) -#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)) - -/* 0xC : ef_ana_trim_0 */ -#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC) -#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0 -#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U) -#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U) -#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS) -#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)) - -/* 0x10 : ef_sw_usage_0 */ -#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10) -#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0 -#define EF_DATA_0_EF_SW_USAGE_0_POS (0U) -#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U) -#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS) -#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)) - -/* 0x14 : ef_wifi_mac_low */ -#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14) -#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW -#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U) -#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U) -#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS) -#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)) - -/* 0x18 : ef_wifi_mac_high */ -#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18) -#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH -#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U) -#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U) -#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS) -#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)) - -/* 0x1C : ef_key_slot_0_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C) -#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0 -#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)) - -/* 0x20 : ef_key_slot_0_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20) -#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1 -#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)) - -/* 0x24 : ef_key_slot_0_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24) -#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2 -#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)) - -/* 0x28 : ef_key_slot_0_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28) -#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3 -#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)) - -/* 0x2C : ef_key_slot_1_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C) -#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0 -#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)) - -/* 0x30 : ef_key_slot_1_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30) -#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1 -#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)) - -/* 0x34 : ef_key_slot_1_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34) -#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2 -#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)) - -/* 0x38 : ef_key_slot_1_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38) -#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3 -#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)) - -/* 0x3C : ef_key_slot_2_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C) -#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0 -#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)) - -/* 0x40 : ef_key_slot_2_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40) -#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1 -#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)) - -/* 0x44 : ef_key_slot_2_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44) -#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2 -#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)) - -/* 0x48 : ef_key_slot_2_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48) -#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3 -#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)) - -/* 0x4C : ef_key_slot_3_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C) -#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0 -#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)) - -/* 0x50 : ef_key_slot_3_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50) -#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1 -#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)) - -/* 0x54 : ef_key_slot_3_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54) -#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2 -#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)) - -/* 0x58 : ef_key_slot_3_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58) -#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3 -#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)) - -/* 0x5C : ef_key_slot_4_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C) -#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0 -#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)) - -/* 0x60 : ef_key_slot_4_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60) -#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1 -#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)) - -/* 0x64 : ef_key_slot_4_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64) -#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2 -#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)) - -/* 0x68 : ef_key_slot_4_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68) -#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3 -#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)) - -/* 0x6C : ef_key_slot_5_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C) -#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0 -#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)) - -/* 0x70 : ef_key_slot_5_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70) -#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1 -#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)) - -/* 0x74 : ef_key_slot_5_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74) -#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2 -#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)) - -/* 0x78 : ef_key_slot_5_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78) -#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3 -#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)) - -/* 0x7C : ef_data_0_lock */ -#define EF_DATA_0_LOCK_OFFSET (0x7C) -#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1 -#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U) -#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U) -#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS) -#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)) -#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE -#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U) -#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U) -#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS) -#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)) -#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD -#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U) -#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U) -#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS) -#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0 -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)) -#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC -#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U) -#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U) -#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS) -#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)) -#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD -#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U) -#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U) -#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS) -#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)) - -struct ef_data_0_reg { - /* 0x0 : ef_cfg_0 */ - union { - struct - { - uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t ef_sboot_en : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_11 : 4; /* [11: 8], rsvd, 0x0 */ - uint32_t ef_sw_usage_1 : 2; /* [13:12], r/w, 0x0 */ - uint32_t rsvd0 : 1; /* [ 14], r/w, 0x0 */ - uint32_t rsvd1 : 1; /* [ 15], r/w, 0x0 */ - uint32_t rsvd2 : 1; /* [ 16], r/w, 0x0 */ - uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ - uint32_t reserved_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t rsvd3 : 1; /* [ 19], r/w, 0x0 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t rsvd4 : 1; /* [ 21], r/w, 0x0 */ - uint32_t rsvd5 : 1; /* [ 22], r/w, 0x0 */ - uint32_t rsvd6 : 1; /* [ 23], r/w, 0x0 */ - uint32_t reserved_24_25 : 2; /* [25:24], rsvd, 0x0 */ - uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ - uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_cfg_0; - - /* 0x4 : ef_dbg_pwd_low */ - union { - struct - { - uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_dbg_pwd_low; - - /* 0x8 : ef_dbg_pwd_high */ - union { - struct - { - uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_dbg_pwd_high; - - /* 0xC : ef_ana_trim_0 */ - union { - struct - { - uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_ana_trim_0; - - /* 0x10 : ef_sw_usage_0 */ - union { - struct - { - uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_sw_usage_0; - - /* 0x14 : ef_wifi_mac_low */ - union { - struct - { - uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_wifi_mac_low; - - /* 0x18 : ef_wifi_mac_high */ - union { - struct - { - uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_wifi_mac_high; - - /* 0x1C : ef_key_slot_0_w0 */ - union { - struct - { - uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w0; - - /* 0x20 : ef_key_slot_0_w1 */ - union { - struct - { - uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w1; - - /* 0x24 : ef_key_slot_0_w2 */ - union { - struct - { - uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w2; - - /* 0x28 : ef_key_slot_0_w3 */ - union { - struct - { - uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w3; - - /* 0x2C : ef_key_slot_1_w0 */ - union { - struct - { - uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w0; - - /* 0x30 : ef_key_slot_1_w1 */ - union { - struct - { - uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w1; - - /* 0x34 : ef_key_slot_1_w2 */ - union { - struct - { - uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w2; - - /* 0x38 : ef_key_slot_1_w3 */ - union { - struct - { - uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w3; - - /* 0x3C : ef_key_slot_2_w0 */ - union { - struct - { - uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w0; - - /* 0x40 : ef_key_slot_2_w1 */ - union { - struct - { - uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w1; - - /* 0x44 : ef_key_slot_2_w2 */ - union { - struct - { - uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w2; - - /* 0x48 : ef_key_slot_2_w3 */ - union { - struct - { - uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w3; - - /* 0x4C : ef_key_slot_3_w0 */ - union { - struct - { - uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w0; - - /* 0x50 : ef_key_slot_3_w1 */ - union { - struct - { - uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w1; - - /* 0x54 : ef_key_slot_3_w2 */ - union { - struct - { - uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w2; - - /* 0x58 : ef_key_slot_3_w3 */ - union { - struct - { - uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w3; - - /* 0x5C : ef_key_slot_4_w0 */ - union { - struct - { - uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w0; - - /* 0x60 : ef_key_slot_4_w1 */ - union { - struct - { - uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w1; - - /* 0x64 : ef_key_slot_4_w2 */ - union { - struct - { - uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w2; - - /* 0x68 : ef_key_slot_4_w3 */ - union { - struct - { - uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w3; - - /* 0x6C : ef_key_slot_5_w0 */ - union { - struct - { - uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w0; - - /* 0x70 : ef_key_slot_5_w1 */ - union { - struct - { - uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w1; - - /* 0x74 : ef_key_slot_5_w2 */ - union { - struct - { - uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w2; - - /* 0x78 : ef_key_slot_5_w3 */ - union { - struct - { - uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w3; - - /* 0x7C : ef_data_0_lock */ - union { - struct - { - uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */ - uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */ - uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */ - uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */ - uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */ - uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */ - uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */ - uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */ - uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */ - uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */ - uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */ - uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */ - uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */ - uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */ - uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */ - uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */ - uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */ - uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */ - uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_data_0_lock; -}; - -typedef volatile struct ef_data_0_reg ef_data_0_reg_t; - -#endif /* __EF_DATA_0_REG_H__ */ diff --git a/drivers/soc/bl602/std/port/bl602_flash.c b/drivers/soc/bl602/std/port/bl602_flash.c deleted file mode 100644 index 0361e306..00000000 --- a/drivers/soc/bl602/std/port/bl602_flash.c +++ /dev/null @@ -1,254 +0,0 @@ -#include "bl602_glb.h" -#include "bl602_xip_sflash.h" -#include "bl602_xip_sflash_ext.h" -#include "bl602_sf_cfg.h" -#include "bl602_sf_cfg_ext.h" -#include "bflb_flash.h" - -static uint32_t g_jedec_id = 0; -static SPI_Flash_Cfg_Type g_flash_cfg; - -void ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_Qspi_Enable(p_flash_cfg); - } -} - -void ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { - L1C_Set_Wrap(DISABLE); - } else { - L1C_Set_Wrap(ENABLE); - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(p_flash_cfg); - } - } -} - -/** - * @brief flash_config_init - * - * @return int - */ -static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) -{ - int ret = -1; - uint8_t isAesEnable = 0; - uint32_t jid = 0; - uint32_t offset = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(&isAesEnable); - XIP_SFlash_State_Save(p_flash_cfg, &offset); - SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); - arch_memcpy(jedec_id, (uint8_t *)&jid, 3); - jid &= 0xFFFFFF; - g_jedec_id = jid; - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg); - if (ret == 0) { - p_flash_cfg->mid = (jid & 0xff); - } - - /* Set flash controler from p_flash_cfg */ - flash_set_qspi_enable(p_flash_cfg); - flash_set_l1c_wrap(p_flash_cfg); - XIP_SFlash_State_Restore_Ext(p_flash_cfg, offset); - XIP_SFlash_Opt_Exit(isAesEnable); - bflb_irq_restore(flag); - - return ret; -} - -/** - * @brief multi flash adapter - * - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_init(void) -{ - int ret = -1; - uint8_t clkDelay = 1; - uint8_t clkInvert = 1; - uint32_t jedec_id = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - SFlash_Cache_Flush(); - SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg); - SFlash_Cache_Flush(); - bflb_irq_restore(flag); - if (g_flash_cfg.mid != 0xff) { - return 0; - } - clkDelay = g_flash_cfg.clkDelay; - clkInvert = g_flash_cfg.clkInvert; - g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f; - - ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); - - g_flash_cfg.clkDelay = clkDelay; - g_flash_cfg.clkInvert = clkInvert; - - return ret; -} - -uint32_t bflb_flash_get_jedec_id(void) -{ - uint32_t jid = 0; - - jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16); - return jid; -} - -void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) -{ - *cfg_addr = (uint8_t *)&g_flash_cfg; - *len = sizeof(SPI_Flash_Cfg_Type); -} - -void bflb_flash_set_iomode(uint8_t iomode) -{ - g_flash_cfg.ioMode &= ~0x1f; - if (iomode == 4) { - g_flash_cfg.ioMode |= iomode; - } else { - g_flash_cfg.ioMode |= 0x10; - g_flash_cfg.ioMode |= iomode; - } -} - -ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void) -{ - return SF_Ctrl_Get_Flash_Image_Offset(); -} - -/** - * @brief flash erase - * - * @param startaddr - * @param endaddr - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len) -{ - int ret = -1; - uint8_t isAesEnable = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(&isAesEnable); - ret = XIP_SFlash_Erase_Need_Lock_Ext(&g_flash_cfg, startaddr, startaddr + len - 1); - XIP_SFlash_Opt_Exit(isAesEnable); - bflb_irq_restore(flag); - - return ret; -} - -/** - * @brief flash write data - * - * @param addr - * @param data - * @param len - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - int ret = -1; - uint8_t isAesEnable = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(&isAesEnable); - ret = XIP_SFlash_Write_Need_Lock_Ext(&g_flash_cfg, addr, data, len); - XIP_SFlash_Opt_Exit(isAesEnable); - bflb_irq_restore(flag); - - return ret; -} - -/** - * @brief flash read data - * - * @param addr - * @param data - * @param len - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - int ret = -1; - uint8_t isAesEnable = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(&isAesEnable); - ret = XIP_SFlash_Read_Need_Lock_Ext(&g_flash_cfg, addr, data, len); - XIP_SFlash_Opt_Exit(isAesEnable); - bflb_irq_restore(flag); - - return ret; -} - -int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) -{ - uint8_t isAesEnable = 0; - uint32_t tmp[1]; - int stat; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - - XIP_SFlash_Opt_Enter(&isAesEnable); - /* To make it simple, exit cont read anyway */ - SFlash_Reset_Continue_Read(&g_flash_cfg); - - if (g_flash_cfg.cReadSupport == 0) { - cont_read = 0; - } - - if (cont_read == 1) { - stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - - if (0 != stat) { - XIP_SFlash_Opt_Exit(isAesEnable); - return -1; - } - } - - /* Set default value */ - SFlash_Cache_Enable_Set(0xf); - - if (cache_enable) { - SF_Ctrl_Set_Flash_Image_Offset(flash_offset); - SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable); - } - XIP_SFlash_Opt_Exit(isAesEnable); - - return 0; -} - -void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config) -{ - uint8_t hw_key_enable = 0; - - if (config->key == NULL) { - hw_key_enable = 1; - } - - SF_Ctrl_AES_Set_Key_BE(config->region, (uint8_t *)config->key, config->keybits); - SF_Ctrl_AES_Set_IV_BE(config->region, (uint8_t *)config->iv, config->start_addr); - SF_Ctrl_AES_Set_Region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable); -} - -void bflb_flash_aes_enable(void) -{ - SF_Ctrl_AES_Enable(); -} - -void bflb_flash_aes_disable(void) -{ - SF_Ctrl_AES_Disable(); -} \ No newline at end of file diff --git a/drivers/soc/bl602/std/src/bl602_clock.c b/drivers/soc/bl602/std/src/bl602_clock.c index eb1c6c12..6dc62ec4 100644 --- a/drivers/soc/bl602/std/src/bl602_clock.c +++ b/drivers/soc/bl602/std/src/bl602_clock.c @@ -60,7 +60,7 @@ /** @defgroup CLOCK_Private_Variables * @{ */ -//static Clock_Cfg_Type clkCfg; +//static inline Clock_Cfg_Type clkCfg; /*@} end of group CLOCK_Private_Variables */ @@ -86,7 +86,7 @@ * @{ */ -static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) +static inline uint32_t Clock_Xtal_Output(void) { uint32_t tmpVal; @@ -121,7 +121,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) } } -static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_XClk_Mux_Output(uint8_t sel) { if (sel == 0) { /* rc32m */ @@ -132,7 +132,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) +static inline uint8_t Clock_Get_MCU_XClk_Sel_Val(void) { uint32_t tmpVal = 0; @@ -142,7 +142,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) return (tmpVal & 0x1); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_MCU_Root_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -152,7 +152,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) return ((tmpVal >> 1) & 0x1); } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_MCU_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* pll 48m */ @@ -171,7 +171,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) { uint32_t tmpVal; @@ -188,7 +188,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) +static inline uint8_t Clock_Get_MCU_HClk_Div_Val(void) { uint32_t tmpVal; @@ -197,7 +197,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) +static inline uint8_t Clock_Get_Peri_BClk_Div_Val(void) { uint32_t tmpVal; @@ -206,7 +206,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) +static inline uint32_t Clock_F32k_Mux_Output(uint8_t sel) { uint32_t tmpVal; uint32_t div = 0; @@ -225,7 +225,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) +static inline uint8_t Clock_Get_F32k_Sel_Val(void) { uint32_t tmpVal; @@ -281,7 +281,7 @@ uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type) } } -static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* fclk */ @@ -292,7 +292,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -301,7 +301,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) +static inline uint8_t Clock_Get_UART_Div_Val(void) { uint32_t tmpVal; @@ -310,13 +310,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(void) +static inline uint32_t Clock_SPI_Clk_Mux_Output(void) { /* pbclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) +static inline uint8_t Clock_Get_SPI_Div_Val(void) { uint32_t tmpVal; @@ -325,13 +325,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output() +static inline uint32_t Clock_I2C_Clk_Mux_Output() { /* pbclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) +static inline uint8_t Clock_Get_I2C_Div_Val(void) { uint32_t tmpVal; @@ -340,7 +340,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) +static inline uint8_t Clock_Get_GPADC_Div_Val(void) { uint32_t tmpVal; @@ -349,7 +349,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel) { if (sel == 0) { /* 96m */ @@ -360,7 +360,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -369,7 +369,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel) { uint32_t div = 0; @@ -382,7 +382,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -391,7 +391,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* pll 32m */ @@ -402,7 +402,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) +static inline uint8_t Clock_Get_GPDAC_Div_Val(void) { uint32_t tmpVal; @@ -411,7 +411,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -420,7 +420,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL); } -// static uint32_t ATTR_CLOCK_SECTION Clock_PWM_Clk_Mux_Output(uint8_t sel) +// static inline uint32_t Clock_PWM_Clk_Mux_Output(uint8_t sel) // { // if (sel == 0) { // /* xclk */ @@ -434,7 +434,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) // } // } -// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Div_Val(void) +// static inline uint8_t Clock_Get_PWM_Div_Val(void) // { // uint32_t tmpVal; @@ -443,7 +443,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) // return tmpVal; // } -// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Clk_Sel_Val(void) +// static inline uint8_t Clock_Get_PWM_Clk_Sel_Val(void) // { // uint32_t tmpVal; @@ -452,13 +452,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) // return BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL); // } -static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void) +static inline uint32_t Clock_IR_Clk_Mux_Output(void) { /* xclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) +static inline uint8_t Clock_Get_IR_Div_Val(void) { uint32_t tmpVal; @@ -467,7 +467,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void) { uint32_t tmpVal; @@ -476,7 +476,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* 120m */ @@ -490,7 +490,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* sf sel2 */ @@ -507,7 +507,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -516,7 +516,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) +static inline uint8_t Clock_Get_SF_Div_Val(void) { uint32_t tmpVal; diff --git a/drivers/soc/bl602/std/src/bl602_ef_ctrl.c b/drivers/soc/bl602/std/src/bl602_ef_ctrl.c deleted file mode 100644 index f08b5fc5..00000000 --- a/drivers/soc/bl602/std/src/bl602_ef_ctrl.c +++ /dev/null @@ -1,1872 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_sec_ef_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl602_ef_ctrl.h" -#include "ef_data_0_reg.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) -#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) -#define EF_CTRL_DFT_TIMEOUT_VAL (160 * 1000) -#ifndef BOOTROM -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#else -#define EF_CTRL_LOAD_BEFORE_READ_R0 -#endif -#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, EF_CTRL_EFUSE_R0_SIZE / 4) - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Switch efuse region 0 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Program */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - BL602_Delay_US(4); - - /* Trigger */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/*@} end of group SEC_EF_CTRL_Private_Functions */ - -/** @defgroup SEC_EF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Load efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - EF_CTRL_DATA0_CLEAR; - - /* Trigger read */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - BL602_Delay_US(10); - - /* Wait for efuse control idle*/ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - timeout--; - - if (timeout == 0) { - break; - } - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || - - (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); - - /* Switch to AHB clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse busy status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse whether finish loading - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { - return SET; - } else { - return RESET; - } -} -#endif - -/****************************************************************************/ /** - * @brief Efuse write debug password - * - * @param passWdLow: password low 32 bits - * @param passWdHigh: password high 32 bits - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read debug password - * - * @param passWdLow: password low 32 bits pointer to store value - * @param passWdHigh: password high 32 bits pointer to store value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh) -{ - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read LDO11 Vout sel trim - * - * @param Ldo11VoutSelValue: Ldo11VoutSelValue - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_Ldo11VoutSel_Opt(uint8_t *Ldo11VoutSelValue) -{ - uint32_t tmp; - Efuse_Ldo11VoutSelTrim_Info_Type *trim = (Efuse_Ldo11VoutSelTrim_Info_Type *)&tmp; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH)) >> 23; - - if (tmp & 0x01) { - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3)) >> 7; - - } else { - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3)) >> 7; - } - if (trim->en) { - if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->sel_value, 4)) { - *Ldo11VoutSelValue = trim->sel_value; - return SUCCESS; - } - } - return ERROR; -} - -/****************************************************************************/ /** - * @brief Efuse read LDO11 Vout sel trim - * - * @param TxPower: TxPower - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_TxPower_ATE(int8_t *TxPower) -{ - uint32_t tmp; - Efuse_TxPower_Info_Type *trim = (Efuse_TxPower_Info_Type *)&tmp; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH)) >> 23; - if (tmp & 0x01) { - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3)) >> 0; - } else { - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3)) >> 0; - } - //if(trim->en){ - if ((tmp >> 17) & 0x01) { //old en bit will be no longer used, now use bit17 as en bit - if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->txpower, 5)) { - if (trim->txpower >= 16) { - *TxPower = trim->txpower - 32; - } else { - *TxPower = trim->txpower; - } - - return SUCCESS; - } - } - return ERROR; -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE); - cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS); - cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN); - cfg->ef_no_hd_boot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_NO_HD_BOOT_EN); -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]); - - if (aes[0] != EF_CTRL_SF_AES_NONE) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN, 1); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE); - sign[0] = (EF_Ctrl_Sign_Type)(tmpVal2 & 0x01); - - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN); - - if (tmpVal2) { - aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE); - } else { - aes[0] = EF_CTRL_SF_AES_NONE; - } -} - -/****************************************************************************/ /** - * @brief Get whether do RC32K and RC32M trim - * - * @param None - * - * @return 1 for enable trim RC32M and RC32K, 0 for not - * -*******************************************************************************/ -uint8_t EF_Ctrl_Get_Trim_Enable(void) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - return BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_TRIM_EN); -} - -/****************************************************************************/ /** - * @brief Analog Trim parity calculate - * - * @param val: Value of efuse trim data - * @param len: Length of bit to calculate - * - * @return Parity bit value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) -{ - uint8_t cnt = 0; - uint8_t i = 0; - - for (i = 0; i < len; i++) { - if (val & (1 << i)) { - cnt++; - } - } - - return cnt & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse write analog trim - * - * @param index: index of analog trim - * @param trim: trim value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (index == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, trim); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read analog trim - * - * @param index: index of analog trim - * @param trim: trim value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (index == 0) { - *trim = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - } -} - -/****************************************************************************/ /** - * @brief Efuse read RC32M trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - trim->trimRc32mCodeFrExt = (tmpVal >> 10) & 0xff; - trim->trimRc32mCodeFrExtParity = (tmpVal >> 18) & 0x01; - trim->trimRc32mExtCodeEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32K trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - trim->trimRc32kCodeFrExt = (tmpVal >> 20) & 0x3ff; - trim->trimRc32kCodeFrExtParity = (tmpVal >> 30) & 0x01; - trim->trimRc32kExtCodeEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read TSEN trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - trim->tsenRefcodeCornerEn = tmpVal & 0x01; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - trim->tsenRefcodeCorner = tmpVal & 0xfff; - trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); - trim->tsenRefcodeCornerVersion = (tmpVal >> 30) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read ADC Gain trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - trim->adcGainCoeff = (tmpVal >> 1) & 0xfff; - trim->adcGainCoeffParity = (tmpVal >> 13) & 0x01; - trim->adcGainCoeffEn = (tmpVal >> 14) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write software usage - * - * @param index: index of software usage - * @param usage: usage value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) -{ - /* switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (index == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param usage: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (index == 0) { - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param program: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index == 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write MAC address - * - * @param mac[6]: MAC address buffer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse Ctrl get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[6]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0; - uint32_t cnt = 0; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[7]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - machigh[2] = (tmpVal >> 16) & 0xff; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for MAC address - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_MAC_Address(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Whether a value bits is all zero - * - * @param val: value to check - * @param start: start bit - * @param len: total length of bits to check - * - * @return 1 for all bits zero 0 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) -{ - uint32_t mask = 0; - - val = (val >> start); - - if (len >= 32) { - mask = 0xffffffff; - } else { - mask = (1 << len) - 1; - } - - if ((val & mask) == 0) { - return 1; - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief Whether MAC address slot is empty - * - * @param slot: MAC address slot - * @param reload: whether reload to check - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff; - uint32_t part1Empty = 0, part2Empty = 0; - - if (slot == 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); - } else if (slot == 2) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } - - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32)); - part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22)); - - return (part1Empty && part2Empty); -} - -/****************************************************************************/ /** - * @brief Efuse write optional MAC address - * - * @param slot: MAC address slot - * @param mac[6]: MAC address buffer - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0, cnt; - - if (slot >= 3) { - return ERROR; - } - - /* Change to local order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - if (slot == 2) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - } else { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - } - - /* The low 32 bits */ - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, BL_RDWD_FRM_BYTEP(maclow)); - } - - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - cnt = 0; - - for (i = 0; i < 6; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - tmpVal |= ((cnt & 0x3f) << 16); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, tmpVal); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, tmpVal); - } - - if (program) { - if (slot == 2) { - EF_Ctrl_Program_Efuse_0(); - } else { - EF_Ctrl_Program_Efuse_0(); - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read optional MAC address - * - * @param slot: MAC address slot - * @param mac[6]: MAC address buffer - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal = 0; - uint32_t i = 0; - uint32_t cnt = 0; - - if (slot >= 3) { - return ERROR; - } - - /* Trigger read data from efuse */ - if (reload) { - if (slot == 2) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } else { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - } - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - } - - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } - - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read chip ID - * - * @param chipID[8]: Chip ID buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) -{ - chipID[6] = 0; - chipID[7] = 0; - return EF_Ctrl_Read_MAC_Address(chipID); -} - -/****************************************************************************/ /** - * @brief Efuse read device info - * - * @param deviceInfo: Device info pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo) -{ - uint32_t tmpVal; - uint32_t *p = (uint32_t *)deviceInfo; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - *p = tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - deviceInfo->chip_ver = (tmpVal >> 8) & 0x07; -} - -/****************************************************************************/ /** - * @brief Whether Capcode slot is empty - * - * @param slot: Cap code slot - * @param reload: Whether reload - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp = 0xffffffff; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - return (EF_Ctrl_Is_All_Bits_Zero(tmp, 2, 8)); - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); - return (EF_Ctrl_Is_All_Bits_Zero(tmp, 22, 8)); - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - return (EF_Ctrl_Is_All_Bits_Zero(tmp, 22, 8)); - } - - return 0; -} - -/****************************************************************************/ /** - * @brief Efuse write Cap code - * - * @param slot: Cap code slot - * @param code: Cap code value - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program) -{ - uint32_t tmp; - uint8_t trim; - - if (slot >= 3) { - return ERROR; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } - - trim = code; - trim |= ((EF_Ctrl_Get_Trim_Parity(code, 6)) << 6); - trim |= (1 << 7); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp | (trim << 2)); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, tmp | (trim << 22)); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, tmp | (trim << 22)); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - - while (SET == EF_Ctrl_Busy()) - ; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read Cap code - * - * @param slot: Cap code slot - * @param code: Cap code pointer - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload) -{ - uint32_t tmp; - Efuse_Capcode_Info_Type *trim = (Efuse_Capcode_Info_Type *)&tmp; - - if (slot >= 3) { - return ERROR; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0)) >> 2; - } else if (slot == 1) { - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1)) >> 22; - } else if (slot == 2) { - tmp = (BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH)) >> 22; - } - - if (trim->en) { - if (trim->parity == EF_Ctrl_Get_Trim_Parity(trim->capCode, 6)) { - *code = trim->capCode; - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Whether power offset slot is empty - * - * @param slot: Power offset code slot - * @param reload: Whether reload - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp1 = 0xffffffff; - uint32_t part1Empty = 0, part2Empty = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 15, 17)); - part2Empty = 1; - } else if (slot == 1) { - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 16)); - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 1)); - } else if (slot == 2) { - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 16)); - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 1, 1)); - } - - return (part1Empty && part2Empty); -} - -/****************************************************************************/ /** - * @brief Efuse write power offset - * - * @param slot: Power offset slot - * @param pwrOffset[3]: Power offset value array - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program) -{ - uint64_t tmp = 0; - uint32_t k = 0; - uint64_t Value = 0; - uint8_t parity; - - if (slot >= 3) { - return ERROR; - } - - for (k = 0; k < 3; k++) { - /* Use 5 bits as signed value */ - if (pwrOffset[k] > 15) { - pwrOffset[k] = 15; - } - - if (pwrOffset[k] < -16) { - pwrOffset[k] = -16; - } - - tmp = ((uint64_t)((pwrOffset[k]) & 0x1f)) << (k * 5); - Value += tmp; - } - - parity = EF_Ctrl_Get_Trim_Parity(Value, 15); - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - tmp |= (Value << 16); - tmp |= (1 << 15); - tmp |= (uint32_t)(parity << 31); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp); - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - tmp |= (Value << 0); - tmp |= (uint32_t)(parity << 15); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmp); - - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - tmp |= (1 << 0); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp); - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - tmp |= (Value << 16); - tmp |= (uint32_t)(parity << 31); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmp); - - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - tmp |= (1 << 1); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, tmp); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - - while (SET == EF_Ctrl_Busy()) - ; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read poweroffset value - * - * @param slot: Power offset slot - * @param pwrOffset[3]: Power offset array - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload) -{ - uint64_t pwrOffsetValue = 0; - - uint32_t tmp = 0, k; - uint8_t en = 0, parity = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - en = (tmp >> 15) & 0x01; - pwrOffsetValue = (tmp >> 16) & 0x7fff; - parity = (tmp >> 31) & 0x01; - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - pwrOffsetValue = (tmp >> 0) & 0x7fff; - parity = (tmp >> 15) & 0x01; - - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - en = (tmp >> 0) & 0x01; - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - pwrOffsetValue = (tmp >> 16) & 0x7fff; - parity = (tmp >> 31) & 0x01; - - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - en = (tmp >> 1) & 0x01; - } - - if (en) { - if (parity == EF_Ctrl_Get_Trim_Parity(pwrOffsetValue, 15)) { - for (k = 0; k < 3; k++) { - tmp = (pwrOffsetValue >> (k * 5)) & 0x1f; - - if (tmp >= 16) { - pwrOffset[k] = tmp - 32; - } else { - pwrOffset[k] = tmp; - } - } - - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Efuse write AES key - * - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - - if (index > 5) { - return; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Every key is 4 words len*/ - BL602_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read AES key from specified region and index - * - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - - if (index > 5) { - return; - } - - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R0; - - /* Every key is 4 words len*/ - BL602_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for aes key - * - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if (index > 5) { - return; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index <= 3) { - tmpVal |= (1 << (index + 19)); - } else { - tmpVal |= (1 << (index + 19)); - tmpVal |= (1 << (index - 4 + 13)); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for aes key - * - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if (index > 5) { - return; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 26)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Program data to efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Add delay for CLK to be stable */ - BL602_Delay_US(4); - - BL602_MemCpy4(pEfuseStart0 + index, data, len); - - EF_Ctrl_Program_Efuse_0(); -} - -/****************************************************************************/ /** - * @brief Read data from efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - BL602_MemCpy4(data, pEfuseStart0 + index, len); -} - -/****************************************************************************/ /** - * @brief Write data to efuse region 0 without program - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Add delay for CLK to be stable */ - BL602_Delay_US(4); - - BL602_MemCpy4(pEfuseStart0 + index, data, len); -} - -/****************************************************************************/ /** - * @brief Read data from efuse region 0 without reload - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - BL602_MemCpy4(data, pEfuseStart0 + index, len); -} - -/****************************************************************************/ /** - * @brief Clear efuse data register - * - * @param index: index of efuse in word - * @param len: data length - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - uint32_t i = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart0[index + i] = 0; - } -} -#endif - -/****************************************************************************/ /** - * @brief efuse ctrl crc enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); - BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); - BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc busy status - * - * @param None - * - * @return DISABLE or ENABLE - * -*******************************************************************************/ -BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); -} - -/****************************************************************************/ /** - * @brief efuse ctrl set golden value - * - * @param goldenValue: Crc golden value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) -{ - BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc result - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Crc_Result(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/std/src/bl602_hbn.c b/drivers/soc/bl602/std/src/bl602_hbn.c index cda54a12..9f64ea3b 100644 --- a/drivers/soc/bl602/std/src/bl602_hbn.c +++ b/drivers/soc/bl602/std/src/bl602_hbn.c @@ -36,7 +36,7 @@ #include "bl602_hbn.h" #include "bl602_glb.h" -#include "bl602_xip_sflash.h" +#include "bflb_xip_sflash.h" // #include "risc-v/Core/Include/clic.h" /** @addtogroup BL602_Peripheral_Driver diff --git a/drivers/soc/bl602/std/src/bl602_romapi.c b/drivers/soc/bl602/std/src/bl602_romapi.c index c22dbcc6..5680504c 100644 --- a/drivers/soc/bl602/std/src/bl602_romapi.c +++ b/drivers/soc/bl602/std/src/bl602_romapi.c @@ -341,9 +341,9 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) #endif __ALWAYS_INLINE -void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flash_cfg) { - return RomDriver_HBN_Power_Down_Flash(flashCfg); + return RomDriver_HBN_Power_Down_Flash(flash_cfg); } #if 0 @@ -567,461 +567,465 @@ void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void) } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg) { - return RomDriver_SFlash_Init(pSfCtrlCfg); + return RomDriver_SFlash_Init(p_sf_ctrl_cfg); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +int ATTR_TCM_SECTION bflb_sflash_setspimode(uint8_t mode) { return RomDriver_SFlash_SetSPIMode(mode); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +int ATTR_TCM_SECTION bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen); + return RomDriver_SFlash_Read_Reg(flash_cfg, reg_index, reg_value, reg_len); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) +int ATTR_TCM_SECTION bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen); + return RomDriver_SFlash_Write_Reg(flash_cfg, reg_index, reg_value, reg_len); } __ALWAYS_INLINE -BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) +int ATTR_TCM_SECTION bflb_sflash_busy(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Busy(flashCfg); + return RomDriver_SFlash_Busy(flash_cfg); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +int ATTR_TCM_SECTION bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Write_Enable(flashCfg); + return RomDriver_SFlash_Write_Enable(flash_cfg); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) +int ATTR_TCM_SECTION bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Qspi_Enable(flashCfg); + return RomDriver_SFlash_Qspi_Enable(flash_cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); + return RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) +int ATTR_TCM_SECTION bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Chip_Erase(flashCfg); + return RomDriver_SFlash_Chip_Erase(flash_cfg); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) +int ATTR_TCM_SECTION bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sec_num) { - return RomDriver_SFlash_Sector_Erase(flashCfg, secNum); + return RomDriver_SFlash_Sector_Erase(flash_cfg, sec_num); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num) { - return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum); + return RomDriver_SFlash_Blk32_Erase(flash_cfg, blk_num); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +int ATTR_TCM_SECTION bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num) { - return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum); + return RomDriver_SFlash_Blk64_Erase(flash_cfg, blk_num); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) +int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t startaddr, uint32_t endaddr) { - return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr); + return RomDriver_SFlash_Erase(flash_cfg, startaddr, endaddr); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len) { - return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len); + return RomDriver_SFlash_Program(flash_cfg, io_mode, addr, data, len); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) +void ATTR_TCM_SECTION bflb_sflash_get_uniqueid(uint8_t *data, uint8_t idLen) { return RomDriver_SFlash_GetUniqueId(data, idLen); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) +void ATTR_TCM_SECTION bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data) { - return RomDriver_SFlash_GetJedecId(flashCfg, data); + return RomDriver_SFlash_GetJedecId(flash_cfg, data); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) +void ATTR_TCM_SECTION bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr) { return RomDriver_SFlash_GetDeviceId(data); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_Powerdown(void) +void ATTR_TCM_SECTION bflb_sflash_powerdown(void) { return RomDriver_SFlash_Powerdown(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Releae_Powerdown(flashCfg); + return RomDriver_SFlash_Releae_Powerdown(flash_cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_SetBurstWrap(flashCfg); + return RomDriver_SFlash_SetBurstWrap(flash_cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_DisableBurstWrap(flashCfg); + return RomDriver_SFlash_DisableBurstWrap(flash_cfg); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) +int ATTR_TCM_SECTION bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Software_Reset(flashCfg); + return RomDriver_SFlash_Software_Reset(flash_cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Reset_Continue_Read(flashCfg); + return RomDriver_SFlash_Reset_Continue_Read(flash_cfg); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) +int ATTR_TCM_SECTION bflb_sflash_set_idbus_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank) { - return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len); + return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg, io_mode, cont_read, addr, len); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) +int ATTR_TCM_SECTION bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank) { - return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead); + return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg, io_mode, cont_read); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable) +int ATTR_TCM_SECTION bflb_sflash_cache_enable_set(uint8_t way_disable) { - return RomDriver_SFlash_Cache_Enable_Set(wayDisable); + return RomDriver_SFlash_Cache_Enable_Set(way_disable); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Flush(void) +int ATTR_TCM_SECTION bflb_sflash_cache_flush(void) { return RomDriver_SFlash_Cache_Flush(); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) +int ATTR_TCM_SECTION bflb_sflash_cache_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t way_disable) { - return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable); + return RomDriver_SFlash_Cache_Read_Enable(flash_cfg, io_mode, cont_read, way_disable); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) +void ATTR_TCM_SECTION bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high) { - return RomDriver_SFlash_Cache_Hit_Count_Get(hitCountLow, hitCountHigh); + return RomDriver_SFlash_Cache_Hit_Count_Get(hit_count_low, hit_count_high); } __ALWAYS_INLINE -uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void) +uint32_t ATTR_TCM_SECTION bflb_l1c_miss_count_get(void) { return RomDriver_SFlash_Cache_Miss_Count_Get(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) +void ATTR_TCM_SECTION bflb_sflash_cache_read_disable(void) { return RomDriver_SFlash_Cache_Read_Disable(); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len) { - return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len); + return RomDriver_SFlash_Read(flash_cfg, io_mode, cont_read, addr, data, len); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen); + return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg, read_reg_cmd, reg_value, reg_len); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen); + return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg, write_reg_cmd, reg_value, reg_len); } #if 0 __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) +int ATTR_TCM_SECTION bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flashContRead) { - return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead); + return RomDriver_SFlash_Restore_From_Powerdown(p_flash_cfg, flashContRead); } #endif __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +int ATTR_TCM_SECTION bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin) { - return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); + return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) +void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void) { return RomDriver_SF_Cfg_Init_Internal_Flash_Gpio(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) +int ATTR_TCM_SECTION bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin) { - return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); + return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Cfg_Restore_GPIO17_Fun(uint8_t fun) +void ATTR_TCM_SECTION bflb_sf_cfg_restore_gpio17_fun(uint8_t fun) { return RomDriver_SF_Cfg_Restore_GPIO17_Fun(fun); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) { - return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg); + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) +int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default) { - return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); + return RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg, restore_default); } __ALWAYS_INLINE -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) +uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) { - return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg); + uint8_t auto_scan = 0; + uint8_t flash_pin = 0; + auto_scan = ((flash_pin_cfg >> 7) & 1); + flash_pin = (flash_pin_cfg & 0x7F); + return RomDriver_SF_Cfg_Flash_Identify(call_from_flash, auto_scan, flash_pin, restore_default, p_flash_cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +void ATTR_TCM_SECTION bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg) { return RomDriver_SF_Ctrl_Enable(cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel) +void ATTR_TCM_SECTION bflb_sf_ctrl_select_pad(uint8_t sel) { return RomDriver_SF_Ctrl_Select_Pad(sel); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +void ATTR_TCM_SECTION bflb_sf_ctrl_set_owner(uint8_t owner) { return RomDriver_SF_Ctrl_Set_Owner(owner); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Disable(void) +void ATTR_TCM_SECTION bflb_sf_ctrl_disable(void) { return RomDriver_SF_Ctrl_Disable(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_be(void) { return RomDriver_SF_Ctrl_AES_Enable_BE(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_le(void) { return RomDriver_SF_Ctrl_AES_Enable_LE(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hw_key, uint32_t start_addr, uint32_t end_addr, uint8_t locked) { - return RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked); + return RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hw_key, start_addr, end_addr, locked); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t keyType) { return RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t keyType) { return RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset) { - return RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset); + return RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addr_offset); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset) { - return RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset); + return RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addr_offset); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable(void) { return RomDriver_SF_Ctrl_AES_Enable(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) +void ATTR_TCM_SECTION bflb_sf_ctrl_aes_disable(void) { return RomDriver_SF_Ctrl_AES_Disable(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +void ATTR_TCM_SECTION bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank) { - return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset); + return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset); } __ALWAYS_INLINE -uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) +uint32_t ATTR_TCM_SECTION bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank) { return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +void ATTR_TCM_SECTION bflb_sf_ctrl_select_clock(uint8_t sahb_type) { - return RomDriver_SF_Ctrl_Select_Clock(sahbType); + return RomDriver_SF_Ctrl_Select_Clock(sahb_type); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +void ATTR_TCM_SECTION bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg) { return RomDriver_SF_Ctrl_SendCmd(cfg); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +void ATTR_TCM_SECTION bflb_sf_ctrl_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) { - return RomDriver_SF_Ctrl_Icache_Set(cfg, cmdValid); + return RomDriver_SF_Ctrl_Icache_Set(cfg, cmd_valid); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +void ATTR_TCM_SECTION bflb_sf_ctrl_icache2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) { - return RomDriver_SF_Ctrl_Icache2_Set(cfg, cmdValid); + return RomDriver_SF_Ctrl_Icache2_Set(cfg, cmd_valid); } __ALWAYS_INLINE -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) +uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_busy_state(void) { return RomDriver_SF_Ctrl_GetBusyState(); } __ALWAYS_INLINE -uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) +uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_is_aes_enable(void) { return RomDriver_SF_Ctrl_Is_AES_Enable(); } __ALWAYS_INLINE -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) +uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_clock_delay(void) { return RomDriver_SF_Ctrl_Get_Clock_Delay(); } __ALWAYS_INLINE -void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) +void ATTR_TCM_SECTION bflb_sf_ctrl_set_clock_delay(uint8_t delay) { return RomDriver_SF_Ctrl_Set_Clock_Delay(delay); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) +int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset); + return RomDriver_XIP_SFlash_State_Save(p_flash_cfg, offset); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset) +int ATTR_TCM_SECTION bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, offset); + return RomDriver_XIP_SFlash_State_Restore(p_flash_cfg, offset); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr) +int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, startaddr, endaddr); + return RomDriver_XIP_SFlash_Erase_Need_Lock(p_flash_cfg, startaddr, startaddr+len-1); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, data, len); + return RomDriver_XIP_SFlash_Write_Need_Lock(p_flash_cfg, addr, data, len); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, data, len); + return RomDriver_XIP_SFlash_Read_Need_Lock(p_flash_cfg, addr, data, len); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +int ATTR_TCM_SECTION bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, data); + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(p_flash_cfg, data); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, data); + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(p_flash_cfg, data); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen) +int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t idLen, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, data, idLen); + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(p_flash_cfg, data, idLen); } __ALWAYS_INLINE -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); } __ALWAYS_INLINE -void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) +void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable) { - return RomDriver_XIP_SFlash_Opt_Enter(aesEnable); + return RomDriver_XIP_SFlash_Opt_Enter(aes_enable); } __ALWAYS_INLINE -void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) +void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable) { - return RomDriver_XIP_SFlash_Opt_Exit(aesEnable); + return RomDriver_XIP_SFlash_Opt_Exit(aes_enable); } __ALWAYS_INLINE diff --git a/drivers/soc/bl602/std/src/bl602_romdriver.c b/drivers/soc/bl602/std/src/bl602_romdriver.c new file mode 100644 index 00000000..e14b4772 --- /dev/null +++ b/drivers/soc/bl602/std/src/bl602_romdriver.c @@ -0,0 +1,291 @@ +/** + ****************************************************************************** + * @file bl602_romdriver.c + * @version V1.0 + * @date + * @brief This file is the standard driver c file + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +#include "bl602_romdriver.h" +#include + +/** @addtogroup BL602_Periph_Driver + * @{ + */ + +/** @defgroup ROMDRIVER + * @brief ROMDRIVER common functions + * @{ + */ + +/** @defgroup ROMDRIVER_Private_Type + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Type*/ + +/** @defgroup ROMDRIVER_Private_Defines + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Defines */ + +/** @defgroup ROMDRIVER_Private_Variables + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Variables */ + +/** @defgroup ROMDRIVER_Global_Variables + * @{ + */ + +uint32_t const romDriverTable[] = { + 0x06020002, + 0x00000000, + 0x00000000, + 0x00000000, + + [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG, + [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG, + [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL, + [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode, + [ROM_API_INDEX_AON_Get_Xtal_CapCode] = (uint32_t)AON_Get_Xtal_CapCode, + [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL, + [ROM_API_INDEX_AON_Power_On_BG] = (uint32_t)AON_Power_On_BG, + [ROM_API_INDEX_AON_Power_Off_BG] = (uint32_t)AON_Power_Off_BG, + [ROM_API_INDEX_AON_Power_On_LDO11_SOC] = (uint32_t)AON_Power_On_LDO11_SOC, + [ROM_API_INDEX_AON_Power_Off_LDO11_SOC] = (uint32_t)AON_Power_Off_LDO11_SOC, + [ROM_API_INDEX_AON_Power_On_LDO15_RF] = (uint32_t)AON_Power_On_LDO15_RF, + [ROM_API_INDEX_AON_Power_Off_LDO15_RF] = (uint32_t)AON_Power_Off_LDO15_RF, + [ROM_API_INDEX_AON_Power_On_SFReg] = (uint32_t)AON_Power_On_SFReg, + [ROM_API_INDEX_AON_Power_Off_SFReg] = (uint32_t)AON_Power_Off_SFReg, + [ROM_API_INDEX_AON_LowPower_Enter_PDS0] = (uint32_t)AON_LowPower_Enter_PDS0, + [ROM_API_INDEX_AON_LowPower_Exit_PDS0] = (uint32_t)AON_LowPower_Exit_PDS0, + + [ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us, + + [ROM_API_INDEX_BL602_Delay_US] = (uint32_t)BL602_Delay_US, + [ROM_API_INDEX_BL602_Delay_MS] = (uint32_t)BL602_Delay_MS, + [ROM_API_INDEX_BL602_MemCpy] = (uint32_t)BL602_MemCpy, + [ROM_API_INDEX_BL602_MemCpy4] = (uint32_t)BL602_MemCpy4, + [ROM_API_INDEX_BL602_MemCpy_Fast] = (uint32_t)BL602_MemCpy_Fast, + [ROM_API_INDEX_BL602_MemSet] = (uint32_t)BL602_MemSet, + [ROM_API_INDEX_BL602_MemSet4] = (uint32_t)BL602_MemSet4, + [ROM_API_INDEX_BL602_MemCmp] = (uint32_t)BL602_MemCmp, + + [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0, + [ROM_API_INDEX_EF_Ctrl_Program_Efuse_0] = (uint32_t)EF_Ctrl_Program_Efuse_0, + [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0, + [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy, + [ROM_API_INDEX_EF_Ctrl_AutoLoad_Done] = (uint32_t)EF_Ctrl_AutoLoad_Done, + [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity, + [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim, + [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim, + [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear, + + [ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel, + [ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div, + [ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div, + [ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div, + + [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL] = (uint32_t)Update_SystemCoreClockWith_XTAL, + + [ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK, + + [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M, + + [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK, + [ROM_API_INDEX_GLB_Set_PKA_CLK_Sel] = (uint32_t)GLB_Set_PKA_CLK_Sel, + [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset, + [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset, + [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset, + [ROM_API_INDEX_GLB_Select_Internal_Flash] = (uint32_t)GLB_Select_Internal_Flash, + [ROM_API_INDEX_GLB_Select_External_Flash] = (uint32_t)GLB_Select_External_Flash, + [ROM_API_INDEX_GLB_Deswap_Flash_Pin] = (uint32_t)GLB_Deswap_Flash_Pin, + [ROM_API_INDEX_GLB_Swap_Flash_Pin] = (uint32_t)GLB_Swap_Flash_Pin, + [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable, + [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable, + [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ, + [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun, + + [ROM_API_INDEX_HBN_Mode_Enter] = (uint32_t)HBN_Mode_Enter, + [ROM_API_INDEX_HBN_Power_Down_Flash] = (uint32_t)HBN_Power_Down_Flash, + [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable, + [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset, + [ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout] = (uint32_t)HBN_Set_Ldo11_Aon_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout] = (uint32_t)HBN_Set_Ldo11_Rt_Vout, + [ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout] = (uint32_t)HBN_Set_Ldo11_Soc_Vout, + [ROM_API_INDEX_HBN_32K_Sel] = (uint32_t)HBN_32K_Sel, + [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel, + [ROM_API_INDEX_HBN_Power_On_Xtal_32K] = (uint32_t)HBN_Power_On_Xtal_32K, + [ROM_API_INDEX_HBN_Power_Off_Xtal_32K] = (uint32_t)HBN_Power_Off_Xtal_32K, + [ROM_API_INDEX_HBN_Power_On_RC32K] = (uint32_t)HBN_Power_On_RC32K, + [ROM_API_INDEX_HBN_Power_Off_RC32K] = (uint32_t)HBN_Power_Off_RC32K, + [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K, + [ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg] = (uint32_t)HBN_Hw_Pu_Pd_Cfg, + [ROM_API_INDEX_HBN_Pin_WakeUp_Mask] = (uint32_t)HBN_Pin_WakeUp_Mask, + [ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO7_Dbg_Pull_Cfg, + [ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup] = (uint32_t)HBN_Set_Embedded_Flash_Pullup, + + [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap, + [ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable, + [ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set, + + [ROM_API_INDEX_PDS_Reset] = (uint32_t)PDS_Reset, + [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable, + [ROM_API_INDEX_PDS_Force_Config] = (uint32_t)PDS_Force_Config, + [ROM_API_INDEX_PDS_RAM_Config] = (uint32_t)PDS_RAM_Config, + [ROM_API_INDEX_PDS_Default_Level_Config] = (uint32_t)PDS_Default_Level_Config, + [ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M, + [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref, + [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref] = (uint32_t)PDS_Select_XTAL_As_PLL_Ref, + [ROM_API_INDEX_PDS_Power_On_PLL] = (uint32_t)PDS_Power_On_PLL, + [ROM_API_INDEX_PDS_Enable_PLL_All_Clks] = (uint32_t)PDS_Enable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Disable_PLL_All_Clks] = (uint32_t)PDS_Disable_PLL_All_Clks, + [ROM_API_INDEX_PDS_Enable_PLL_Clk] = (uint32_t)PDS_Enable_PLL_Clk, + [ROM_API_INDEX_PDS_Disable_PLL_Clk] = (uint32_t)PDS_Disable_PLL_Clk, + [ROM_API_INDEX_PDS_Power_Off_PLL] = (uint32_t)PDS_Power_Off_PLL, + + [ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring] = (uint32_t)SEC_Eng_Turn_On_Sec_Ring, + [ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring] = (uint32_t)SEC_Eng_Turn_Off_Sec_Ring, + + [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init, + [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode, + [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg, + [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg, + [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy, + [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable, + [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable, + [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable, + [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase, + [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase, + [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase, + [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase, + [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase, + [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program, + [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId, + [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId, + [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId, + [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown, + [ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown, + [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap, + [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap, + [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset, + [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read, + [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg, + [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Enable_Set] = (uint32_t)SFlash_Cache_Enable_Set, + [ROM_API_INDEX_SFlash_Cache_Flush] = (uint32_t)SFlash_Cache_Flush, + [ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable, + [ROM_API_INDEX_SFlash_Cache_Hit_Count_Get] = (uint32_t)SFlash_Cache_Hit_Count_Get, + [ROM_API_INDEX_SFlash_Cache_Miss_Count_Get] = (uint32_t)SFlash_Cache_Miss_Count_Get, + [ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable, + [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read, + [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd, + [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown, + + [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Internal_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun] = (uint32_t)SF_Cfg_Restore_GPIO17_Fun, + [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock, + [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio, + [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify, + [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable, + [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad, + [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner, + [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key, + [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV, + [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE, + [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable, + [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset, + [ROM_API_INDEX_SF_Ctrl_Select_Clock] = (uint32_t)SF_Ctrl_Select_Clock, + [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd, + [ROM_API_INDEX_SF_Ctrl_Icache_Set] = (uint32_t)SF_Ctrl_Icache_Set, + [ROM_API_INDEX_SF_Ctrl_Icache2_Set] = (uint32_t)SF_Ctrl_Icache2_Set, + [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState, + [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable, + [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay, + [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay, + + [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save, + [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore, + [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock, + [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock, + [ROM_API_INDEX_XIP_SFlash_Opt_Enter] = (uint32_t)XIP_SFlash_Opt_Enter, + [ROM_API_INDEX_XIP_SFlash_Opt_Exit] = (uint32_t)XIP_SFlash_Opt_Exit, + + [ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32, + + [ROM_API_INDEX_FUNC_EMPTY_START... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef, +}; + +/*@} end of group ROMDRIVER_Global_Variables */ + +/** @defgroup ROMDRIVER_Private_FunctionDeclaration + * @{ + */ + +/*@} end of group ROMDRIVER_Private_FunctionDeclaration */ + +/** @defgroup ROMDRIVER_Private_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Private_Functions */ + +/** @defgroup ROMDRIVER_Public_Functions + * @{ + */ + +/*@} end of group ROMDRIVER_Public_Functions */ + +/*@} end of group ROMDRIVER_COMMON */ + +/*@} end of group BL602_Periph_Driver */ diff --git a/drivers/soc/bl602/std/src/bl602_sf_cfg.c b/drivers/soc/bl602/std/src/bl602_sf_cfg.c deleted file mode 100644 index 8cbc7398..00000000 --- a/drivers/soc/bl602/std/src/bl602_sf_cfg.c +++ /dev/null @@ -1,2193 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_sf_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl602_glb.h" -#include "bl602_sf_cfg.h" -#include "bl602_xip_sflash.h" -#include "soft_crc.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_Private_Macros */ - -/** @defgroup SF_CFG_Private_Types - * @{ - */ -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; - -/*@} end of group SF_CFG_Private_Types */ - -/** @defgroup SF_CFG_Private_Variables - * @{ - */ -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; -#if 0 -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80BV = -{ - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; -#endif -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x9d, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x00, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x06, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 5, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 32 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 8 / 8, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0x12, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32C = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 45, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx_Q80B_F16B = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x0B, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x14, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 6000, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x0B, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 6000, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x85, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x85, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x68, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1440ef, - //.name="Winb_80DV_08_33", - .cfg = &flashCfg_Winb_80DV, - }, - { - .jedecID = 0x1540ef, - //.name="Winb_16DV_16_33", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1570ef, - //.name="Winb_16jV_16_33_DTR", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1640ef, - //.name="Winb_32FV_32_33", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1460ef, - //.name="Winb_80EW_08_18", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1560ef, - //.name="Winb_16FW_16_18", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1660ef, - //.name="Winb_32FW_32_18", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1860ef, - //.name="Winb_128FW_128_18", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1680ef, - //.name="Winb_32JW_32_18", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x13605e, - //.name="Zbit_04_33", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x14605e, - //.name="Zbit_08_33", - .cfg = &flashCfg_Winb_80EW_16JV_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x14609d, - //.name="ISSI_08_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x15609d, - //.name="ISSI_16_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x16609d, - //.name="ISSI_32_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x14709d, - //.name="ISSI_08_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x15709d, - //.name="ISSI_16_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x16709d, - //.name="ISSI_32_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x1440C8, - //.name="GD_Q08E_08_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1540C8, - //.name="GD_Q16E_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1640C8, - //.name="GD_Q32C_32_33", - .cfg = &flashCfg_Gd_Q32C, - }, - { - .jedecID = 0x1460C8, - //.name="GD_LQ08C_08_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1560C8, - //.name="GD_LE16C_16_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1660C8, - //.name="GD_LQ32D_32_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1465C8, - //.name="GD_WQ80E_80_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1565C8, - //.name="GD_WQ16E_16_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1665C8, - //.name="GD_WQ32E_32_33", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x3425C2, - //.name="MX_25V80_08_18", - .cfg = &flashCfg_Mxic, - }, - { - .jedecID = 0x3525C2, - //.name="MX_25U16_35_18", - .cfg = &flashCfg_Mxic_1635F, - }, - { - .jedecID = 0x3625C2, - //.name="MX_25V32_32_18", - .cfg = &flashCfg_Mxic, - }, - { - .jedecID = 0x13400B, - //.name="XT_25F04D_04_33", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x15400B, - //.name="XT_25F16B_16_33", - .cfg = &flashCfg_Xtx_Q80B_F16B, - }, - { - .jedecID = 0x16400B, - //.name="XT_25F32B_32_33", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x14600B, - //.name="XT_25Q80B_08_18", - .cfg = &flashCfg_Xtx_Q80B_F16B, - }, - { - .jedecID = 0x16600B, - //.name="XT_25Q32B_32_18", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x146085, - //.name="Puya_Q80L/H_08_18/33", - .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, - }, - { - .jedecID = 0x156085, - //.name="Puya_Q16H_16_33", - .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, - }, - { - .jedecID = 0x166085, - //.name="Puya_Q32H_32_33", - .cfg = &flashCfg_Puya_Q32H, - }, - { - .jedecID = 0x154068, - //.name="Boya_Q16B_16_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x164068, - //.name="Boya_Q32B_32_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x174068, - //.name="Boya_Q64A_64_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x184068, - //.name="Boya_Q128A_128_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x14605E, - //.name="FT_VQ80", - .cfg = &flashCfg_FT_VQ80, - } -}; - -/*@} end of group SF_CFG_Private_Variables */ - -/** @defgroup SF_CFG_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_Global_Variables */ - -/** @defgroup SF_CFG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_FLASH; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else { - gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - - if (i == 0 || i == 1) { - /*flash clk and cs is output*/ - cfg.gpioMode = GPIO_MODE_OUTPUT; - } else { - /*data are bidir*/ - cfg.gpioMode = GPIO_MODE_AF; - } - - GLB_GPIO_Init(&cfg); - } -} - -/****************************************************************************/ /** - * @brief Init internal flash GPIO according to flash GPIO config - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) -{ - GLB_GPIO_Cfg_Type gpioCfg = { - .gpioPin = GLB_GPIO_PIN_0, - .gpioFun = GPIO_FUN_SWGPIO, - .gpioMode = GPIO_MODE_INPUT, - .pullType = GPIO_PULL_NONE, - .drive = 0, - .smtCtrl = 1, - }; - - /* Turn on Flash pad, GPIO23 - GPIO28 */ - for (uint32_t pin = 23; pin < 29; pin++) { - gpioCfg.gpioPin = pin; - - if (pin == 24) { - gpioCfg.pullType = GPIO_PULL_DOWN; - } else { - gpioCfg.pullType = GPIO_PULL_NONE; - } - - GLB_GPIO_Init(&gpioCfg); - } -} - -/****************************************************************************/ /** - * @brief Deinit external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_SWGPIO; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - - } else { - gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - GLB_GPIO_Init(&cfg); - } -} - -/****************************************************************************/ /** - * @brief Restore GPIO17 function - * - * @param fun: GPIO17 function - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Cfg_Restore_GPIO17_Fun(uint8_t fun) -{ - GLB_GPIO_Cfg_Type cfg; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioPin = GLB_GPIO_PIN_17; - cfg.gpioFun = fun; - GLB_GPIO_Init(&cfg); -} - -/*@} end of group SF_CFG_Private_Functions */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - - if (flashID == 0) { - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL602_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); - - if (BL602_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - BL602_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - BL602_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Init flash GPIO according to flash Pin config - * - * @param flashPinCfg: Specify flash Pin config - * @param restoreDefault: Wether to restore default setting - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) -{ - if (restoreDefault) { - /* Set Default first */ - SF_Ctrl_Select_Pad(SF_CTRL_EMBEDDED_SEL); - GLB_Select_Internal_Flash(); - GLB_Swap_Flash_Pin(); - //SF_Cfg_Deinit_Ext_Flash_Gpio(0); - SF_Cfg_Deinit_Ext_Flash_Gpio(1); - SF_Cfg_Init_Internal_Flash_Gpio(); - } - - if (flashPinCfg > 0) { - /*01: deswap flash PIN - 10: use ext flash 1(GPIO17-22) - 11: use ext flash 0(GPIO0-2, 20-22) - */ - if (flashPinCfg == BFLB_FLASH_CFG_DESWAP) { - SF_Ctrl_Select_Pad(SF_CTRL_EMBEDDED_SEL); - /*DONOT Swap flash PIN*/ - GLB_Deswap_Flash_Pin(); - } else { - SF_Ctrl_Select_Pad(flashPinCfg - 1); - GLB_Select_External_Flash(); - SF_Cfg_Init_Ext_Flash_Gpio(flashPinCfg - BFLB_FLASH_CFG_EXT0_17_22); - } - } -} - -/****************************************************************************/ /** - * @brief Identify one flash - * - * @param callFromFlash: code run at flash or ram - * @param autoScan: Auto scan all GPIO pin - * @param flashPinCfg: Specify flash GPIO config, not auto scan - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * - * @return Flash ID - * -*******************************************************************************/ -__WEAK -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, - uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) -{ - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t offset; - BL_Err_Type stat; - uint8_t gpio17_fun = 0; - - BL602_MemCpy_Fast(pFlashCfg, &flashCfg_Gd_Q80E_Q16E, sizeof(SPI_Flash_Cfg_Type)); - - if (callFromFlash == 1) { - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - return 0; - } - } - - if (autoScan) { - flashPinCfg = 0; - - do { - if (flashPinCfg > BFLB_FLASH_CFG_EXT1_0_2_20_22) { - jdecId = 0; - break; - } - - if (flashPinCfg > BFLB_FLASH_CFG_EXT0_17_22) { - /*flashPinCfg=2 has make gpio17 into jtag,but not success*/ - SF_Cfg_Restore_GPIO17_Fun(gpio17_fun); - } - - /* select media gpio */ - if (flashPinCfg == BFLB_FLASH_CFG_EXT0_17_22) { - gpio17_fun = GLB_GPIO_Get_Fun(GLB_GPIO_PIN_17); - } - - SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = 0; - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - flashPinCfg++; - } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); - } else { - /* select media gpio */ - SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - } - - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - BL602_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - break; - } - } - - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return jdecId; - } else { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); - } -} -#endif - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c b/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c index 2a9ceca6..d5059ec1 100644 --- a/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c +++ b/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c @@ -35,9 +35,9 @@ */ #include "bl602_glb.h" -#include "bl602_sf_cfg.h" #include "bl602_sf_cfg_ext.h" -#include "bl602_xip_sflash.h" +#include "bflb_sf_cfg.h" +#include "bflb_xip_sflash.h" #include "bl602_romdriver.h" #include "soft_crc.h" @@ -60,626 +60,626 @@ * @{ */ typedef struct { - uint32_t jedecID; + uint32_t jedec_id; char *name; - const SPI_Flash_Cfg_Type *cfg; -}Flash_Info_t; + const spi_flash_cfg_type *cfg; +}flash_info_t; /*@} end of group SF_CFG_EXT_Private_Types */ /** @defgroup SF_CFG_EXT_Private_Variables * @{ */ -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_25Q08={ - .resetCreadCmd=0xff, - .resetCreadCmdSize=3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_fm_25q08={ + .reset_c_read_cmd=0xff, + .reset_c_read_cmd_size=3, .mid=0xc8, - .deBurstWrapCmd=0x77, - .deBurstWrapCmdDmyClk=0x3, - .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, - .deBurstWrapData=0xF0, + .de_burst_wrap_cmd=0x77, + .de_burst_wrap_cmd_dmy_clk=0x3, + .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data=0xF0, /*reg*/ - .writeEnableCmd=0x06, - .wrEnableIndex=0x00, - .wrEnableBit=0x01, - .wrEnableReadRegLen=0x01, + .write_enable_cmd=0x06, + .wr_enable_index=0x00, + .wr_enable_bit=0x01, + .wr_enable_read_reg_len=0x01, - .qeIndex=1, - .qeBit=0x01, - .qeWriteRegLen=0x02, - .qeReadRegLen=0x1, + .qe_index=1, + .qe_bit=0x01, + .qe_write_reg_len=0x02, + .qe_read_reg_len=0x1, - .busyIndex=0, - .busyBit=0x00, - .busyReadRegLen=0x1, - .releasePowerDown=0xab, + .busy_index=0, + .busy_bit=0x00, + .busy_read_reg_len=0x1, + .release_powerdown=0xab, - .readRegCmd[0]=0x05, - .readRegCmd[1]=0x35, - .writeRegCmd[0]=0x01, - .writeRegCmd[1]=0x01, + .read_reg_cmd[0]=0x05, + .read_reg_cmd[1]=0x35, + .write_reg_cmd[0]=0x01, + .write_reg_cmd[1]=0x01, - .fastReadQioCmd=0xeb, - .frQioDmyClk=16/8, - .cReadSupport=1, - .cReadMode=0xa0, + .fast_read_qio_cmd=0xeb, + .fr_qio_dmy_clk=16/8, + .c_read_support=1, + .c_read_mode=0xa0, - .burstWrapCmd=0x77, - .burstWrapCmdDmyClk=0x3, - .burstWrapDataMode=SF_CTRL_DATA_4_LINES, - .burstWrapData=0x40, + .burst_wrap_cmd=0x77, + .burst_wrap_cmd_dmy_clk=0x3, + .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .burst_wrap_data=0x40, /*erase*/ - .chipEraseCmd=0xc7, - .sectorEraseCmd=0x20, - .blk32EraseCmd=0x52, - .blk64EraseCmd=0xd8, + .chip_erase_cmd=0xc7, + .sector_erase_cmd=0x20, + .blk32_erase_cmd=0x52, + .blk64_erase_cmd=0xd8, /*write*/ - .pageProgramCmd=0x02, - .qpageProgramCmd=0x32, - .qppAddrMode=SF_CTRL_ADDR_1_LINE, + .page_program_cmd=0x02, + .qpage_program_cmd=0x32, + .qpp_addr_mode=SF_CTRL_ADDR_1_LINE, - .ioMode=SF_CTRL_QIO_MODE, - .clkDelay=1, - .clkInvert=0x01, + .io_mode=SF_CTRL_QIO_MODE, + .clk_delay=1, + .clk_invert=0x01, - .resetEnCmd=0x66, - .resetCmd=0x99, - .cRExit=0xff, - .wrEnableWriteRegLen=0x00, + .reset_en_cmd=0x66, + .reset_cmd=0x99, + .c_rexit=0xff, + .wr_enable_write_reg_len=0x00, /*id*/ - .jedecIdCmd=0x9f, - .jedecIdCmdDmyClk=0, - .qpiJedecIdCmd=0x9f, - .qpiJedecIdCmdDmyClk=0x00, - .sectorSize=4, - .pageSize=256, + .jedec_id_cmd=0x9f, + .jedec_id_cmd_dmy_clk=0, + .qpi_jedec_id_cmd=0x9f, + .qpi_jedec_id_cmd_dmy_clk=0x00, + .sector_size=4, + .page_size=256, /*read*/ - .fastReadCmd=0x0b, - .frDmyClk=8/8, - .qpiFastReadCmd =0x0b, - .qpiFrDmyClk=8/8, - .fastReadDoCmd=0x3b, - .frDoDmyClk=8/8, - .fastReadDioCmd=0xbb, - .frDioDmyClk=0, - .fastReadQoCmd=0x6b, - .frQoDmyClk=8/8, + .fast_read_cmd=0x0b, + .fr_dmy_clk=8/8, + .qpi_fast_read_cmd =0x0b, + .qpi_fr_dmy_clk=8/8, + .fast_read_do_cmd=0x3b, + .fr_do_dmy_clk=8/8, + .fast_read_dio_cmd=0xbb, + .fr_dio_dmy_clk=0, + .fast_read_qo_cmd=0x6b, + .fr_qo_dmy_clk=8/8, - .qpiFastReadQioCmd=0xeb, - .qpiFrQioDmyClk=16/8, - .qpiPageProgramCmd=0x02, - .writeVregEnableCmd=0x50, + .qpi_fast_read_qio_cmd=0xeb, + .qpi_fr_qio_dmy_clk=16/8, + .qpi_page_program_cmd=0x02, + .write_vreg_enable_cmd=0x50, /* qpi mode */ - .enterQpi=0x38, - .exitQpi=0xff, + .enter_qpi=0x38, + .exit_qpi=0xff, /*AC*/ - .timeEsector=300, - .timeE32k=1200, - .timeE64k=1200, - .timePagePgm=5, - .timeCe=33000, - .pdDelay=20, - .qeData=0, + .time_e_sector=300, + .time_e_32k=1200, + .time_e_64k=1200, + .time_page_pgm=5, + .time_ce=33000, + .pd_delay=20, + .qe_data=0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={ - .resetCreadCmd=0xff, - .resetCreadCmdSize=3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_gd_md_40d={ + .reset_c_read_cmd=0xff, + .reset_c_read_cmd_size=3, .mid=0x51, - .deBurstWrapCmd=0x77, - .deBurstWrapCmdDmyClk=0x3, - .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, - .deBurstWrapData=0xF0, + .de_burst_wrap_cmd=0x77, + .de_burst_wrap_cmd_dmy_clk=0x3, + .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data=0xF0, /*reg*/ - .writeEnableCmd=0x06, - .wrEnableIndex=0x00, - .wrEnableBit=0x01, - .wrEnableReadRegLen=0x01, + .write_enable_cmd=0x06, + .wr_enable_index=0x00, + .wr_enable_bit=0x01, + .wr_enable_read_reg_len=0x01, - .qeIndex=1, - .qeBit=0x01, - .qeWriteRegLen=0x02, - .qeReadRegLen=0x1, + .qe_index=1, + .qe_bit=0x01, + .qe_write_reg_len=0x02, + .qe_read_reg_len=0x1, - .busyIndex=0, - .busyBit=0x00, - .busyReadRegLen=0x1, - .releasePowerDown=0xab, + .busy_index=0, + .busy_bit=0x00, + .busy_read_reg_len=0x1, + .release_powerdown=0xab, - .readRegCmd[0]=0x05, - .readRegCmd[1]=0x35, - .writeRegCmd[0]=0x01, - .writeRegCmd[1]=0x01, + .read_reg_cmd[0]=0x05, + .read_reg_cmd[1]=0x35, + .write_reg_cmd[0]=0x01, + .write_reg_cmd[1]=0x01, - .fastReadQioCmd=0xeb, - .frQioDmyClk=16/8, - .cReadSupport=0, - .cReadMode=0xA0, + .fast_read_qio_cmd=0xeb, + .fr_qio_dmy_clk=16/8, + .c_read_support=0, + .c_read_mode=0xA0, - .burstWrapCmd=0x77, - .burstWrapCmdDmyClk=0x3, - .burstWrapDataMode=SF_CTRL_DATA_4_LINES, - .burstWrapData=0x40, + .burst_wrap_cmd=0x77, + .burst_wrap_cmd_dmy_clk=0x3, + .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .burst_wrap_data=0x40, /*erase*/ - .chipEraseCmd=0xc7, - .sectorEraseCmd=0x20, - .blk32EraseCmd=0x52, - .blk64EraseCmd=0xd8, + .chip_erase_cmd=0xc7, + .sector_erase_cmd=0x20, + .blk32_erase_cmd=0x52, + .blk64_erase_cmd=0xd8, /*write*/ - .pageProgramCmd=0x02, - .qpageProgramCmd=0x32, - .qppAddrMode=SF_CTRL_ADDR_1_LINE, + .page_program_cmd=0x02, + .qpage_program_cmd=0x32, + .qpp_addr_mode=SF_CTRL_ADDR_1_LINE, - .ioMode=0x11, - .clkDelay=1, - .clkInvert=0x01, + .io_mode=0x11, + .clk_delay=1, + .clk_invert=0x01, - .resetEnCmd=0x66, - .resetCmd=0x99, - .cRExit=0xff, - .wrEnableWriteRegLen=0x00, + .reset_en_cmd=0x66, + .reset_cmd=0x99, + .c_rexit=0xff, + .wr_enable_write_reg_len=0x00, /*id*/ - .jedecIdCmd=0x9f, - .jedecIdCmdDmyClk=0, - .qpiJedecIdCmd=0x9f, - .qpiJedecIdCmdDmyClk=0x00, - .sectorSize=4, - .pageSize=256, + .jedec_id_cmd=0x9f, + .jedec_id_cmd_dmy_clk=0, + .qpi_jedec_id_cmd=0x9f, + .qpi_jedec_id_cmd_dmy_clk=0x00, + .sector_size=4, + .page_size=256, /*read*/ - .fastReadCmd=0x0b, - .frDmyClk=8/8, - .qpiFastReadCmd =0x0b, - .qpiFrDmyClk=8/8, - .fastReadDoCmd=0x3b, - .frDoDmyClk=8/8, - .fastReadDioCmd=0xbb, - .frDioDmyClk=0, - .fastReadQoCmd=0x6b, - .frQoDmyClk=8/8, + .fast_read_cmd=0x0b, + .fr_dmy_clk=8/8, + .qpi_fast_read_cmd =0x0b, + .qpi_fr_dmy_clk=8/8, + .fast_read_do_cmd=0x3b, + .fr_do_dmy_clk=8/8, + .fast_read_dio_cmd=0xbb, + .fr_dio_dmy_clk=0, + .fast_read_qo_cmd=0x6b, + .fr_qo_dmy_clk=8/8, - .qpiFastReadQioCmd=0xeb, - .qpiFrQioDmyClk=16/8, - .qpiPageProgramCmd=0x02, - .writeVregEnableCmd=0x50, + .qpi_fast_read_qio_cmd=0xeb, + .qpi_fr_qio_dmy_clk=16/8, + .qpi_page_program_cmd=0x02, + .write_vreg_enable_cmd=0x50, /* qpi mode */ - .enterQpi=0x38, - .exitQpi=0xff, + .enter_qpi=0x38, + .exit_qpi=0xff, /*AC*/ - .timeEsector=300, - .timeE32k=1200, - .timeE64k=1200, - .timePagePgm=5, - .timeCe=33000, - .pdDelay=20, - .qeData=0, + .time_e_sector=300, + .time_e_32k=1200, + .time_e_64k=1200, + .time_page_pgm=5, + .time_ce=33000, + .pd_delay=20, + .qe_data=0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={ - .resetCreadCmd=0xff, - .resetCreadCmdSize=3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_xm25qh16={ + .reset_c_read_cmd=0xff, + .reset_c_read_cmd_size=3, .mid=0x20, - .deBurstWrapCmd=0x77, - .deBurstWrapCmdDmyClk=0x3, - .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, - .deBurstWrapData=0xF0, + .de_burst_wrap_cmd=0x77, + .de_burst_wrap_cmd_dmy_clk=0x3, + .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data=0xF0, /*reg*/ - .writeEnableCmd=0x06, - .wrEnableIndex=0x00, - .wrEnableBit=0x01, - .wrEnableReadRegLen=0x01, + .write_enable_cmd=0x06, + .wr_enable_index=0x00, + .wr_enable_bit=0x01, + .wr_enable_read_reg_len=0x01, - .qeIndex=1, - .qeBit=0x01, - .qeWriteRegLen=0x01, - .qeReadRegLen=0x1, + .qe_index=1, + .qe_bit=0x01, + .qe_write_reg_len=0x01, + .qe_read_reg_len=0x1, - .busyIndex=0, - .busyBit=0x00, - .busyReadRegLen=0x1, - .releasePowerDown=0xab, + .busy_index=0, + .busy_bit=0x00, + .busy_read_reg_len=0x1, + .release_powerdown=0xab, - .readRegCmd[0]=0x05, - .readRegCmd[1]=0x35, - .writeRegCmd[0]=0x01, - .writeRegCmd[1]=0x31, + .read_reg_cmd[0]=0x05, + .read_reg_cmd[1]=0x35, + .write_reg_cmd[0]=0x01, + .write_reg_cmd[1]=0x31, - .fastReadQioCmd=0xeb, - .frQioDmyClk=16/8, - .cReadSupport=1, - .cReadMode=0x20, + .fast_read_qio_cmd=0xeb, + .fr_qio_dmy_clk=16/8, + .c_read_support=1, + .c_read_mode=0x20, - .burstWrapCmd=0x77, - .burstWrapCmdDmyClk=0x3, - .burstWrapDataMode=SF_CTRL_DATA_4_LINES, - .burstWrapData=0x40, + .burst_wrap_cmd=0x77, + .burst_wrap_cmd_dmy_clk=0x3, + .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .burst_wrap_data=0x40, /*erase*/ - .chipEraseCmd=0xc7, - .sectorEraseCmd=0x20, - .blk32EraseCmd=0x52, - .blk64EraseCmd=0xd8, + .chip_erase_cmd=0xc7, + .sector_erase_cmd=0x20, + .blk32_erase_cmd=0x52, + .blk64_erase_cmd=0xd8, /*write*/ - .pageProgramCmd=0x02, - .qpageProgramCmd=0x32, - .qppAddrMode=SF_CTRL_ADDR_1_LINE, + .page_program_cmd=0x02, + .qpage_program_cmd=0x32, + .qpp_addr_mode=SF_CTRL_ADDR_1_LINE, - .ioMode=SF_CTRL_QIO_MODE, - .clkDelay=1, - .clkInvert=0x01, + .io_mode=SF_CTRL_QIO_MODE, + .clk_delay=1, + .clk_invert=0x01, - .resetEnCmd=0x66, - .resetCmd=0x99, - .cRExit=0xff, - .wrEnableWriteRegLen=0x00, + .reset_en_cmd=0x66, + .reset_cmd=0x99, + .c_rexit=0xff, + .wr_enable_write_reg_len=0x00, /*id*/ - .jedecIdCmd=0x9f, - .jedecIdCmdDmyClk=0, - .qpiJedecIdCmd=0x9f, - .qpiJedecIdCmdDmyClk=0x00, - .sectorSize=4, - .pageSize=256, + .jedec_id_cmd=0x9f, + .jedec_id_cmd_dmy_clk=0, + .qpi_jedec_id_cmd=0x9f, + .qpi_jedec_id_cmd_dmy_clk=0x00, + .sector_size=4, + .page_size=256, /*read*/ - .fastReadCmd=0x0b, - .frDmyClk=8/8, - .qpiFastReadCmd =0x0b, - .qpiFrDmyClk=8/8, - .fastReadDoCmd=0x3b, - .frDoDmyClk=8/8, - .fastReadDioCmd=0xbb, - .frDioDmyClk=0, - .fastReadQoCmd=0x6b, - .frQoDmyClk=8/8, + .fast_read_cmd=0x0b, + .fr_dmy_clk=8/8, + .qpi_fast_read_cmd =0x0b, + .qpi_fr_dmy_clk=8/8, + .fast_read_do_cmd=0x3b, + .fr_do_dmy_clk=8/8, + .fast_read_dio_cmd=0xbb, + .fr_dio_dmy_clk=0, + .fast_read_qo_cmd=0x6b, + .fr_qo_dmy_clk=8/8, - .qpiFastReadQioCmd=0xeb, - .qpiFrQioDmyClk=16/8, - .qpiPageProgramCmd=0x02, - .writeVregEnableCmd=0x50, + .qpi_fast_read_qio_cmd=0xeb, + .qpi_fr_qio_dmy_clk=16/8, + .qpi_page_program_cmd=0x02, + .write_vreg_enable_cmd=0x50, /* qpi mode */ - .enterQpi=0x38, - .exitQpi=0xff, + .enter_qpi=0x38, + .exit_qpi=0xff, /*AC*/ - .timeEsector=400, - .timeE32k=1600, - .timeE64k=2000, - .timePagePgm=5, - .timeCe=33000, - .pdDelay=3, - .qeData=0, + .time_e_sector=400, + .time_e_32k=1600, + .time_e_64k=2000, + .time_page_pgm=5, + .time_ce=33000, + .pd_delay=3, + .qe_data=0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25={ - .resetCreadCmd=0xff, - .resetCreadCmdSize=3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_mx_kh25={ + .reset_c_read_cmd=0xff, + .reset_c_read_cmd_size=3, .mid=0xc2, - .deBurstWrapCmd=0x77, - .deBurstWrapCmdDmyClk=0x3, - .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, - .deBurstWrapData=0xF0, + .de_burst_wrap_cmd=0x77, + .de_burst_wrap_cmd_dmy_clk=0x3, + .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data=0xF0, /*reg*/ - .writeEnableCmd=0x06, - .wrEnableIndex=0x00, - .wrEnableBit=0x01, - .wrEnableReadRegLen=0x01, + .write_enable_cmd=0x06, + .wr_enable_index=0x00, + .wr_enable_bit=0x01, + .wr_enable_read_reg_len=0x01, - .qeIndex=1, - .qeBit=0x01, - .qeWriteRegLen=0x01, - .qeReadRegLen=0x1, + .qe_index=1, + .qe_bit=0x01, + .qe_write_reg_len=0x01, + .qe_read_reg_len=0x1, - .busyIndex=0, - .busyBit=0x00, - .busyReadRegLen=0x1, - .releasePowerDown=0xab, + .busy_index=0, + .busy_bit=0x00, + .busy_read_reg_len=0x1, + .release_powerdown=0xab, - .readRegCmd[0]=0x05, - .readRegCmd[1]=0x00, - .writeRegCmd[0]=0x01, - .writeRegCmd[1]=0x00, + .read_reg_cmd[0]=0x05, + .read_reg_cmd[1]=0x00, + .write_reg_cmd[0]=0x01, + .write_reg_cmd[1]=0x00, - .fastReadQioCmd=0xeb, - .frQioDmyClk=16/8, - .cReadSupport=0, - .cReadMode=0x20, + .fast_read_qio_cmd=0xeb, + .fr_qio_dmy_clk=16/8, + .c_read_support=0, + .c_read_mode=0x20, - .burstWrapCmd=0x77, - .burstWrapCmdDmyClk=0x3, - .burstWrapDataMode=SF_CTRL_DATA_4_LINES, - .burstWrapData=0x40, + .burst_wrap_cmd=0x77, + .burst_wrap_cmd_dmy_clk=0x3, + .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .burst_wrap_data=0x40, /*erase*/ - .chipEraseCmd=0xc7, - .sectorEraseCmd=0x20, - .blk32EraseCmd=0x52, - .blk64EraseCmd=0xd8, + .chip_erase_cmd=0xc7, + .sector_erase_cmd=0x20, + .blk32_erase_cmd=0x52, + .blk64_erase_cmd=0xd8, /*write*/ - .pageProgramCmd=0x02, - .qpageProgramCmd=0x32, - .qppAddrMode=SF_CTRL_ADDR_1_LINE, + .page_program_cmd=0x02, + .qpage_program_cmd=0x32, + .qpp_addr_mode=SF_CTRL_ADDR_1_LINE, - .ioMode=0x11, - .clkDelay=1, - .clkInvert=0x01, + .io_mode=0x11, + .clk_delay=1, + .clk_invert=0x01, - .resetEnCmd=0x66, - .resetCmd=0x99, - .cRExit=0xff, - .wrEnableWriteRegLen=0x00, + .reset_en_cmd=0x66, + .reset_cmd=0x99, + .c_rexit=0xff, + .wr_enable_write_reg_len=0x00, /*id*/ - .jedecIdCmd=0x9f, - .jedecIdCmdDmyClk=0, - .qpiJedecIdCmd=0x9f, - .qpiJedecIdCmdDmyClk=0x00, - .sectorSize=4, - .pageSize=256, + .jedec_id_cmd=0x9f, + .jedec_id_cmd_dmy_clk=0, + .qpi_jedec_id_cmd=0x9f, + .qpi_jedec_id_cmd_dmy_clk=0x00, + .sector_size=4, + .page_size=256, /*read*/ - .fastReadCmd=0x0b, - .frDmyClk=8/8, - .qpiFastReadCmd =0x0b, - .qpiFrDmyClk=8/8, - .fastReadDoCmd=0x3b, - .frDoDmyClk=8/8, - .fastReadDioCmd=0xbb, - .frDioDmyClk=0, - .fastReadQoCmd=0x6b, - .frQoDmyClk=8/8, + .fast_read_cmd=0x0b, + .fr_dmy_clk=8/8, + .qpi_fast_read_cmd =0x0b, + .qpi_fr_dmy_clk=8/8, + .fast_read_do_cmd=0x3b, + .fr_do_dmy_clk=8/8, + .fast_read_dio_cmd=0xbb, + .fr_dio_dmy_clk=0, + .fast_read_qo_cmd=0x6b, + .fr_qo_dmy_clk=8/8, - .qpiFastReadQioCmd=0xeb, - .qpiFrQioDmyClk=16/8, - .qpiPageProgramCmd=0x02, - .writeVregEnableCmd=0x50, + .qpi_fast_read_qio_cmd=0xeb, + .qpi_fr_qio_dmy_clk=16/8, + .qpi_page_program_cmd=0x02, + .write_vreg_enable_cmd=0x50, /* qpi mode */ - .enterQpi=0x38, - .exitQpi=0xff, + .enter_qpi=0x38, + .exit_qpi=0xff, /*AC*/ - .timeEsector=300, - .timeE32k=1200, - .timeE64k=1200, - .timePagePgm=5, - .timeCe=33000, - .pdDelay=20, - .qeData=0, + .time_e_sector=300, + .time_e_32k=1200, + .time_e_64k=1200, + .time_page_pgm=5, + .time_ce=33000, + .pd_delay=20, + .qe_data=0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_ZD_25Q16B={ - .resetCreadCmd=0xff, - .resetCreadCmdSize=3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_zd_25q16b={ + .reset_c_read_cmd=0xff, + .reset_c_read_cmd_size=3, .mid=0xba, - .deBurstWrapCmd=0x77, - .deBurstWrapCmdDmyClk=0x3, - .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, - .deBurstWrapData=0xF0, + .de_burst_wrap_cmd=0x77, + .de_burst_wrap_cmd_dmy_clk=0x3, + .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data=0xF0, /*reg*/ - .writeEnableCmd=0x06, - .wrEnableIndex=0x00, - .wrEnableBit=0x01, - .wrEnableReadRegLen=0x01, + .write_enable_cmd=0x06, + .wr_enable_index=0x00, + .wr_enable_bit=0x01, + .wr_enable_read_reg_len=0x01, - .qeIndex=1, - .qeBit=0x01, - .qeWriteRegLen=0x02, - .qeReadRegLen=0x1, + .qe_index=1, + .qe_bit=0x01, + .qe_write_reg_len=0x02, + .qe_read_reg_len=0x1, - .busyIndex=0, - .busyBit=0x00, - .busyReadRegLen=0x1, - .releasePowerDown=0xab, + .busy_index=0, + .busy_bit=0x00, + .busy_read_reg_len=0x1, + .release_powerdown=0xab, - .readRegCmd[0]=0x05, - .readRegCmd[1]=0x35, - .writeRegCmd[0]=0x01, - .writeRegCmd[1]=0x01, + .read_reg_cmd[0]=0x05, + .read_reg_cmd[1]=0x35, + .write_reg_cmd[0]=0x01, + .write_reg_cmd[1]=0x01, - .fastReadQioCmd=0xeb, - .frQioDmyClk=16/8, - .cReadSupport=1, - .cReadMode=0xa0, + .fast_read_qio_cmd=0xeb, + .fr_qio_dmy_clk=16/8, + .c_read_support=1, + .c_read_mode=0xa0, - .burstWrapCmd=0x77, - .burstWrapCmdDmyClk=0x3, - .burstWrapDataMode=SF_CTRL_DATA_4_LINES, - .burstWrapData=0x40, + .burst_wrap_cmd=0x77, + .burst_wrap_cmd_dmy_clk=0x3, + .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES, + .burst_wrap_data=0x40, /*erase*/ - .chipEraseCmd=0xc7, - .sectorEraseCmd=0x20, - .blk32EraseCmd=0x52, - .blk64EraseCmd=0xd8, + .chip_erase_cmd=0xc7, + .sector_erase_cmd=0x20, + .blk32_erase_cmd=0x52, + .blk64_erase_cmd=0xd8, /*write*/ - .pageProgramCmd=0x02, - .qpageProgramCmd=0x32, - .qppAddrMode=SF_CTRL_ADDR_1_LINE, + .page_program_cmd=0x02, + .qpage_program_cmd=0x32, + .qpp_addr_mode=SF_CTRL_ADDR_1_LINE, - .ioMode=0x14, - .clkDelay=1, - .clkInvert=0x01, + .io_mode=0x14, + .clk_delay=1, + .clk_invert=0x01, - .resetEnCmd=0x66, - .resetCmd=0x99, - .cRExit=0xff, - .wrEnableWriteRegLen=0x00, + .reset_en_cmd=0x66, + .reset_cmd=0x99, + .c_rexit=0xff, + .wr_enable_write_reg_len=0x00, /*id*/ - .jedecIdCmd=0x9f, - .jedecIdCmdDmyClk=0, - .qpiJedecIdCmd=0x9f, - .qpiJedecIdCmdDmyClk=0x00, - .sectorSize=4, - .pageSize=256, + .jedec_id_cmd=0x9f, + .jedec_id_cmd_dmy_clk=0, + .qpi_jedec_id_cmd=0x9f, + .qpi_jedec_id_cmd_dmy_clk=0x00, + .sector_size=4, + .page_size=256, /*read*/ - .fastReadCmd=0x0b, - .frDmyClk=8/8, - .qpiFastReadCmd =0x0b, - .qpiFrDmyClk=8/8, - .fastReadDoCmd=0x3b, - .frDoDmyClk=8/8, - .fastReadDioCmd=0xbb, - .frDioDmyClk=0, - .fastReadQoCmd=0x6b, - .frQoDmyClk=8/8, + .fast_read_cmd=0x0b, + .fr_dmy_clk=8/8, + .qpi_fast_read_cmd =0x0b, + .qpi_fr_dmy_clk=8/8, + .fast_read_do_cmd=0x3b, + .fr_do_dmy_clk=8/8, + .fast_read_dio_cmd=0xbb, + .fr_dio_dmy_clk=0, + .fast_read_qo_cmd=0x6b, + .fr_qo_dmy_clk=8/8, - .qpiFastReadQioCmd=0xeb, - .qpiFrQioDmyClk=16/8, - .qpiPageProgramCmd=0x02, - .writeVregEnableCmd=0x50, + .qpi_fast_read_qio_cmd=0xeb, + .qpi_fr_qio_dmy_clk=16/8, + .qpi_page_program_cmd=0x02, + .write_vreg_enable_cmd=0x50, /* qpi mode */ - .enterQpi=0x38, - .exitQpi=0xff, + .enter_qpi=0x38, + .exit_qpi=0xff, /*AC*/ - .timeEsector=300, - .timeE32k=1200, - .timeE64k=1200, - .timePagePgm=5, - .timeCe=33000, - .pdDelay=20, - .qeData=0, + .time_e_sector=300, + .time_e_32k=1200, + .time_e_64k=1200, + .time_page_pgm=5, + .time_ce=33000, + .pd_delay=20, + .qe_data=0, }; -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={ +static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[]={ { - .jedecID=0x1440A1, + .jedec_id=0x1440A1, //.name="FM_25Q08", - .cfg=&flashCfg_FM_25Q08, + .cfg=&flashcfg_fm_25q08, }, { - .jedecID=0x134051, + .jedec_id=0x134051, //.name="GD_MD04D_04_33", - .cfg=&flashCfg_Gd_Md_40D, + .cfg=&flashcfg_gd_md_40d, }, { - .jedecID=0x144020, + .jedec_id=0x144020, //.name="XM_25QH80_80_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x154020, + .jedec_id=0x154020, //.name="XM_25QH16_16_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x164020, + .jedec_id=0x164020, //.name="XM_25QH32_32_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x174020, + .jedec_id=0x174020, //.name="XM_25QH64_64_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x1320C2, + .jedec_id=0x1320C2, //.name="MX_KH40_04_33", - .cfg=&flashCfg_MX_KH25, + .cfg=&flashcfg_mx_kh25, }, { - .jedecID=0x1420C2, + .jedec_id=0x1420C2, //.name="MX_KH80_08_33", - .cfg=&flashCfg_MX_KH25, + .cfg=&flashcfg_mx_kh25, }, { - .jedecID=0x1520C2, + .jedec_id=0x1520C2, //.name="MX_KH16_16_33", - .cfg=&flashCfg_MX_KH25, + .cfg=&flashcfg_mx_kh25, }, { - .jedecID=0x13325E, + .jedec_id=0x13325E, //.name="ZB_D40B_80_33", - .cfg=&flashCfg_MX_KH25, + .cfg=&flashcfg_mx_kh25, }, { - .jedecID=0x14325E, + .jedec_id=0x14325E, //.name="ZB_D80B_80_33", - .cfg=&flashCfg_MX_KH25, + .cfg=&flashcfg_mx_kh25, }, { - .jedecID=0x15405E, + .jedec_id=0x15405E, //.name="ZB_25Q16B_15_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x16405E, + .jedec_id=0x16405E, //.name="ZB_25Q32B_16_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x17405E, + .jedec_id=0x17405E, //.name="ZB_25VQ64_64_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x15605E, + .jedec_id=0x15605E, //.name="ZB_25VQ16_16_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x15345E, + .jedec_id=0x15345E, //.name="ZB_25WQ16_16_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x1560EB, + .jedec_id=0x1560EB, //.name="TH_25Q16", - .cfg=&flashCfg_FM_25Q08, + .cfg=&flashcfg_fm_25q08, }, { - .jedecID=0x1740C8, + .jedec_id=0x1740C8, //.name="GD_25Q64E_64_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x1840C8, + .jedec_id=0x1840C8, //.name="GD_25Q127C_128_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x176085, + .jedec_id=0x176085, //.name="Puya_P25Q64H_64_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, { - .jedecID=0x17400B, + .jedec_id=0x17400B, //.name="XT_25F64B", - .cfg=&flashCfg_FM_25Q08, + .cfg=&flashcfg_fm_25q08, }, { - .jedecID=0x1560BA, + .jedec_id=0x1560BA, //.name="ZD_25Q16B", - .cfg=&flashCfg_ZD_25Q16B, + .cfg=&flashcfg_zd_25q16b, }, { - .jedecID=0x1460CD, + .jedec_id=0x1460CD, //.name="TH_25Q80HB", - .cfg=&flashCfg_FM_25Q08, + .cfg=&flashcfg_fm_25q08, }, { - .jedecID=0x1870EF, + .jedec_id=0x1870EF, //.name="W25Q128JV_128_33", - .cfg=&flashCfg_XM25QH16, + .cfg=&flashcfg_xm25qh16, }, }; @@ -704,82 +704,85 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={ /****************************************************************************//** * @brief Get flash config according to flash ID * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer + * @param flash_id: Flash ID + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg) +int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type * p_flash_cfg, + uint8_t group, uint8_t bank) { uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type)+8]; - uint32_t crc,*pCrc; - char flashCfgMagic[] = "FCFG"; + uint8_t buf[sizeof(spi_flash_cfg_type)+8]; + uint32_t crc,*p_crc; + char flash_cfg_magic[] = "FCFG"; - if(flashID==0){ - XIP_SFlash_Read_Via_Cache_Need_Lock(8+BL602_FLASH_XIP_BASE,buf,sizeof(SPI_Flash_Cfg_Type)+8); - if(BL602_MemCmp(buf,flashCfgMagic,4)==0){ - crc=BFLB_Soft_CRC32((uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type)); - pCrc=(uint32_t *)(buf+4+sizeof(SPI_Flash_Cfg_Type)); - if(*pCrc==crc){ - BL602_MemCpy_Fast(pFlashCfg,(uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS ; + if(flash_id==0){ + bflb_xip_sflash_read_via_cache_need_lock(8+BL602_FLASH_XIP_BASE,buf,sizeof(spi_flash_cfg_type)+8,group,bank); + if(BL602_MemCmp(buf,flash_cfg_magic,4)==0){ + crc=BFLB_Soft_CRC32((uint8_t *)buf+4,sizeof(spi_flash_cfg_type)); + p_crc=(uint32_t *)(buf+4+sizeof(spi_flash_cfg_type)); + if(*p_crc==crc){ + BL602_MemCpy_Fast(p_flash_cfg,(uint8_t *)buf+4,sizeof(spi_flash_cfg_type)); + return 0 ; } } }else{ - if(SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS){ - return SUCCESS; + if(bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank) == 0){ + return 0; } - for(i=0;iioMode&0xf,1,0,32); + ret=bflb_sf_cfg_flash_identify(call_from_flash,flash_in_cfg,restore_default,p_flash_cfg,group,bank); + if(call_from_flash){ + bflb_sflash_set_xip_cfg(p_flash_cfg,p_flash_cfg->io_mode&0xf,1,0,32,bank); } if((ret&BFLB_FLASH_ID_VALID_FLAG)!=0){ return ret; } - jdecId=(ret&0xffffff); - for(i=0;i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl602_sf_ctrl.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Private_Macros - * @{ - */ - -/*@} end of group SF_CTRL_Private_Macros */ - -/** @defgroup SF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SF_CTRL_Private_Types */ - -/** @defgroup SF_CTRL_Private_Variables - * @{ - */ -#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) -#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100) - -/*@} end of group SF_CTRL_Private_Variables */ - -/** @defgroup SF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SF_CTRL_Global_Variables */ - -/** @defgroup SF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SF_CTRL_Private_Functions - * @{ - */ - -/*@} end of group SF_CTRL_Private_Functions */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Enable serail flash controller - * - * @param cfg: serial flash controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - if (cfg == NULL) { - return; - } - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (cfg->clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - /* Serail out inverted, so sf ctrl send on negative edge */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); - - /* Set do di and oe delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4, tmpVal); - - /* Enable AHB access sram buffer and enable sf interface */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); - - SF_Ctrl_Set_Owner(cfg->owner); -} - -/****************************************************************************/ /** - * @brief Flash pad select - * - * @param sel: pad type - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Sel sel) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_SEL(sel)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set flash controller owner:I/D AHB or system AHB - * - * @param owner: owner type - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - /* Set owner */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); - - /* Set iahb to flash interface */ - if (owner == SF_CTRL_OWNER_IAHB) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable flash controller - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable flash controller AES with big indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable flash controller AES with little indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Serial flash controller set AES region - * - * @param region: region number - * @param enable: enable or not - * @param hwKey: hardware key or software key - * @param startAddr: region start address - * @param endAddr: region end address - * @param locked: lock this region or not - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, - uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); - uint32_t tmpVal; - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_CFG); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); - /* sf_aes_end =1 means 1,11,1111,1111 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - tmpVal -= 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, !region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - tmpVal += 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} - -/****************************************************************************/ /** - * @brief Enable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set flash image offset - * - * @param addrOffset: Address offset value - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) -{ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); -} - -/****************************************************************************/ /** - * @brief Get flash image offset - * - * @param None - * - * @return :Address offset value - * -*******************************************************************************/ -__WEAK -uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) -{ - return BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); -} - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param sahbType: Serial flash controller clock sahb sram select - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (sahbType == SF_CTRL_SAHB_CLOCK) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); - } else if (sahbType == SF_CTRL_FLASH_CLOCK) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param cfg: Serial flash controller command configuration pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { - return; - } - - /* Clear trigger */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_2, cfg->cmdBuf[1]); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); - } - - /* Configure cmd */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_CMD_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_CMD_BYTE, 0); - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, 0); - } - - /* Configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, cfg->nbData - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_RW, cfg->rwFlag); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); - - //switch sf_clk_sahb_sram_sel = 1 - SF_Ctrl_Select_Clock(SF_CTRL_FLASH_CLOCK); - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); - return; - } - } - - //switch sf_clk_sahb_sram_sel = 0 - SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); -} - -/****************************************************************************/ /** - * @brief Config SF controller for I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Config SF controller for I/D cache write - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, cache may need no command - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Icache2_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_4, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_5, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get SF Ctrl busy state - * - * @param None - * - * @return SET for SF ctrl busy or RESET for SF ctrl not busy - * -*******************************************************************************/ -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Check is serial flash controller AES enable - * - * @param None - * - * @return Wether AES is enable - * -*******************************************************************************/ -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - return BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN); -} - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param None - * - * @return Clock delay value - * -*******************************************************************************/ -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { - return 0; - } else { - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } -} - -/****************************************************************************/ /** - * @brief Set flash controller clock delay value - * - * @param delay: Clock delay value - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (delay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Controller interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void) -{ - /* TODO: Not implemented */ -} -#endif - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/std/src/bl602_sflash.c b/drivers/soc/bl602/std/src/bl602_sflash.c deleted file mode 100644 index d0784417..00000000 --- a/drivers/soc/bl602/std/src/bl602_sflash.c +++ /dev/null @@ -1,1549 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl602_sflash.h" -#include "bl602_sf_ctrl.h" -#include "bl602_l1c.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLASH - * @{ - */ - -/** @defgroup SFLASH_Private_Macros - * @{ - */ - -/*@} end of group SFLASH_Private_Macros */ - -/** @defgroup SFLASH_Private_Types - * @{ - */ - -/*@} end of group SFLASH_Private_Types */ - -/** @defgroup SFLASH_Private_Variables - * @{ - */ -#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) - -/*@} end of group SFLASH_Private_Variables */ - -/** @defgroup SFLASH_Global_Variables - * @{ - */ - -/*@} end of group SFLASH_Global_Variables */ - -/** @defgroup SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SFLASH_Private_Fun_Declaration */ - -/** @defgroup SFLASH_Private_Functions - * @{ - */ - -/*@} end of group SFLASH_Private_Functions */ - -/** @defgroup SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init serial flash control interface - * - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) -{ - SF_Ctrl_Enable(pSfCtrlCfg); -} - -/****************************************************************************/ /** - * @brief Set serial flash control interface SPI or QPI mode - * - * @param mode: Serial flash interface mode - * - * @return BFLB_RET:SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) -{ - BL_Err_Type stat = SUCCESS; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); - - return stat; -} - -/****************************************************************************/ /** - * @brief Read flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - BL602_Delay_US(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - BL602_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Write flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - BL602_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Check flash busy status - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SET for busy or RESET for not busy - * -*******************************************************************************/ -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); - - if ((stat & (1 << flashCfg->busyBit)) == 0) { - return RESET; - } - - return SET; -} - -/****************************************************************************/ /** - * @brief Enable flash write function - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Write enable*/ - flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); - - if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { - return SUCCESS; - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Enable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); - } else { - stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); - stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); - } - } else { - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit % 8)); - } else { - stat = flashCfg->qeData; - } - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Enable flash volatile register write enable - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); -} - -/****************************************************************************/ /** - * @brief Erase flash whole chip - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeCe * 3) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one sector - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param secNum: flash sector number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) -{ - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeEsector * 3) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one 64K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 64K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeE64k * 3) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: progran mode:SPI mode or QPI mode - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - BL_Err_Type stat; - uint8_t cmd; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - cmd = flashCfg->pageProgramCmd; - } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->qpageProgramCmd; - } else { - return ERROR; - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = flashCfg->pageSize - addr % flashCfg->pageSize; - - if (curLen > len - i) { - curLen = len - i; - } - - /* Prepare command */ - BL602_MemCpy_Fast(flashCtrlBuf, data, curLen); - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(100); - cnt++; - - if (cnt > flashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get flash unique ID - * - * @param data: data pointer to store read data - * @param idLen: unique ID len - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = 4; - cmd = 0x4B; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = idLen; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - BL602_MemCpy(data, flashCtrlBuf, idLen); -} - -/****************************************************************************/ /** - * @brief Get flash jedec ID - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = flashCfg->jedecIdCmdDmyClk; - cmd = flashCfg->jedecIdCmd; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - BL602_MemCpy(data, flashCtrlBuf, 3); -} - -/****************************************************************************/ /** - * @brief Get flash device ID - * - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t addr = 0x00000001; - uint8_t readMode = 0xFF; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - dummyClks = 2; - cmd = 0x94; - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.cmdBuf[1] = (readMode << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 4; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 2; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - BL602_MemCpy(data, flashCtrlBuf, 2); -} - -/****************************************************************************/ /** - * @brief Set flash power down - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_Powerdown(void) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - uint32_t timeOut = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = 0xB9; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} - -/****************************************************************************/ /** - * @brief Release flash power down for wake up - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t cmd; - uint32_t timeOut = 0; - - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = flashCfg->releasePowerDown; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} - -/****************************************************************************/ /** - * @brief Set flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((flashCfg->ioMode >> 4) & 0x01) == 1) { - /* Disable burst wrap ,just return */ - return; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; - dummyClks = flashCfg->burstWrapCmdDmyClk; - cmd = flashCfg->burstWrapCmd; - wrapData = flashCfg->burstWrapData; - BL602_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} - -/****************************************************************************/ /** - * @brief Disable flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; - dummyClks = flashCfg->deBurstWrapCmdDmyClk; - cmd = flashCfg->deBurstWrapCmd; - wrapData = flashCfg->deBurstWrapData; - BL602_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} - -/****************************************************************************/ /** - * @brief Software reset flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) -{ - uint16_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset enable */ - flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - /* Wait for write done */ - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(100); - cnt++; - - if (cnt > 20) { - return ERROR; - } - } - - SF_Ctrl_SendCmd(&flashCmd); - - /* Reset */ - flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - BL602_Delay_US(50); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Reset flash continous read mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset continous read */ - BL602_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = flashCfg->resetCreadCmdSize; - SF_Ctrl_SendCmd(&flashCmd); -} - -/****************************************************************************/ /** - * @brief Set I/D bus read flash configuration in flash controller - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: address to read/write - * @param len: data length to read/write - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) -{ - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmdValid = 1; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - /*prepare command**/ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - flashCmd.cmdBuf[0] = (cmd << 24) | addr; - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; - cmdValid = 0; - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = len; - SF_Ctrl_Icache_Set(&flashCmd, cmdValid); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable I/D bus read from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) -{ - BL_Err_Type stat; - - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 4); - - if (SUCCESS != stat) { - return stat; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable cache - * - * @param wayDisable: cache way disable config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Enable_Set(uint8_t wayDisable) -{ - uint32_t tmpVal; - uint32_t cnt = 0; - - /* Set cacheable to 0 */ - tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); - tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS); - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN); - BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); - /*Set Tag RAM to zero */ - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN); - BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); - /* Left space for hardware change status*/ - __NOP(); - __NOP(); - __NOP(); - __NOP(); - tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN); - BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); - /* Left space for hardware change status*/ - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - /* Polling for invalid done */ - do { - BL602_Delay_US(1); - cnt++; - tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); - } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100); - - tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS); - BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); - - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS); - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS); - tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN); - BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); - - tmpVal |= (wayDisable << L1C_WAY_DIS_POS); - - /* If way disable is 0x0f, cacheable can't be set */ - if (wayDisable != 0x0f) { - tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); - } - - BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Flush cache - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Flush(void) -{ - uint32_t tmpVal; - - /* Disable early respone */ - tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); - SFlash_Cache_Enable_Set((tmpVal >> L1C_WAY_DIS_POS) & 0xf); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable cache read from flash with cache - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param wayDisable: cache way disable config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) -{ - BL_Err_Type stat; - - /* Cache now only support 32 bytes read */ - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32); - - if (SUCCESS != stat) { - return stat; - } - - return SFlash_Cache_Enable_Set(wayDisable); -} - -/****************************************************************************/ /** - * @brief Get cache hit count - * - * @param hitCountLow: hit count low 32 bits pointer - * @param hitCountHigh: hit count high 32 bits pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh) -{ - *hitCountLow = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB); - *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB); -} - -/****************************************************************************/ /** - * @brief Get cache miss count - * - * @param None - * - * @return Cache miss count - * -*******************************************************************************/ -__WEAK -uint32_t ATTR_TCM_SECTION SFlash_Cache_Miss_Count_Get(void) -{ - return BL_RD_REG(L1C_BASE, L1C_MISS_CNT); -} - -/****************************************************************************/ /** - * @brief Disable read from flash with cache - * - * @param None - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE); - BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return None - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - - /* Read data */ - for (i = 0; i < len;) { - /* Prepare command */ - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - curLen = len - i; - - if (curLen >= FLASH_CTRL_BUF_SIZE) { - curLen = FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - BL602_MemCpy_Fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read flash register with read command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param readRegCmd: read command - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = readRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - BL602_Delay_US(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - BL602_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Write flash register with write command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param writeRegCmd: write command - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - BL602_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = writeRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - BL602_Delay_US(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/*@} end of group SFLASH_Public_Functions */ - -/*@} end of group SFLASH */ - -/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/std/src/bl602_sflash_ext.c b/drivers/soc/bl602/std/src/bl602_sflash_ext.c index 8d147e5a..36a3d997 100644 --- a/drivers/soc/bl602/std/src/bl602_sflash_ext.c +++ b/drivers/soc/bl602/std/src/bl602_sflash_ext.c @@ -36,7 +36,7 @@ #include "bl602_l1c.h" #include "bl602_sflash_ext.h" -#include "bl602_sf_ctrl.h" +#include "bflb_sf_ctrl.h" #include "l1c_reg.h" /** @addtogroup BL602_Peripheral_Driver @@ -64,6 +64,18 @@ */ #define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) +#define SFLASH_L1C_BASE_ADDR (0x40009000) +#define SFLASH_L1C_CONFIG_OFFSET (0x0) +#define SFLASH_L1C_CACHEABLE (1<<0U) +#define SFLASH_L1C_CNT_EN (1<<1U) +#define SFLASH_L1C_INVALID_EN (1<<2U) +#define SFLASH_L1C_INVALID_DONE (1<<3U) +#define SFLASH_L1C_WAY_DIS_SHIFT (8U) +#define SFLASH_L1C_WAY_DIS_MASK (0xf<ioMode & 0xf; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; /* Wake flash up from power down */ - SFlash_Releae_Powerdown(pFlashCfg); + bflb_sflash_release_powerdown(p_flash_cfg); BL602_Delay_US(120); - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); + bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id); - if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { - SFlash_Qspi_Enable(pFlashCfg); + if (SF_CTRL_QO_MODE == io_mode || SF_CTRL_QIO_MODE == io_mode) { + bflb_sflash_qspi_enable(p_flash_cfg); } - if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { + if (((p_flash_cfg->io_mode >> 4) & 0x01) == 1) { /* unwrap */ L1C_Set_Wrap(DISABLE); } else { /* burst wrap */ L1C_Set_Wrap(ENABLE); /* For command that is setting register instead of send command, we need write enable */ - SFlash_Write_Enable(pFlashCfg); - SFlash_SetBurstWrap(pFlashCfg); + bflb_sflash_write_enable(p_flash_cfg); + bflb_sflash_set_burst_wrap(p_flash_cfg); } - if (flashContRead) { - stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + if (flash_cont_read) { + stat = bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); + stat = bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, 0); } else { - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32); + stat = bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 0, 0, 32, 0); } return stat; @@ -138,467 +151,565 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *p /****************************************************************************/ /** * @brief Sflash enable RCV mode to recovery for erase while power drop * - * @param pFlashCfg: Flash configuration pointer - * @param rCmd: Read RCV register cmd - * @param wCmd: Write RCV register cmd - * @param bitPos: RCV register bit pos + * @param p_flash_cfg: Flash configuration pointer + * @param r_cmd: Read RCV register cmd + * @param w_cmd: Write RCV register cmd + * @param bit_pos: RCV register bit pos * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) +int ATTR_TCM_SECTION bflb_sflash_rcv_enable(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos) { - BL_Err_Type stat; + int stat = -1; uint32_t cnt = 0; - uint32_t tempVal = 0; + uint32_t regval = 0; - while (SET == SFlash_Busy(pFlashCfg)) { + while (SET == bflb_sflash_busy(p_flash_cfg)) { BL602_Delay_US(500); cnt++; if (cnt > 20000 * 3) { - return ERROR; + return -1; } } - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); + stat = bflb_sflash_read_reg_with_cmd(p_flash_cfg, r_cmd, (uint8_t *)®val, 1); - if (SUCCESS != stat) { - stat = ERROR; + if (0 != stat) { + stat = -1; } - if (((tempVal >> bitPos) & 0x01) > 0) { - return SUCCESS; + if (((regval >> bit_pos) & 0x01) > 0) { + return 0; } - tempVal |= (uint32_t)(1 << bitPos); - stat = SFlash_Write_Enable(pFlashCfg); + regval |= (uint32_t)(1 << bit_pos); + stat = bflb_sflash_write_enable(p_flash_cfg); - if (SUCCESS != stat) { - stat = ERROR; + if (0 != stat) { + stat = -1; } - stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1); + stat = bflb_sflash_write_reg_with_cmd(p_flash_cfg, w_cmd, (uint8_t *)®val, 1); - if (SUCCESS != stat) { + if (0 != stat) { return stat; } - while (SET == SFlash_Busy(pFlashCfg)) { + while (SET == bflb_sflash_busy(p_flash_cfg)) { BL602_Delay_US(500); cnt++; if (cnt > 20000 * 3) { - return ERROR; + return -1; } } - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); + stat = bflb_sflash_read_reg_with_cmd(p_flash_cfg, r_cmd, (uint8_t *)®val, 1); - if (SUCCESS != stat) { - stat = ERROR; + if (0 != stat) { + stat = -1; } - if (((tempVal >> bitPos) & 0x01) <= 0) { - return ERROR; + if (((regval >> bit_pos) & 0x01) <= 0) { + return -1; } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Erase flash security register one block * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer + * @param p_flash_cfg: Flash configuration pointer + * @param p_sec_reg_cfg: Security register configuration pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) +int ATTR_TCM_SECTION bflb_sflash_erase_security_register(spi_flash_cfg_type *p_flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg) { uint32_t cnt = 0; uint8_t cmd = 0; - uint8_t secOptMode = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t sec_opt_mode = 0; + uint32_t time_out = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; + if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) { + sec_opt_mode = 1; - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + time_out = SFCTRL_BUSY_STATE_TIMEOUT; - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; + while (SET == bflb_sf_ctrl_get_busy_state()) { + time_out--; - if (timeOut == 0) { - return TIMEOUT; + if (time_out == 0) { + return -2; } } } - BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg); + int stat = bflb_sflash_write_enable(p_flash_cfg); - if (stat != SUCCESS) { + if (stat != 0) { return stat; } - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - cmd = pSecRegCfg->eraseCmd; - flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; + cmd = p_sec_reg_cfg->erase_cmd; + flash_cmd.cmd_buf[0] = (cmd << 24) | (p_sec_reg_cfg->block_num << 12); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; - SF_Ctrl_SendCmd(&flashCmd); + bflb_sf_ctrl_sendcmd(&flash_cmd); - while (SET == SFlash_Busy(pFlashCfg)) { + while (SET == bflb_sflash_busy(p_flash_cfg)) { BL602_Delay_US(500); cnt++; - if (cnt > pFlashCfg->timeEsector * 3) { - return ERROR; + if (cnt > p_flash_cfg->time_e_sector * 3) { + return -1; } } - if (secOptMode > 0) { - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (sec_opt_mode > 0) { + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + time_out = SFCTRL_BUSY_STATE_TIMEOUT; - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; + while (SET == bflb_sf_ctrl_get_busy_state()) { + time_out--; - if (timeOut == 0) { - return TIMEOUT; + if (time_out == 0) { + return -2; } } } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Program flash security register one block * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer + * @param p_flash_cfg: Flash configuration pointer + * @param p_sec_reg_cfg: Security register configuration pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) +int ATTR_TCM_SECTION bflb_sflash_program_security_register(spi_flash_cfg_type *p_flash_cfg, + struct sflash_sec_reg_cfg *p_sec_reg_cfg) { - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; + uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t i = 0, cur_len = 0; uint32_t cnt = 0; - BL_Err_Type stat; + int stat = -1; uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t sec_opt_mode = 0; + uint8_t *data = p_sec_reg_cfg->data; + uint32_t addr = p_sec_reg_cfg->addr; + uint32_t len = p_sec_reg_cfg->len; + uint32_t current_addr = 0; + uint32_t time_out = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; + if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) { + sec_opt_mode = 1; - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + time_out = SFCTRL_BUSY_STATE_TIMEOUT; - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; + while (SET == bflb_sf_ctrl_get_busy_state()) { + time_out--; - if (timeOut == 0) { - return TIMEOUT; + if (time_out == 0) { + return -2; } } } - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - cmd = pSecRegCfg->programCmd; + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.addr_size = 3; + cmd = p_sec_reg_cfg->program_cmd; for (i = 0; i < len;) { /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(pFlashCfg); + stat = bflb_sflash_write_enable(p_flash_cfg); - if (stat != SUCCESS) { + if (stat != 0) { return stat; } /* Get current programmed length within page size */ - curLen = 256 - addr % 256; + cur_len = 256 - addr % 256; - if (curLen > len - i) { - curLen = len - i; + if (cur_len > len - i) { + cur_len = len - i; } - currentAddr = (pSecRegCfg->blockNum << 12) | addr; + current_addr = (p_sec_reg_cfg->block_num << 12) | addr; /* Prepare command */ - BL602_MemCpy_Fast(flashCtrlBuf, data, curLen); - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - flashCmd.nbData = curLen; + BL602_MemCpy_Fast(flash_ctrl_buf, data, cur_len); + flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr); + flash_cmd.nb_data = cur_len; - SF_Ctrl_SendCmd(&flashCmd); + bflb_sf_ctrl_sendcmd(&flash_cmd); /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; + addr += cur_len; + i += cur_len; + data += cur_len; /* Wait for write done */ cnt = 0; - while (SET == SFlash_Busy(pFlashCfg)) { + while (SET == bflb_sflash_busy(p_flash_cfg)) { BL602_Delay_US(100); cnt++; - if (cnt > pFlashCfg->timePagePgm * 20) { - return ERROR; + if (cnt > p_flash_cfg->time_page_pgm * 20) { + return -1; } } } - if (secOptMode > 0) { - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (sec_opt_mode > 0) { + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + time_out = SFCTRL_BUSY_STATE_TIMEOUT; - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; + while (SET == bflb_sf_ctrl_get_busy_state()) { + time_out--; - if (timeOut == 0) { - return TIMEOUT; + if (time_out == 0) { + return -2; } } } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Read data from flash security register one block * - * @param pSecRegCfg: Security register configuration pointer + * @param p_sec_reg_cfg: Security register configuration pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg) +int ATTR_TCM_SECTION bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg) { - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; + uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE; + uint32_t cur_len, i; uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t sec_opt_mode = 0; + uint8_t *data = p_sec_reg_cfg->data; + uint32_t addr = p_sec_reg_cfg->addr; + uint32_t len = p_sec_reg_cfg->len; + uint32_t current_addr = 0; + uint32_t time_out = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; + if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) { + sec_opt_mode = 1; - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + time_out = SFCTRL_BUSY_STATE_TIMEOUT; - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; + while (SET == bflb_sf_ctrl_get_busy_state()) { + time_out--; - if (timeOut == 0) { - return TIMEOUT; + if (time_out == 0) { + return -2; } } } - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - flashCmd.dummyClks = 1; - cmd = pSecRegCfg->readCmd; + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; + flash_cmd.dummy_clks = 1; + cmd = p_sec_reg_cfg->read_cmd; /* Read data */ for (i = 0; i < len;) { - currentAddr = (pSecRegCfg->blockNum << 12) | addr; + current_addr = (p_sec_reg_cfg->block_num << 12) | addr; /* Prepare command */ - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - curLen = len - i; + flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr); + cur_len = len - i; - if (curLen >= FLASH_CTRL_BUF_SIZE) { - curLen = FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; + if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) { + cur_len = NOR_FLASH_CTRL_BUF_SIZE; + flash_cmd.nb_data = cur_len; } else { /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; + flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2; } - SF_Ctrl_SendCmd(&flashCmd); + bflb_sf_ctrl_sendcmd(&flash_cmd); - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + time_out = SFCTRL_BUSY_STATE_TIMEOUT; - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; + while (SET == bflb_sf_ctrl_get_busy_state()) { + time_out--; - if (timeOut == 0) { - return TIMEOUT; + if (time_out == 0) { + return -2; } } - BL602_MemCpy_Fast(data, flashCtrlBuf, curLen); + BL602_MemCpy_Fast(data, flash_ctrl_buf, cur_len); - addr += curLen; - i += curLen; - data += curLen; + addr += cur_len; + i += cur_len; + data += cur_len; } - if (secOptMode > 0) { - if (((uint32_t)&flashCmd) % 4 == 0) { - BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (sec_opt_mode > 0) { + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL602_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); + flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24); + flash_cmd.rw_flag = SF_CTRL_WRITE; + bflb_sf_ctrl_sendcmd(&flash_cmd); - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; + time_out = SFCTRL_BUSY_STATE_TIMEOUT; - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; + while (SET == bflb_sf_ctrl_get_busy_state()) { + time_out--; - if (timeOut == 0) { - return TIMEOUT; + if (time_out == 0) { + return -2; } } } - return SUCCESS; + return 0; } /****************************************************************************//** * @brief Clear flash status register * - * @param pFlashCfg: Flash configuration pointer + * @param p_flash_cfg: Flash configuration pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg) { uint32_t ret = 0; - uint32_t qeValue = 0; - uint32_t regValue = 0; - uint32_t readValue = 0; - uint8_t readRegValue0 = 0; - uint8_t readRegValue1 = 0; + uint32_t qe_value = 0; + uint32_t reg_value = 0; + uint32_t read_value = 0; + uint8_t read_reg_value0 = 0; + uint8_t read_reg_value1 = 0; - if((pFlashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){ - qeValue = 1; + if((p_flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE){ + qe_value = 1; } - SFlash_Read_Reg(pFlashCfg, 0, (uint8_t *)&readRegValue0, 1); - SFlash_Read_Reg(pFlashCfg, 1, (uint8_t *)&readRegValue1, 1); - readValue = (readRegValue0|(readRegValue1<<8)); - if ((readValue & (~((1<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit)) | - (1<<(pFlashCfg->busyIndex*8+pFlashCfg->busyBit)) | - (1<<(pFlashCfg->wrEnableIndex*8+pFlashCfg->wrEnableBit))))) == 0){ - return SUCCESS; + bflb_sflash_read_reg(p_flash_cfg, 0, (uint8_t *)&read_reg_value0, 1); + bflb_sflash_read_reg(p_flash_cfg, 1, (uint8_t *)&read_reg_value1, 1); + read_value = (read_reg_value0|(read_reg_value1<<8)); + if ((read_value & (~((1<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit)) | + (1<<(p_flash_cfg->busy_index*8+p_flash_cfg->busy_bit)) | + (1<<(p_flash_cfg->wr_enable_index*8+p_flash_cfg->wr_enable_bit))))) == 0){ + return 0; } - ret = SFlash_Write_Enable(pFlashCfg); - if (SUCCESS != ret) { - return ERROR; + ret = bflb_sflash_write_enable(p_flash_cfg); + if (0 != ret) { + return -1; } - if (pFlashCfg->qeWriteRegLen == 2) { - regValue = (qeValue<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit)); - SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 2); + if (p_flash_cfg->qe_write_reg_len == 2) { + reg_value = (qe_value<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit)); + bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 2); } else { - if (pFlashCfg->qeIndex == 0) { - regValue = (qeValue<qeBit); + if (p_flash_cfg->qe_index == 0) { + reg_value = (qe_value<qe_bit); } else { - regValue = 0; + reg_value = 0; } - SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 1); - ret = SFlash_Write_Enable(pFlashCfg); - if (SUCCESS != ret) { - return ERROR; + bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 1); + ret = bflb_sflash_write_enable(p_flash_cfg); + if (0 != ret) { + return -1; } - if (pFlashCfg->qeIndex == 1) { - regValue = (qeValue<qeBit); + if (p_flash_cfg->qe_index == 1) { + reg_value = (qe_value<qe_bit); } else { - regValue = 0; + reg_value = 0; } - SFlash_Write_Reg(pFlashCfg, 1, (uint8_t *)®Value, 1); + bflb_sflash_write_reg(p_flash_cfg, 1, (uint8_t *)®_value, 1); } - return SUCCESS; + return 0; +} + +/****************************************************************************/ /** + * @brief Enable cache + * + * @param way_disable: cache way disable config + * + * @return 0 or -1 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_cache_enable_set(uint8_t way_disable) +{ + uint32_t regval = 0; + + uint32_t cnt = 0; + + /* Set cacheable to 0 */ + regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET); + regval &= ~SFLASH_L1C_CACHEABLE; + regval |= SFLASH_L1C_BYPASS; + regval &= ~SFLASH_L1C_WAY_DIS_MASK; + regval &= ~SFLASH_L1C_CNT_EN; + putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET); + + regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET); + /*Set Tag RAM to zero */ + regval &= ~SFLASH_L1C_INVALID_EN; + putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + regval|= SFLASH_L1C_INVALID_EN; + putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET); + /* Left space for hardware change status*/ + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* Polling for invalid done */ + do { + BL602_Delay_US(1); + cnt++; + regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET); + } while (!((regval&SFLASH_L1C_INVALID_DONE) > 0 ? 1:0) && cnt < 100); + + regval |= SFLASH_L1C_BYPASS; + putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET); + + regval &= ~SFLASH_L1C_BYPASS; + regval &= ~SFLASH_L1C_WAY_DIS_MASK; + regval |= SFLASH_L1C_CNT_EN; + putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET); + + regval &= ~SFLASH_L1C_WAY_DIS_MASK; + regval |= (way_disable << SFLASH_L1C_WAY_DIS_SHIFT); + + /* If way disable is 0x0f, cacheable can't be set */ + if (way_disable != 0x0f) { + regval |= SFLASH_L1C_CACHEABLE; + } else { + regval &= ~SFLASH_L1C_CACHEABLE; + } + + putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET); + + return 0; +} + +/****************************************************************************/ /** + * @brief Flush cache + * + * @param None + * + * @return 0 or -1 + * +*******************************************************************************/ +__WEAK +int ATTR_TCM_SECTION bflb_sflash_cache_flush(void) +{ + uint32_t regval = 0; + uint32_t way_disable = 0; + + /* Disable early respone */ + regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET); + way_disable = (regval&SFLASH_L1C_WAY_DIS_MASK) >> SFLASH_L1C_WAY_DIS_SHIFT; + bflb_sflash_cache_enable_set(way_disable & 0xf); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + return 0; } /*@} end of group SFLASH_EXT_Public_Functions */ diff --git a/drivers/soc/bl602/std/src/bl602_xip_sflash.c b/drivers/soc/bl602/std/src/bl602_xip_sflash.c deleted file mode 100644 index 873c8201..00000000 --- a/drivers/soc/bl602/std/src/bl602_xip_sflash.c +++ /dev/null @@ -1,434 +0,0 @@ -/** - ****************************************************************************** - * @file bl602_xip_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl602_xip_sflash.h" - -/** @addtogroup BL602_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Private_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Macros */ - -/** @defgroup XIP_SFLASH_Private_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Types */ - -/** @defgroup XIP_SFLASH_Private_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Variables */ - -/** @defgroup XIP_SFLASH_Global_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Global_Variables */ - -/** @defgroup XIP_SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ - -/** @defgroup XIP_SFLASH_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Save flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) -{ - /* XIP_SFlash_Delay */ - volatile uint32_t i = 32 * 2; - - while (i--) - ; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); - /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */ - SFlash_Software_Reset(pFlashCfg); - /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); - /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); - /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); - - /* Clear offset setting*/ - *offset = SF_Ctrl_Get_Flash_Image_Offset(); - SF_Ctrl_Set_Flash_Image_Offset(0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Restore flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset) -{ - uint32_t tmp[1]; - - SF_Ctrl_Set_Flash_Image_Offset(offset); - - SFlash_SetBurstWrap(pFlashCfg); - SFlash_Read(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - - return SUCCESS; -} - -/*@} end of group XIP_SFLASH_Private_Functions */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, endaddr); - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return stat; -} - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param pFlashCfg: Flash config pointer - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - } else { - stat = SFlash_Program(pFlashCfg, SF_CTRL_QIO_MODE, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return stat; -} - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param pFlashCfg: Flash config pointer - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - } else { - stat = SFlash_Read(pFlashCfg, SF_CTRL_QIO_MODE, 0, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return stat; -} - -/****************************************************************************/ /** - * @brief Get Flash Jedec ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Jedec ID Read from flash - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get Flash Device ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Device ID Read from flash - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - } else { - SFlash_GetDeviceId(data); - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get Flash Unique ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Device ID Read from flash - * @param idLen: Unique id len - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32); - } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore(pFlashCfg, offset); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash via XIP - * - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) -{ - uint32_t offset; - - if (addr >= BL602_FLASH_XIP_BASE && addr < BL602_FLASH_XIP_END) { - offset = SF_Ctrl_Get_Flash_Image_Offset(); - SF_Ctrl_Set_Flash_Image_Offset(0); - /* Flash read */ - BL602_MemCpy_Fast(data, (void *)(addr), len); - SF_Ctrl_Set_Flash_Image_Offset(offset); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @return 0 - * -*******************************************************************************/ -__WEAK -int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len) -{ - __disable_irq(); - XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, dst, len); - __enable_irq(); - return 0; -} - -/****************************************************************************//** - * @brief Program flash one region with lock - * - * @param pFlashCfg: Flash config pointer - * @param addr: Start address to be programed - * @param src: Data pointer to be programed - * @param len: Data length to be programed - * - * @return 0 - * -*******************************************************************************/ -__WEAK -int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len) -{ - __disable_irq(); - XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, src, len); - __enable_irq(); - return 0; -} - -/****************************************************************************//** - * @brief Erase flash one region with lock - * - * @param pFlashCfg: Flash config pointer - * @param addr: Start address to be erased - * @param len: Data length to be erased - * - * @return 0 - * -*******************************************************************************/ -__WEAK -int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len) -{ - __disable_irq(); - XIP_SFlash_Erase_Need_Lock(pFlashCfg, addr, addr + len - 1); - __enable_irq(); - return 0; -} - -/****************************************************************************//** - * @brief XIP SFlash option save - * - * @param aesEnable: AES enable status pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) -{ - *aesEnable = SF_Ctrl_Is_AES_Enable(); - - if (*aesEnable) { - SF_Ctrl_AES_Disable(); - } -} - -/****************************************************************************/ /** - * @brief XIP SFlash option restore - * - * @param aesEnable: AES enable status - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) -{ - if (aesEnable) { - SF_Ctrl_AES_Enable(); - } -} -#endif - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL602_Peripheral_Driver */ diff --git a/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c b/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c index 647629a2..8a9e8df6 100644 --- a/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c +++ b/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c @@ -35,9 +35,9 @@ */ #include "string.h" -#include "bl602_sf_cfg.h" +#include "bflb_sf_cfg.h" #include "bl602_sf_cfg_ext.h" -#include "bl602_xip_sflash.h" +#include "bflb_xip_sflash.h" #include "bl602_xip_sflash_ext.h" /** @addtogroup BL602_Peripheral_Driver @@ -64,8 +64,8 @@ * @{ */ -static SPI_Flash_Cfg_Type flashCfg; -static uint8_t aesEnable; +static spi_flash_cfg_type flash_cfg; +static uint8_t aes_enable; /*@} end of group XIP_SFLASH_EXT_Private_Variables */ @@ -94,66 +94,68 @@ static uint8_t aesEnable; /****************************************************************************//** * @brief Save flash controller state * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param offset: CPU XIP flash offset pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset) +int ATTR_TCM_SECTION bflb_xip_sflash_state_save_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t *offset, + uint8_t group, uint8_t bank) { /* XIP_SFlash_Delay */ volatile uint32_t i=32*2; while(i--); - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); + bflb_sflash_reset_continue_read(p_flash_cfg); /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */ - SFlash_Software_Reset(pFlashCfg); + bflb_sflash_software_reset(p_flash_cfg); /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); - if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { + bflb_sflash_disable_burst_wrap(p_flash_cfg); + if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) { /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); + bflb_sflash_qspi_enable(p_flash_cfg); } /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); + bflb_sflash_disable_burst_wrap(p_flash_cfg); /* Clear offset setting*/ - *offset=SF_Ctrl_Get_Flash_Image_Offset(); - SF_Ctrl_Set_Flash_Image_Offset(0); + *offset=bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); - return SUCCESS; + return 0; } /****************************************************************************//** * @brief Restore flash controller state * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param offset: CPU XIP flash offset * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset) +int ATTR_TCM_SECTION bflb_xip_sflash_state_restore_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, + uint8_t group, uint8_t bank) { uint32_t tmp[1]; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - SF_Ctrl_Set_Flash_Image_Offset(offset); + bflb_sf_ctrl_set_flash_image_offset(offset, group, bank); - if (((pFlashCfg->ioMode >> 4) & 0x01) == 0) { - if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(pFlashCfg); + if (((p_flash_cfg->io_mode >> 4) & 0x01) == 0) { + if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) { + bflb_sflash_set_burst_wrap(p_flash_cfg); } } - SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); - return SUCCESS; + return 0; } /*@} end of group XIP_SFLASH_EXT_Public_Functions */ @@ -165,29 +167,30 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pF /****************************************************************************/ /** * @brief Erase flash one region * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param startaddr: start address to erase * @param endaddr: end address(include this address) to erase * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr) +int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, + uint32_t endaddr, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + uint8_t io_mode = p_flash_cfg->io_mode&0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat=XIP_SFlash_State_Save(pFlashCfg,&offset); - if(stat!=SUCCESS){ - SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + bflb_xip_sflash_opt_enter(&aes_enable); + stat=bflb_xip_sflash_state_save(p_flash_cfg,&offset,group,bank); + if(stat!=0){ + bflb_sflash_set_xip_cfg(p_flash_cfg,io_mode,1,0,32,bank); }else{ - stat=SFlash_Erase(pFlashCfg,startaddr,endaddr); - XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + stat=bflb_sflash_erase(p_flash_cfg,startaddr,endaddr); + bflb_xip_sflash_state_restore_ext(p_flash_cfg,offset,group,bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); return stat; } @@ -195,30 +198,31 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type * /****************************************************************************/ /** * @brief Program flash one region * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param addr: start address to be programed * @param data: data pointer to be programed * @param len: data length to be programed * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, + uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + uint8_t io_mode = p_flash_cfg->io_mode&0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat=XIP_SFlash_State_Save(pFlashCfg,&offset); - if(stat!=SUCCESS){ - SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + bflb_xip_sflash_opt_enter(&aes_enable); + stat=bflb_xip_sflash_state_save(p_flash_cfg,&offset,group,bank); + if(stat!=0){ + bflb_sflash_set_xip_cfg(p_flash_cfg,io_mode,1,0,32,bank); }else{ - stat= SFlash_Program(pFlashCfg,ioMode,addr,data,len); - XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + stat= bflb_sflash_program(p_flash_cfg,io_mode,addr,data,len); + bflb_xip_sflash_state_restore_ext(p_flash_cfg,offset,group,bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); return stat; } @@ -226,30 +230,31 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type * /****************************************************************************/ /** * @brief Read data from flash * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param addr: flash read start address * @param data: data pointer to store data read from flash * @param len: data length to read * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, + uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + uint8_t io_mode = p_flash_cfg->io_mode&0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat=XIP_SFlash_State_Save(pFlashCfg,&offset); - if(stat!=SUCCESS){ - SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32); + bflb_xip_sflash_opt_enter(&aes_enable); + stat=bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + if(stat!=0){ + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); }else{ - stat=SFlash_Read(pFlashCfg,ioMode,0,addr, data,len); - XIP_SFlash_State_Restore_Ext(pFlashCfg,offset); + stat=bflb_sflash_read(p_flash_cfg, io_mode,0, addr, data, len); + bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); return stat; } @@ -257,24 +262,25 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *p /****************************************************************************//** * @brief Clear flash status register need lock * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + uint8_t io_mode = p_flash_cfg->io_mode&0xf; - stat=XIP_SFlash_State_Save(pFlashCfg, &offset); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + stat=bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - stat=SFlash_Clear_Status_Register(pFlashCfg); - XIP_SFlash_State_Restore_Ext(pFlashCfg, offset); + stat=bflb_sflash_clear_status_register(p_flash_cfg); + bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank); } return stat; @@ -283,109 +289,113 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flas /****************************************************************************//** * @brief Get Flash Jedec ID * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param data: data pointer to store Jedec ID Read from flash * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +int ATTR_TCM_SECTION bflb_xip_sflash_getjedecid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore_Ext(pFlashCfg, offset); + bflb_sflash_get_jedecid(p_flash_cfg, data); + bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank); } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Get Flash Device ID * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param data: data pointer to store Device ID Read from flash * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data) +int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, + uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - SFlash_GetDeviceId(data); - XIP_SFlash_State_Restore_Ext(pFlashCfg, offset); + bflb_sflash_get_deviceid(data, is_32bits_addr); + bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank); } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Get Flash Unique ID * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param data: data pointer to store Device ID Read from flash - * @param idLen: Unique id len + * @param id_len: Unique id len * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen) +int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t id_len, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore_Ext(pFlashCfg, offset); + bflb_sflash_get_uniqueid(data, id_len); + bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank); } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Sflash enable RCV mode to recovery for erase while power drop need lock * - * @param pFlashCfg: Flash config pointer - * @param rCmd: Read RCV register cmd - * @param wCmd: Write RCV register cmd - * @param bitPos: RCV register bit pos + * @param p_flash_cfg: Flash config pointer + * @param r_cmd: Read RCV register cmd + * @param w_cmd: Write RCV register cmd + * @param bit_pos: RCV register bit pos * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) +int ATTR_TCM_SECTION bflb_xip_sflash_rcv_enable_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, + uint8_t bit_pos, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat = -1; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32 , bank); } else { - stat = SFlash_RCV_Enable(pFlashCfg, rCmd, wCmd, bitPos); - XIP_SFlash_State_Restore_Ext(pFlashCfg, offset); + stat = bflb_sflash_rcv_enable(p_flash_cfg, r_cmd, w_cmd, bit_pos); + bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank); } return stat; @@ -394,7 +404,7 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type /****************************************************************************//** * @brief Read data from flash with lock * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param addr: flash read start address * @param dst: data pointer to store data read from flash * @param len: data length to read @@ -403,10 +413,10 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len) +int ATTR_TCM_SECTION bflb_xip_sflash_read_with_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t addr, uint8_t *dst, int len) { __disable_irq(); - XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg, addr, dst, len); + bflb_xip_sflash_read_need_lock_ext(p_flash_cfg, addr, dst, len, 0, 0); __enable_irq(); return 0; } @@ -414,7 +424,7 @@ int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg /****************************************************************************//** * @brief Program flash one region with lock * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param addr: Start address to be programed * @param src: Data pointer to be programed * @param len: Data length to be programed @@ -423,10 +433,10 @@ int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len) +int ATTR_TCM_SECTION bflb_ip_sflash_write_with_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t addr, uint8_t *src, int len) { __disable_irq(); - XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg, addr, src, len); + bflb_xip_sflash_write_need_lock_ext(p_flash_cfg, addr, src, len, 0, 0); __enable_irq(); return 0; } @@ -434,7 +444,7 @@ int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCf /****************************************************************************//** * @brief Erase flash one region with lock * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param addr: Start address to be erased * @param len: Data length to be erased * @@ -442,10 +452,10 @@ int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCf * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len) +int ATTR_TCM_SECTION bflb_xip_sflash_erase_with_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t addr, int len) { __disable_irq(); - XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg, addr, addr + len - 1); + bflb_xip_sflash_erase_need_lock_ext(p_flash_cfg, addr, addr + len - 1, 0, 0); __enable_irq(); return 0; } @@ -453,16 +463,16 @@ int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCf /****************************************************************************//** * @brief Clear flash status register with lock * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * * @return 0 * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_with_lock(spi_flash_cfg_type *p_flash_cfg) { __disable_irq(); - XIP_SFlash_Clear_Status_Register_Need_Lock(pFlashCfg); + bflb_xip_sflash_clear_status_register_need_lock(p_flash_cfg, 0, 0); __enable_irq(); return 0; } @@ -470,19 +480,19 @@ int ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_With_Lock(SPI_Flash_Cfg_Ty /****************************************************************************//** * @brief Sflash enable RCV mode to recovery for erase while power drop with lock * - * @param pFlashCfg: Flash config pointer - * @param rCmd: Read RCV register cmd - * @param wCmd: Write RCV register cmd - * @param bitPos: RCV register bit pos + * @param p_flash_cfg: Flash config pointer + * @param r_cmd: Read RCV register cmd + * @param w_cmd: Write RCV register cmd + * @param bit_pos: RCV register bit pos * * @return 0 * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) +int ATTR_TCM_SECTION bflb_xip_sflash_rcv_enable_with_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos) { __disable_irq(); - XIP_SFlash_RCV_Enable_Need_Lock(pFlashCfg, rCmd, wCmd, bitPos); + bflb_xip_sflash_rcv_enable_need_lock(p_flash_cfg, r_cmd, w_cmd, bit_pos, 0, 0); __enable_irq(); return 0; } @@ -490,29 +500,29 @@ int ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_With_Lock(SPI_Flash_Cfg_Type *pFlashC /****************************************************************************//** * @brief Read data from flash with lock * - * @param pFlashCfg:Flash config pointer + * @param p_flash_cfg:Flash config pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_xip_sflash_init(spi_flash_cfg_type *p_flash_cfg) { uint32_t ret; - if(pFlashCfg==NULL){ + if(p_flash_cfg==NULL){ /* Get flash config identify */ - XIP_SFlash_Opt_Enter(&aesEnable); - ret=SF_Cfg_Flash_Identify_Ext(1,1,0,0,&flashCfg); - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_enter(&aes_enable); + ret=bflb_sf_cfg_flash_identify_ext(1, 0x80, 0, &flash_cfg, 0, 0); + bflb_xip_sflash_opt_exit(aes_enable); if((ret&BFLB_FLASH_ID_VALID_FLAG)==0){ - return ERROR; + return -1; } }else{ - memcpy(&flashCfg,pFlashCfg,sizeof(flashCfg)); + memcpy(&flash_cfg,p_flash_cfg,sizeof(flash_cfg)); } - return SUCCESS; + return 0; } /****************************************************************************//** @@ -526,12 +536,12 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg) * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len) +int ATTR_TCM_SECTION bflb_xip_sflash_read(uint32_t addr, uint8_t *dst, int len) { __disable_irq(); - XIP_SFlash_Opt_Enter(&aesEnable); - XIP_SFlash_Read_Need_Lock_Ext(&flashCfg, addr, dst, len); - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_enter(&aes_enable); + bflb_xip_sflash_read_need_lock_ext(&flash_cfg, addr, dst, len, 0, 0); + bflb_xip_sflash_opt_exit(aes_enable); __enable_irq(); return 0; } @@ -547,12 +557,12 @@ int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len) * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len) +int ATTR_TCM_SECTION bflb_xip_sflash_write(uint32_t addr, uint8_t *src, int len) { __disable_irq(); - XIP_SFlash_Opt_Enter(&aesEnable); - XIP_SFlash_Write_Need_Lock_Ext(&flashCfg, addr, src, len); - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_enter(&aes_enable); + bflb_xip_sflash_write_need_lock_ext(&flash_cfg, addr, src, len, 0, 0); + bflb_xip_sflash_opt_exit(aes_enable); __enable_irq(); return 0; } @@ -567,12 +577,12 @@ int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len) * *******************************************************************************/ __WEAK -int ATTR_TCM_SECTION XIP_SFlash_Erase(uint32_t addr, int len) +int ATTR_TCM_SECTION bflb_xip_sflash_erase(uint32_t addr, int len) { __disable_irq(); - XIP_SFlash_Opt_Enter(&aesEnable); - XIP_SFlash_Erase_Need_Lock_Ext(&flashCfg, addr, addr + len - 1); - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_enter(&aes_enable); + bflb_xip_sflash_erase_need_lock_ext(&flash_cfg, addr, addr + len - 1, 0, 0); + bflb_xip_sflash_opt_exit(aes_enable); __enable_irq(); return 0; } diff --git a/drivers/soc/bl616/std/CMakeLists.txt b/drivers/soc/bl616/std/CMakeLists.txt index 3d804bde..c10c3ba2 100644 --- a/drivers/soc/bl616/std/CMakeLists.txt +++ b/drivers/soc/bl616/std/CMakeLists.txt @@ -19,10 +19,6 @@ sdk_library_add_sources(src/bl616_glb.c) sdk_library_add_sources(src/bl616_hbn.c) sdk_library_add_sources(src/bl616_l1c.c) sdk_library_add_sources(src/bl616_pds.c) -sdk_library_add_sources(src/bl616_sf_cfg.c) -sdk_library_add_sources(src/bl616_sf_ctrl.c) -sdk_library_add_sources(src/bl616_sflash.c) -sdk_library_add_sources(src/bl616_xip_sflash.c) endif() sdk_library_add_sources(src/bl616_common.c) @@ -31,6 +27,7 @@ sdk_library_add_sources(src/bl616_sdh.c) sdk_library_add_sources(src/bl616_tzc_sec.c) sdk_library_add_sources(src/bl616_psram.c) sdk_library_add_sources(src/bl616_audac.c) +sdk_library_add_sources(src/bl616_auadc.c) if(CONFIG_RF) sdk_library_add_sources(src/bl616_mfg_efuse.c) @@ -39,7 +36,6 @@ sdk_library_add_sources(src/bl616_mfg_media.c) endif() sdk_library_add_sources(port/bl616_clock.c) -sdk_library_add_sources(port/bl616_flash.c) sdk_add_include_directories( include diff --git a/drivers/soc/bl616/std/include/bl616_auadc.h b/drivers/soc/bl616/std/include/bl616_auadc.h new file mode 100644 index 00000000..5193d81a --- /dev/null +++ b/drivers/soc/bl616/std/include/bl616_auadc.h @@ -0,0 +1,170 @@ +#ifndef _BFLB_AUADC_H +#define _BFLB_AUADC_H + +#include "bflb_core.h" + +/** + * @defgroup AUADC_SAMPLING_RATE auadc sampling rate + */ +#define AUADC_SAMPLING_RATE_8K 0 /* audio mode */ +#define AUADC_SAMPLING_RATE_16K 1 /* audio mode */ +#define AUADC_SAMPLING_RATE_24K 2 /* audio mode, same as 22.02K, adjust the AUPLL clock */ +#define AUADC_SAMPLING_RATE_32K 3 /* audio mode */ +#define AUADC_SAMPLING_RATE_48K 4 /* audio mode, same as 44.1K, adjust the AUPLL clock */ +#define AUADC_SAMPLING_RATE_MEASURE_128K 8 /* only used in ADC measurement mode */ +#define AUADC_SAMPLING_RATE_MEASURE_256K 9 /* only used in ADC measurement mode */ +#define AUADC_SAMPLING_RATE_MEASURE_512K 10 /* only used in ADC measurement mode */ +/** + * @} + */ + +/** + * @defgroup AUADC_INPUT_MODE auadc input mode + */ +#define AUADC_INPUT_MODE_ADC 0 /* Analog ADC */ +#define AUADC_INPUT_MODE_PDM_L 1 /* PDM left channel */ +#define AUADC_INPUT_MODE_PDM_R 2 /* PDM right channel */ +/** + * @} + */ + +/** + * @defgroup AUADC_DATA_FORMAT auadc data format + */ +#define AUADC_DATA_FORMAT_16BIT 3 +#define AUADC_DATA_FORMAT_20BIT 2 +#define AUADC_DATA_FORMAT_24BIT 1 +#define AUADC_DATA_FORMAT_32BIT 0 +/** + * @} + */ + +/** + * @brief AUADC_ADC_ANALOG_CH auadc adc input ch + */ +#define AUADC_ADC_ANALOG_CH_0 0 +#define AUADC_ADC_ANALOG_CH_1 1 +#define AUADC_ADC_ANALOG_CH_2 2 +#define AUADC_ADC_ANALOG_CH_3 3 +#define AUADC_ADC_ANALOG_CH_4 4 +#define AUADC_ADC_ANALOG_CH_5 5 +#define AUADC_ADC_ANALOG_CH_6 6 +#define AUADC_ADC_ANALOG_CH_7 7 +/** + * @} + */ + +/** + * @brief AUADC_ADC_MEASURE_RATE auadc adc Sampling rate in measurement mode + */ + +#define AUADC_ADC_MEASURE_RATE_SPS_2_5 0 +#define AUADC_ADC_MEASURE_RATE_SPS_5 1 +#define AUADC_ADC_MEASURE_RATE_SPS_10 2 +#define AUADC_ADC_MEASURE_RATE_SPS_20 3 +#define AUADC_ADC_MEASURE_RATE_SPS_25 4 +#define AUADC_ADC_MEASURE_RATE_SPS_50 5 +#define AUADC_ADC_MEASURE_RATE_SPS_100 6 +#define AUADC_ADC_MEASURE_RATE_SPS_200 7 +#define AUADC_ADC_MEASURE_RATE_SPS_400 8 +#define AUADC_ADC_MEASURE_RATE_SPS_800 9 +#define AUADC_ADC_MEASURE_RATE_SPS_1000 10 +#define AUADC_ADC_MEASURE_RATE_SPS_2000 11 +#define AUADC_ADC_MEASURE_RATE_SPS_4000 12 + +/** + * @} + */ + +/** + * @brief AUADC_ADC_MODE auadc adc mode + */ +#define AUADC_ADC_MODE_AUDIO 0 +#define AUADC_ADC_MODE_MEASURE 1 +/** + * @} + */ + +/** + * @brief AUADC_ADC_PGA_MODE auadc adc mode, Ac or DC, differential or single + */ +#define AUADC_ADC_PGA_MODE_AC_DIFFER 0 +#define AUADC_ADC_PGA_MODE_AC_SINGLE 1 +#define AUADC_ADC_PGA_MODE_DC_DIFFER 2 +#define AUADC_ADC_PGA_MODE_DC_SINGLE 3 +/** + * @} + */ + +/** @defgroup AUADC_INTSTS auadc interrupt status definition + * @{ + */ +#define AUADC_INTSTS_FIFO_OVER (1 << 1) +#define AUADC_INTSTS_FIFO_UNDER (1 << 2) +#define AUADC_INTSTS_FIFO_AVAILABLE (1 << 3) +/** + * @} + */ + +/** @defgroup AUADC_CMD auadc feature control cmd definition + * @{ + */ +#define AUADC_CMD_RECORD_START (0x01) +#define AUADC_CMD_RECORD_STOP (0x02) +#define AUADC_CMD_SET_VOLUME_VAL (0x03) +#define AUADC_CMD_SET_PGA_GAIN_VAL (0x04) +#define AUADC_CMD_CLEAR_RX_FIFO (0x05) +#define AUADC_CMD_GET_RX_FIFO_CNT (0x06) +/** + * @} + */ + +/** + * @brief auadc initialization configuration structure + * + * @param sampling_rate auadc sampling rate, use @ref AUADC_SAMPLING_RATE + * @param input_mode auadc mode, use @ref AUADC_INPUT_MODE + * @param data_format auadc fifo data format, use @ref AUADC_DATA_FORMAT + * @param fifo_threshold auadc tx fifo threshold, 0 ~ 15 + */ +struct bflb_auadc_init_config_s { + uint8_t sampling_rate; + uint8_t input_mode; + uint8_t data_format; + uint8_t fifo_threshold; +}; + +/** + * @brief auadc adc analog initialization configuration structure + * + * @param analog_adc_en auadc sampling rate, use true or false + * @param adc_mode auadc adc work pattern, use @ref AUADC_ADC_MODE + * @param adc_pga_mode auadc adc PGA mode, use @ref AUADC_ADC_PGA_MODE + * @param adc_pga_posi_ch auadc adc positive channel selection, use @ref AUADC_ADC_ANALOG_CH + * @param adc_pga_nega_ch auadc adc negative channel selection, This channel is valid only when adc_pga_mode is differential, use @ref AUADC_ADC_ANALOG_CH + * @param adc_pga_gain auadc adc PGA Gain control, 6dB ~ 42dB, step by 3db + * @param adc_measure_rate auadc adc sampling rate in measurement mode @256K_measure, use @ref AUADC_ADC_MEASURE_RATE + */ +struct bflb_auadc_adc_init_config_s { + uint8_t auadc_analog_en; + uint8_t adc_mode; + uint8_t adc_pga_mode; + uint8_t adc_pga_posi_ch; + uint8_t adc_pga_nega_ch; + uint8_t adc_pga_gain; + uint8_t adc_measure_rate; +}; + +int bflb_auadc_init(struct bflb_device_s *dev, const struct bflb_auadc_init_config_s *config); + +int bflb_auadc_adc_init(struct bflb_device_s *dev, const struct bflb_auadc_adc_init_config_s *config); + +int bflb_auadc_link_rxdma(struct bflb_device_s *dev, bool enable); + +int bflb_auadc_int_mask(struct bflb_device_s *dev, uint32_t mask); + +int bflb_auadc_get_intstatus(struct bflb_device_s *dev); + +int bflb_auadc_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); + +#endif \ No newline at end of file diff --git a/drivers/soc/bl616/std/include/bl616_common_s.h b/drivers/soc/bl616/std/include/bl616_common_s.h deleted file mode 100644 index 1f5a8abe..00000000 --- a/drivers/soc/bl616/std/include/bl616_common_s.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef __BL616_COMMON_S_H__ -#define __BL616_COMMON_S_H__ - -#include "bl616.h" -#include "bl616_common.h" -#include "bflb_platform.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup COMMON_S - * @{ - */ - -/** @defgroup COMMON_S_Public_Types - * @{ - */ - -/*@} end of group COMMON_S_Public_Types */ - -/** @defgroup COMMON_S_Public_Constants - * @{ - */ - -/** @defgroup DRIVER_INT_PERIPH - * @{ - */ - -/*@} end of group DRIVER_INT_PERIPH */ - -/** @defgroup DRIVER_INT_MASK - * @{ - */ - -/*@} end of group COMMON_S_Public_Constants */ - -/** @defgroup COMMON_S_Public_Macros - * @{ - */ - -/** - * @brief error_number Type definition - */ -typedef enum { - COPY_SUCCESS = 0, - PARAM_ERROR = 1, - BUFFER_OVERLAP = 2, - SIZE_MISMATCHING = 3, - DST_OVERFLOW = 4, -}errno_t; - -/** - * @brief Interrupt callback function type - */ - -/*@} end of group DRIVER_Public_Macro */ - -/** @defgroup DRIVER_Public_FunctionDeclaration - * @brief DRIVER functions declaration - * @{ - */ - -errno_t memcpy_s(void *dst, size_t dstSize, const void *src, size_t count); - -/*@} end of group DRIVER_COMMON_S */ - -#endif /* __BL616_COMMON_S_H__ */ diff --git a/drivers/soc/bl616/std/include/bl616_glb.h b/drivers/soc/bl616/std/include/bl616_glb.h index d309144c..21052332 100644 --- a/drivers/soc/bl616/std/include/bl616_glb.h +++ b/drivers/soc/bl616/std/include/bl616_glb.h @@ -42,11 +42,11 @@ #include "pds_reg.h" #include "bl616_gpio.h" #include "bl616_hbn.h" -#include "bl616_sf_ctrl.h" -#include "bl616_sf_cfg.h" #include "bl616_aon.h" #include "bl616_pds.h" #include "bl616_common.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" /** @addtogroup BL616_Peripheral_Driver * @{ diff --git a/drivers/soc/bl616/std/include/bl616_glb_gpio.h b/drivers/soc/bl616/std/include/bl616_glb_gpio.h index 23299d0d..490b7ef6 100644 --- a/drivers/soc/bl616/std/include/bl616_glb_gpio.h +++ b/drivers/soc/bl616/std/include/bl616_glb_gpio.h @@ -41,11 +41,10 @@ #include "pds_reg.h" #include "bl616_gpio.h" #include "bl616_hbn.h" -#include "bl616_sf_ctrl.h" -// #include "bl616_sf_cfg.h" #include "bl616_aon.h" #include "bl616_pds.h" #include "bl616_common.h" +#include "bflb_sf_ctrl.h" /** @addtogroup BL616_Peripheral_Driver * @{ diff --git a/drivers/soc/bl616/std/include/bl616_hbn.h b/drivers/soc/bl616/std/include/bl616_hbn.h index 73e8e4a7..866d0b39 100644 --- a/drivers/soc/bl616/std/include/bl616_hbn.h +++ b/drivers/soc/bl616/std/include/bl616_hbn.h @@ -39,8 +39,8 @@ #include "hbn_reg.h" #include "bl616_aon.h" #include "bl616_l1c.h" -#include "bl616_sflash.h" #include "bl616_common.h" +#include "bflb_sflash.h" /** @addtogroup BL616_Peripheral_Driver * @{ @@ -293,7 +293,7 @@ typedef struct uint32_t sleepTime; /*!< HBN sleep time */ uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ HBN_LEVEL_Type hbnLevel; /*!< HBN level */ HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ uint8_t dcdcPuSeq; /*!< power on dcdc sequence */ @@ -579,7 +579,7 @@ void HBN_OUT1_IRQHandler(void); #endif /*----------*/ void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); -void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg); void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq); BL_Err_Type HBN_Reset(void); /*----------*/ diff --git a/drivers/soc/bl616/std/include/bl616_mfg_flash.h b/drivers/soc/bl616/std/include/bl616_mfg_flash.h index 935bffa8..4480272b 100644 --- a/drivers/soc/bl616/std/include/bl616_mfg_flash.h +++ b/drivers/soc/bl616/std/include/bl616_mfg_flash.h @@ -2,7 +2,7 @@ #define __BL616_MFG_FLASH_H__ #include "stdint.h" -#include "bl616_xip_sflash.h" +#include "bflb_xip_sflash.h" typedef struct rf_para_flash_tag { uint32_t magic; //"RFPA" @@ -16,7 +16,7 @@ typedef struct rf_para_flash_tag { uint32_t crc32; } rf_para_flash_t; -int mfg_flash_init(SPI_Flash_Cfg_Type *flashCfg); +int mfg_flash_init(spi_flash_cfg_type *flashCfg); int mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program); void mfg_flash_write_xtal_capcode(void); int mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload); diff --git a/drivers/soc/bl616/std/include/bl616_mfg_media.h b/drivers/soc/bl616/std/include/bl616_mfg_media.h index c65c56b8..c325f802 100644 --- a/drivers/soc/bl616/std/include/bl616_mfg_media.h +++ b/drivers/soc/bl616/std/include/bl616_mfg_media.h @@ -5,8 +5,8 @@ #include "bl616_mfg_efuse.h" #include "bl616_mfg_flash.h" -int mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg); -int mfg_media_init_with_lock(SPI_Flash_Cfg_Type *flashCfg); +int mfg_media_init_need_lock(spi_flash_cfg_type *flashCfg); +int mfg_media_init_with_lock(spi_flash_cfg_type *flashCfg); uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload); int mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program); int mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program); diff --git a/drivers/soc/bl616/std/include/bl616_pds.h b/drivers/soc/bl616/std/include/bl616_pds.h index e2a4bba8..07ca104e 100644 --- a/drivers/soc/bl616/std/include/bl616_pds.h +++ b/drivers/soc/bl616/std/include/bl616_pds.h @@ -41,10 +41,10 @@ #include "bl616_clock.h" #include "bl616_aon.h" #include "bl616_hbn.h" -#include "bl616_sflash.h" -#include "bl616_sf_ctrl.h" #include "bl616_common.h" #include "bl616_acomp.h" +#include "bflb_sflash.h" +#include "bflb_sf_ctrl.h" #define PDS_WAKEUP_BY_PDS_TIMER_EN PDS_WAKEUP_BY_PDS_TIMER_EN #define PDS_WAKEUP_BY_PDS_TIMER_EN_POS (10U) @@ -445,7 +445,7 @@ typedef struct uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ uint8_t flashContRead; /*!< Whether enable flash continue read */ uint32_t sleepTime; /*!< PDS sleep time */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ void (*preCbFun)(void); /*!< Pre callback function */ void (*postCbFun)(void); /*!< Post callback function */ @@ -547,8 +547,8 @@ BL_Err_Type PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask); BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig); BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set); BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad); -BL_Err_Type PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg); -BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg); +BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg); +BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg); BL_Err_Type PDS_Disable_GPIO_Keep(void); BL_Err_Type PDS_Set_MCU0_Clock_Enable(void); BL_Err_Type PDS_Set_MCU0_Clock_Disable(void); diff --git a/drivers/soc/bl616/std/include/bl616_romapi_patch.h b/drivers/soc/bl616/std/include/bl616_romapi_patch.h index 3b775cce..53259618 100644 --- a/drivers/soc/bl616/std/include/bl616_romapi_patch.h +++ b/drivers/soc/bl616/std/include/bl616_romapi_patch.h @@ -36,9 +36,9 @@ #ifndef __BL616_ROMAPI_PATCH_H__ #define __BL616_ROMAPI_PATCH_H__ +#include "bflb_sflash.h" +#include "bflb_xip_sflash.h" #include "bl616_pds.h" -#include "bl616_sflash.h" -#include "bl616_xip_sflash.h" #include "bl616_clock.h" // #include "bl616_uart.h" diff --git a/drivers/soc/bl616/std/include/bl616_romdriver_e907.h b/drivers/soc/bl616/std/include/bl616_romdriver_e907.h index b8cda46c..2e23abef 100644 --- a/drivers/soc/bl616/std/include/bl616_romdriver_e907.h +++ b/drivers/soc/bl616/std/include/bl616_romdriver_e907.h @@ -37,12 +37,15 @@ #define __BL616_ROMDRIVER_E907_H__ #include "bl616_glb.h" +#include "bl616_glb_gpio.h" #include "bl616_pds.h" #include "bl616_hbn.h" #include "bl616_clock.h" -#include "bl616_sflash.h" -#include "bl616_xip_sflash.h" #include "bl616_ef_ctrl.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sflash.h" +#include "bflb_sf_cfg.h" +#include "bflb_xip_sflash.h" // #include "bl616_uart.h" /** @addtogroup bl616_Peripheral_Driver @@ -1393,7 +1396,7 @@ typedef enum { ((void (*) (HBN_APP_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter]) #define RomDriver_HBN_Power_Down_Flash \ - ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash]) #define RomDriver_L1C_DCache_Clean_All \ ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Clean_All]) @@ -1462,10 +1465,10 @@ typedef enum { ((BL_Err_Type (*) (PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, PDS_CTRL_RAM3_Type *ram3Cfg, PDS_CTRL_RAM4_Type *ram4Cfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config]) #define RomDriver_PDS_Set_Flash_Pad_Pull_None \ - ((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None]) + ((BL_Err_Type (*) (uint8_t pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None]) #define RomDriver_PDS_Set_Flash_Pad_Pull_None_Fast \ - ((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast]) + ((BL_Err_Type (*) (uint8_t pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast]) #define RomDriver_PDS_Set_GPIO_Pad_IntClr \ ((BL_Err_Type (*) (PDS_GPIO_INT_SET_Type set))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr]) @@ -1510,40 +1513,40 @@ typedef enum { ((BL_Sts_Type (*) (PDS_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_PDS_Get_IntStatus]) #define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ - ((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) + ((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) #define RomDriver_SF_Cfg_Flash_Init \ - ((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Init]) + ((int (*) (uint8_t sel, const struct sf_ctrl_cfg_type *pSfCtrlCfg, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Init]) #define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ - ((BL_Err_Type (*) (uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) + ((int (*) (uint32_t flashID, spi_flash_cfg_type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) #define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ - ((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) + ((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) #define RomDriver_SF_Cfg_Init_Flash2_Gpio \ - ((BL_Err_Type (*) (uint8_t swap))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash2_Gpio]) + ((int (*) (uint8_t swap))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash2_Gpio]) #define RomDriver_SF_Cfg_Init_Flash_Gpio \ - ((BL_Err_Type (*) (SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) + ((int (*) (uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) #define RomDriver_SF_Cfg_Sbus2_Flash_Init \ - ((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init]) + ((int (*) (uint8_t sel, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init]) #define RomDriver_SF_Cfg_Flash_Identify \ - ((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + ((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type *pFlashCfg, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) #define RomDriver_SF_Ctrl_GetBusyState \ - ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) + ((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) #define RomDriver_SF_Ctrl_Is_AES_Enable \ - ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) + ((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]) #define RomDriver_SF_Ctrl_Is_Sbus2_Enable \ - ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable]) + ((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable]) #define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \ - ((uint32_t (*) (uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) + ((uint32_t (*) (uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) #define RomDriver_SF_Ctrl_Get_Clock_Delay \ ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]) @@ -1573,13 +1576,13 @@ typedef enum { ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE]) #define RomDriver_SF_Ctrl_AES_Set_Key \ - ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) + ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) #define RomDriver_SF_Ctrl_AES_Set_Key_BE \ - ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) + ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) #define RomDriver_SF_Ctrl_AES_Set_Mode \ - ((void (*) (SF_Ctrl_AES_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Mode]) + ((void (*) (uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Mode]) #define RomDriver_SF_Ctrl_AES_Set_Region \ ((void (*) (uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) @@ -1591,16 +1594,16 @@ typedef enum { ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV_BE]) #define RomDriver_SF_Ctrl_AES_XTS_Set_Key \ - ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key]) + ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key]) #define RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE \ - ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE]) + ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE]) #define RomDriver_SF_Ctrl_Bank2_Enable \ - ((void (*) (const SF_Ctrl_Bank2_Cfg *bank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Bank2_Enable]) + ((void (*) (const struct sf_ctrl_bank2_cfg *bank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Bank2_Enable]) #define RomDriver_SF_Ctrl_Cmds_Set \ - ((void (*) (SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set]) + ((void (*) (struct sf_ctrl_cmds_cfg *cmdsCfg, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set]) #define RomDriver_SF_Ctrl_Disable \ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) @@ -1609,19 +1612,19 @@ typedef enum { ((void (*) (uint8_t disable))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable_Wrap_Access]) #define RomDriver_SF_Ctrl_Enable \ - ((void (*) (const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) + ((void (*) (const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) #define RomDriver_SF_Ctrl_Flash2_Read_Icache_Set \ - ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set]) + ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set]) #define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \ - ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]) + ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]) #define RomDriver_SF_Ctrl_Lock_Flash_Image_Offset \ ((void (*) (uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Lock_Flash_Image_Offset]) #define RomDriver_SF_Ctrl_Remap_Set \ - ((void (*) (SF_Ctrl_Remap_Type remap, uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Remap_Set]) + ((void (*) (uint8_t remap, uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Remap_Set]) #define RomDriver_SF_Ctrl_Sbus2_Hold_Sram \ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Hold_Sram]) @@ -1630,7 +1633,7 @@ typedef enum { ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Release_Sram]) #define RomDriver_SF_Ctrl_Sbus2_Replace \ - ((void (*) (SF_Ctrl_Pad_Type pad))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Replace]) + ((void (*) (uint8_t pad))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Replace]) #define RomDriver_SF_Ctrl_Sbus2_Revoke_replace \ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Revoke_replace]) @@ -1639,109 +1642,109 @@ typedef enum { ((void (*) (uint8_t clkDelay, uint8_t rxClkInvert))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Set_Delay]) #define RomDriver_SF_Ctrl_Sbus_Select_Bank \ - ((void (*) (SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank]) + ((void (*) (uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank]) #define RomDriver_SF_Ctrl_Select_Pad \ - ((void (*) (SF_Ctrl_Pin_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) + ((void (*) (uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) #define RomDriver_SF_Ctrl_SendCmd \ - ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) + ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) #define RomDriver_SF_Ctrl_Set_Clock_Delay \ ((void (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) #define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \ - ((void (*) (uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset]) + ((void (*) (uint32_t addrOffset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset]) #define RomDriver_SF_Ctrl_Set_IO_Delay \ - ((void (*) (SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_IO_Delay]) + ((void (*) (uint8_t pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_IO_Delay]) #define RomDriver_SF_Ctrl_Set_Owner \ - ((void (*) (SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) + ((void (*) (uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) #define RomDriver_SFlash_Blk32_Erase \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) #define RomDriver_SFlash_Blk64_Erase \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) #define RomDriver_SFlash_Chip_Erase \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) + ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) #define RomDriver_SFlash_Erase \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) #define RomDriver_SFlash_Erase_Security_Register \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase_Security_Register]) + ((int (*) (spi_flash_cfg_type *pFlashCfg, struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase_Security_Register]) #define RomDriver_SFlash_IDbus_Read_Enable \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) #define RomDriver_SFlash_Program \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) #define RomDriver_SFlash_Program_Security_Register \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Program_Security_Register]) + ((int (*) (spi_flash_cfg_type *pFlashCfg, struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Program_Security_Register]) #define RomDriver_SFlash_Qspi_Disable \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Disable]) + ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Disable]) #define RomDriver_SFlash_Qspi_Enable \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) + ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) #define RomDriver_SFlash_RCV_Enable \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos))ROM_APITABLE[ROM_API_INDEX_SFlash_RCV_Enable]) + ((int (*) (spi_flash_cfg_type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos))ROM_APITABLE[ROM_API_INDEX_SFlash_RCV_Enable]) #define RomDriver_SFlash_Read \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) #define RomDriver_SFlash_Read_Reg \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) #define RomDriver_SFlash_Read_Reg_With_Cmd \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) #define RomDriver_SFlash_Read_Security_Register \ - ((BL_Err_Type (*) (SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Security_Register]) + ((int (*) (struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Security_Register]) #define RomDriver_SFlash_Restore_From_Powerdown \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) + ((int (*) (spi_flash_cfg_type *pFlashCfg, uint8_t flashContRead, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) #define RomDriver_SFlash_Sector_Erase \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) #define RomDriver_SFlash_Set32BitsAddrMode \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Set32BitsAddrMode]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Set32BitsAddrMode]) #define RomDriver_SFlash_SetSPIMode \ - ((BL_Err_Type (*) (SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) + ((int (*) (uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) #define RomDriver_SFlash_Set_IDbus_Cfg \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint32_t len, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) #define RomDriver_SFlash_Software_Reset \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) + ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) #define RomDriver_SFlash_Write_Enable \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) + ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) #define RomDriver_SFlash_Write_Reg \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) #define RomDriver_SFlash_Write_Reg_With_Cmd \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) + ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) #define RomDriver_SFlash_Busy \ - ((BL_Sts_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) + ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) #define RomDriver_SFlash_DisableBurstWrap \ - ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) #define RomDriver_SFlash_GetDeviceId \ - ((void (*) (uint8_t *data, BL_Fun_Type is32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) + ((void (*) (uint8_t *data, uint8_t is32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) #define RomDriver_SFlash_GetJedecId \ - ((void (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) + ((void (*) (spi_flash_cfg_type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) #define RomDriver_SFlash_GetUniqueId \ ((void (*) (uint8_t *data, uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) @@ -1750,22 +1753,22 @@ typedef enum { ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Disable]) #define RomDriver_SFlash_Init \ - ((void (*) (const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) + ((void (*) (const struct sf_ctrl_cfg_type *pSfCtrlCfg, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) #define RomDriver_SFlash_Powerdown \ ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) #define RomDriver_SFlash_Release_Powerdown \ - ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Release_Powerdown]) + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Release_Powerdown]) #define RomDriver_SFlash_Reset_Continue_Read \ - ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) #define RomDriver_SFlash_SetBurstWrap \ - ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) #define RomDriver_SFlash_Volatile_Reg_Write_Enable \ - ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) + ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) #define RomDriver_UART_AutoBaudDetection \ ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type autoBaud))ROM_APITABLE[ROM_API_INDEX_UART_AutoBaudDetection]) @@ -1876,31 +1879,31 @@ typedef enum { ((uint8_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetTxFifoCount]) #define RomDriver_XIP_SFlash_Erase_Need_Lock \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) #define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) #define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) #define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) #define RomDriver_XIP_SFlash_Read_Need_Lock \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) #define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ ((BL_Err_Type (*) (uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) #define RomDriver_XIP_SFlash_State_Restore \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t offset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) #define RomDriver_XIP_SFlash_State_Save \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t *offset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) #define RomDriver_XIP_SFlash_Write_Need_Lock \ - ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) + ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) #define RomDriver_XIP_SFlash_Opt_Enter \ ((void (*) (uint8_t *aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter]) diff --git a/drivers/soc/bl616/std/include/bl616_sf_cfg.h b/drivers/soc/bl616/std/include/bl616_sf_cfg.h deleted file mode 100644 index ba6299c3..00000000 --- a/drivers/soc/bl616/std/include/bl616_sf_cfg.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_sf_cfg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL616_SF_CFG_H__ -#define __BL616_SF_CFG_H__ - -#include "string.h" -#include "bl616_glb.h" -#include "bl616_glb_gpio.h" -#include "bl616_sflash.h" -#include "bl616_sf_ctrl.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Public_Types - * @{ - */ - -/*@} end of group SF_CFG_Public_Types */ - -/** @defgroup SF_CFG_Public_Constants - * @{ - */ - -/*@} end of group SF_CFG_Public_Constants */ - -/** @defgroup SF_CFG_Public_Macros - * @{ - */ -/* Flash option sf2 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_8 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_4 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_7 -#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_5 -#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_6 -#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_9 -/* Flash option sf3 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_11 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_15 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_12 -#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_14 -#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_13 -#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_10 -#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 -#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF - -/*@} end of group SF_CFG_Public_Macros */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); -BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault); -BL_Err_Type SF_Cfg_Init_Flash2_Gpio(uint8_t swap); -BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); -BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); -uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); -BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL616_Peripheral_Driver */ - -#endif /* __BL616_SF_CFG_H__ */ diff --git a/drivers/soc/bl616/std/include/bl616_sf_ctrl.h b/drivers/soc/bl616/std/include/bl616_sf_ctrl.h deleted file mode 100644 index 394de88c..00000000 --- a/drivers/soc/bl616/std/include/bl616_sf_ctrl.h +++ /dev/null @@ -1,483 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_sf_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL616_SF_CTRL_H__ -#define __BL616_SF_CTRL_H__ - -#include "sf_ctrl_reg.h" -#include "bl616_common.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Serial flash pad type definition - */ -typedef enum { - SF_CTRL_PAD1, /*!< SF Ctrl pad 1 */ - SF_CTRL_PAD2, /*!< SF Ctrl pad 2 */ - SF_CTRL_PAD3, /*!< SF Ctrl pad 3 */ -} SF_Ctrl_Pad_Type; - -/** - * @brief Serial flash config pin select type definition - */ -typedef enum { - SF_IO_EMB_SWAP_IO3IO0 = 0x0, /*!< SF select embedded flash swap io3 with io0 */ - SF_IO_EMB_SWAP_IO3IO0_IO2CS = 0x1, /*!< SF select embedded flash swap io3 with io0 and io2 with cs */ - SF_IO_EMB_SWAP_NONE = 0x2, /*!< SF select embedded flash no swap */ - SF_IO_EMB_SWAP_IO2CS = 0x3, /*!< SF select embedded flash swap io2 with cs */ - SF_IO_EXT_SF2_SWAP_IO3IO0 = 0x4, /*!< SF select external flash SF2 use gpio4-9 and SF2 swap io3 with io0 */ - SF_IO_EXT_SF3 = 0x8, /*!< SF select external flash SF3 use gpio10-15 */ - SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 = 0x14, /*!< SF select embedded flash swap io3 with io0 and SF2 swap io3 with io0*/ - SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0 = 0x15, /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 swap io3 with io0 */ - SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0 = 0x16, /*!< SF select embedded flash no swap and SF2 swap io3 with io0 */ - SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0 = 0x17, /*!< SF select embedded flash swap io2 with cs, and SF2 swap io3 with io0 */ - SF_IO_EXT_SF2 = 0x24, /*!< SF select external flash SF2 use gpio4-9 */ - SF_IO_EMB_SWAP_IO3IO0_AND_SF2 = 0x34, /*!< SF select embedded flash swap io3 with io0 and SF2 use gpio4-9 */ - SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2 = 0x35, /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 use gpio4-9 */ - SF_IO_EMB_SWAP_NONE_AND_SF2 = 0x36, /*!< SF select embedded flash no swap and SF2 use gpio4-9 */ - SF_IO_EMB_SWAP_IO2CS_AND_SF2 = 0x37, /*!< SF select embedded flash swap io2 with cs and SF2 use gpio4-9 */ -} SF_Ctrl_Pin_Select; - -/** - * @brief Serial flash select bank control type definition - */ -typedef enum { - SF_CTRL_FLASH_BANK0, /*!< SF Ctrl select flash bank0 */ - SF_CTRL_FLASH_BANK1, /*!< SF Ctrl select flash bank1 */ -} SF_Ctrl_Bank_Select; - -/** - * @brief Serial flash controller wrap mode type definition - */ -typedef enum { - SF_CTRL_WRAP_MODE_0, /*!< Cmds bypass wrap commands to macro, original mode */ - SF_CTRL_WRAP_MODE_1, /*!< Cmds handle wrap commands, original mode */ - SF_CTRL_WRAP_MODE_2, /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */ - SF_CTRL_WRAP_MODE_3, /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */ -} SF_Ctrl_Wrap_Mode; - -/** - * @brief Serail flash controller wrap mode len type definition - */ -typedef enum { - SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */ - SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */ - SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */ - SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */ - SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */ - SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */ - SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */ - SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */ - SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */ - SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */ -} SF_Ctrl_Wrap_Len_Type; - -/** - * @brief Serail flash controller memory remap type define - */ -typedef enum { - SF_CTRL_ORIGINAL_MEMORY_MAP, /*!< Remap none, use two addr map when use dual flash */ - SF_CTRL_REMAP_16MB, /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */ - SF_CTRL_REMAP_8MB, /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */ - SF_CTRL_REMAP_4MB, /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */ -} SF_Ctrl_Remap_Type; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ - SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ -} SF_Ctrl_Owner_Type; - -/** - * @brief Read and write type definition - */ -typedef enum { - SF_CTRL_READ, /*!< Serail flash read command flag */ - SF_CTRL_WRITE, /*!< Serail flash write command flag */ -} SF_Ctrl_RW_Type; - -/** - * @brief Serail flash interface IO type definition - */ -typedef enum { - SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ - SF_CTRL_DO_MODE, /*!< Dual Output mode define */ - SF_CTRL_QO_MODE, /*!< Quad Output mode define */ - SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ - SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ -} SF_Ctrl_IO_Type; - -/** - * @brief Serail flash controller interface mode type definition - */ -typedef enum { - SF_CTRL_SPI_MODE, /*!< SPI mode define */ - SF_CTRL_QPI_MODE, /*!< QPI mode define */ -} SF_Ctrl_Mode_Type; - -/** - * @brief Serail flash controller command mode type definition - */ -typedef enum { - SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ - SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ -} SF_Ctrl_Cmd_Mode_Type; - -/** - * @brief Serail flash controller address mode type definition - */ -typedef enum { - SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ - SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ - SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ -} SF_Ctrl_Addr_Mode_Type; - -/** - * @brief Serail flash controller dummy mode type definition - */ -typedef enum { - SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ - SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ - SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ -} SF_Ctrl_Dmy_Mode_Type; - -/** - * @brief Serail flash controller data mode type definition - */ -typedef enum { - SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ - SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ - SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ -} SF_Ctrl_Data_Mode_Type; - -/** - * @brief Serail flash controller AES mode type definition - */ -typedef enum { - SF_CTRL_AES_CTR_MODE, /*!< Serail flash AES CTR mode */ - SF_CTRL_AES_XTS_MODE, /*!< Serail flash AES XTS mode */ -} SF_Ctrl_AES_Mode_Type; - -/** - * @brief Serail flash controller AES key len type definition - */ -typedef enum { - SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ - SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ - SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ - SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ -} SF_Ctrl_AES_Key_Type; - -/** - * @brief Serail flash controller configuration structure type definition - */ -typedef struct -{ - SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ - BL_Fun_Type en32bAddr; /*!< Sflash enable 32-bits address */ - uint8_t clkDelay; /*!< Clock count for read due to pad delay */ - uint8_t clkInvert; /*!< Clock invert */ - uint8_t rxClkInvert; /*!< RX clock invert */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ -} SF_Ctrl_Cfg_Type; - -/** - * @brief SF Ctrl bank2 controller configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type sbus2Select; /*!< Select sbus2 as 2nd flash controller */ - BL_Fun_Type bank2RxClkInvertSrc; /*!< Select bank2 rx clock invert source */ - BL_Fun_Type bank2RxClkInvertSel; /*!< Select inveted bank2 rx clock */ - BL_Fun_Type bank2DelaySrc; /*!< Select bank2 read delay source */ - uint8_t bank2ClkDelay; /*!< Bank2 read delay cycle = n + 1 */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ - SF_Ctrl_Remap_Type remap; /*!< Select dual flash memory remap set */ - uint8_t remapLock; /*!< Select memory remap lock */ -} SF_Ctrl_Bank2_Cfg; - -/** - * @brief SF Ctrl cmds configuration structure type definition - */ -typedef struct -{ - uint8_t ackLatency; /*!< SF Ctrl ack latency cycles */ - BL_Fun_Type cmdsCoreEn; /*!< SF Ctrl cmds core enable */ - BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */ - SF_Ctrl_Wrap_Mode cmdsWrapMode; /*!< SF Ctrl cmds wrap mode */ - SF_Ctrl_Wrap_Len_Type cmdsWrapLen; /*!< SF Ctrl cmds wrap length */ -} SF_Ctrl_Cmds_Cfg; - -/** - * @brief Serail flash command configuration structure type definition - */ -typedef struct -{ - uint8_t rwFlag; /*!< Read write flag */ - SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ - SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ - uint8_t addrSize; /*!< Address size */ - uint8_t dummyClks; /*!< Dummy clocks */ - SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ - SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ - uint8_t rsv[1]; /*!< */ - uint32_t nbData; /*!< Transfer number of bytes */ - uint32_t cmdBuf[2]; /*!< Command buffer */ -} SF_Ctrl_Cmd_Cfg_Type; - -/*@} end of group SF_CTRL_Public_Types */ - -/** @defgroup SF_CTRL_Public_Constants - * @{ - */ - -/** @defgroup SF_CTRL_PAD_TYPE - * @{ - */ -#define IS_SF_CTRL_PAD_TYPE(type) (((type) == SF_CTRL_PAD1) || \ - ((type) == SF_CTRL_PAD2) || \ - ((type) == SF_CTRL_PAD3)) - -/** @defgroup SF_CTRL_PIN_SELECT - * @{ - */ -#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO3IO0) || \ - ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS) || \ - ((type) == SF_IO_EMB_SWAP_NONE) || \ - ((type) == SF_IO_EMB_SWAP_IO2CS) || \ - ((type) == SF_IO_EXT_SF2_SWAP_IO3IO0) || \ - ((type) == SF_IO_EXT_SF3) || \ - ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0) || \ - ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0) || \ - ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0) || \ - ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) || \ - ((type) == SF_IO_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2) || \ - ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2) || \ - ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2) || \ - ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2)) - - -/** @defgroup SF_CTRL_BANK_SELECT - * @{ - */ -#define IS_SF_CTRL_BANK_SELECT(type) (((type) == SF_CTRL_FLASH_BANK0) || \ - ((type) == SF_CTRL_FLASH_BANK1)) - -/** @defgroup SF_CTRL_WRAP_MODE - * @{ - */ -#define IS_SF_CTRL_WRAP_MODE(type) (((type) == SF_CTRL_WRAP_MODE_0) || \ - ((type) == SF_CTRL_WRAP_MODE_1) || \ - ((type) == SF_CTRL_WRAP_MODE_2) || \ - ((type) == SF_CTRL_WRAP_MODE_3)) - -/** @defgroup SF_CTRL_WRAP_LEN_TYPE - * @{ - */ -#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \ - ((type) == SF_CTRL_WRAP_LEN_16) || \ - ((type) == SF_CTRL_WRAP_LEN_32) || \ - ((type) == SF_CTRL_WRAP_LEN_64) || \ - ((type) == SF_CTRL_WRAP_LEN_128) || \ - ((type) == SF_CTRL_WRAP_LEN_256) || \ - ((type) == SF_CTRL_WRAP_LEN_512) || \ - ((type) == SF_CTRL_WRAP_LEN_1024) || \ - ((type) == SF_CTRL_WRAP_LEN_2048) || \ - ((type) == SF_CTRL_WRAP_LEN_4096)) - -/** @defgroup SF_CTRL_REMAP_TYPE - * @{ - */ -#define IS_SF_CTRL_REMAP_TYPE(type) (((type) == SF_CTRL_ORIGINAL_MEMORY_MAP) || \ - ((type) == SF_CTRL_REMAP_16MB) || \ - ((type) == SF_CTRL_REMAP_8MB) || \ - ((type) == SF_CTRL_REMAP_4MB)) - -/** @defgroup SF_CTRL_OWNER_TYPE - * @{ - */ -#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ - ((type) == SF_CTRL_OWNER_IAHB)) - -/** @defgroup SF_CTRL_RW_TYPE - * @{ - */ -#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ - ((type) == SF_CTRL_WRITE)) - -/** @defgroup SF_CTRL_IO_TYPE - * @{ - */ -#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ - ((type) == SF_CTRL_DO_MODE) || \ - ((type) == SF_CTRL_QO_MODE) || \ - ((type) == SF_CTRL_DIO_MODE) || \ - ((type) == SF_CTRL_QIO_MODE)) - -/** @defgroup SF_CTRL_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ - ((type) == SF_CTRL_QPI_MODE)) - -/** @defgroup SF_CTRL_CMD_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ - ((type) == SF_CTRL_CMD_4_LINES)) - -/** @defgroup SF_CTRL_ADDR_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ - ((type) == SF_CTRL_ADDR_2_LINES) || \ - ((type) == SF_CTRL_ADDR_4_LINES)) - -/** @defgroup SF_CTRL_DMY_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ - ((type) == SF_CTRL_DUMMY_2_LINES) || \ - ((type) == SF_CTRL_DUMMY_4_LINES)) - -/** @defgroup SF_CTRL_DATA_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ - ((type) == SF_CTRL_DATA_2_LINES) || \ - ((type) == SF_CTRL_DATA_4_LINES)) - -/** @defgroup SF_CTRL_AES_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_MODE_TYPE(type) (((type) == SF_CTRL_AES_CTR_MODE) || \ - ((type) == SF_CTRL_AES_XTS_MODE)) - -/** @defgroup SF_CTRL_AES_KEY_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ - ((type) == SF_CTRL_AES_256BITS) || \ - ((type) == SF_CTRL_AES_192BITS) || \ - ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) - -/*@} end of group SF_CTRL_Public_Constants */ - -/** @defgroup SF_CTRL_Public_Macros - * @{ - */ -#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF -#define NOR_FLASH_CTRL_BUF_SIZE 256 -#define NAND_FLASH_CTRL_BUF_SIZE 512 - -/*@} end of group SF_CTRL_Public_Macros */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void); -#endif -void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); -void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg); -void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay); -void SF_Ctrl_Sbus2_Hold_Sram(void); -void SF_Ctrl_Sbus2_Release_Sram(void); -BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void); -void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad); -void SF_Ctrl_Sbus2_Revoke_replace(void); -void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert); -void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr); -uint8_t SF_Ctrl_Get_Clock_Delay(void); -void SF_Ctrl_Set_Clock_Delay(uint8_t delay); -uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void); -void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock); -void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel); -void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); -void SF_Ctrl_Disable(void); -void SF_Ctrl_AES_Enable_BE(void); -void SF_Ctrl_AES_Enable_LE(void); -void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, - uint8_t locked); -void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode); -void SF_Ctrl_AES_Enable(void); -void SF_Ctrl_AES_Disable(void); -BL_Sts_Type SF_Ctrl_Is_AES_Enable(void); -void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock); -void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); -void SF_Ctrl_Disable_Wrap_Access(uint8_t disable); -void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -BL_Sts_Type SF_Ctrl_GetBusyState(void); - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL616_Peripheral_Driver */ - -#endif /* __BL616_SF_CTRL_H__ */ diff --git a/drivers/soc/bl616/std/include/bl616_sflash.h b/drivers/soc/bl616/std/include/bl616_sflash.h deleted file mode 100644 index 2cdab119..00000000 --- a/drivers/soc/bl616/std/include/bl616_sflash.h +++ /dev/null @@ -1,220 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_sflah.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL616_SFLAH_H__ -#define __BL616_SFLAH_H__ - -#include "bl616_common.h" -#include "bl616_sf_ctrl.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLAH - * @{ - */ - -/** @defgroup SFLAH_Public_Types - * @{ - */ - -/** - * @brief Serial flash configuration structure type definition - */ -typedef struct -{ - uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */ - uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - uint8_t resetEnCmd; /*!< Flash enable reset command */ - uint8_t resetCmd; /*!< Flash reset command */ - uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ - uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ - uint8_t jedecIdCmd; /*!< JEDEC ID command */ - uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ - uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ - uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ - uint8_t sectorSize; /*!< *1024bytes */ - uint8_t mid; /*!< Manufacturer ID */ - uint16_t pageSize; /*!< Page size */ - uint8_t chipEraseCmd; /*!< Chip erase cmd */ - uint8_t sectorEraseCmd; /*!< Sector erase command */ - uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ - uint8_t blk64EraseCmd; /*!< Block 64K erase command */ - uint8_t writeEnableCmd; /*!< Need before every erase or program */ - uint8_t pageProgramCmd; /*!< Page program cmd */ - uint8_t qpageProgramCmd; /*!< QIO page program cmd */ - uint8_t qppAddrMode; /*!< QIO page program address mode */ - uint8_t fastReadCmd; /*!< Fast read command */ - uint8_t frDmyClk; /*!< Fast read command dummy clock */ - uint8_t qpiFastReadCmd; /*!< QPI fast read command */ - uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ - uint8_t fastReadDoCmd; /*!< Fast read dual output command */ - uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ - uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ - uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ - uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ - uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ - uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ - uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ - uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ - uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ - uint8_t qpiPageProgramCmd; /*!< QPI program command */ - uint8_t writeVregEnableCmd; /*!< Enable write reg */ - uint8_t wrEnableIndex; /*!< Write enable register index */ - uint8_t qeIndex; /*!< Quad mode enable register index */ - uint8_t busyIndex; /*!< Busy status register index */ - uint8_t wrEnableBit; /*!< Write enable bit pos */ - uint8_t qeBit; /*!< Quad enable bit pos */ - uint8_t busyBit; /*!< Busy status bit pos */ - uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ - uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ - uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ - uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ - uint8_t releasePowerDown; /*!< Release power down command */ - uint8_t busyReadRegLen; /*!< Register length of contain busy status */ - uint8_t readRegCmd[4]; /*!< Read register command buffer */ - uint8_t writeRegCmd[4]; /*!< Write register command buffer */ - uint8_t enterQpi; /*!< Enter qpi command */ - uint8_t exitQpi; /*!< Exit qpi command */ - uint8_t cReadMode; /*!< Config data for continuous read mode */ - uint8_t cRExit; /*!< Config data for exit continuous read mode */ - uint8_t burstWrapCmd; /*!< Enable burst wrap command */ - uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ - uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t burstWrapData; /*!< Data to enable burst wrap */ - uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ - uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ - uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ - uint16_t timeEsector; /*!< 4K erase time */ - uint16_t timeE32k; /*!< 32K erase time */ - uint16_t timeE64k; /*!< 64K erase time */ - uint16_t timePagePgm; /*!< Page program time */ - uint16_t timeCe; /*!< Chip erase time in ms */ - uint8_t pdDelay; /*!< Release power down command delay time for wake up */ - uint8_t qeData; /*!< QE set data */ -} __attribute__((packed)) SPI_Flash_Cfg_Type; - -/** - * @brief Serial flash security register configuration - */ -typedef struct -{ - uint8_t eraseCmd; /*!< Erase security register command */ - uint8_t programCmd; /*!< Program security register command */ - uint8_t readCmd; /*!< Read security register command */ - uint8_t enterSecOptCmd; /*!< Enter security register option mode command */ - uint8_t exitSecOptCmd; /*!< Exit security register option mode command */ - uint8_t blockNum; /*!< Security register block number */ - uint8_t *data; /*!< Data pointer to be program/read */ - uint32_t addr; /*!< Start address to be program/read */ - uint32_t len; /*!< Data length to be program/read */ -} SFlash_Sec_Reg_Cfg; -/*@} end of group SFLAH_Public_Types */ - -/** @defgroup SFLAH_Public_Constants - * @{ - */ - -/*@} end of group SFLAH_Public_Constants */ - -/** @defgroup SFLAH_Public_Macros - * @{ - */ -#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) -#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) -#define BFLB_SPIFLASH_CMD_INVALID 0xff - -/*@} end of group SFLAH_Public_Macros */ - -/** @defgroup SFLAH_Public_Functions - * @{ - */ -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); -BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); -BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum); -BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr); -void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen); -void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data); -void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr); -void SFlash_Powerdown(void); -void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, - SF_Ctrl_Bank_Select bank); -void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr); -BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, - uint32_t len, SF_Ctrl_Bank_Select bank); -BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - SF_Ctrl_Bank_Select bank); -void SFlash_IDbus_Read_Disable(void); -BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos); -BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, - SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, - uint32_t len); -BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); - -BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *flashCfg); - -/*@} end of group SFLAH_Public_Functions */ - -/*@} end of group SFLAH */ - -/*@} end of group BL616_Peripheral_Driver */ - -#endif /* __BL616_SFLAH_H__ */ diff --git a/drivers/soc/bl616/std/include/bl616_xip_sflash.h b/drivers/soc/bl616/std/include/bl616_xip_sflash.h deleted file mode 100644 index e25ed98f..00000000 --- a/drivers/soc/bl616/std/include/bl616_xip_sflash.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_xip_sflash.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL616_XIP_SFLASH_H__ -#define __BL616_XIP_SFLASH_H__ - -#include "bl616_common.h" -#include "bl616_sflash.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Public_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Types */ - -/** @defgroup XIP_SFLASH_Public_Constants - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Constants */ - -/** @defgroup XIP_SFLASH_Public_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Macros */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ -BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, - int len, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, - uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, - uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, - uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len); -void XIP_SFlash_Opt_Enter(uint8_t *aesEnable); -void XIP_SFlash_Opt_Exit(uint8_t aesEnable); - -BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank); - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL616_Peripheral_Driver */ - -#endif /* __BL616_XIP_SFLASH_H__ */ diff --git a/drivers/soc/bl616/std/include/hardware/auadc_reg.h b/drivers/soc/bl616/std/include/hardware/auadc_reg.h index b9fd9a2f..89fee9bc 100644 --- a/drivers/soc/bl616/std/include/hardware/auadc_reg.h +++ b/drivers/soc/bl616/std/include/hardware/auadc_reg.h @@ -48,15 +48,7 @@ #define AUADC_PDM_ADC_1_OFFSET (0xC0C) /* pdm_adc_1 */ #define AUADC_PDM_DAC_0_OFFSET (0xC10) /* pdm_dac_0 */ #define AUADC_PDM_PDM_0_OFFSET (0xC1C) /* pdm_pdm_0 */ -#define AUADC_PDM_RSVD0_OFFSET (0xC20) /* pdm_rsvd0 */ -#define AUADC_PDM_DBG_0_OFFSET (0xC24) /* pdm_dbg_0 */ -#define AUADC_PDM_DBG_1_OFFSET (0xC28) /* pdm_dbg_1 */ -#define AUADC_PDM_DBG_2_OFFSET (0xC2C) /* pdm_dbg_2 */ -#define AUADC_PDM_DBG_3_OFFSET (0xC30) /* pdm_dbg_3 */ -#define AUADC_PDM_DBG_4_OFFSET (0xC34) /* pdm_dbg_4 */ #define AUADC_PDM_ADC_S0_OFFSET (0xC38) /* pdm_adc_s0 */ -#define AUADC_PDM_ADC_S1_OFFSET (0xC3C) /* pdm_adc_s1 */ -#define AUADC_PDM_ADC_S2_OFFSET (0xC40) /* pdm_adc_s2 */ #define AUADC_AUDADC_ANA_CFG1_OFFSET (0xC60) /* audadc_ana_cfg1 */ #define AUADC_AUDADC_ANA_CFG2_OFFSET (0xC64) /* audadc_ana_cfg2 */ #define AUADC_AUDADC_CMD_OFFSET (0xC68) /* audadc_cmd */ @@ -101,35 +93,10 @@ #define AUADC_ADC_0_PDM_SEL_SHIFT (3U) #define AUADC_ADC_0_PDM_SEL_MASK (0x7 << AUADC_ADC_0_PDM_SEL_SHIFT) -/* 0xC20 : pdm_rsvd0 */ - -/* 0xC24 : pdm_dbg_0 */ -#define AUADC_ADC_TEST_CLKIN_EN (1 << 21U) -#define AUADC_ADC_TEST_DIN_EN (1 << 23U) -#define AUADC_AUD_TEST_READ_SEL_SHIFT (24U) -#define AUADC_AUD_TEST_READ_SEL_MASK (0x3f << AUADC_AUD_TEST_READ_SEL_SHIFT) - -/* 0xC28 : pdm_dbg_1 */ -#define AUADC_AUD_TEST_READ_SHIFT (0U) -#define AUADC_AUD_TEST_READ_MASK (0xffffffff << AUADC_AUD_TEST_READ_SHIFT) - -/* 0xC2C : pdm_dbg_2 */ -#define AUADC_ADC_FIR_4S_VAL_SHIFT (0U) -#define AUADC_ADC_FIR_4S_VAL_MASK (0xfffff << AUADC_ADC_FIR_4S_VAL_SHIFT) -#define AUADC_ADC_0_FIR_4S_EN (1 << 20U) - -/* 0xC30 : pdm_dbg_3 */ - -/* 0xC34 : pdm_dbg_4 */ - /* 0xC38 : pdm_adc_s0 */ #define AUADC_ADC_S0_VOLUME_SHIFT (0U) #define AUADC_ADC_S0_VOLUME_MASK (0x1ff << AUADC_ADC_S0_VOLUME_SHIFT) -/* 0xC3C : pdm_adc_s1 */ - -/* 0xC40 : pdm_adc_s2 */ - /* 0xC60 : audadc_ana_cfg1 */ #define AUADC_AUDADC_PGA_CHOP_CKSEL (1 << 0U) #define AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT (1U) diff --git a/drivers/soc/bl616/std/port/bl616_clock.c b/drivers/soc/bl616/std/port/bl616_clock.c index a03db7ac..6d14ecd5 100644 --- a/drivers/soc/bl616/std/port/bl616_clock.c +++ b/drivers/soc/bl616/std/port/bl616_clock.c @@ -14,6 +14,8 @@ uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx) return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI); } else if (type == BFLB_DEVICE_TYPE_I2C) { return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2C0); + } else if (type == BFLB_DEVICE_TYPE_I2S) { + return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2S); } else if (type == BFLB_DEVICE_TYPE_SDH) { return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SDH); } diff --git a/drivers/soc/bl616/std/port/bl616_flash.c b/drivers/soc/bl616/std/port/bl616_flash.c deleted file mode 100644 index dc621740..00000000 --- a/drivers/soc/bl616/std/port/bl616_flash.c +++ /dev/null @@ -1,626 +0,0 @@ -#include "bl616_glb.h" -#include "bl616_xip_sflash.h" -#include "bl616_sf_cfg.h" -#include "bl616_ef_cfg.h" -#include "bflb_flash.h" - -static uint32_t flash1_size = 4 * 1024 * 1024; -static uint32_t flash2_size = 2 * 1024 * 1024; -static uint32_t g_jedec_id = 0; -static uint32_t g_jedec_id2 = 0; -static SPI_Flash_Cfg_Type g_flash_cfg = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /* reg */ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /* erase */ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /* write */ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x10, - .clkDelay = 0, - .clkInvert = 0x03, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /* id */ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /* read */ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /* AC */ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; -static SPI_Flash_Cfg_Type g_flash2_cfg = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /* reg */ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /* erase */ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /* write */ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x10, - .clkDelay = 0, - .clkInvert = 0x03, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /* id */ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /* read */ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /* AC */ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static bflb_efuse_device_info_type deviceInfo; - -uint32_t bflb_flash2_get_jedec_id(void) -{ - uint32_t jid = 0; - - jid = ((g_jedec_id2 & 0xff) << 16) + (g_jedec_id2 & 0xff00) + ((g_jedec_id2 & 0xff0000) >> 16); - return jid; -} - -static void flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - /* bit0-3 for clk delay */ - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN)) { - cfg->clkDelay = BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } else { - cfg->clkDelay = 0; - } - cfg->clkInvert = 0; - /* bit0 for clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL) & 1) << 0); - /* bit1 for rx clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL) & 1) << 1); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); - /* bit4-6 for do delay */ - cfg->clkDelay |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL) & 7) << 4); - /* bit2-4 for di delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL) & 7) << 2); - /* bit5-7 for oe delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL) & 7) << 5); -} - -static void ATTR_TCM_SECTION flash_set_cmds(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - SF_Ctrl_Cmds_Cfg cmds_cfg = { - .ackLatency = 1, - .cmdsCoreEn = 1, - .cmdsEn = 1, - .cmdsWrapMode = 1, - .cmdsWrapLen = 9, - }; - - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - cmds_cfg.cmdsWrapMode = 2; - cmds_cfg.cmdsWrapLen = 2; - } - SF_Ctrl_Cmds_Set(&cmds_cfg, 0); -} - -static void ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_Qspi_Enable(p_flash_cfg); - } -} - -static void ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { - L1C_Set_Wrap(DISABLE); - } else { - L1C_Set_Wrap(ENABLE); - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(p_flash_cfg); - } - } -} - -/** - * @brief flash_config_init - * - * @return int - */ -static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) -{ - int ret = -1; - uint8_t isAesEnable = 0; - uint32_t jid = 0; - uint32_t offset = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(&isAesEnable); - XIP_SFlash_State_Save(p_flash_cfg, &offset, 0, 0); - SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); - arch_memcpy(jedec_id, (uint8_t *)&jid, 3); - jid &= 0xFFFFFF; - g_jedec_id = jid; - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg); - if (ret == 0) { - p_flash_cfg->mid = (jid & 0xff); - } - - // p_flash_cfg->ioMode = 0x11; - // p_flash_cfg->cReadSupport = 0x00; - - /* Set flash controler from p_flash_cfg */ - flash_set_cmds(p_flash_cfg); - flash_set_qspi_enable(p_flash_cfg); - flash_set_l1c_wrap(p_flash_cfg); - XIP_SFlash_State_Restore(p_flash_cfg, offset, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - bflb_irq_restore(flag); - - return ret; -} - -/** - * @brief flash2 init - * - * @return int - */ -static int ATTR_TCM_SECTION flash2_init(void) -{ - int stat = -1; - uint32_t ret = 0; - uint32_t jid = 0; - - SF_Ctrl_Bank2_Cfg sfBank2Cfg = { - .sbus2Select = ENABLE, - .bank2RxClkInvertSrc = DISABLE, - .bank2RxClkInvertSel = DISABLE, - .bank2DelaySrc = DISABLE, - .bank2ClkDelay = 1, - .doDelay = 0, - .diDelay = 0, - .oeDelay = 0, - .remap = SF_CTRL_REMAP_4MB, - .remapLock = 1, - }; - SF_Ctrl_Cmds_Cfg cmdsCfg = { - .ackLatency = 1, - .cmdsCoreEn = 1, - .cmdsEn = 1, - .cmdsWrapMode = 1, - .cmdsWrapLen = SF_CTRL_WRAP_LEN_4096, - }; - - if (deviceInfo.memoryInfo == 0) { - /* memoryInfo==0, external flash */ - flash1_size = 64 * 1024 * 1024; - flash2_size = 0; - } else if (deviceInfo.memoryInfo == 1) { - flash1_size = 2 * 1024 * 1024; - flash2_size = 0; - } else if (deviceInfo.memoryInfo == 2) { - flash1_size = 4 * 1024 * 1024; - flash2_size = 0; - } else if (deviceInfo.memoryInfo == 3) { - /* memoryInfo==3, embedded 4MB+2MB flash */ - flash1_size = 4 * 1024 * 1024; - flash2_size = 2 * 1024 * 1024; - } else { - flash1_size = 8 * 1024 * 1024; - flash2_size = 0; - } - - if (flash2_size > 0) { - SF_Cfg_Sbus2_Flash_Init(SF_IO_EMB_SWAP_IO3IO0_AND_SF2, &sfBank2Cfg); - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - ret = SF_Cfg_Flash_Identify_Ext(0, SF_IO_EMB_SWAP_IO3IO0_AND_SF2, 0, &g_flash2_cfg, 0, SF_CTRL_FLASH_BANK1); - if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) { - return -1; - } - g_flash2_cfg.ioMode = 0x11; - g_flash2_cfg.cReadSupport = 0; - g_flash2_cfg.cReadMode = 0xff; - SFlash_GetJedecId(&g_flash2_cfg, (uint8_t *)&jid); - jid &= 0xFFFFFF; - g_jedec_id2 = jid; - - SF_Ctrl_Cmds_Set(&cmdsCfg, SF_CTRL_FLASH_BANK1); - stat = SFlash_IDbus_Read_Enable(&g_flash2_cfg, (g_flash2_cfg.ioMode & 0xf), 0, SF_CTRL_FLASH_BANK1); - if (0 != stat) { - return -1; - } - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return 0; -} - -/** - * @brief multi flash adapter - * - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_init(void) -{ - int ret = -1; - uint32_t jedec_id = 0; - - bflb_ef_ctrl_get_device_info(&deviceInfo); - - jedec_id = GLB_Get_Flash_Id_Value(); - if (jedec_id != 0) { - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jedec_id, &g_flash_cfg); - if (ret == 0) { - g_jedec_id = jedec_id; - g_flash_cfg.ioMode &= 0x0f; - flash_get_clock_delay(&g_flash_cfg); - flash2_init(); - return 0; - } - } - - g_flash_cfg.ioMode &= 0x0f; - ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); - - g_flash_cfg.ioMode &= 0x0f; - flash_get_clock_delay(&g_flash_cfg); - GLB_Set_Flash_Id_Value(g_jedec_id); - - flash2_init(); - - return ret; -} - -uint32_t bflb_flash_get_jedec_id(void) -{ - uint32_t jid = 0; - - jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16); - return jid; -} - -void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) -{ - *cfg_addr = (uint8_t *)&g_flash_cfg; - *len = sizeof(SPI_Flash_Cfg_Type); -} - -void bflb_flash_set_iomode(uint8_t iomode) -{ - g_flash_cfg.ioMode &= ~0x1f; - if (iomode == 4) { - g_flash_cfg.ioMode |= iomode; - } else { - g_flash_cfg.ioMode |= 0x10; - g_flash_cfg.ioMode |= iomode; - } -} - -ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void) -{ - return SF_Ctrl_Get_Flash_Image_Offset(0, 0); -} - -/** - * @brief erase flash via sbus - * - * @param flash absolute startaddr - * @param flash absolute endaddr - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len) -{ - int stat = -1; - uintptr_t flag; - - if ((startaddr + len) > (flash1_size + flash2_size)) { - return -ENOMEM; - } else if ((startaddr + len) <= flash1_size) { - flag = bflb_irq_save(); - stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, len, 0, 0); - bflb_irq_restore(flag); - } else if (startaddr >= flash1_size) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - stat = SFlash_Erase(&g_flash2_cfg, startaddr, startaddr + len - 1); - SF_Ctrl_Sbus2_Revoke_replace(); - } else { - flag = bflb_irq_save(); - stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, flash1_size - startaddr, 0, 0); - bflb_irq_restore(flag); - if (stat != 0) { - return stat; - } - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - stat = SFlash_Erase(&g_flash2_cfg, flash1_size, startaddr + len - flash1_size - 1); - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return stat; -} - -/** - * @brief write flash data via sbus - * - * @param flash absolute addr - * @param data - * @param len - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - int stat = -1; - uintptr_t flag; - - if ((addr + len) > (flash1_size + flash2_size)) { - return -ENOMEM; - } else if ((addr + len) <= flash1_size) { - flag = bflb_irq_save(); - stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - bflb_irq_restore(flag); - } else if (addr >= flash1_size) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - stat = SFlash_Program(&g_flash2_cfg, SF_CTRL_DO_MODE, addr, data, len); - SF_Ctrl_Sbus2_Revoke_replace(); - } else { - flag = bflb_irq_save(); - stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0); - bflb_irq_restore(flag); - if (stat != 0) { - return stat; - } - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - stat = SFlash_Program(&g_flash2_cfg, SF_CTRL_DO_MODE, flash1_size, data + (flash1_size - addr), addr + len - flash1_size); - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return stat; -} - -/** - * @brief read flash data via sbus - * - * @param flash absolute addr - * @param data - * @param len - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - int stat = -1; - uintptr_t flag; - - if ((addr + len) > (flash1_size + flash2_size)) { - return -ENOMEM; - } else if ((addr + len) <= flash1_size) { - flag = bflb_irq_save(); - stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - bflb_irq_restore(flag); - } else if (addr >= flash1_size) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - stat = SFlash_Read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, addr, data, len); - SF_Ctrl_Sbus2_Revoke_replace(); - } else { - flag = bflb_irq_save(); - stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0); - bflb_irq_restore(flag); - if (stat != 0) { - return stat; - } - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - stat = SFlash_Read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, flash1_size, data + (flash1_size - addr), addr + len - flash1_size); - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return stat; -} - -int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) -{ - uint8_t isAesEnable = 0; - uint32_t tmp[1]; - int stat; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - - XIP_SFlash_Opt_Enter(&isAesEnable); - /* To make it simple, exit cont read anyway */ - SFlash_Reset_Continue_Read(&g_flash_cfg); - - if (g_flash_cfg.cReadSupport == 0) { - cont_read = 0; - } - - if (cont_read == 1) { - stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - - if (0 != stat) { - XIP_SFlash_Opt_Exit(isAesEnable); - return -1; - } - } - - /* TODO: Set default value */ - SF_Ctrl_Set_Flash_Image_Offset(flash_offset, 0, 0); - SFlash_IDbus_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, 0); - - XIP_SFlash_Opt_Exit(isAesEnable); - - return 0; -} - -void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config) -{ - uint8_t hw_key_enable = 0; - - if (config->key == NULL) { - hw_key_enable = 1; - } - - SF_Ctrl_AES_Set_Key_BE(config->region, (uint8_t *)config->key, config->keybits); - SF_Ctrl_AES_Set_IV_BE(config->region, (uint8_t *)config->iv, config->start_addr); - SF_Ctrl_AES_Set_Region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable); -} - -void bflb_flash_aes_enable(void) -{ - SF_Ctrl_AES_Enable(); -} - -void bflb_flash_aes_disable(void) -{ - SF_Ctrl_AES_Disable(); -} \ No newline at end of file diff --git a/drivers/soc/bl616/std/src/bl616_auadc.c b/drivers/soc/bl616/std/src/bl616_auadc.c new file mode 100644 index 00000000..64795625 --- /dev/null +++ b/drivers/soc/bl616/std/src/bl616_auadc.c @@ -0,0 +1,292 @@ +#include "bl616.h" +#include "bl616_auadc.h" +#include "hardware/auadc_reg.h" + +int bflb_auadc_init(struct bflb_device_s *dev, const struct bflb_auadc_init_config_s *config) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + AUADC_AUDPDM_TOP_OFFSET); + /* enable clk */ + regval |= AUADC_AUDIO_CKG_EN; + /* sampling rate */ + regval &= ~AUADC_ADC_RATE_MASK; + regval |= config->sampling_rate << AUADC_ADC_RATE_SHIFT; + putreg32(regval, reg_base + AUADC_AUDPDM_TOP_OFFSET); + + /* disable ch0 and enable dma interface */ + regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET); + regval &= ~AUADC_ADC_0_EN; + regval |= AUADC_ADC_ITF_EN; + putreg32(regval, reg_base + AUADC_AUDPDM_ITF_OFFSET); + + /* pdm or adc input */ + regval = getreg32(reg_base + AUADC_PDM_DAC_0_OFFSET); + if (config->input_mode == AUADC_INPUT_MODE_ADC) { + regval &= ~AUADC_ADC_0_SRC; + } else { + regval |= AUADC_ADC_0_SRC; + } + putreg32(regval, reg_base + AUADC_PDM_DAC_0_OFFSET); + + /* pdm cfg */ + regval = getreg32(reg_base + AUADC_PDM_PDM_0_OFFSET); + if (config->input_mode == AUADC_INPUT_MODE_PDM_L || config->input_mode == AUADC_INPUT_MODE_PDM_R) { + /* enable pdm */ + regval |= AUADC_PDM_0_EN; + /* pdm_l or pdm_r input */ + regval &= ~AUADC_ADC_0_PDM_SEL_MASK; + if (config->input_mode == AUADC_INPUT_MODE_PDM_L) { + regval |= 0 << AUADC_ADC_0_PDM_SEL_SHIFT; + } else if (config->input_mode == AUADC_INPUT_MODE_PDM_R) { + regval |= 1 << AUADC_ADC_0_PDM_SEL_SHIFT; + } + } else { + /* disable pdm */ + regval &= ~AUADC_PDM_0_EN; + } + putreg32(regval, reg_base + AUADC_PDM_PDM_0_OFFSET); + + regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET); + /* audio osr configuration */ + if (config->input_mode != AUADC_INPUT_MODE_ADC && (config->sampling_rate == AUADC_SAMPLING_RATE_32K || config->sampling_rate == AUADC_SAMPLING_RATE_48K)) { + /* osr 64 */ + regval |= AUADC_AUDADC_AUDIO_OSR_SEL; + } else { + /* osr 128 */ + regval &= ~AUADC_AUDADC_AUDIO_OSR_SEL; + } + putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET); + + /* fifo configuration */ + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + /* data format */ + regval &= ~AUADC_RX_DATA_MODE_MASK; + regval |= config->data_format << AUADC_RX_DATA_MODE_SHIFT; + + /* fifo threshold */ + regval &= ~AUADC_RX_TRG_LEVEL_MASK; + regval |= config->fifo_threshold << AUADC_RX_TRG_LEVEL_SHIFT; + regval &= ~AUADC_RX_DRQ_CNT_MASK; + + /* disable record */ + regval &= ~AUADC_RX_CH_EN; + + /* 24bit sample */ + regval &= ~AUADC_RX_DATA_RES_MASK; + regval |= 3 << AUADC_RX_DATA_RES_SHIFT; + + /* disable fifo dma and int */ + regval &= ~AUADC_RX_DRQ_EN; + regval &= ~AUADC_RXA_INT_EN; + regval &= ~AUADC_RXU_INT_EN; + regval &= ~AUADC_RXO_INT_EN; + + /* clear fifo */ + regval |= AUADC_RX_FIFO_FLUSH; + putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + + /* enable ch0 */ + regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET); + regval |= AUADC_ADC_0_EN; + putreg32(regval, reg_base + AUADC_AUDPDM_ITF_OFFSET); + + return 0; +} + +int bflb_auadc_adc_init(struct bflb_device_s *dev, const struct bflb_auadc_adc_init_config_s *adc_analog_cfg) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + + if (adc_analog_cfg->auadc_analog_en == false) { + /* disable analog and channel */ + regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET); + regval &= ~AUADC_AUDADC_PGA_PU; + regval &= ~AUADC_AUDADC_SDM_PU; + regval &= ~AUADC_AUDADC_CHANNEL_EN_MASK; + putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET); + return 0; + } + + /* power up, and SDM reset */ + regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET); + regval |= AUADC_AUDADC_PGA_PU; + regval |= AUADC_AUDADC_SDM_PU; + regval &= ~AUADC_AUDADC_CONV; + putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET); + + /* select analog channel */ + regval &= ~AUADC_AUDADC_CHANNEL_SELP_MASK; + regval &= ~AUADC_AUDADC_CHANNEL_SELN_MASK; + regval |= adc_analog_cfg->adc_pga_posi_ch << AUADC_AUDADC_CHANNEL_SELP_SHIFT; + regval |= adc_analog_cfg->adc_pga_nega_ch << AUADC_AUDADC_CHANNEL_SELN_SHIFT; + + /* PGA mode */ + regval &= ~AUADC_AUDADC_PGA_MODE_MASK; + regval |= adc_analog_cfg->adc_pga_mode << AUADC_AUDADC_PGA_MODE_SHIFT; + + /* PGA gain */ + regval &= ~AUADC_AUDADC_PGA_GAIN_MASK; + regval |= (adc_analog_cfg->adc_pga_gain / 3) << AUADC_AUDADC_PGA_GAIN_SHIFT; + + /* adc mode */ + if (adc_analog_cfg->adc_mode == AUADC_ADC_MODE_AUDIO) { + regval &= ~AUADC_AUDADC_MEAS_FILTER_EN; + } else { + regval |= AUADC_AUDADC_MEAS_FILTER_EN; + } + + /* measuring mode rate */ + regval &= ~AUADC_AUDADC_MEAS_ODR_SEL_MASK; + regval |= adc_analog_cfg->adc_measure_rate << AUADC_AUDADC_MEAS_ODR_SEL_SHIFT; + + /* enable analog channel */ + regval &= ~AUADC_AUDADC_CHANNEL_EN_MASK; + if (adc_analog_cfg->adc_pga_mode == AUADC_ADC_PGA_MODE_AC_DIFFER || adc_analog_cfg->adc_pga_mode == AUADC_ADC_PGA_MODE_DC_DIFFER) { + regval |= 0x03 << AUADC_AUDADC_CHANNEL_EN_SHIFT; + } else { + regval |= 0x02 << AUADC_AUDADC_CHANNEL_EN_SHIFT; + } + putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET); + + /* SDM conversion start */ + regval |= AUADC_AUDADC_CONV; + putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET); + + return 0; +} + +int bflb_auadc_link_rxdma(struct bflb_device_s *dev, bool enable) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + if (enable) { + regval |= AUADC_RX_DRQ_EN; + } else { + regval &= ~AUADC_RX_DRQ_EN; + } + putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + + return 0; +} + +int bflb_auadc_int_mask(struct bflb_device_s *dev, uint32_t int_sts) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + + /* fifo int */ + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + regval &= ~int_sts; + putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + + return 0; +} + +int bflb_auadc_int_unmask(struct bflb_device_s *dev, uint32_t int_sts) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + + /* fifo int */ + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + regval |= int_sts; + putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + + return 0; +} + +int bflb_auadc_get_intstatus(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t regval; + int32_t int_sts; + + reg_base = dev->reg_base; + int_sts = 0; + + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_STATUS_OFFSET); + if (regval & AUADC_RXO_INT) { + int_sts |= AUADC_INTSTS_FIFO_OVER; + } + if (regval & AUADC_RXU_INT) { + int_sts |= AUADC_INTSTS_FIFO_UNDER; + } + if (regval & AUADC_RXA_INT) { + int_sts |= AUADC_INTSTS_FIFO_AVAILABLE; + } + + return int_sts; +} + +int bflb_auadc_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +{ + int ret = 0; + uint32_t reg_base; + uint32_t regval; + int16_t volume_val; + + reg_base = dev->reg_base; + + switch (cmd) { + case AUADC_CMD_RECORD_START: + /* record start */ + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + regval |= AUADC_RX_CH_EN; + putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + break; + + case AUADC_CMD_RECORD_STOP: + /* record stop */ + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + regval &= ~AUADC_RX_CH_EN; + putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + break; + + case AUADC_CMD_SET_VOLUME_VAL: + /* set volume value dB, arg range -191 to + 36, 0.5dB step, range -95.5dB to +18dB*/ + volume_val = (uint16_t)((int16_t)arg * 2); + regval = getreg32(reg_base + AUADC_PDM_ADC_S0_OFFSET); + regval &= ~AUADC_ADC_S0_VOLUME_MASK; + regval |= (volume_val << AUADC_ADC_S0_VOLUME_SHIFT) & AUADC_ADC_S0_VOLUME_MASK; + putreg32(regval, reg_base + AUADC_PDM_ADC_S0_OFFSET); + break; + + case AUADC_CMD_SET_PGA_GAIN_VAL: + /* set adc pga gain, range 6dB ~ 42dB, step by 3db */ + volume_val = arg / 3; + regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET); + regval &= ~AUADC_AUDADC_PGA_GAIN_MASK; + regval |= (volume_val << AUADC_AUDADC_PGA_GAIN_SHIFT) & AUADC_AUDADC_PGA_GAIN_MASK; + putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET); + break; + + case AUADC_CMD_CLEAR_RX_FIFO: + /* get rx fifo cnt */ + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + regval |= AUADC_RX_FIFO_FLUSH; + putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET); + break; + + case AUADC_CMD_GET_RX_FIFO_CNT: + /* get rx fifo cnt */ + regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_STATUS_OFFSET); + ret = (regval & AUADC_RXA_CNT_MASK) >> AUADC_RXA_CNT_SHIFT; + } + + return ret; +} \ No newline at end of file diff --git a/drivers/soc/bl616/std/src/bl616_audac.c b/drivers/soc/bl616/std/src/bl616_audac.c index e1a5da92..ced0677c 100644 --- a/drivers/soc/bl616/std/src/bl616_audac.c +++ b/drivers/soc/bl616/std/src/bl616_audac.c @@ -244,13 +244,13 @@ int bflb_audac_get_intstatus(struct bflb_device_s *dev) /* fifo int */ regval = getreg32(reg_base + AUDAC_FIFO_STATUS_OFFSET); - if (regval | AUDAC_TXO_INT) { + if (regval & AUDAC_TXO_INT) { int_sts |= AUDAC_INTSTS_FIFO_OVER; } - if (regval | AUDAC_TXU_INT) { + if (regval & AUDAC_TXU_INT) { int_sts |= AUDAC_INTSTS_FIFO_UNDER; } - if (regval | AUDAC_TXA_INT) { + if (regval & AUDAC_TXA_INT) { int_sts |= AUDAC_INTSTS_FIFO_AVAILABLE; } diff --git a/drivers/soc/bl616/std/src/bl616_clock.c b/drivers/soc/bl616/std/src/bl616_clock.c index ded8e319..60e1e093 100644 --- a/drivers/soc/bl616/std/src/bl616_clock.c +++ b/drivers/soc/bl616/std/src/bl616_clock.c @@ -84,7 +84,7 @@ * @{ */ -static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut) +static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut) { return pllOut; } @@ -99,26 +99,25 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clock tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG6), CCI_AUPLL_SDMIN); if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) { - switch (xtalType) - { + switch (xtalType) { /* Calculation method:xtal_freq * 1000 * aupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */ case GLB_XTAL_NONE: return (0); case GLB_XTAL_24M: /* 491519500;451576000;399996000;3840000000 */ vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2); - break; + break; case GLB_XTAL_32M: /* 491519500;451578000;400000000;3840000000 */ - vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4); - break; + vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4); + break; case GLB_XTAL_38P4M: /* 491517000;451579500;399998250;3840000000 */ - vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4); + vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4); break; case GLB_XTAL_40M: /* 491518500;451577000;400000000;383999000 */ - vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4); + vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4); break; case GLB_XTAL_26M: /* 491518000;451578500;399997500;383995000 */ @@ -126,8 +125,8 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clock break; case GLB_XTAL_RC32M: /* 491519500;451578000;400000000;3840000000 */ - vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4); - break; + vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4); + break; default: return (0); } @@ -135,16 +134,16 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clock return (0); } - if ( (vcoFreq >= 491000000) && (vcoFreq <= 492000000) ) { + if ((vcoFreq >= 491000000) && (vcoFreq <= 492000000)) { /* vcoFreq:491517000~491519500 */ vcoFreq = 491520000; - } else if ( (vcoFreq >= 451000000) && (vcoFreq <= 452000000) ) { + } else if ((vcoFreq >= 451000000) && (vcoFreq <= 452000000)) { /* vcoFreq:451577000~451579500 */ vcoFreq = 451580000; - } else if ( (vcoFreq >= 399000000) && (vcoFreq <= 401000000) ) { + } else if ((vcoFreq >= 399000000) && (vcoFreq <= 401000000)) { /* vcoFreq:451577000~451579500 */ vcoFreq = 400000000; - } else if ( (vcoFreq >= 383000000) && (vcoFreq <= 385000000) ) { + } else if ((vcoFreq >= 383000000) && (vcoFreq <= 385000000)) { /* vcoFreq:383995000~3840000000 */ vcoFreq = 384000000; } else { @@ -175,17 +174,16 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clock } } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output() +static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output() { uint32_t tmpVal = 0; tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG1), CCI_AUPLL_POSTDIV); return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1) / tmpVal; - } -static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) +static inline uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) { uint8_t xtalType = 0; @@ -213,7 +211,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) } } -static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) { if (sel == 0) { /* rc32m */ @@ -226,7 +224,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) { uint32_t tmpVal; uint32_t div = 0; @@ -245,7 +243,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) { uint32_t tmpVal; @@ -254,7 +252,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 160m */ @@ -273,7 +271,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void) { uint32_t tmpVal; @@ -282,7 +280,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 80m */ @@ -291,14 +289,14 @@ static uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel) /* aupll div5 clk */ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5); } else if (sel == 2) { - /* aupll div6 clk */ + /* aupll div6 clk */ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV6); } else { return 0; } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void) { uint32_t tmpVal; @@ -307,7 +305,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* aupll div2 clk */ @@ -326,7 +324,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) { uint32_t tmpVal; @@ -336,7 +334,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) return (tmpVal & 0x1); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -346,7 +344,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) return ((tmpVal >> 1) & 0x1); } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) { uint32_t tmpVal; @@ -363,7 +361,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) { uint32_t tmpVal; @@ -372,7 +370,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) { uint32_t tmpVal; @@ -428,20 +426,20 @@ uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type) } } -static uint32_t ATTR_CLOCK_SECTION Clock_PARAMB_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_PARAMB_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 320m */ return Clock_Get_WIFI_PLL_Output(320 * 1000 * 1000); } else if (sel == 1) { - /* aupll div1 clk */ + /* aupll div1 clk */ return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1); } else { return 0; } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Div_Val(void) +static inline uint8_t Clock_Get_PSRAMB_Clk_Div_Val(void) { uint32_t tmpVal; @@ -450,7 +448,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_PSRAMB_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -459,7 +457,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL); } -uint32_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk(void) +uint32_t Clock_Get_PSRAMB_Clk(void) { uint32_t div = 0; @@ -468,7 +466,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk(void) return Clock_PARAMB_Clk_Mux_Output(Clock_Get_PSRAMB_Clk_Sel_Val()) / (div + 1); } -static uint32_t ATTR_CLOCK_SECTION Clock_ISP_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_ISP_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 80m */ @@ -484,7 +482,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_ISP_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_ISP_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_ISP_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -493,12 +491,12 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_ISP_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_ISP_MUXPLL_80M_SEL); } -uint32_t ATTR_CLOCK_SECTION Clock_Get_ISP_Clk(void) +uint32_t Clock_Get_ISP_Clk(void) { return Clock_ISP_Clk_Mux_Output(Clock_Get_ISP_Clk_Sel_Val()); } -static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mcu bclk */ @@ -512,7 +510,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -521,7 +519,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL)); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) +static inline uint8_t Clock_Get_UART_Div_Val(void) { uint32_t tmpVal; @@ -530,7 +528,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_PKA_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_PKA_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mcu pbclk */ @@ -543,7 +541,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_PKA_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PKA_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_PKA_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -552,13 +550,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PKA_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void) +static inline uint32_t Clock_IR_Clk_Mux_Output(void) { /* xclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) +static inline uint8_t Clock_Get_IR_Div_Val(void) { uint32_t tmpVal; @@ -567,7 +565,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void) { uint32_t tmpVal; @@ -576,7 +574,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 120m */ @@ -593,7 +591,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* sf sel2 */ @@ -610,7 +608,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -619,7 +617,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) +static inline uint8_t Clock_Get_SF_Div_Val(void) { uint32_t tmpVal; @@ -628,7 +626,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SPI_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mux 160Mkz */ @@ -639,7 +637,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SPI_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -648,7 +646,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) +static inline uint8_t Clock_Get_SPI_Div_Val(void) { uint32_t tmpVal; @@ -657,7 +655,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_PEC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_PEC_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mux 160Mkz */ @@ -668,7 +666,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_PEC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PEC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_PEC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -677,7 +675,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PEC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PEC_Div_Val(void) +static inline uint8_t Clock_Get_PEC_Div_Val(void) { uint32_t tmpVal; @@ -686,7 +684,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PEC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_DBI_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_DBI_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mux 160Mkz */ @@ -697,7 +695,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DBI_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DBI_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_DBI_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -706,7 +704,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DBI_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DBI_Div_Val(void) +static inline uint8_t Clock_Get_DBI_Div_Val(void) { uint32_t tmpVal; @@ -715,7 +713,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DBI_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_I2C_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mcu pblck */ @@ -728,7 +726,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_I2C_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -737,7 +735,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) +static inline uint8_t Clock_Get_I2C_Div_Val(void) { uint32_t tmpVal; @@ -746,7 +744,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel) { if (sel == 0) { /* audio pll clk */ @@ -757,7 +755,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -766,7 +764,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) +static inline uint8_t Clock_Get_GPADC_Div_Val(void) { uint32_t tmpVal; @@ -775,7 +773,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel) { uint32_t div = 0; @@ -788,13 +786,13 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_I2S_Clk_Mux_Output(void) +static inline uint32_t Clock_I2S_Clk_Mux_Output(void) { /* audio pll clk */ return Clock_Get_Audio_PLL_Output(); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2S_Div_Val(void) +static inline uint8_t Clock_Get_I2S_Div_Val(void) { uint32_t tmpVal; @@ -803,13 +801,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2S_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_ADC_Clk_Mux_Output(void) +static inline uint32_t Clock_ADC_Clk_Mux_Output(void) { /* audio pll clk */ return Clock_Get_Audio_PLL_Output(); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_ADC_Div_Val(void) +static inline uint8_t Clock_Get_ADC_Div_Val(void) { uint32_t tmpVal; @@ -818,7 +816,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_ADC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_SOLO_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -827,7 +825,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 32m */ @@ -841,7 +839,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) +static inline uint8_t Clock_Get_GPDAC_Div_Val(void) { uint32_t tmpVal; @@ -850,7 +848,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -859,7 +857,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_SDH_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SDH_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 96m */ @@ -870,7 +868,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SDH_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SDH_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -879,7 +877,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Div_Val(void) +static inline uint8_t Clock_Get_SDH_Div_Val(void) { uint32_t tmpVal; @@ -888,7 +886,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* xclk */ @@ -904,7 +902,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -913,7 +911,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void) +static inline uint8_t Clock_Get_CAM_Div_Val(void) { uint32_t tmpVal; @@ -929,7 +927,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void) * @return Audio ADC clock value * *******************************************************************************/ -uint32_t ATTR_CLOCK_SECTION Clock_Audio_ADC_Clock_Get(void) +uint32_t Clock_Audio_ADC_Clock_Get(void) { uint32_t clock = 0; uint32_t div = 0; @@ -949,7 +947,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_Audio_ADC_Clock_Get(void) * @return Peripheral1 clock value * *******************************************************************************/ -uint32_t ATTR_CLOCK_SECTION Clock_Peripheral_Clock_Get(BL_Peripheral_Type type) +uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type) { uint32_t clock = 0; uint32_t div = 0; @@ -1003,7 +1001,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_Peripheral_Clock_Get(BL_Peripheral_Type type) /*!< emi clock */ case BL_PERIPHERAL_CLOCK_EMI: - /* mcu pblck */ + /* mcu pblck */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK); /*!< isp clock */ @@ -1217,9 +1215,9 @@ uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Source_Clock(void) case GLB_CORE_ID_M0: if (tmpVal == BL_MTIMER_SOURCE_CLOCK_MCU_XCLK) { coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); - } else{ + } else { coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); - } + } break; default: coreFreq = 0; @@ -1258,7 +1256,7 @@ uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Clock(void) coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); } else { coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); - } + } break; default: coreFreq = 0; diff --git a/drivers/soc/bl616/std/src/bl616_common_s.c b/drivers/soc/bl616/std/src/bl616_common_s.c deleted file mode 100644 index 9bd9d5af..00000000 --- a/drivers/soc/bl616/std/src/bl616_common_s.c +++ /dev/null @@ -1,135 +0,0 @@ -#include "bl616_common_s.h" -#include -#include "bflb_platform.h" -#include "bl616_glb.h" -#include "bl616_dma.h" -#include "bl616_i2s.h" -#include "bl616_i2c.h" -#include "bl616_uart.h" -#include "bl616_clock.h" - -/** @addtogroup BL616_Periph_Driver - * @{ - */ - -/** @defgroup DRIVER_COMMON_S DRIVER_COMMON_S - * @brief Digger driver common_s functions - * @{ - */ - -/** @defgroup DRIVER_Private_Type - * @{ - */ - -/*@} end of group DRIVER_Private_Type*/ - -/** @defgroup DRIVER_Private_Defines - * @{ - */ - -/*@} end of group DRIVER_Private_Defines */ - -/** @defgroup DRIVER_Private_Variables - * @{ - */ - -/*@} end of group DRIVER_Private_Variables */ - -/** @defgroup DRIVER_Global_Variables - * @{ - */ - -/*@} end of group DRIVER_Global_Variables */ - -/** @defgroup DRIVER_Private_FunctionDeclaration - * @{ - */ - -/*@} end of group DRIVER_Private_FunctionDeclaration */ - -/** @defgroup DRIVER_Private_Functions - * @{ - */ - -/*@} end of group DRIVER_Private_Functions */ - -/** @defgroup DRIVER_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Char memcpy safe - * - * @param dst: Destination - * @param dstSize: Destination size - * @param src: Source - * @param count: Count of char - * - * @return Destination pointer - * - *******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -static inline uint8_t ATTR_TCM_SECTION is_mem_in_ram(uint32_t addr, size_t size) -{ - /* bl616 all ram */ - /* 0x20FC0000 + 480K */ - /* 0x60FC0000 + 480K */ - /* 0x22FC0000 + 480K */ - /* 0x62FC0000 + 480K */ - if((((BL616_ALLRAM_BASE<=addr)&&((addr+size)<=BL616_ALLRAM_END))|| - ((BL616_ALLRAM_CACHEABLE_BASE<=addr)&&((addr+size)<=BL616_ALLRAM_CACHEABLE_END))|| - ((BL616_ALLRAM_BUSREMAP_BASE<=addr)&&((addr+size)<=BL616_ALLRAM_BUSREMAP_END))|| - ((BL616_ALLRAM_BUSREMAP_CACHEABLE_BASE<=addr)&&((addr+size)<=BL616_ALLRAM_BUSREMAP_CACHEABLE_END)))){ - return 1; - } - - return 0; -} -#endif - -/****************************************************************************/ /** - * @brief Char memcpy safe - * - * @param dst: Destination - * @param dstSize: Destination size - * @param src: Source - * @param count: Count of char - * - * @return Destination pointer - * - *******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -errno_t ATTR_TCM_SECTION memcpy_s(void *dst, size_t dstSize, const void *src, size_t count) -{ - /* param NULL */ - if((NULL==dst)||(NULL==src)){ - return PARAM_ERROR; - } - - /* memory overlap */ - if(!((((uint32_t)src + count)<(uint32_t)dst)||((uint32_t)src>((uint32_t)dst + dstSize)))){ - return BUFFER_OVERLAP; - } - - /* size mismatch */ - if(count > dstSize){ - return SIZE_MISMATCHING; - } - - /* dst overflow */ - if(!is_mem_in_ram((uint32_t)dst, dstSize)){ - return DST_OVERFLOW; - } - - memcpy(dst, src, count); - - return COPY_SUCCESS; -} -#endif - -/*@} end of group DRIVER_Public_Functions */ - -/*@} end of group DRIVER_COMMON */ - -/*@} end of group BL616_Periph_Driver */ diff --git a/drivers/soc/bl616/std/src/bl616_ef_ctrl.c b/drivers/soc/bl616/std/src/bl616_ef_ctrl.c deleted file mode 100644 index 9b5f53d5..00000000 --- a/drivers/soc/bl616/std/src/bl616_ef_ctrl.c +++ /dev/null @@ -1,1522 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_ef_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl616_ef_ctrl.h" -#include "ef_data_reg.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) -#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) -#define EF_CTRL_DFT_TIMEOUT_VAL (160 * 1000) -#ifndef BOOTROM -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#else -#define EF_CTRL_LOAD_BEFORE_READ_R0 -#endif -#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, EF_CTRL_EFUSE_R0_SIZE / 4) - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief get custom USB PID VID - * - * @param PID - * - * @param VID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) -{ - uint32_t tmpVal; - - EF_Ctrl_Read_Sw_Usage(4, &tmpVal); - - pid[0] = (uint16_t)(tmpVal & 0xFFFF); - vid[0] = (uint16_t)(tmpVal >> 16); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Switch efuse region 0 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Program */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - arch_delay_us(4); - - /* Trigger */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Load efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - EF_CTRL_DATA0_CLEAR; - - /* Trigger read */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - arch_delay_us(10); - - /* Wait for efuse control idle */ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - timeout--; - - if (timeout == 0) { - break; - } - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || - - (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); - - /* Switch to AHB clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse busy status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) -{ - if (BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0), EF_CTRL_EF_IF_0_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse whether finish loading - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { - return SET; - } else { - return RESET; - } -} -#endif - -/****************************************************************************/ /** - * @brief Efuse write debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits - * @param passWdHigh: password high 32 bits - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD_HIGH, passWdHigh); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD2_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD2_HIGH, passWdHigh); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits pointer to store value - * @param passWdHigh: password high 32 bits pointer to store value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh) -{ - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (slot == 0) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD_HIGH); - } else if (slot == 1) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD2_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DBG_PWD2_HIGH); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_RD_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_WR_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_EF_DBG_MODE, cfg->ef_dbg_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_EF_DBG_JTAG_1_DIS, cfg->ef_dbg_jtag_1_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_EF_SBOOT_EN, cfg->ef_sboot_en); - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0); - - cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_EF_DBG_MODE); - cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_EF_DBG_JTAG_0_DIS); - cfg->ef_dbg_jtag_1_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_EF_DBG_JTAG_1_DIS); - cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_EF_SBOOT_EN); -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (aes[0] != EF_CTRL_SF_AES_NONE) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_EF_SF_AES_MODE, aes[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0, tmpVal); - } - - if (EF_CTRL_SIGN_NONE != sign[0]) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_EF_SBOOT_SIGN_MODE, sign[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_0, tmpVal); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security boot configuration - * - * @param aes[2]: AES configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2]) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0); - - aes[1] = aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_EF_SF_AES_MODE); -} - -/****************************************************************************/ /** - * @brief Efuse read bus remap configuration - * - * @param None - * - * @return ENABLE or DISABLE - * -*******************************************************************************/ -BL_Fun_Type EF_Ctrl_Read_Bus_Remap(void) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_DATA_EF_BUS_RMP_SW_EN)) { - return ENABLE; - } - return DISABLE; -} - -/****************************************************************************/ /** - * @brief Efuse Set sf key re sel - * - * @param ef_sf_key_re_sel: Efuse sf key re sel - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel) -{ - uint32_t tmpVal; - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_EF_SF_KEY_RE_SEL, ef_sf_key_re_sel); - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_CFG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Analog Trim parity calculate - * - * @param val: Value of efuse trim data - * @param len: Length of bit to calculate - * - * @return Parity bit value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) -{ - uint8_t cnt = 0; - uint8_t i = 0; - - for (i = 0; i < len; i++) { - if (val & (1 << i)) { - cnt++; - } - } - - return cnt & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC dis - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DcdcDis_Trim(Efuse_Ana_DcdcDis_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DAT_1_RSVD_1); - trim->dcdcDisAonEn = (tmpVal >> 19) & 0x01; - trim->dcdcDisAonParity = (tmpVal >> 18) & 0x01; - trim->dcdcDisAon = (tmpVal >> 17) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC vout sel - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DcdcVoutSel_Trim(Efuse_Ana_DcdcVoutSel_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DAT_1_RSVD_1); - trim->dcdcVoutSelAonEn = (tmpVal >> 16) & 0x01; - trim->dcdcVoutSelAonParity = (tmpVal >> 15) & 0x01; - trim->dcdcVoutSelAon = (tmpVal >> 10) & 0x1F; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO18IO vout sel - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_Ldo18ioVoutSel_Trim(Efuse_Ana_Ldo18ioVoutSel_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W3); - trim->ldo18ioVoutSelEn = (tmpVal >> 25) & 0x01; - trim->ldo18ioVoutSelParity = (tmpVal >> 24) & 0x01; - trim->ldo18ioVoutSelAon = (tmpVal >> 20) & 0x0F; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO18IO bypass - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_Ldo18ioBypass_Trim(Efuse_Ana_Ldo18ioBypass_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DAT_1_RSVD_1); - trim->ldo18ioBypassEn = (tmpVal >> 9) & 0x01; - trim->ldo18ioBypassParity = (tmpVal >> 8) & 0x01; - trim->ldo18ioBypassAon = (tmpVal >> 4) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO33 vout trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_Ldo33VoutTrim_Trim(Efuse_Ana_Ldo33VoutTrim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W3); - trim->ldo33VoutTrimAonEn = (tmpVal >> 13) & 0x01; - trim->ldo33VoutTrimAonParity = (tmpVal >> 12) & 0x01; - trim->ldo33VoutTrimAon = (tmpVal >> 8) & 0x0F; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO18IO vout trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_Ldo18ioVoutTrim_Trim(Efuse_Ana_Ldo18ioVoutTrim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W3); - trim->ldo18ioVoutTrimEn = (tmpVal >> 19) & 0x01; - trim->ldo18ioVoutTrimParity = (tmpVal >> 18) & 0x01; - trim->ldo18ioVoutTrimAon = (tmpVal >> 14) & 0x0F; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC vout trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DcdcVoutTrim_Trim(Efuse_Ana_DcdcVoutTrim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W3); - trim->dcdcVoutTrimAonEn = (tmpVal >> 31) & 0x01; - trim->dcdcVoutTrimAonParity = (tmpVal >> 30) & 0x01; - trim->dcdcVoutTrimAon = (tmpVal >> 26) & 0x0F; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO11SOC vout trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_Ldo11socVoutTrim_Trim(Efuse_Ana_Ldo11socVoutTrim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W3); - trim->ldo11socVoutTrimAonEn = (tmpVal >> 7) & 0x01; - trim->ldo11socVoutTrimAonTrim = (tmpVal >> 6) & 0x01; - trim->ldo11socVoutTrimAon = (tmpVal >> 2) & 0x0F; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32M trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W3); - trim->rc32mCodeFrExt2En = (tmpVal >> 1) & 0x01; - trim->rc32mCodeFrExt2Parity = (tmpVal >> 0) & 0x01; - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - trim->rc32mCodeFrExt2 = (tmpVal >> 4) & 0xFF; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32K trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_10_W3); - trim->rc32kCodeFrExtEn = (tmpVal >> 19) & 0x01; - trim->rc32kCodeFrExtParity = (tmpVal >> 18) & 0x01; - trim->rc32kCodeFrExt = (tmpVal >> 8) & 0x3FF; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read USB20 rcal code - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_Usb20RcalCode_Trim(Efuse_Ana_Usb20RcalCode_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DAT_1_RSVD_2); - trim->usb20RcalCodeAonEn = (tmpVal >> 15) & 0x01; - trim->usb20RcalCodeAonParity = (tmpVal >> 14) & 0x01; - trim->usb20RcalCodeAon = (tmpVal >> 8) & 0x3F; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read TSEN trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DAT_1_RSVD_0); - trim->tsenRefcodeCorner = (tmpVal >> 0) & 0xfff; - trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; - trim->tsenRefcodeCornerEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read ADC Gain trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_DAT_1_RSVD_0); - trim->adcGainCoeff = (tmpVal >> 14) & 0xfff; - trim->adcGainCoeffParity = (tmpVal >> 26) & 0x01; - trim->adcGainCoeffEn = (tmpVal >> 27) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write software usage - * - * @param index: index of software usage - * @param usage: usage value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) -{ - /* switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - switch (index) { - case 0: - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_0, usage); - break; - - case 1: - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_1, usage); - break; - - case 2: - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_2, usage); - break; - - case 3: - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_3, usage); - break; - - case 4: - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W0, usage); - break; - - default: - break; - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param usage: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - switch (index) { - case 0: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_0); - break; - - case 1: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_1); - break; - - case 2: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_2); - break; - - case 3: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_3); - break; - - case 4: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_KEY_SLOT_11_W0); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param program: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index == 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_WR_LOCK_SW_USAGE_0); - } else if (index == 1) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_WR_LOCK_SW_USAGE_1); - } else if (index == 2) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_WR_LOCK_SW_USAGE_2); - } else if (index == 3) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_WR_LOCK_SW_USAGE_3); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write MAC address - * - * @param mac[6]: MAC address buffer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - BL_WR_REG(EF_DATA_BASE, EF_DATA_EF_WIFI_MAC_HIGH, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse Ctrl get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[6]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0; - uint32_t cnt = 0; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[7]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - machigh[2] = (tmpVal >> 16) & 0xff; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for MAC address - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_MAC_Address(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_WR_LOCK_WIFI_MAC); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Whether a value bits is all zero - * - * @param val: value to check - * @param start: start bit - * @param len: total length of bits to check - * - * @return 1 for all bits zero 0 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) -{ - uint32_t mask = 0; - - val = (val >> start); - - if (len >= 32) { - mask = 0xffffffff; - } else { - mask = (1 << len) - 1; - } - - if ((val & mask) == 0) { - return 1; - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief Efuse read chip ID - * - * @param chipID[8]: Chip ID buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) -{ - chipID[6] = 0; - chipID[7] = 0; - return EF_Ctrl_Read_MAC_Address_Raw(chipID); -} - -/****************************************************************************/ /** - * @brief Efuse read flash dly coe - * - * @param None - * - * @return flash dly coe value - * -*******************************************************************************/ -uint8_t EF_Ctrl_Read_FlashDlyCoe(void) -{ - EF_CTRL_LOAD_BEFORE_READ_R0; - - return BL_GET_REG_BITS_VAL(BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK), EF_DATA_FLASH_DLY_COE); -} - -/****************************************************************************/ /** - * @brief Efuse write AES key - * - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - /* slot_w0~slot_w3,slot_w11 in ef_data0 - slot_w4~slot_w10,in ef_data1 */ - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if ((index <= 3) || (index == 11)) { - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - ARCH_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); - } else if ((index < 11) && (index > 3)) { - index = index - 4; - - /* Every key is 4 words len*/ - ARCH_MemCpy4(pAESKeyStart1 + index * 4, keyData, len); - } - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read AES key from specified region and index - * - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R0; - - if ((index <= 3) || (index == 11)) { - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); - } else if ((index < 11) && (index > 3)) { - index = index - 4; - - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart1 + index * 4, len); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for aes key - * - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if ((index <= 3) || (index == 11)) { - index = ((index == 11) ? 8 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 17)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - } else if ((index < 11) && (index > 3)) { - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 15)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - } - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for aes key - *0 - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if ((index <= 3) || (index == 11)) { - index = ((index == 11) ? 4 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 27)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - } else if ((index < 11) && (index > 3)) { - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 25)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - } - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Program data to efuse - * - * @param offset: offset of efuse address to program - * @param pword: data pointer to buffer which is aligned to word - * @param count: count of data in words to program - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct(uint32_t offset, uint32_t *pword, uint32_t count) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + offset); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Add delay for CLK to be stable */ - arch_delay_us(4); - - if (pword != NULL) { - ARCH_MemCpy4(pEfuseStart0, pword, count); - } - - EF_Ctrl_Program_Efuse_0(); -} - -/****************************************************************************/ /** - * @brief Read data from efuse - * - * @param offset: offset of efuse address to read - * @param pword: data pointer to buffer which is aligned to word - * @param count: count of data in words to read - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct(uint32_t offset, uint32_t *pword, uint32_t count) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + offset); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - ARCH_MemCpy4(pword, pEfuseStart0, count); -} - -/****************************************************************************/ /** - * @brief Clear efuse data register - * - * @param index: index of efuse in word - * @param len: data length - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - uint32_t i = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart0[index + i] = 0; - } -} -#endif - -/****************************************************************************/ /** - * @brief efuse ctrl crc enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc busy status - * - * @param None - * - * @return DISABLE or ENABLE - * -*******************************************************************************/ -BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); -} - -/****************************************************************************/ /** - * @brief efuse ctrl set golden value - * - * @param goldenValue: Crc golden value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) -{ - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc result - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Crc_Result(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL616_Peripheral_Driver */ diff --git a/drivers/soc/bl616/std/src/bl616_glb.c b/drivers/soc/bl616/std/src/bl616_glb.c index e8b22804..a6fa4edf 100644 --- a/drivers/soc/bl616/std/src/bl616_glb.c +++ b/drivers/soc/bl616/std/src/bl616_glb.c @@ -1950,7 +1950,6 @@ BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType) BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); return SUCCESS; - } /****************************************************************************/ /** @@ -3381,9 +3380,9 @@ BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType) * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue) { - BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue|BFLB_FLASH_ID_VALID_FLAG)); + BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue | BFLB_FLASH_ID_VALID_FLAG)); return SUCCESS; } @@ -3396,13 +3395,13 @@ BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) * @return flash id * *******************************************************************************/ -uint32_t GLB_Get_Flash_Id_Value(void) +uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void) { uint32_t tmpVal = 0; tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1); - if ((tmpVal&BFLB_FLASH_ID_VALID_FLAG) != 0) { - return (tmpVal&BFLB_FLASH_ID_VALID_MASK); + if ((tmpVal & BFLB_FLASH_ID_VALID_FLAG) != 0) { + return (tmpVal & BFLB_FLASH_ID_VALID_MASK); } return 0x00000000; @@ -3704,20 +3703,20 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_Slave_Grp_0_CLK(GLB_SLAVE_GRP_0_Type slav * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type * pllCfgList) +BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type *pllCfgList) { GLB_PLL_REF_CLK_Type refClk; - + if (xtalType == GLB_XTAL_RC32M) { refClk = GLB_PLL_REFCLK_RC32M; } else { refClk = GLB_PLL_REFCLK_XTAL; } - + GLB_Power_Off_WIFIPLL(); GLB_WIFIPLL_Ref_Clk_Sel(refClk); GLB_Power_On_WIFIPLL(&(pllCfgList[xtalType]), 1); - + return SUCCESS; } @@ -3730,20 +3729,20 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type * pllCfgList) +BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type *pllCfgList) { GLB_PLL_REF_CLK_Type refClk; - + if (xtalType == GLB_XTAL_RC32M) { refClk = GLB_PLL_REFCLK_RC32M; } else { refClk = GLB_PLL_REFCLK_XTAL; } - + GLB_Power_Off_AUPLL(); GLB_AUPLL_Ref_Clk_Sel(refClk); GLB_Power_On_AUPLL(&(pllCfgList[xtalType]), 1); - + return SUCCESS; } @@ -3758,12 +3757,12 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, cons BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_384M(void) { /* GLB_XTAL_Type */ - uint8_t xtalType=GLB_XTAL_NONE; + uint8_t xtalType = GLB_XTAL_NONE; /* we take 384M for CPU use,so set LDO to 1.2V*/ HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P20V); HBN_Get_Xtal_Type(&xtalType); - return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType,audioPllCfg_384M); + return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_384M); } /****************************************************************************/ /** @@ -3777,10 +3776,10 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_384M(void) BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_400M(void) { /* GLB_XTAL_Type */ - uint8_t xtalType=GLB_XTAL_NONE; + uint8_t xtalType = GLB_XTAL_NONE; HBN_Get_Xtal_Type(&xtalType); - return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType,audioPllCfg_400M); + return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_400M); } /****************************************************************************/ /** @@ -3794,10 +3793,10 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_400M(void) BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_451P58M(void) { /* GLB_XTAL_Type */ - uint8_t xtalType=GLB_XTAL_NONE; + uint8_t xtalType = GLB_XTAL_NONE; HBN_Get_Xtal_Type(&xtalType); - return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType,audioPllCfg_451P58M); + return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_451P58M); } /****************************************************************************/ /** @@ -3811,10 +3810,10 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_451P58M(void) BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_491P52M(void) { /* GLB_XTAL_Type */ - uint8_t xtalType=GLB_XTAL_NONE; + uint8_t xtalType = GLB_XTAL_NONE; HBN_Get_Xtal_Type(&xtalType); - return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType,audioPllCfg_491P52M); + return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_491P52M); } /*@} end of group GLB_Public_Functions */ diff --git a/drivers/soc/bl616/std/src/bl616_mfg_flash.c b/drivers/soc/bl616/std/src/bl616_mfg_flash.c index 56eb7d61..260ee7a2 100644 --- a/drivers/soc/bl616/std/src/bl616_mfg_flash.c +++ b/drivers/soc/bl616/std/src/bl616_mfg_flash.c @@ -3,19 +3,19 @@ //static rf_para_flash_t rf_para; //static uint32_t rf_para_addr = 0; -//static SPI_Flash_Cfg_Type *pFlashCfg; +//static spi_flash_cfg_type *pFlashCfg; //#define RF_PARA_MAGIC_FLAG 0x41504652 #define RF_PARA_MAGIC_FLAG 0x41 #define RF_PARA_VALID_FLAG 0x5A #define RF_PARA_PART_NAME "rf_para" -static BL_Err_Type PtTable_Flash_Read(uint32_t addr, uint8_t *data, uint32_t len) +static int PtTable_Flash_Read(uint32_t addr, uint8_t *data, uint32_t len) { - return SUCCESS; + return 0; } -int mfg_flash_init(SPI_Flash_Cfg_Type *flashCfg) +int mfg_flash_init(spi_flash_cfg_type *flashCfg) { PtTable_Flash_Read(0, NULL, 0); return -1; diff --git a/drivers/soc/bl616/std/src/bl616_mfg_media.c b/drivers/soc/bl616/std/src/bl616_mfg_media.c index d47067b4..f39b81ec 100644 --- a/drivers/soc/bl616/std/src/bl616_mfg_media.c +++ b/drivers/soc/bl616/std/src/bl616_mfg_media.c @@ -2,7 +2,7 @@ static uint8_t rf_para_on_flash = 0; -int mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg) +int mfg_media_init_need_lock(spi_flash_cfg_type *flashCfg) { if (0 == mfg_flash_init(flashCfg)) { rf_para_on_flash = 1; @@ -12,13 +12,14 @@ int mfg_media_init_need_lock(SPI_Flash_Cfg_Type *flashCfg) return 0; } -int mfg_media_init_with_lock(SPI_Flash_Cfg_Type *flashCfg) +int mfg_media_init_with_lock(spi_flash_cfg_type *flashCfg) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_init_need_lock(flashCfg); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -44,10 +45,11 @@ int mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program) int mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_write_xtal_capcode_pre_need_lock(capcode, program); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -63,9 +65,10 @@ void mfg_media_write_xtal_capcode_need_lock(void) void mfg_media_write_xtal_capcode_with_lock(void) { - __disable_irq(); + uintptr_t flag; + flag = bflb_irq_save(); mfg_media_write_xtal_capcode_need_lock(); - __enable_irq(); + bflb_irq_restore(flag); } int mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode, uint8_t reload) @@ -80,10 +83,11 @@ int mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode, uint8_t reload) int mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode, uint8_t reload) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_read_xtal_capcode_need_lock(capcode, reload); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -114,10 +118,11 @@ int mfg_media_write_hp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t p int mfg_media_write_hp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_write_hp_poweroffset_pre_need_lock(pwrOffset, program); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -133,9 +138,11 @@ void mfg_media_write_hp_poweroffset_need_lock(void) void mfg_media_write_hp_poweroffset_with_lock(void) { - __disable_irq(); + uintptr_t flag; + + flag = bflb_irq_save(); mfg_media_write_hp_poweroffset_need_lock(); - __enable_irq(); + bflb_irq_restore(flag); } int mfg_media_read_hp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload) @@ -150,10 +157,11 @@ int mfg_media_read_hp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload int mfg_media_read_hp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_read_hp_poweroffset_need_lock(pwrOffset, reload); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -184,10 +192,11 @@ int mfg_media_write_lp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t p int mfg_media_write_lp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_write_lp_poweroffset_pre_need_lock(pwrOffset, program); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -203,9 +212,11 @@ void mfg_media_write_lp_poweroffset_need_lock(void) void mfg_media_write_lp_poweroffset_with_lock(void) { - __disable_irq(); + uintptr_t flag; + + flag = bflb_irq_save(); mfg_media_write_lp_poweroffset_need_lock(); - __enable_irq(); + bflb_irq_restore(flag); } int mfg_media_read_lp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload) @@ -220,10 +231,11 @@ int mfg_media_read_lp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload int mfg_media_read_lp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_read_lp_poweroffset_need_lock(pwrOffset, reload); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -254,10 +266,11 @@ int mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6], uint8_t program) int mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6], uint8_t program) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_write_macaddr_pre_need_lock(mac, program); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -273,9 +286,11 @@ void mfg_media_write_macaddr_need_lock(void) void mfg_media_write_macaddr_with_lock(void) { - __disable_irq(); + uintptr_t flag; + + flag = bflb_irq_save(); mfg_media_write_macaddr_need_lock(); - __enable_irq(); + bflb_irq_restore(flag); } int mfg_media_read_macaddr_need_lock(uint8_t mac[6], uint8_t reload) @@ -290,10 +305,11 @@ int mfg_media_read_macaddr_need_lock(uint8_t mac[6], uint8_t reload) int mfg_media_read_macaddr_with_lock(uint8_t mac[6], uint8_t reload) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_read_macaddr_need_lock(mac, reload); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -326,10 +342,11 @@ int mfg_media_write_bz_poweroffset_pre_need_lock(int8_t pwrOffset[5], uint8_t pr int mfg_media_write_bz_poweroffset_pre_with_lock(int8_t pwrOffset[5], uint8_t program) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_write_bz_poweroffset_pre_need_lock(pwrOffset, program); - __enable_irq(); + bflb_irq_restore(flag); return ret; } @@ -345,9 +362,11 @@ void mfg_media_write_bz_poweroffset_need_lock(void) void mfg_media_write_bz_poweroffset_with_lock(void) { - __disable_irq(); + uintptr_t flag; + + flag = bflb_irq_save(); mfg_media_write_bz_poweroffset_need_lock(); - __enable_irq(); + bflb_irq_restore(flag); } int mfg_media_read_bz_poweroffset_need_lock(int8_t pwrOffset[5], uint8_t reload) @@ -362,10 +381,11 @@ int mfg_media_read_bz_poweroffset_need_lock(int8_t pwrOffset[5], uint8_t reload) int mfg_media_read_bz_poweroffset_with_lock(int8_t pwrOffset[5], uint8_t reload) { int ret; + uintptr_t flag; - __disable_irq(); + flag = bflb_irq_save(); ret = mfg_media_read_bz_poweroffset_need_lock(pwrOffset, reload); - __enable_irq(); + bflb_irq_restore(flag); return ret; } diff --git a/drivers/soc/bl616/std/src/bl616_romapi_e907.c b/drivers/soc/bl616/std/src/bl616_romapi_e907.c index 2808c902..f7e11000 100644 --- a/drivers/soc/bl616/std/src/bl616_romapi_e907.c +++ b/drivers/soc/bl616/std/src/bl616_romapi_e907.c @@ -1448,8 +1448,8 @@ void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg){ #endif __ALWAYS_INLINE ATTR_TCM_SECTION -void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_HBN_Power_Down_Flash(flashCfg); +void HBN_Power_Down_Flash(spi_flash_cfg_type *flash_cfg){ + return RomDriver_HBN_Power_Down_Flash(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION @@ -1567,12 +1567,12 @@ BL_Err_Type PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2 } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg){ +BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg){ return RomDriver_PDS_Set_Flash_Pad_Pull_None(pinCfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg){ +BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg){ return RomDriver_PDS_Set_Flash_Pad_Pull_None_Fast(pinCfg); } @@ -1647,510 +1647,510 @@ BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType){ } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin){ - return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); +int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin){ + return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){ - return RomDriver_SF_Cfg_Flash_Init(sel,pSfCtrlCfg,pBank2Cfg); +int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg){ + return RomDriver_SF_Cfg_Flash_Init(sel,p_sf_ctrl_cfg,p_bank2_cfg); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg){ - return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID,pFlashCfg); +int bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *flash_cfg){ + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id,flash_cfg); } #endif __ALWAYS_INLINE -BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin){ - return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); +int bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin){ + return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SF_Cfg_Init_Flash2_Gpio(uint8_t swap){ +int bflb_sf_cfg_init_flash2_gpio(uint8_t swap){ return RomDriver_SF_Cfg_Init_Flash2_Gpio(swap); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault){ - return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg,restoreDefault); +int bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default){ + return RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg,restore_default); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){ - return RomDriver_SF_Cfg_Sbus2_Flash_Init(sel,pBank2Cfg); +int bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg){ + return RomDriver_SF_Cfg_Sbus2_Flash_Init(sel,p_bank2_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_SF_Cfg_Flash_Identify(callFromFlash,flashPinCfg,restoreDefault,pFlashCfg,group,bank); +uint32_t bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, spi_flash_cfg_type *flash_cfg, uint8_t group, uint8_t bank){ + return RomDriver_SF_Cfg_Flash_Identify(call_from_flash,flash_pin_cfg,restore_default,flash_cfg,group,bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Sts_Type SF_Ctrl_GetBusyState(void){ +uint8_t bflb_sf_ctrl_get_busy_state(void){ return RomDriver_SF_Ctrl_GetBusyState(); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Sts_Type SF_Ctrl_Is_AES_Enable(void){ +uint8_t bflb_sf_ctrl_is_aes_enable(void){ return RomDriver_SF_Ctrl_Is_AES_Enable(); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void){ +uint8_t bflb_sf_ctrl_is_sbus2_enable(void){ return RomDriver_SF_Ctrl_Is_Sbus2_Enable(); } __ALWAYS_INLINE ATTR_TCM_SECTION -uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank){ +uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank){ return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(group,bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -uint8_t SF_Ctrl_Get_Clock_Delay(void){ +uint8_t bflb_sf_ctrl_get_clock_delay(void){ return RomDriver_SF_Ctrl_Get_Clock_Delay(); } __ALWAYS_INLINE ATTR_TCM_SECTION -uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void){ +uint8_t bflb_sf_ctrl_get_wrap_queue_value(void){ return RomDriver_SF_Ctrl_Get_Wrap_Queue_Value(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr){ - return RomDriver_SF_Ctrl_32bits_Addr_En(en32BitsAddr); +void bflb_sf_ctrl_32bits_addr_en(BL_Fun_Type en_32bits_addr){ + return RomDriver_SF_Ctrl_32bits_Addr_En(en_32bits_addr); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Disable(void){ +void bflb_sf_ctrl_aes_disable(void){ return RomDriver_SF_Ctrl_AES_Disable(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Enable(void){ +void bflb_sf_ctrl_aes_enable(void){ return RomDriver_SF_Ctrl_AES_Enable(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Enable_BE(void){ +void bflb_sf_ctrl_aes_enable_be(void){ return RomDriver_SF_Ctrl_AES_Enable_BE(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Enable_LE(void){ +void bflb_sf_ctrl_aes_enable_le(void){ return RomDriver_SF_Ctrl_AES_Enable_LE(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset){ - return RomDriver_SF_Ctrl_AES_Set_IV(region,iv,addrOffset); +void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset){ + return RomDriver_SF_Ctrl_AES_Set_IV(region,iv,addr_offset); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset){ - return RomDriver_SF_Ctrl_AES_Set_IV_BE(region,iv,addrOffset); +void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset){ + return RomDriver_SF_Ctrl_AES_Set_IV_BE(region,iv,addr_offset); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){ - return RomDriver_SF_Ctrl_AES_Set_Key(region,key,keyType); +void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type){ + return RomDriver_SF_Ctrl_AES_Set_Key(region,key,key_type); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){ - return RomDriver_SF_Ctrl_AES_Set_Key_BE(region,key,keyType); +void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type){ + return RomDriver_SF_Ctrl_AES_Set_Key_BE(region,key,key_type); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode){ +void bflb_sf_ctrl_aes_set_mode(uint8_t mode){ return RomDriver_SF_Ctrl_AES_Set_Mode(mode); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked){ - return RomDriver_SF_Ctrl_AES_Set_Region(region,enable,hwKey,startAddr,endAddr,locked); +void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t start_addr, uint32_t end_addr, uint8_t locked){ + return RomDriver_SF_Ctrl_AES_Set_Region(region,enable,hwKey,start_addr,end_addr,locked); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset){ - return RomDriver_SF_Ctrl_AES_XTS_Set_IV(region,iv,addrOffset); +void bflb_sf_ctrl_aes_xts_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset){ + return RomDriver_SF_Ctrl_AES_XTS_Set_IV(region,iv,addr_offset); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset){ - return RomDriver_SF_Ctrl_AES_XTS_Set_IV_BE(region,iv,addrOffset); +void bflb_sf_ctrl_aes_xts_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset){ + return RomDriver_SF_Ctrl_AES_XTS_Set_IV_BE(region,iv,addr_offset); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){ - return RomDriver_SF_Ctrl_AES_XTS_Set_Key(region,key,keyType); +void bflb_sf_ctrl_aes_xts_set_key(uint8_t region, uint8_t *key, uint8_t key_type){ + return RomDriver_SF_Ctrl_AES_XTS_Set_Key(region,key,key_type); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){ - return RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE(region,key,keyType); +void bflb_sf_ctrl_aes_xts_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type){ + return RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE(region,key,key_type); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg){ - return RomDriver_SF_Ctrl_Bank2_Enable(bank2Cfg); +void bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2_cfg){ + return RomDriver_SF_Ctrl_Bank2_Enable(bank2_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank){ - return RomDriver_SF_Ctrl_Cmds_Set(cmdsCfg,bank); +void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t bank){ + return RomDriver_SF_Ctrl_Cmds_Set(cmds_cfg,bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Disable(void){ +void bflb_sf_ctrl_disable(void){ return RomDriver_SF_Ctrl_Disable(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Disable_Wrap_Access(uint8_t disable){ +void bflb_sf_ctrl_disable_wrap_access(uint8_t disable){ return RomDriver_SF_Ctrl_Disable_Wrap_Access(disable); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg){ +void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg){ return RomDriver_SF_Ctrl_Enable(cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid){ - return RomDriver_SF_Ctrl_Flash2_Read_Icache_Set(cfg,cmdValid); +void bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid){ + return RomDriver_SF_Ctrl_Flash2_Read_Icache_Set(cfg,cmd_valid); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid){ - return RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg,cmdValid); +void bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid){ + return RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg,cmd_valid); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock){ +void bflb_sf_ctrl_lock_flash_image_offset(uint8_t lock){ return RomDriver_SF_Ctrl_Lock_Flash_Image_Offset(lock); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock){ +void bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock){ return RomDriver_SF_Ctrl_Remap_Set(remap,lock); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Sbus2_Hold_Sram(void){ +void bflb_sf_ctrl_sbus2_hold_sram(void){ return RomDriver_SF_Ctrl_Sbus2_Hold_Sram(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Sbus2_Release_Sram(void){ +void bflb_sf_ctrl_sbus2_release_sram(void){ return RomDriver_SF_Ctrl_Sbus2_Release_Sram(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad){ +void bflb_sf_ctrl_sbus2_replace(uint8_t pad){ return RomDriver_SF_Ctrl_Sbus2_Replace(pad); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Sbus2_Revoke_replace(void){ +void bflb_sf_ctrl_sbus2_revoke_replace(void){ return RomDriver_SF_Ctrl_Sbus2_Revoke_replace(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert){ - return RomDriver_SF_Ctrl_Sbus2_Set_Delay(clkDelay,rxClkInvert); +void bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert){ + return RomDriver_SF_Ctrl_Sbus2_Set_Delay(clk_delay,rx_clk_invert); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank){ +void bflb_sf_ctrl_sbus_select_bank(uint8_t bank){ return RomDriver_SF_Ctrl_Sbus_Select_Bank(bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel){ +void bflb_sf_ctrl_select_pad(uint8_t sel){ return RomDriver_SF_Ctrl_Select_Pad(sel); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg){ +void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg){ return RomDriver_SF_Ctrl_SendCmd(cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Set_Clock_Delay(uint8_t delay){ +void bflb_sf_ctrl_set_clock_delay(uint8_t delay){ return RomDriver_SF_Ctrl_Set_Clock_Delay(delay); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset,group,bank); +void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank){ + return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset,group,bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay){ - return RomDriver_SF_Ctrl_Set_IO_Delay(pad,doDelay,diDelay,oeDelay); +void bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t do_delay, uint8_t di_delay, uint8_t oe_delay){ + return RomDriver_SF_Ctrl_Set_IO_Delay(pad,do_delay,di_delay,oe_delay); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner){ +void bflb_sf_ctrl_set_owner(uint8_t owner){ return RomDriver_SF_Ctrl_Set_Owner(owner); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum){ - return RomDriver_SFlash_Blk32_Erase(flashCfg,blkNum); +int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num){ + return RomDriver_SFlash_Blk32_Erase(flash_cfg,blk_num); } #endif __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum){ - return RomDriver_SFlash_Blk64_Erase(flashCfg,blkNum); +int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num){ + return RomDriver_SFlash_Blk64_Erase(flash_cfg,blk_num); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Chip_Erase(flashCfg); +int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Chip_Erase(flash_cfg); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr){ - return RomDriver_SFlash_Erase(flashCfg,startaddr,endaddr); +int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr){ + return RomDriver_SFlash_Erase(flash_cfg,start_addr,end_addr); } #endif __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg){ - return RomDriver_SFlash_Erase_Security_Register(pFlashCfg,pSecRegCfg); +int bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg){ + return RomDriver_SFlash_Erase_Security_Register(flash_cfg,p_sec_reg_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, SF_Ctrl_Bank_Select bank){ - return RomDriver_SFlash_IDbus_Read_Enable(flashCfg,ioMode,contRead,bank); +int bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank){ + return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg,io_mode,cont_read,bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len){ - return RomDriver_SFlash_Program(flashCfg,ioMode,addr,data,len); +int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len){ + return RomDriver_SFlash_Program(flash_cfg,io_mode,addr,data,len); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg){ - return RomDriver_SFlash_Program_Security_Register(pFlashCfg,pSecRegCfg); +int bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg){ + return RomDriver_SFlash_Program_Security_Register(flash_cfg,p_sec_reg_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Qspi_Disable(flashCfg); +int bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Qspi_Disable(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Qspi_Enable(flashCfg); +int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Qspi_Enable(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos){ - return RomDriver_SFlash_RCV_Enable(pFlashCfg,rCmd,wCmd,bitPos); +int bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos){ + return RomDriver_SFlash_RCV_Enable(flash_cfg,r_cmd,w_cmd,bit_pos); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len){ - return RomDriver_SFlash_Read(flashCfg,ioMode,contRead,addr,data,len); +int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len){ + return RomDriver_SFlash_Read(flash_cfg,io_mode,cont_read,addr,data,len); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen){ - return RomDriver_SFlash_Read_Reg(flashCfg,regIndex,regValue,regLen); +int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Read_Reg(flash_cfg,reg_index,reg_value,reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen){ - return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg,readRegCmd,regValue,regLen); +int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg,read_reg_cmd,reg_value,reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg){ - return RomDriver_SFlash_Read_Security_Register(pSecRegCfg); +int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg){ + return RomDriver_SFlash_Read_Security_Register(p_sec_reg_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, SF_Ctrl_Bank_Select bank){ - return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg,flashContRead,bank); +int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, uint8_t flash_cont_read, uint8_t bank){ + return RomDriver_SFlash_Restore_From_Powerdown(flash_cfg,flash_cont_read,bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum){ - return RomDriver_SFlash_Sector_Erase(flashCfg,secNum); +int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sec_num){ + return RomDriver_SFlash_Sector_Erase(flash_cfg,sec_num); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr){ - return RomDriver_SFlash_Set32BitsAddrMode(flashCfg,en32BitsAddr); +int bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, BL_Fun_Type en_32bits_addr){ + return RomDriver_SFlash_Set32BitsAddrMode(flash_cfg,en_32bits_addr); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode){ +int bflb_sflash_set_spi_mode(uint8_t mode){ return RomDriver_SFlash_SetSPIMode(mode); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank){ - return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg,ioMode,contRead,addr,len,bank); +int bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank){ + return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg,io_mode,cont_read,addr,len,bank); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Software_Reset(flashCfg); +int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Software_Reset(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Write_Enable(flashCfg); +int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Write_Enable(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen){ - return RomDriver_SFlash_Write_Reg(flashCfg,regIndex,regValue,regLen); +int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Write_Reg(flash_cfg,reg_index,reg_value,reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen){ - return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg,writeRegCmd,regValue,regLen); +int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len){ + return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg,write_reg_cmd,reg_value,reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Busy(flashCfg); +int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Busy(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_DisableBurstWrap(flashCfg); +void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_DisableBurstWrap(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr){ - return RomDriver_SFlash_GetDeviceId(data,is32BitsAddr); +void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr){ + return RomDriver_SFlash_GetDeviceId(data,is_32bits_addr); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data){ - return RomDriver_SFlash_GetJedecId(flashCfg,data); +void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data){ + return RomDriver_SFlash_GetJedecId(flash_cfg,data); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen){ - return RomDriver_SFlash_GetUniqueId(data,idLen); +void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len){ + return RomDriver_SFlash_GetUniqueId(data,id_len); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_IDbus_Read_Disable(void){ +void bflb_sflash_idbus_read_disable(void){ return RomDriver_SFlash_IDbus_Read_Disable(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){ - return RomDriver_SFlash_Init(pSfCtrlCfg,pBank2Cfg); +void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg){ + return RomDriver_SFlash_Init(p_sf_ctrl_cfg,p_bank2_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_Powerdown(void){ +void bflb_sflash_powerdown(void){ return RomDriver_SFlash_Powerdown(); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Release_Powerdown(flashCfg); +void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Release_Powerdown(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Reset_Continue_Read(flashCfg); +void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Reset_Continue_Read(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_SetBurstWrap(flashCfg); +void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_SetBurstWrap(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION -void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){ - return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); +void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg){ + return RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg,startaddr,len,group,bank); +int bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, int len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Erase_Need_Lock(flash_cfg,start_addr,len,group,bank); } #endif #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg,is32BitsAddr,data,group,bank); +int bflb_xip_sflash_getdeviceid_need_lock(spi_flash_cfg_type *flash_cfg, BL_Fun_Type is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(flash_cfg,is_32bits_addr,data,group,bank); } #endif #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg,data,group,bank); +int bflb_xip_sflash_getjedecid_need_lock(spi_flash_cfg_type *flash_cfg, uint8_t *data, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(flash_cfg,data,group,bank); } #endif #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg,data,idLen,group,bank); +int bflb_xip_sflash_getuniqueid_need_lock(spi_flash_cfg_type *flash_cfg, uint8_t *data, uint8_t id_len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(flash_cfg,data,id_len,group,bank); } #endif #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg,addr,data,len,group,bank); +int bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Read_Need_Lock(flash_cfg,addr,data,len,group,bank); } #endif #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len){ +int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len){ return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr,data,len); } #endif __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_State_Restore(pFlashCfg,offset,group,bank); +int bflb_xip_sflash_state_restore(spi_flash_cfg_type *flash_cfg, uint32_t offset, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_State_Restore(flash_cfg,offset,group,bank); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_State_Save(pFlashCfg,offset,group,bank); +int bflb_xip_sflash_state_save(spi_flash_cfg_type *flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_State_Save(flash_cfg,offset,group,bank); } #endif #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){ - return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg,addr,data,len,group,bank); +int bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank){ + return RomDriver_XIP_SFlash_Write_Need_Lock(flash_cfg,addr,data,len,group,bank); } #endif __ALWAYS_INLINE ATTR_TCM_SECTION -void XIP_SFlash_Opt_Enter(uint8_t *aesEnable){ - return RomDriver_XIP_SFlash_Opt_Enter(aesEnable); +void bflb_xip_sflash_opt_enter(uint8_t *aes_enable){ + return RomDriver_XIP_SFlash_Opt_Enter(aes_enable); } __ALWAYS_INLINE ATTR_TCM_SECTION -void XIP_SFlash_Opt_Exit(uint8_t aesEnable){ - return RomDriver_XIP_SFlash_Opt_Exit(aesEnable); +void bflb_xip_sflash_opt_exit(uint8_t aes_enable){ + return RomDriver_XIP_SFlash_Opt_Exit(aes_enable); } #if 0 diff --git a/drivers/soc/bl616/std/src/bl616_romapi_patch.c b/drivers/soc/bl616/std/src/bl616_romapi_patch.c index d2bda9d9..3e02bf03 100644 --- a/drivers/soc/bl616/std/src/bl616_romapi_patch.c +++ b/drivers/soc/bl616/std/src/bl616_romapi_patch.c @@ -211,694 +211,699 @@ const GLB_SLAVE_GRP_0_TBL_Type ATTR_CLOCK_CONST_SECTION glb_slave_grp_0_table[GL typedef struct { - uint32_t jedecID; + uint32_t jedec_id; char *name; - const SPI_Flash_Cfg_Type *cfg; + const spi_flash_cfg_type *cfg; } Flash_Info_t; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_LQ64E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_GD_LQ64E = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xc8, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xa0, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3d, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, + .time_e_sector = 500, + .time_e_32k = 2000, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 3, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_Q64E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_GD_Q64E = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xc8, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Winb_16JV = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xef, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xa0, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3d, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 3, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Winb_64JV = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xef, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0xFF, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x3f, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, + .time_e_sector = 400, + .time_e_32k = 1600, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 3, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Winb_256FV = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xef, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xa0, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = 0x24, - .clkDelay = 1, - .clkInvert = 0x3f, + .io_mode = 0x24, + .clk_delay = 1, + .clk_invert = 0x3f, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, + .time_e_sector = 400, + .time_e_32k = 1600, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 3, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25U256 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Mxic_25U256 = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xc2, - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, + .de_burst_wrap_cmd = 0xC0, + .de_burst_wrap_cmd_dmy_clk = 0x00, + .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .de_burst_wrap_data = 0x10, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, + .qe_index = 0, + .qe_bit = 0x06, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x15, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x15, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xA5, - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, + .burst_wrap_cmd = 0xC0, + .burst_wrap_cmd_dmy_clk = 0x00, + .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE, + .burst_wrap_data = 0x02, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x38, + .qpp_addr_mode = SF_CTRL_ADDR_4_LINES, - .ioMode = (SF_CTRL_QIO_MODE | 0x20), - .clkDelay = 1, - .clkInvert = 0x3f, + .io_mode = (SF_CTRL_QIO_MODE | 0x20), + .clk_delay = 1, + .clk_invert = 0x3f, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .enter_32bits_addr_cmd = 0xb7, + .exit_32bits_addr_cmd = 0xe9, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 400, - .timeE32k = 1000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, + .time_e_sector = 400, + .time_e_32k = 1000, + .time_e_64k = 2000, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { +static const ATTR_TCM_CONST_SECTION Flash_Info_t flash_infos[] = { { - .jedecID = 0x1740ef, + .jedec_id = 0x1740ef, //.name="WB_64JV_64_33", - .cfg = &flashCfg_Winb_64JV, + .cfg = &flash_cfg_Winb_64JV, }, { - .jedecID = 0x1940ef, + .jedec_id = 0x1940ef, //.name="WB_256FV_256_33", - .cfg = &flashCfg_Winb_256FV, + .cfg = &flash_cfg_Winb_256FV, }, { - .jedecID = 0x1760ef, + .jedec_id = 0x1760ef, //.name="WB_64JW_64_18", - .cfg = &flashCfg_Winb_64JV, + .cfg = &flash_cfg_Winb_64JV, }, { - .jedecID = 0x1570ef, + .jedec_id = 0x1570ef, //.name="WB_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flash_cfg_Winb_16JV, }, { - .jedecID = 0x1740c8, + .jedec_id = 0x1740c8, //.name="GD_64E_64_33", - .cfg = &flashCfg_GD_Q64E, + .cfg = &flash_cfg_GD_Q64E, }, { - .jedecID = 0x1760c8, + .jedec_id = 0x1760c8, //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_GD_LQ64E, + .cfg = &flash_cfg_GD_LQ64E, }, { - .jedecID = 0x1860c8, + .jedec_id = 0x1860c8, //.name="GD_LQ128E_128_18", - .cfg = &flashCfg_GD_LQ64E, + .cfg = &flash_cfg_GD_LQ64E, }, { - .jedecID = 0x15345e, + .jedec_id = 0x15345e, //.name="ZB_WQ16A_16_33", - .cfg = &flashCfg_GD_Q64E, + .cfg = &flash_cfg_GD_Q64E, }, { - .jedecID = 0x15405e, + .jedec_id = 0x15405e, //.name="ZB_16B_16_33", - .cfg = &flashCfg_GD_Q64E, + .cfg = &flash_cfg_GD_Q64E, }, { - .jedecID = 0x16405e, + .jedec_id = 0x16405e, //.name="ZB_32B_32_33", - .cfg = &flashCfg_GD_Q64E, + .cfg = &flash_cfg_GD_Q64E, }, { - .jedecID = 0x17405e, + .jedec_id = 0x17405e, //.name="ZB_VQ64_64_33", - .cfg = &flashCfg_GD_Q64E, + .cfg = &flash_cfg_GD_Q64E, }, { - .jedecID = 0x15605e, + .jedec_id = 0x18405e, + //.name="ZB_VQ128_64_33", + .cfg = &flash_cfg_GD_LQ64E, + }, + { + .jedec_id = 0x15605e, //.name="ZB_VQ16_16_33", - .cfg = &flashCfg_GD_Q64E, + .cfg = &flash_cfg_GD_Q64E, }, { - .jedecID = 0x3925c2, + .jedec_id = 0x3925c2, //.name="MX_U25643G_256_18", - .cfg = &flashCfg_Mxic_25U256, + .cfg = &flash_cfg_Mxic_25U256, }, { - .jedecID = 0x144020, + .jedec_id = 0x144020, //.name="XM_QH80_08_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flash_cfg_Winb_16JV, }, { - .jedecID = 0x154020, + .jedec_id = 0x154020, //.name="XM_QH16_16_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flash_cfg_Winb_16JV, }, { - .jedecID = 0x164020, + .jedec_id = 0x164020, //.name="XM_QH32_32_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flash_cfg_Winb_16JV, }, { - .jedecID = 0x174020, + .jedec_id = 0x174020, //.name="XM_QH64_64_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flash_cfg_Winb_16JV, }, { - .jedecID = 0x174220, + .jedec_id = 0x174220, //.name="XM_QW64_64_1833", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flash_cfg_Winb_16JV, }, { - .jedecID = 0x17400b, + .jedec_id = 0x17400b, //.name="XT_F64B_64_33", - .cfg = &flashCfg_GD_LQ64E, + .cfg = &flash_cfg_GD_LQ64E, }, }; @@ -910,252 +915,255 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { /****************************************************************************/ /** * @brief Erase flash one 32K block * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number + * @param flash_cfg: Serial flash parameter configuration pointer + * @param blk_num: flash 32K block number * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) +int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num) { uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); + uint8_t is_32bits_addr = 0; + struct sf_ctrl_cmd_cfg_type flash_cmd; + int stat = bflb_sflash_write_enable(flash_cfg); - if (stat != SUCCESS) { + if (stat != 0) { return stat; } - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uintptr_t)&flash_cmd) % 4 == 0) { + ARCH_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); + ARCH_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; + is_32bits_addr = (flash_cfg->io_mode & 0x20); + /* rw_flag don't care */ + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.addr_size = 3; - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24); + if (is_32bits_addr > 0) { + flash_cmd.addr_size++; + flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) >> 8); + flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) << 24); } else { - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); + flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blk_num); } - SF_Ctrl_SendCmd(&flashCmd); + bflb_sf_ctrl_sendcmd(&flash_cmd); - while (SET == SFlash_Busy(flashCfg)) { + while (SET == bflb_sflash_busy(flash_cfg)) { arch_delay_us(500); cnt++; - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; + if (cnt > flash_cfg->time_e_32k * 3) { + return -1; } } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Erase flash one region * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase + * @param flash_cfg: Serial flash parameter configuration pointer + * @param start_addr: start address to erase + * @param end_addr: end address(include this address) to erase * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) +int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr) { uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; + uint32_t erase_len = 0; + int ret = 0; - if (startaddr > endaddr) { - return ERROR; + if (start_addr > end_addr) { + return -1; } - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; + while (start_addr <= end_addr) { + len = end_addr - start_addr + 1; - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { + if (flash_cfg->blk64_erase_cmd != BFLB_SPIFLASH_CMD_INVALID && + (start_addr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK64K_SIZE - flash_cfg->sector_size * 1024)) { /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { + ret = bflb_sflash_blk64_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK64K_SIZE); + erase_len = BFLB_SPIFLASH_BLK64K_SIZE; + } else if (flash_cfg->blk32_erase_cmd != BFLB_SPIFLASH_CMD_INVALID && + (start_addr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && + len > (BFLB_SPIFLASH_BLK32K_SIZE - flash_cfg->sector_size * 1024)) { /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; + ret = bflb_sflash_blk32_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK32K_SIZE); + erase_len = BFLB_SPIFLASH_BLK32K_SIZE; } else { /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; + start_addr = ((start_addr) & (~(flash_cfg->sector_size * 1024 - 1))); + ret = bflb_sflash_sector_erase(flash_cfg, start_addr / flash_cfg->sector_size / 1024); + erase_len = flash_cfg->sector_size * 1024; } - startaddr += eraseLen; + start_addr += erase_len; - if (ret != SUCCESS) { - return ERROR; + if (ret != 0) { + return -1; } } - return SUCCESS; + return 0; } /****************************************************************************//** * @brief Clear flash status register * - * @param flashCfg: Flash configuration pointer + * @param flash_cfg: Flash configuration pointer * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *flashCfg) +int ATTR_TCM_SECTION bflb_SFlash_Clear_Status_Register(spi_flash_cfg_type *flash_cfg) { uint32_t ret = 0; - uint32_t qeValue = 0; - uint32_t regValue = 0; - uint32_t readValue = 0; - uint8_t readRegValue0 = 0; - uint8_t readRegValue1 = 0; + uint32_t qe_value = 0; + uint32_t reg_value = 0; + uint32_t read_value = 0; + uint8_t read_reg_value0 = 0; + uint8_t read_reg_value1 = 0; - if((flashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (flashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){ - qeValue = 1; + if((flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE){ + qe_value = 1; } - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&readRegValue0, 1); - SFlash_Read_Reg(flashCfg, 1, (uint8_t *)&readRegValue1, 1); - readValue = (readRegValue0|(readRegValue1<<8)); - if ((readValue & (~((1<<(flashCfg->qeIndex*8+flashCfg->qeBit)) | - (1<<(flashCfg->busyIndex*8+flashCfg->busyBit)) | - (1<<(flashCfg->wrEnableIndex*8+flashCfg->wrEnableBit))))) == 0){ - return SUCCESS; + bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&read_reg_value0, 1); + bflb_sflash_read_reg(flash_cfg, 1, (uint8_t *)&read_reg_value1, 1); + read_value = (read_reg_value0|(read_reg_value1<<8)); + if ((read_value & (~((1<<(flash_cfg->qe_index*8+flash_cfg->qe_bit)) | + (1<<(flash_cfg->busy_index*8+flash_cfg->busy_bit)) | + (1<<(flash_cfg->wr_enable_index*8+flash_cfg->wr_enable_bit))))) == 0){ + return 0; } - ret = SFlash_Write_Enable(flashCfg); - if (SUCCESS != ret) { - return ERROR; + ret = bflb_sflash_write_enable(flash_cfg); + if (0 != ret) { + return -1; } - if (flashCfg->qeWriteRegLen == 2) { - regValue = (qeValue<<(flashCfg->qeIndex*8+flashCfg->qeBit)); - SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 2); + if (flash_cfg->qe_write_reg_len == 2) { + reg_value = (qe_value<<(flash_cfg->qe_index*8+flash_cfg->qe_bit)); + bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 2); } else { - if (flashCfg->qeIndex == 0) { - regValue = (qeValue<qeBit); + if (flash_cfg->qe_index == 0) { + reg_value = (qe_value<qe_bit); } else { - regValue = 0; + reg_value = 0; } - SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 1); - ret = SFlash_Write_Enable(flashCfg); + bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 1); + ret = bflb_sflash_write_enable(flash_cfg); if (SUCCESS != ret) { - return ERROR; + return -1; } - if (flashCfg->qeIndex == 1) { - regValue = (qeValue<qeBit); + if (flash_cfg->qe_index == 1) { + reg_value = (qe_value<qe_bit); } else { - regValue = 0; + reg_value = 0; } - SFlash_Write_Reg(flashCfg, 1, (uint8_t *)®Value, 1); + bflb_sflash_write_reg(flash_cfg, 1, (uint8_t *)®_value, 1); } - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Get flash config according to flash ID patch * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer + * @param flash_id: Flash ID + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) { uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - char flashCfgMagic[] = "FCFG"; + uint8_t buf[sizeof(spi_flash_cfg_type) + 8]; + uint32_t crc, *p_crc; + uint32_t xip_offset; + char flash_cfg_magic[] = "FCFG"; - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL616_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, 0, SF_CTRL_FLASH_BANK0); + if (flash_id == 0) { + xip_offset = bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); + bflb_xip_sflash_read_via_cache_need_lock(8 + BL616_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank); + bflb_sf_ctrl_set_flash_image_offset(xip_offset, group, bank); - if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); + if (ARCH_MemCmp(buf, flash_cfg_magic, 4) == 0) { + crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); + p_crc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type)); - if (*pCrc == crc) { - arch_memcpy_fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; + if (*p_crc == crc) { + arch_memcpy_fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); + return 0; } } } else { - if (RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS) { - return SUCCESS; + if (RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg) == 0) { + return 0; } - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == flash_id) { + arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); + return 0; } } } - return ERROR; + return -1; } /****************************************************************************/ /** * @brief Identify one flash patch * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer + * @param call_from_flash: code run at flash or ram + * @param flash_pin_cfg: Bit 7: autoscan, Bit6-0: flash GPIO config + * @param restore_default: Wether restore default flash GPIO config + * @param p_flash_cfg: Flash config pointer * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * * @return Flash ID * *******************************************************************************/ -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) +uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, + uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) { - uint32_t jdecId = 0; + uint32_t jedec_id = 0; uint32_t i = 0; uint32_t ret = 0; - ret = SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); - if (callFromFlash) { - SFlash_Set_IDbus_Cfg(pFlashCfg, pFlashCfg->ioMode & 0xf, 1, 0, 32, bank); + ret = bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank); + if (call_from_flash) { + bflb_sflash_set_xip_cfg(p_flash_cfg, p_flash_cfg->io_mode & 0xf, 1, 0, 32, bank); } if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) { return ret; } - jdecId = (ret & 0xffffff); - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + jedec_id = (ret & 0xffffff); + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == jedec_id) { + arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); break; } } - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - return jdecId; + if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) { + return jedec_id; } else { - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); + return (jedec_id | BFLB_FLASH_ID_VALID_FLAG); } } @@ -1165,39 +1173,42 @@ uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8 * @param addr: flash read start address * @param data: data pointer to store data read from flash * @param len: data length to read + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) +int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, + uint8_t group, uint8_t bank) { uint32_t offset; addr = addr & (BL616_FLASH_XIP_END - BL616_FLASH_XIP_BASE - 1); addr |= BL616_FLASH_XIP_BASE; - offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0); + offset = bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); /* Flash read */ - arch_memcpy_fast(data, (void *)(uintptr_t)(addr - SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0)), len); - SF_Ctrl_Set_Flash_Image_Offset(offset, 0, SF_CTRL_FLASH_BANK0); + arch_memcpy_fast(data, (void *)(uintptr_t)(addr - bflb_sf_ctrl_get_flash_image_offset(group, bank)), len); + bflb_sf_ctrl_set_flash_image_offset(offset, group, bank); - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Save flash controller state * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param offset: CPU XIP flash offset pointer * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, + uint8_t group, uint8_t bank) { /* XIP_SFlash_Delay */ volatile uint32_t i = 32 * 2; @@ -1206,60 +1217,60 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg ; if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); + bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2); } - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); + bflb_sflash_reset_continue_read(p_flash_cfg); /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); + bflb_sflash_disable_burst_wrap(p_flash_cfg); /* Enable 32Bits addr mode again in case reset command make it reset */ - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { + bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1); + if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) { /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); + bflb_sflash_qspi_enable(p_flash_cfg); } /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); + bflb_sflash_disable_burst_wrap(p_flash_cfg); /* Clear offset setting*/ - *offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); + *offset = bflb_sf_ctrl_get_flash_image_offset(group, bank); + bflb_sf_ctrl_set_flash_image_offset(0, group, bank); - return SUCCESS; + return 0; } /****************************************************************************/ /** * @brief Erase flash one region * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase + * @param p_flash_cfg: Flash config pointer + * @param start_addr: start address to erase * @param len: data length to erase * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr, + int len, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat; uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); + stat = bflb_sflash_erase(p_flash_cfg, start_addr, start_addr + len - 1); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); return stat; } @@ -1267,35 +1278,35 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFla /****************************************************************************/ /** * @brief Program flash one region * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param addr: start address to be programed * @param data: data pointer to be programed * @param len: data length to be programed * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, + uint32_t len, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat; uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); + stat = bflb_sflash_program(p_flash_cfg, io_mode, addr, data, len); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); return stat; } @@ -1303,35 +1314,35 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFla /****************************************************************************/ /** * @brief Read data from flash * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param addr: flash read start address * @param data: data pointer to store data read from flash * @param len: data length to read * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, + uint32_t len, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat; uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); + stat = bflb_sflash_read(p_flash_cfg, io_mode, 0, addr, data, len); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); return stat; } @@ -1339,131 +1350,131 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlas /****************************************************************************/ /** * @brief Get Flash Jedec ID * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param data: data pointer to store Jedec ID Read from flash * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_xip_sflash_getjedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat; uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); + bflb_sflash_get_jedecid(p_flash_cfg, data); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); - return SUCCESS; + return stat; } /****************************************************************************/ /** * @brief Get Flash Device ID * - * @param pFlashCfg: Flash config pointer - * @param is32BitsAddr: Is flash addr mode in 32-bits + * @param p_flash_cfg: Flash config pointer + * @param is_32bits_addr: Is flash addr mode in 32-bits * @param data: data pointer to store Device ID Read from flash * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_xip_sflash_getdeviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, BL_Fun_Type is_32bits_addr, + uint8_t *data, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat; uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - SFlash_GetDeviceId(data, is32BitsAddr); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); + bflb_sflash_get_deviceid(data, is_32bits_addr); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); - return SUCCESS; + return stat; } /****************************************************************************/ /** * @brief Get Flash Unique ID * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param data: data pointer to store Device ID Read from flash * @param idLen: Unique id len * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_xip_sflash_getuniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, + uint8_t idLen, uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat; uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; + uint8_t aes_enable = 0; + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); + bflb_xip_sflash_opt_enter(&aes_enable); + stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); + bflb_sflash_get_uniqueid(data, idLen); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); } - XIP_SFlash_Opt_Exit(aesEnable); + bflb_xip_sflash_opt_exit(aes_enable); - return SUCCESS; + return stat; } /****************************************************************************//** * @brief Clear flash status register need lock * - * @param pFlashCfg: Flash config pointer + * @param p_flash_cfg: Flash config pointer * @param group: CPU group id 0 or 1 * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) +int ATTR_TCM_SECTION bflb_XIP_SFlash_Clear_Status_Register_Need_Lock(spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) { - BL_Err_Type stat; + int stat; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; + uint8_t io_mode = p_flash_cfg->io_mode&0xf; - stat=XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); + stat=bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank); } else { - stat=SFlash_Clear_Status_Register(pFlashCfg); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); + stat=bflb_sflash_clear_status_register(p_flash_cfg); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank); } return stat; @@ -1683,7 +1694,7 @@ BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType) * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue) { BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue | BFLB_FLASH_ID_VALID_FLAG)); @@ -1698,7 +1709,7 @@ BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) * @return flash id * *******************************************************************************/ -uint32_t GLB_Get_Flash_Id_Value(void) +uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void) { uint32_t tmpVal = 0; diff --git a/drivers/soc/bl616/std/src/bl616_sf_cfg.c b/drivers/soc/bl616/std/src/bl616_sf_cfg.c deleted file mode 100644 index 8fedd233..00000000 --- a/drivers/soc/bl616/std/src/bl616_sf_cfg.c +++ /dev/null @@ -1,3022 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_sf_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl616_sf_cfg.h" -#include "bl616_xip_sflash.h" -#include "soft_crc.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_Private_Macros */ - -/** @defgroup SF_CFG_Private_Types - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; -#endif - -/*@} end of group SF_CFG_Private_Types */ - -/** @defgroup SF_CFG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16FW_32JW_32FW_32FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_128JW_128JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x9d, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x00, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x06, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 5, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x51, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_DO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 32 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 8 / 8, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0x12, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x15, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = (SF_CTRL_QIO_MODE | 0x20), - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x0B, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 6000, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x85, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x85, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya40 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x68, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_DO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x68, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc2, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x00, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x00, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = (SF_CTRL_DO_MODE | 0x10), - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV= { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x24, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1440ef, - //.name="Winb_80DV_08_33", - .cfg = &flashCfg_Winb_80DV, - }, - { - .jedecID = 0x1540ef, - //.name="Winb_16DV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1640ef, - //.name="Winb_32FV_32_33", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1840ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_128JW_128JV, - }, - { - .jedecID = 0x1870ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_128JW_128JV, - }, - { - .jedecID = 0x1460ef, - //.name="Winb_80EW_08_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1560ef, - //.name="Winb_16FW_16_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1660ef, - //.name="Winb_32FW_32_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1860ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_128JW_128JV, - }, - { - .jedecID = 0x1680ef, - //.name="Winb_32JW_32_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1880ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_128JW_128JV, - }, - { - .jedecID = 0x13605e, - //.name="Zbit_04_33", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x14605e, - //.name="Zbit_08_33", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x14609d, - //.name="ISSI_08_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x15609d, - //.name="ISSI_16_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x16609d, - //.name="ISSI_32_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x14709d, - //.name="ISSI_08_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x15709d, - //.name="ISSI_16_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x16709d, - //.name="ISSI_32_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x134051, - //.name="GD_MD04D_04_33", - .cfg = &flashCfg_Gd_Md_40D, - }, - { - .jedecID = 0x1440C8, - //.name="GD_Q08E_08_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1540C8, - //.name="GD_Q16E_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1640C8, - //.name="GD_Q32C_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1840C8, - //.name="GD_Q128E_128_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1460C8, - //.name="GD_LQ08C_08_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1560C8, - //.name="GD_LE16C_16_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1660C8, - //.name="GD_LQ32D_32_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1465C8, - //.name="GD_WQ80E_80_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1565C8, - //.name="GD_WQ16E_16_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1665C8, - //.name="GD_WQ32E_32_33", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x3425C2, - //.name="MX_25V80_08_18", - .cfg = &flashCfg_Mxic, - }, - { - .jedecID = 0x3525C2, - //.name="MX_25U16_35_18", - .cfg = &flashCfg_Mxic_1635F, - }, - { - .jedecID = 0x3625C2, - //.name="MX_25V32_32_18", - .cfg = &flashCfg_Mxic, - }, - { - .jedecID = 0x1820C2, - //.name="MX_25L128_128_33", - .cfg = &flashCfg_Mxic_1635F, - }, - { - .jedecID = 0x1920C2, - //.name="MX_25L256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID = 0x15400B, - //.name="XT_25F16B_16_33", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x16400B, - //.name="XT_25F32B_32_33", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x18400B, - //.name="XT_25F128B_128_33", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x14600B, - //.name="XT_25Q80B_08_18", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x16600B, - //.name="XT_25Q32B_32_18", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x146085, - //.name="Puya_Q80L/H_08_18/33", - .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, - }, - { - .jedecID = 0x156085, - //.name="Puya_Q16H_16_33", - .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, - }, - { - .jedecID = 0x166085, - //.name="Puya_Q32H_32_33", - .cfg = &flashCfg_Puya_Q32H, - }, - { - .jedecID = 0x134068, - //.name="Boya_Q04B_04_33", - .cfg = &flashCfg_Boya40, - }, - { - .jedecID = 0x144068, - //.name="Boya_Q08B_08_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x154068, - //.name="Boya_Q16B_16_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x164068, - //.name="Boya_Q32B_32_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x174068, - //.name="Boya_Q64A_64_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x184068, - //.name="Boya_Q128A_128_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x14605E, - //.name="FT_VQ80", - .cfg = &flashCfg_FT_VQ80, - }, - { - .jedecID = 0x1320c2, - //.name="MX_KH40_04_33", - .cfg = &flashCfg_MX_KH25, - }, - { - .jedecID = 0x1420c2, - //.name="MX_KH80_08_33", - .cfg = &flashCfg_MX_KH25, - }, - { - .jedecID = 0x1520c2, - //.name="MX_KH16_16_33", - .cfg = &flashCfg_MX_KH25, - }, - { - .jedecID = 0x1740ef, - //.name="WB_64JV_64_33", - .cfg = &flashCfg_Winb_128JW_128JV, - }, - { - .jedecID = 0x1940ef, - //.name="WB_256FV_256_33", - .cfg = &flashCfg_Winb_256FV, - }, - { - .jedecID = 0x1760ef, - //.name="WB_64JW_64_18", - .cfg = &flashCfg_Winb_128JW_128JV, - }, - { - .jedecID = 0x1570ef, - //.name="WB_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1740c8, - //.name="GD_64E_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1860c8, - //.name="GD_LQ128E_128_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x15345e, - //.name="ZB_WQ16A_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15405e, - //.name="ZB_16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x16405e, - //.name="ZB_32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x17405e, - //.name="ZB_VQ64_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15605e, - //.name="ZB_VQ16_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x3925c2, - //.name="MX_U25643G_256_18", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID = 0x144020, - //.name="XM_QH80_08_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x154020, - //.name="XM_QH16_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x164020, - //.name="XM_QH32_32_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x174020, - //.name="XM_QH64_64_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x174220, - //.name="XM_QW64_64_1833", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x17400b, - //.name="XT_F64B_64_33", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, -}; -#endif - -/*@} end of group SF_CFG_Private_Variables */ - -/** @defgroup SF_CFG_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_Global_Variables */ - -/** @defgroup SF_CFG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 2; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_FLASH; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else if (extFlashPin == 1) { - gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - - if (i == 0 || i == 1) { - /* flash clk and cs is output */ - cfg.gpioMode = GPIO_MODE_OUTPUT; - } else { - /* data are bidir */ - cfg.gpioMode = GPIO_MODE_AF; - } - - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Deinit external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_GPIO; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else if (extFlashPin == 1) { - gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Private_Functions */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL616_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, 0, SF_CTRL_FLASH_BANK0); - - if (ARCH_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - arch_memcpy_fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) -{ - return SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg); -} -#endif - -/****************************************************************************/ /** - * @brief Init flash GPIO according to flash Pin config - * - * @param flashPinCfg: Specify flash Pin config - * @param restoreDefault: Wether to restore default setting - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault) -{ - uint8_t selEmbedded = 0; - uint8_t swapIo2Cs = 0; - uint8_t swapIo3Io0 = 0; - - if (restoreDefault) { - /* Set Default first */ - GLB_Set_SFlash_IO_PARM(1, 1, 0); - SF_Ctrl_Select_Pad(SF_IO_EMB_SWAP_IO3IO0); - - /* Default is set, so return */ - if (flashPinCfg == SF_IO_EMB_SWAP_IO3IO0) { - return SUCCESS; - } - } - - if (flashPinCfg & (1 << 2)) { - /* Init sf2 gpio */ - SF_Cfg_Init_Flash2_Gpio(!((flashPinCfg >> 5) & 1)); - selEmbedded = 0; - } else if (flashPinCfg & (1 << 3)) { - /* Init sf3 gpio */ - SF_Cfg_Init_Ext_Flash_Gpio(1); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* if pin select dual flash, embedded is default */ - if ((flashPinCfg & (1 << 4))) { - selEmbedded = 1; - } - - swapIo3Io0 = ((flashPinCfg >> 1) & 1); - swapIo3Io0 = (!swapIo3Io0); - swapIo2Cs = ((flashPinCfg >> 0) & 1); - GLB_Set_SFlash_IO_PARM(selEmbedded, swapIo3Io0, swapIo2Cs); - SF_Ctrl_Select_Pad(flashPinCfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Init flash2 GPIO - * - * @param swap: Select embedded flash2 swap io3 with io0 - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Flash2_Gpio(uint8_t swap) -{ - SF_Cfg_Init_Ext_Flash_Gpio(0); - GLB_Set_SFlash2_IO_PARM(swap); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint8_t autoScan = 0; - uint8_t flashPin = 0; - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t offset; - BL_Err_Type stat; - - autoScan = ((flashPinCfg >> 7) & 1); - flashPin = (flashPinCfg & 0x7F); - - arch_memcpy_fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type)); - - if (callFromFlash == 1) { - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - return 0; - } - } - - if (autoScan) { - flashPin = 0; - do { - if (!IS_SF_CTRL_PIN_SELECT(flashPin)) { - flashPin++; - continue; - } - if (bank == SF_CTRL_FLASH_BANK1) { - if (flashPin > SF_IO_EMB_SWAP_IO2CS_AND_SF2) { - jdecId = 0; - break; - } - if (flashPin < SF_IO_EXT_SF3) { - flashPin = SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0; - } - if (flashPin == SF_IO_EXT_SF2) { - flashPin++; - } - SF_Cfg_Init_Flash2_Gpio(!((flashPin >> 5) & 1)); - } else { - if (flashPin > SF_IO_EXT_SF2) { - jdecId = 0; - break; - } - if (flashPin > SF_IO_EXT_SF3) { - flashPin = SF_IO_EXT_SF2; - } - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - } - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = 0; - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - flashPin++; - } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); - } else { - /* select media gpio */ - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Cfg_Init_Flash2_Gpio(!((flashPin >> 5) & 1)); - } else { - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - } - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - } - - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - break; - } - } - - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return jdecId; - } else { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); - } -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - return SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg flash init - * - * @param sel: SF pin select - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t selEmbedded = 0; - uint8_t swapIo2Cs = 0; - uint8_t swapIo3Io0 = 0; - - if (sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) { - return ERROR; - } - - if (sel & (1 << 2)) { - SF_Cfg_Init_Flash2_Gpio(!((sel >> 5) & 1)); - selEmbedded = 0; - } else if (sel & (1 << 3)) { - SF_Cfg_Init_Ext_Flash_Gpio(1); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* If pin select dual flash, embedded is default */ - if ((sel & (1 << 4))) { - selEmbedded = 1; - } - - swapIo3Io0 = ((sel >> 1) & 1); - swapIo3Io0 = (!swapIo3Io0); - swapIo2Cs = ((sel >> 0) & 1); - GLB_Set_SFlash_IO_PARM(selEmbedded, swapIo3Io0, swapIo2Cs); - SF_Ctrl_Select_Pad(sel); - - if (sel <= SF_IO_EMB_SWAP_IO2CS) { - /* Embedded pad1 io delay set */ - if (pSfCtrlCfg != NULL) { - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } - } else if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) { - /* Pad2 or pad3 io delay set */ - if (pSfCtrlCfg != NULL) { - SF_Ctrl_Set_IO_Delay(((sel&0xf) >> 2), pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } - } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) - ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { - /* Dual flash mode, embedded pad1 and pad2 io delay set */ - if (pSfCtrlCfg != NULL) { - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } - if (pBank2Cfg != NULL) { - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - } - } - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) - ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - } - } - - SFlash_Init(pSfCtrlCfg, pBank2Cfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg system bus 2 flash init - * - * @param sel: SF pin select - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - if (sel < SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 || sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) { - return ERROR; - } - - /* Init flash2 gpio */ - if (sel & (1 << 2)) { - SF_Cfg_Init_Flash2_Gpio(!((sel >> 5) & 1)); - } - - /* Set remap for flash2 xip mode */ - SF_Ctrl_Remap_Set(pBank2Cfg->remap, pBank2Cfg->remapLock); - - if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) - ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { - /* Dual flash mode, pad2 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - } - if (pBank2Cfg->sbus2Select) { - if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) - ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - } - - SFlash_Init(NULL, pBank2Cfg); - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL616_Peripheral_Driver */ diff --git a/drivers/soc/bl616/std/src/bl616_sf_ctrl.c b/drivers/soc/bl616/std/src/bl616_sf_ctrl.c deleted file mode 100644 index b71a5786..00000000 --- a/drivers/soc/bl616/std/src/bl616_sf_ctrl.c +++ /dev/null @@ -1,1871 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_sf_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl616_sf_ctrl.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Private_Macros - * @{ - */ - -/*@} end of group SF_CTRL_Private_Macros */ - -/** @defgroup SF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SF_CTRL_Private_Types */ - -/** @defgroup SF_CTRL_Private_Variables - * @{ - */ -#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) -#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80) - -/*@} end of group SF_CTRL_Private_Variables */ - -/** @defgroup SF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SF_CTRL_Global_Variables */ - -/** @defgroup SF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SF_CTRL_Private_Functions - * @{ - */ - -/*@} end of group SF_CTRL_Private_Functions */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Enable serail flash controller - * - * @param cfg: serial flash controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - if (cfg == NULL) { - return; - } - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (cfg->en32bAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - if (cfg->clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - /* Serail out inverted, so sf ctrl send on negative edge */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); - - /* Enable AHB access sram buffer and enable sf interface */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); - - SF_Ctrl_Set_Owner(cfg->owner); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serail bank2 controller - * - * @param bank2Cfg: serial bank2 controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg) -{ - uint32_t tmpVal = 0; - - if (bank2Cfg == NULL) { - return; - } - - /* Select if1 bank2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12); - - if (bank2Cfg->bank2RxClkInvertSrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - } - - if (bank2Cfg->bank2DelaySrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal); - - /* Select sbus2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set io delay - * - * @param pad: Pad select - * @param doDelay: DO delay select - * @param diDelay: DI delay select - * @param oeDelay: OE delay select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay) -{ - uint32_t tmpVal = 0; - uint32_t offset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - if (pad == SF_CTRL_PAD1) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET; - } else if (pad == SF_CTRL_PAD2) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET; - } else { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET; - } - - /* Set do di and oe delay */ - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_4, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 hold sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Hold_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 hold sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 release sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Release_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 release sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller sbus2 status - * - * @param None - * - * @return Wether if2 is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_Sbus2_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_EN)) { - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_FN_SEL)) { - return SET; - } else { - return RESET; - } - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 repalce - * - * @param pad: SF pad to replace - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - /* Sbus2 enable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); - - SF_Ctrl_Sbus2_Hold_Sram(); - - /* Sbus2 repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - - if (pad == SF_CTRL_PAD1) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - } else if (pad == SF_CTRL_PAD2) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_PAD_SEL, pad); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl sbus2 revoke replace - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Revoke_replace(void) -{ - uint32_t tmpVal = 0; - - SF_Ctrl_Sbus2_Release_Sram(); - - /* Sbus2 clear repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Sbus2 disable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 clock delay - * - * @param clkDelay: Sbus2 clock delay - * @param rxClkInvert: Sbus2 rx clock invert - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL, rxClkInvert); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (en32BitsAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param None - * - * @return Clock delay value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { - return 0; - } else { - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller clock delay value - * - * @param delay: Clock delay value - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (delay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl get wrap queue value - * - * @param None - * - * @return Wrap queue value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Wrap_Queue_Value(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_Q); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set cmds config - * - * @param cmdsCfg: SF Ctrl cmds config - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_WRAP_MODE(cmdsCfg->cmdsWrapMode)); - CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->cmdsWrapLen)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - if (cmdsCfg->ackLatency) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } - - if (cmdsCfg->cmdsCoreEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } - - if (bank == SF_CTRL_FLASH_BANK1) { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } else { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl pad select - * - * @param sel: Pin select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PIN_SELECT(sel)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) { - /* Single flash mode, disable bank2 */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - - if (sel <= SF_IO_EMB_SWAP_IO2CS) { - /* Select embedded pad1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } else { - /* Select pad2 or pad3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, ((sel&0xf) >> 2)); - } - } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) - ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) { - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl dual flash memory remap set - * - * @param remap: Memory remap set type - * @param lock: Memory remap lock - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_REMAP_TYPE(remap)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP, remap); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl select bank on system bus - * - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank) -{ - /* TODO: sf_if_bk_swap */ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller owner:I/D AHB or system AHB - * - * @param owner: owner type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - /* Set owner */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); - - /* Set iahb to flash interface */ - if (owner == SF_CTRL_OWNER_IAHB) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash controller - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with big indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with little indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES region - * - * @param region: region number - * @param enable: enable or not - * @param hwKey: hardware key or software key - * @param startAddr: region start address - * @param endAddr: region end address - * @param locked: lock this region or not - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, - uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal; - - if (!hwKey) { - regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - } - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_END); - /* sf_aes_end =1 means 1,11,1111,1111 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_END, tmpVal); - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_START); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_START, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - tmpVal -= 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W1_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, (BL_RDWD_FRM_BYTEP(iv))); - tmpVal += 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - tmpVal += 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W2_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - tmpVal -= 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif -#ifndef BFLB_USE_ROM_DRIVER - -/****************************************************************************/ /** - * @brief Set serial flash controller AES mode - * - * @param mode: AES mode select - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_MODE_TYPE(mode)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (mode == SF_CTRL_AES_CTR_MODE) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check is serial flash controller AES enable - * - * @param None - * - * @return Wether AES is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash image offset - * - * @param addrOffset: Address offset value - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET, addrOffset); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET, addrOffset); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Get flash image offset - * - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return :Address offset value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET); - } - } - - return tmpVal; -} -#endif - -/****************************************************************************/ /** - * @brief Lock/unlock sf_id0/sf_id1/sf_bk2_id0/sf_bk2_id1 offset - * - * @param lock: lock or unlock - * - * @return :None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param cfg: Serial flash controller command configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - uint32_t cmdOffset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { - return; - } - - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - /* Clear trigger */ - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Copy command buffer */ - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); - } - - /* Configure cmd */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_CMD_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_CMD_BYTE, 0); - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, 0); - } - - /* Configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, cfg->nbData - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_RW, cfg->rwFlag); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl disable iahb to flash wrap access for XTS mode - * - * @param disable: Disable for 1 and enable for 0 - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable_Wrap_Access(uint8_t disable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (disable) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config SF controller for flash I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config bank2 controller for flash2 I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get SF Ctrl busy state - * - * @param None - * - * @return SET for SF ctrl busy or RESET for SF ctrl not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) -{ - uint32_t tmpVal = 0; - uint32_t cmdOffset = 0; - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_IF_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Controller interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void) -{ - /* TODO: Not implemented */ -} -#endif - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL616_Peripheral_Driver */ diff --git a/drivers/soc/bl616/std/src/bl616_sflash.c b/drivers/soc/bl616/std/src/bl616_sflash.c deleted file mode 100644 index 06fe5f02..00000000 --- a/drivers/soc/bl616/std/src/bl616_sflash.c +++ /dev/null @@ -1,2223 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl616_sflash.h" -#include "bl616_sf_ctrl.h" -#include "bl616_l1c.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLASH - * @{ - */ - -/** @defgroup SFLASH_Private_Macros - * @{ - */ - -/*@} end of group SFLASH_Private_Macros */ - -/** @defgroup SFLASH_Private_Types - * @{ - */ - -/*@} end of group SFLASH_Private_Types */ - -/** @defgroup SFLASH_Private_Variables - * @{ - */ -#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) - -/*@} end of group SFLASH_Private_Variables */ - -/** @defgroup SFLASH_Global_Variables - * @{ - */ - -/*@} end of group SFLASH_Global_Variables */ - -/** @defgroup SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SFLASH_Private_Fun_Declaration */ - -/** @defgroup SFLASH_Private_Functions - * @{ - */ - -/*@} end of group SFLASH_Private_Functions */ - -/** @defgroup SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init serial flash control interface - * - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t clkDelay = 0; - uint8_t rxClkInvert = 0; - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if (pBank2Cfg->bank2DelaySrc) { - clkDelay = pBank2Cfg->bank2ClkDelay; - } else { - if (pSfCtrlCfg != NULL) { - clkDelay = pSfCtrlCfg->clkDelay; - } else { - clkDelay = 1; - } - } - - if (pBank2Cfg->bank2RxClkInvertSrc) { - rxClkInvert = pBank2Cfg->bank2RxClkInvertSel; - } else { - if (pSfCtrlCfg != NULL) { - rxClkInvert = pSfCtrlCfg->rxClkInvert; - } else { - rxClkInvert = 0; - } - } - - SF_Ctrl_Sbus2_Set_Delay(clkDelay, rxClkInvert); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - SF_Ctrl_Bank2_Enable(pBank2Cfg); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - if (pSfCtrlCfg != NULL) { - SF_Ctrl_Enable(pSfCtrlCfg); - } -} -#endif - -/****************************************************************************/ /** - * @brief Set serial flash control interface SPI or QPI mode - * - * @param mode: Serial flash interface mode - * - * @return BFLB_RET:SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) -{ - BL_Err_Type stat = SUCCESS; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register with read command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param readRegCmd: read command - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = readRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register with write command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param writeRegCmd: write command - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = writeRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Check flash busy status - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SET for busy or RESET for not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); - - if ((stat & (1 << flashCfg->busyBit)) == 0) { - return RESET; - } - - return SET; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash write function - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Write enable*/ - flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); - - if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); - } else { - stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); - stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); - } - } else { - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit % 8)); - } else { - stat = flashCfg->qeData; - } - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - stat &= (~(1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex))); - } else { - stat &= (~(1 << (flashCfg->qeBit % 8))); - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash volatile register write enable - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash whole chip - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint32_t timeout = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - timeout = flashCfg->timeCe; - - if ((timeout >> 15) > 0) { - timeout = (timeout & 0x7FFF) * 1000; - } - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > timeout * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one sector - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param secNum: flash sector number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | ((flashCfg->sectorSize * 1024 * secNum) >> 8); - flashCmd.cmdBuf[1] = ((flashCfg->sectorSize * 1024 * secNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeEsector * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 64K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 64K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE64k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash unique ID - * - * @param data: data pointer to store read data - * @param idLen: unique ID len - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = 4; - cmd = 0x4B; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = idLen; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, idLen); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash jedec ID - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = flashCfg->jedecIdCmdDmyClk; - cmd = flashCfg->jedecIdCmd; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 3); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash device ID - * - * @param data: data pointer to store read data - * @param is32BitsAddr: Is flash addr mode in 32-bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t addr = 0x00000001; - uint8_t readMode = 0xFF; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - dummyClks = 2; - cmd = 0x94; - flashCmd.addrSize = 4; - - if (is32BitsAddr) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24) | (readMode << 16); - flashCmd.addrSize++; - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.cmdBuf[1] = (readMode << 24); - } - - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 2; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 2); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash power down - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Powerdown(void) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - uint32_t timeOut = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = 0xB9; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Release flash power down for wake up - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t cmd; - uint32_t timeOut = 0; - - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = flashCfg->releasePowerDown; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Sflash restore from power down - * - * @param pFlashCfg: Flash configuration pointer - * @param flashContRead: Whether enable continuous read - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, - SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat = SUCCESS; - uint32_t jdecId = 0; - uint8_t tmp[8]; - uint8_t ioMode = pFlashCfg->ioMode & 0xf; - - /* Wake flash up from power down */ - SFlash_Release_Powerdown(pFlashCfg); - arch_delay_us(120); - - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - - if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { - SFlash_Qspi_Enable(pFlashCfg); - } - - if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { - /* unwrap */ - L1C_Set_Wrap(DISABLE); - } else { - /* burst wrap */ - L1C_Set_Wrap(ENABLE); - /* For command that is setting register instead of send command, we need write enable */ - SFlash_Write_Enable(pFlashCfg); - SFlash_SetBurstWrap(pFlashCfg); - } - - if (flashContRead) { - stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32, bank); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((flashCfg->ioMode >> 4) & 0x01) == 1) { - /* Disable burst wrap ,just return */ - return; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; - dummyClks = flashCfg->burstWrapCmdDmyClk; - cmd = flashCfg->burstWrapCmd; - wrapData = flashCfg->burstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; - dummyClks = flashCfg->deBurstWrapCmdDmyClk; - cmd = flashCfg->deBurstWrapCmd; - wrapData = flashCfg->deBurstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash 24-bits or 32-bits addr mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - - if ((flashCfg->ioMode & 0x20) == 0) { - return ERROR; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_32bits_Addr_En(en32BitsAddr); - - if (en32BitsAddr) { - cmd = flashCfg->enter32BitsAddrCmd; - } else { - cmd = flashCfg->exit32BitsAddrCmd; - } - - flashCmd.cmdBuf[0] = (cmd << 24); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Software reset flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) -{ - uint16_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset enable */ - flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - /* Wait for write done */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 20) { - return ERROR; - } - } - - SF_Ctrl_SendCmd(&flashCmd); - - /* Reset */ - flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - arch_delay_us(50); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Reset flash continous read mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset continous read */ - ARCH_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = flashCfg->resetCreadCmdSize; - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set I/D bus read flash configuration in flash controller - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: address to read/write - * @param len: data length to read/write - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank) -{ - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmdValid = 1; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /*prepare command**/ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | addr; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = addr; - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; - } - - cmdValid = 0; - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = len; - if (bank == SF_CTRL_FLASH_BANK0) { - SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid); - } else { - SF_Ctrl_Flash2_Read_Icache_Set(&flashCmd, cmdValid); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Enable I/D bus read from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, - uint8_t contRead, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32, bank); - - if (SUCCESS != stat) { - return stat; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Disable read from flash with IDbus - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_IDbus_Read_Disable(void) -{ - //L1C_Cache_Read_Disable(); -} -#endif - -/****************************************************************************/ /** - * @brief Sflash enable RCV mode to recovery for erase while power drop - * - * @param pFlashCfg: Flash configuration pointer - * @param rCmd: Read RCV register cmd - * @param wCmd: Write RCV register cmd - * @param bitPos: RCV register bit pos - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) -{ - BL_Err_Type stat; - uint32_t cnt = 0; - uint32_t tempVal = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) > 0) { - return SUCCESS; - } - - tempVal |= (uint32_t)(1 << bitPos); - stat = SFlash_Write_Enable(pFlashCfg); - - if (SUCCESS != stat) { - stat = ERROR; - } - - stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - return stat; - } - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) <= 0) { - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint32_t cnt = 0; - uint8_t cmd = 0; - uint8_t secOptMode = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = pSecRegCfg->eraseCmd; - flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > pFlashCfg->timeEsector * 3) { - return ERROR; - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Program flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - BL_Err_Type stat; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - cmd = pSecRegCfg->programCmd; - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = 256 - addr % 256; - - if (curLen > len - i) { - curLen = len - i; - } - - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - - /* Prepare command */ - arch_memcpy_fast(flashCtrlBuf, data, curLen); - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > pFlashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash security register one block - * - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - flashCmd.dummyClks = 1; - cmd = pSecRegCfg->readCmd; - - /* Read data */ - for (i = 0; i < len;) { - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - /* Prepare command */ - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - arch_memcpy_fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - - /* Read data */ - for (i = 0; i < len;) { - /* Prepare command */ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] |= (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - arch_memcpy_fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: progran mode:SPI mode or QPI mode - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat; - uint8_t cmd; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - cmd = flashCfg->pageProgramCmd; - } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->qpageProgramCmd; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = flashCfg->pageSize - addr % flashCfg->pageSize; - - if (curLen > len - i) { - curLen = len - i; - } - - /* Prepare command */ - arch_memcpy_fast(flashCtrlBuf, data, curLen); - - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > flashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - return SUCCESS; -} -#endif - - -/****************************************************************************//** - * @brief Clear flash status register - * - * @param flashCfg: Flash configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t ret = 0; - uint32_t qeValue = 0; - uint32_t regValue = 0; - uint32_t readValue = 0; - uint8_t readRegValue0 = 0; - uint8_t readRegValue1 = 0; - - if((flashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (flashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){ - qeValue = 1; - } - - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&readRegValue0, 1); - SFlash_Read_Reg(flashCfg, 1, (uint8_t *)&readRegValue1, 1); - readValue = (readRegValue0|(readRegValue1<<8)); - if ((readValue & (~((1<<(flashCfg->qeIndex*8+flashCfg->qeBit)) | - (1<<(flashCfg->busyIndex*8+flashCfg->busyBit)) | - (1<<(flashCfg->wrEnableIndex*8+flashCfg->wrEnableBit))))) == 0){ - return SUCCESS; - } - - ret = SFlash_Write_Enable(flashCfg); - if (SUCCESS != ret) { - return ERROR; - } - if (flashCfg->qeWriteRegLen == 2) { - regValue = (qeValue<<(flashCfg->qeIndex*8+flashCfg->qeBit)); - SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 2); - } else { - if (flashCfg->qeIndex == 0) { - regValue = (qeValue<qeBit); - } else { - regValue = 0; - } - SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 1); - ret = SFlash_Write_Enable(flashCfg); - if (SUCCESS != ret) { - return ERROR; - } - if (flashCfg->qeIndex == 1) { - regValue = (qeValue<qeBit); - } else { - regValue = 0; - } - SFlash_Write_Reg(flashCfg, 1, (uint8_t *)®Value, 1); - } - return SUCCESS; -} - -/*@} end of group SFLASH_Public_Functions */ - -/*@} end of group SFLASH */ - -/*@} end of group BL616_Peripheral_Driver */ diff --git a/drivers/soc/bl616/std/src/bl616_xip_sflash.c b/drivers/soc/bl616/std/src/bl616_xip_sflash.c deleted file mode 100644 index b915a7ec..00000000 --- a/drivers/soc/bl616/std/src/bl616_xip_sflash.c +++ /dev/null @@ -1,497 +0,0 @@ -/** - ****************************************************************************** - * @file bl616_xip_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl616_xip_sflash.h" - -/** @addtogroup BL616_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Private_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Macros */ - -/** @defgroup XIP_SFLASH_Private_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Types */ - -/** @defgroup XIP_SFLASH_Private_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Variables */ - -/** @defgroup XIP_SFLASH_Global_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Global_Variables */ - -/** @defgroup XIP_SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ - -/** @defgroup XIP_SFLASH_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Save flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* XIP_SFlash_Delay */ - volatile uint32_t i = 32 * 2; - - while (i--) - ; - - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); - /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); - /* Enable 32Bits addr mode again in case reset command make it reset */ - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); - } - /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); - - /* Clear offset setting*/ - *offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Restore flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmp[1]; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank); - - if(((pFlashCfg->ioMode>>4)&0x01) == 0) { - if((pFlashCfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(pFlashCfg); - } - } - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return SUCCESS; -} -#endif - -/*@} end of group XIP_SFLASH_Private_Functions */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase - * @param len: data length to erase - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param pFlashCfg: Flash config pointer - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param pFlashCfg: Flash config pointer - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Jedec ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Jedec ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Device ID - * - * @param pFlashCfg: Flash config pointer - * @param is32BitsAddr: Is flash addr mode in 32-bits - * @param data: data pointer to store Device ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetDeviceId(data, is32BitsAddr); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Unique ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Device ID Read from flash - * @param idLen: Unique id len - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash via XIP - * - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) -{ - uint32_t offset; - - addr = addr & (BL616_FLASH_XIP_END-BL616_FLASH_XIP_BASE-1); - addr |= BL616_FLASH_XIP_BASE; - - offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0); - /* Flash read */ - arch_memcpy_fast(data, (void *)(uintptr_t)(addr - SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0)), len); - SF_Ctrl_Set_Flash_Image_Offset(offset, 0, SF_CTRL_FLASH_BANK0); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief XIP SFlash option save - * - * @param aesEnable: AES enable status pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) -{ - *aesEnable = SF_Ctrl_Is_AES_Enable(); - - if (*aesEnable) { - SF_Ctrl_AES_Disable(); - } -} - -/****************************************************************************/ /** - * @brief XIP SFlash option restore - * - * @param aesEnable: AES enable status - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) -{ - if (aesEnable) { - SF_Ctrl_AES_Enable(); - } -} - -/****************************************************************************//** - * @brief Clear flash status register need lock - * - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; - - stat=XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat=SFlash_Clear_Status_Register(pFlashCfg); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return stat; -} - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL616_Peripheral_Driver */ diff --git a/drivers/soc/bl616/std/startup/interrupt.c b/drivers/soc/bl616/std/startup/interrupt.c index f7087409..a9a4275d 100644 --- a/drivers/soc/bl616/std/startup/interrupt.c +++ b/drivers/soc/bl616/std/startup/interrupt.c @@ -153,7 +153,7 @@ void exception_entry(uintptr_t *regs) printf("%s\r\n", mcause_str[cause & 0xf]); // clang-format off -#ifndef CONFIG_ERR_NOT_DUMP_ALL_REGS +#ifdef CONFIG_TRAP_DUMP_ALL_REGS printf("ra = 0x%08x ", regs[REG_RA]); printf("sp = 0x%08x ", regs[REG_SP]); printf("gp = 0x%08x ", regs[REG_GP]); printf("tp = 0x%08x ", regs[REG_TP]); printf("\n\r"); diff --git a/drivers/soc/bl702/std/CMakeLists.txt b/drivers/soc/bl702/std/CMakeLists.txt index 4a91585c..e45dcbb8 100644 --- a/drivers/soc/bl702/std/CMakeLists.txt +++ b/drivers/soc/bl702/std/CMakeLists.txt @@ -19,18 +19,11 @@ sdk_library_add_sources(src/bl702_hbn.c) sdk_library_add_sources(src/bl702_l1c.c) sdk_library_add_sources(src/bl702_pds.c) -sdk_library_add_sources(src/bl702_sf_cfg.c) -sdk_library_add_sources(src/bl702_sf_cfg_ext.c) -sdk_library_add_sources(src/bl702_sf_ctrl.c) -sdk_library_add_sources(src/bl702_sflash.c) sdk_library_add_sources(src/bl702_sflash_ext.c) -sdk_library_add_sources(src/bl702_xip_sflash.c) sdk_library_add_sources(src/bl702_xip_sflash_ext.c) - -sdk_library_add_sources(src/bl702_psram.c) +sdk_library_add_sources(src/bl702_sf_cfg_ext.c) sdk_library_add_sources(port/bl702_clock.c) -sdk_library_add_sources(port/bl702_flash.c) sdk_add_include_directories( include diff --git a/drivers/soc/bl702/std/include/bl702_glb.h b/drivers/soc/bl702/std/include/bl702_glb.h index 303e9518..c26d60d9 100644 --- a/drivers/soc/bl702/std/include/bl702_glb.h +++ b/drivers/soc/bl702/std/include/bl702_glb.h @@ -41,12 +41,12 @@ #include "bl702_gpio.h" #include "bl702_l1c.h" #include "bl702_hbn.h" -#include "bl702_sf_ctrl.h" -#include "bl702_sf_cfg.h" #include "bl702_aon.h" #include "bl702_ef_ctrl.h" #include "bl702_pds.h" #include "bl702_common.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" /** @addtogroup BL702_Peripheral_Driver * @{ diff --git a/drivers/soc/bl702/std/include/bl702_hbn.h b/drivers/soc/bl702/std/include/bl702_hbn.h index 276e2a8e..90760bb1 100644 --- a/drivers/soc/bl702/std/include/bl702_hbn.h +++ b/drivers/soc/bl702/std/include/bl702_hbn.h @@ -38,8 +38,8 @@ #include "hbn_reg.h" #include "bl702_aon.h" -#include "bl702_sflash.h" #include "bl702_common.h" +#include "bflb_sflash.h" /** @addtogroup BL702_Peripheral_Driver * @{ @@ -272,7 +272,7 @@ typedef struct uint32_t sleepTime; /*!< HBN sleep time */ uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ uint8_t flashPinCfg; /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */ HBN_LEVEL_Type hbnLevel; /*!< HBN level */ HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ @@ -469,7 +469,7 @@ void HBN_OUT1_IRQHandler(void); #endif /*----------*/ void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); -void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg); void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel); BL_Err_Type HBN_Reset(void); BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv); diff --git a/drivers/soc/bl702/std/include/bl702_pds.h b/drivers/soc/bl702/std/include/bl702_pds.h index 8d3a1c2e..f6ab168c 100644 --- a/drivers/soc/bl702/std/include/bl702_pds.h +++ b/drivers/soc/bl702/std/include/bl702_pds.h @@ -40,8 +40,8 @@ #include "bl702_ef_ctrl.h" #include "bl702_aon.h" #include "bl702_hbn.h" -#include "bl702_sflash.h" #include "bl702_common.h" +#include "bflb_sflash.h" /** @addtogroup BL702_Peripheral_Driver * @{ @@ -435,7 +435,7 @@ typedef struct uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ uint8_t flashContRead; /*!< Whether enable flash continue read */ uint32_t sleepTime; /*!< PDS sleep time */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ void (*preCbFun)(void); /*!< Pre callback function */ void (*postCbFun)(void); /*!< Post callback function */ diff --git a/drivers/soc/bl702/std/include/bl702_psram.h b/drivers/soc/bl702/std/include/bl702_psram.h deleted file mode 100644 index 5f9a78b1..00000000 --- a/drivers/soc/bl702/std/include/bl702_psram.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_psram.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL702_PSRAM_H__ -#define __BL702_PSRAM_H__ - -#include "sf_ctrl_reg.h" -#include "bl702_common.h" -#include "bl702_sf_ctrl.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup PSRAM - * @{ - */ - -/** @defgroup PSRAM_Public_Types - * @{ - */ - -/** - * @brief Psram drive strength type definition - */ -typedef enum { - PSRAM_DRIVE_STRENGTH_50_OHMS, /*!< Drive strength 50 ohms(default) */ - PSRAM_DRIVE_STRENGTH_100_OHMS, /*!< Drive strength 100 ohms */ - PSRAM_DRIVE_STRENGTH_200_OHMS, /*!< Drive strength 200 ohms */ -} PSRAM_Drive_Strength; - -/** - * @brief Psram burst length size type definition - */ -typedef enum { - PSRAM_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */ - PSRAM_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */ - PSRAM_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */ - PSRAM_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 bytes(default) */ -} PSRAM_Burst_Length; - -/** - * @brief Psram ctrl mode type definition - */ -typedef enum { - PSRAM_SPI_CTRL_MODE, /*!< Psram SPI ctrl mode */ - PSRAM_QPI_CTRL_MODE, /*!< Psram QPI ctrl mode */ -} PSRAM_Ctrl_Mode; - -/** - * @brief Psram ctrl configuration structure type definition - */ -typedef struct -{ - uint8_t readIdCmd; /*!< Read ID command */ - uint8_t readIdDmyClk; /*!< Read ID command dummy clock */ - uint8_t burstToggleCmd; /*!< Burst toggle length command */ - uint8_t resetEnableCmd; /*!< Psram reset enable command */ - uint8_t resetCmd; /*!< Psram reset command */ - uint8_t enterQuadModeCmd; /*!< Psram enter quad mode command */ - uint8_t exitQuadModeCmd; /*!< Psram exit quad mode command */ - uint8_t readRegCmd; /*!< Read register command */ - uint8_t readRegDmyClk; /*!< Read register command dummy clock */ - uint8_t writeRegCmd; /*!< Write register command */ - uint8_t readCmd; /*!< Psram read command */ - uint8_t readDmyClk; /*!< Psram read command dummy clock */ - uint8_t fReadCmd; /*!< Psram fast read command */ - uint8_t fReadDmyClk; /*!< Psram fast read command dummy clock */ - uint8_t fReadQuadCmd; /*!< Psram fast read quad command */ - uint8_t fReadQuadDmyClk; /*!< Psram fast read quad command dummy clock */ - uint8_t writeCmd; /*!< Psram write command */ - uint8_t quadWriteCmd; /*!< Psram quad write command */ - uint16_t pageSize; /*!< Psram page size */ - PSRAM_Ctrl_Mode ctrlMode; /*!< Psram ctrl mode */ - PSRAM_Drive_Strength driveStrength; /*!< Psram drive strength */ - PSRAM_Burst_Length burstLength; /*!< Psram burst length size */ -} SPI_Psram_Cfg_Type; - -/*@} end of group PSRAM_Public_Types */ - -/** @defgroup PSRAM_Public_Constants - * @{ - */ - -/** @defgroup PSRAM_DRIVE_STRENGTH - * @{ - */ -#define IS_PSRAM_DRIVE_STRENGTH(type) (((type) == PSRAM_DRIVE_STRENGTH_50_OHMS) || \ - ((type) == PSRAM_DRIVE_STRENGTH_100_OHMS) || \ - ((type) == PSRAM_DRIVE_STRENGTH_200_OHMS)) - -/** @defgroup PSRAM_BURST_LENGTH - * @{ - */ -#define IS_PSRAM_BURST_LENGTH(type) (((type) == PSRAM_BURST_LENGTH_16_BYTES) || \ - ((type) == PSRAM_BURST_LENGTH_32_BYTES) || \ - ((type) == PSRAM_BURST_LENGTH_64_BYTES) || \ - ((type) == PSRAM_BURST_LENGTH_512_BYTES)) - -/** @defgroup PSRAM_CTRL_MODE - * @{ - */ -#define IS_PSRAM_CTRL_MODE(type) (((type) == PSRAM_SPI_CTRL_MODE) || \ - ((type) == PSRAM_QPI_CTRL_MODE)) - -/*@} end of group PSRAM_Public_Constants */ - -/** @defgroup PSRAM_Public_Macros - * @{ - */ - -/*@} end of group PSRAM_Public_Macros */ - -/** @defgroup PSRAM_Public_Functions - * @{ - */ - -/** - * @brief PSRAM Functions - */ -void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg); -void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue); -void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue); -BL_Err_Type Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg); -BL_Err_Type Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg); -void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data); -BL_Err_Type Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg); -BL_Err_Type Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg); -BL_Err_Type Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode); -BL_Err_Type Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode); -BL_Err_Type Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len); -BL_Err_Type Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, - BL_Fun_Type wbEn, BL_Fun_Type waEn); -BL_Err_Type Psram_Write(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type Psram_Read(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); - -/*@} end of group PSRAM_Public_Functions */ - -/*@} end of group PSRAM */ - -/*@} end of group BL702_Peripheral_Driver */ - -#endif /* __BL702_PSRAM_H__ */ diff --git a/drivers/soc/bl702/std/include/bl702_romdriver.h b/drivers/soc/bl702/std/include/bl702_romdriver.h index 84723d12..f1971fff 100644 --- a/drivers/soc/bl702/std/include/bl702_romdriver.h +++ b/drivers/soc/bl702/std/include/bl702_romdriver.h @@ -40,10 +40,10 @@ #include "bl702_aon.h" #include "bl702_glb.h" #include "bl702_hbn.h" -#include "bl702_xip_sflash.h" -#include "bl702_sflash.h" -#include "bl702_sf_ctrl.h" -#include "bl702_psram.h" +#include "bflb_spi_psram.h" +#include "bflb_xip_sflash.h" +#include "bflb_sflash.h" +#include "bflb_sf_ctrl.h" // #include "softcrc.h" #define ROMAPI_INDEX_SECT_SIZE (0x800) @@ -406,92 +406,92 @@ typedef enum { ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel]) #define RomDriver_XIP_SFlash_State_Save \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save]) #define RomDriver_XIP_SFlash_State_Restore \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore]) #define RomDriver_XIP_SFlash_Erase_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock]) #define RomDriver_XIP_SFlash_Write_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock]) #define RomDriver_XIP_SFlash_Read_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock]) #define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock]) #define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock]) #define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock]) #define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \ - ((BL_Err_Type(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) + ((int(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock]) #define RomDriver_XIP_SFlash_Read_With_Lock \ - ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * dst, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock]) + ((int (*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * dst, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock]) #define RomDriver_XIP_SFlash_Write_With_Lock \ - ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * src, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock]) + ((int (*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * src, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock]) #define RomDriver_XIP_SFlash_Erase_With_Lock \ - ((int (*)(SPI_Flash_Cfg_Type * pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock]) + ((int (*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock]) #define RomDriver_SFlash_Init \ - ((void (*)(const SF_Ctrl_Cfg_Type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) + ((void (*)(const struct sf_ctrl_cfg_type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init]) #define RomDriver_SFlash_SetSPIMode \ - ((BL_Err_Type(*)(SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) + ((int(*)(uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode]) #define RomDriver_SFlash_Read_Reg \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg]) #define RomDriver_SFlash_Write_Reg \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg]) #define RomDriver_SFlash_Read_Reg_With_Cmd \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd]) #define RomDriver_SFlash_Write_Reg_With_Cmd \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd]) #define RomDriver_SFlash_Busy \ - ((BL_Sts_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy]) #define RomDriver_SFlash_Write_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable]) #define RomDriver_SFlash_Qspi_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable]) #define RomDriver_SFlash_Volatile_Reg_Write_Enable \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]) #define RomDriver_SFlash_Chip_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase]) #define RomDriver_SFlash_Sector_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase]) #define RomDriver_SFlash_Blk32_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase]) #define RomDriver_SFlash_Blk64_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase]) #define RomDriver_SFlash_Erase \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase]) #define RomDriver_SFlash_Program \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program]) #define RomDriver_SFlash_GetUniqueId \ ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId]) #define RomDriver_SFlash_GetJedecId \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) + ((void (*)(spi_flash_cfg_type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId]) #define RomDriver_SFlash_GetDeviceId \ ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId]) #define RomDriver_SFlash_Powerdown \ ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown]) #define RomDriver_SFlash_Releae_Powerdown \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown]) #define RomDriver_SFlash_Restore_From_Powerdown \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) + ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t flashcont_read)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown]) #define RomDriver_SFlash_SetBurstWrap \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap]) #define RomDriver_SFlash_DisableBurstWrap \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap]) #define RomDriver_SFlash_Software_Reset \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) + ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset]) #define RomDriver_SFlash_Reset_Continue_Read \ - ((void (*)(SPI_Flash_Cfg_Type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) + ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read]) #define RomDriver_SFlash_Set_IDbus_Cfg \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg]) #define RomDriver_SFlash_IDbus_Read_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable]) #define RomDriver_SFlash_Cache_Read_Enable \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable]) #define RomDriver_SFlash_Cache_Read_Disable \ ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable]) #define RomDriver_SFlash_Read \ - ((BL_Err_Type(*)(SPI_Flash_Cfg_Type * flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) + ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read]) #define RomDriver_L1C_Cache_Enable_Set \ ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Enable_Set]) @@ -513,23 +513,23 @@ typedef enum { ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set]) #define RomDriver_SF_Ctrl_Enable \ - ((void (*)(const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) + ((void (*)(const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable]) #define RomDriver_SF_Ctrl_Psram_Init \ - ((void (*)(SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Init]) + ((void (*)(struct sf_ctrl_psram_cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Init]) #define RomDriver_SF_Ctrl_Get_Clock_Delay \ ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay]) #define RomDriver_SF_Ctrl_Set_Clock_Delay \ ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay]) #define RomDriver_SF_Ctrl_Cmds_Set \ - ((void (*)(SF_Ctrl_Cmds_Cfg * cmdsCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set]) + ((void (*)(struct sf_ctrl_cmds_cfg * cmdsCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set]) #define RomDriver_SF_Ctrl_Set_Owner \ - ((void (*)(SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) + ((void (*)(uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner]) #define RomDriver_SF_Ctrl_Disable \ ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable]) #define RomDriver_SF_Ctrl_Select_Pad \ - ((void (*)(SF_Ctrl_Pad_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) + ((void (*)(uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad]) #define RomDriver_SF_Ctrl_Select_Bank \ - ((void (*)(SF_Ctrl_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Bank]) + ((void (*)(uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Bank]) #define RomDriver_SF_Ctrl_AES_Enable_BE \ ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE]) #define RomDriver_SF_Ctrl_AES_Enable_LE \ @@ -537,9 +537,9 @@ typedef enum { #define RomDriver_SF_Ctrl_AES_Set_Region \ ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region]) #define RomDriver_SF_Ctrl_AES_Set_Key \ - ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) + ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key]) #define RomDriver_SF_Ctrl_AES_Set_Key_BE \ - ((void (*)(uint8_t region, uint8_t * key, SF_Ctrl_AES_Key_Type keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) + ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE]) #define RomDriver_SF_Ctrl_AES_Set_IV \ ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV]) #define RomDriver_SF_Ctrl_AES_Set_IV_BE \ @@ -555,56 +555,56 @@ typedef enum { #define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \ ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset]) #define RomDriver_SF_Ctrl_Select_Clock \ - ((void (*)(SF_Ctrl_Sahb_Type sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) + ((void (*)(uint8_t sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock]) #define RomDriver_SF_Ctrl_SendCmd \ - ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) + ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd]) #define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \ - ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]) + ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set]) #define RomDriver_SF_Ctrl_Psram_Write_Icache_Set \ - ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set]) + ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set]) #define RomDriver_SF_Ctrl_Psram_Read_Icache_Set \ - ((void (*)(SF_Ctrl_Cmd_Cfg_Type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set]) + ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set]) #define RomDriver_SF_Ctrl_GetBusyState \ ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState]) #define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \ - ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) + ((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]) #define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \ ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]) #define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \ - ((BL_Err_Type(*)(uint32_t flashID, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) + ((BL_Err_Type(*)(uint32_t flashID, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]) #define RomDriver_SF_Cfg_Init_Flash_Gpio \ ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]) #define RomDriver_SF_Cfg_Flash_Identify \ - ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) + ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify]) #define RomDriver_Psram_Init \ - ((void (*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_Cmds_Cfg * cmdsCfg, SF_Ctrl_Psram_Cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_Init]) + ((void (*)(struct spi_psram_cfg_type * psramCfg, struct sf_ctrl_cmds_cfg * cmdsCfg, struct sf_ctrl_psram_cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_Init]) #define RomDriver_Psram_ReadReg \ - ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadReg]) + ((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadReg]) #define RomDriver_Psram_WriteReg \ - ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_WriteReg]) + ((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_WriteReg]) #define RomDriver_Psram_SetDriveStrength \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetDriveStrength]) + ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetDriveStrength]) #define RomDriver_Psram_SetBurstWrap \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetBurstWrap]) + ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetBurstWrap]) #define RomDriver_Psram_ReadId \ - ((void (*)(SPI_Psram_Cfg_Type * psramCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadId]) + ((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadId]) #define RomDriver_Psram_EnterQuadMode \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_EnterQuadMode]) + ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_EnterQuadMode]) #define RomDriver_Psram_ExitQuadMode \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_ExitQuadMode]) + ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_ExitQuadMode]) #define RomDriver_Psram_ToggleBurstLength \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_ToggleBurstLength]) + ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_ToggleBurstLength]) #define RomDriver_Psram_SoftwareReset \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, PSRAM_Ctrl_Mode ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_SoftwareReset]) + ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_SoftwareReset]) #define RomDriver_Psram_Set_IDbus_Cfg \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Set_IDbus_Cfg]) + ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Set_IDbus_Cfg]) #define RomDriver_Psram_Cache_Write_Set \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)) ROM_APITABLE[ROM_API_INDEX_Psram_Cache_Write_Set]) + ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint8_t wtEn, uint8_t wbEn, uint8_t waEn)) ROM_APITABLE[ROM_API_INDEX_Psram_Cache_Write_Set]) #define RomDriver_Psram_Write \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Write]) + ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Write]) #define RomDriver_Psram_Read \ - ((BL_Err_Type(*)(SPI_Psram_Cfg_Type * psramCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Read]) + ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Read]) /*@} end of group ROMDRIVER_Public_Types */ /** @defgroup ROMDRIVER_Public_Constants diff --git a/drivers/soc/bl702/std/include/bl702_sf_cfg.h b/drivers/soc/bl702/std/include/bl702_sf_cfg.h deleted file mode 100644 index 5c050373..00000000 --- a/drivers/soc/bl702/std/include/bl702_sf_cfg.h +++ /dev/null @@ -1,125 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_sf_cfg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL702_SF_CFG_H__ -#define __BL702_SF_CFG_H__ - -#include "string.h" -#include "bl702_sflash.h" -#include "bl702_sf_ctrl.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Public_Types - * @{ - */ - -/*@} end of group SF_CFG_Public_Types */ - -/** @defgroup SF_CFG_Public_Constants - * @{ - */ - -/*@} end of group SF_CFG_Public_Constants */ - -/** @defgroup SF_CFG_Public_Macros - * @{ - */ -/* Flash option 0 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_21 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_19 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_17 -#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_18 -#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_22 -#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_20 -/* Flash option 1 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK1_GPIO GLB_GPIO_PIN_27 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS1_GPIO GLB_GPIO_PIN_25 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA01_GPIO GLB_GPIO_PIN_28 -#define BFLB_EXTFLASH_DATA11_GPIO GLB_GPIO_PIN_24 -#define BFLB_EXTFLASH_DATA21_GPIO GLB_GPIO_PIN_23 -#define BFLB_EXTFLASH_DATA31_GPIO GLB_GPIO_PIN_26 -/* Flash option 2 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK2_GPIO 38 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS2_GPIO 38 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA02_GPIO 38 -#define BFLB_EXTFLASH_DATA12_GPIO 38 -#define BFLB_EXTFLASH_DATA22_GPIO 38 -#define BFLB_EXTFLASH_DATA32_GPIO 38 -#define BFLB_FLASH_CFG_SF2_EXT_23_28 0 -#define BFLB_FLASH_CFG_SF2_INT_512K 1 -#define BFLB_FLASH_CFG_SF2_INT_1M 2 -#define BFLB_FLASH_CFG_SF1_EXT_17_22 3 -#define BFLB_SF2_SWAP_NONE 0 -#define BFLB_SF2_SWAP_CS_IO2 1 -#define BFLB_SF2_SWAP_IO0_IO3 2 -#define BFLB_SF2_SWAP_BOTH 3 -#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 -#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF - -/*@} end of group SF_CFG_Public_Macros */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); -void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault); -uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg); -void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); -void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL702_Peripheral_Driver */ - -#endif /* __BL702_SF_CFG_H__ */ diff --git a/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h b/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h index e1666d72..0cab7d12 100644 --- a/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h +++ b/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h @@ -37,8 +37,8 @@ #define __BL702_SF_CFG_EXT_H__ #include "string.h" -#include "bl702_sflash.h" -#include "bl702_sf_ctrl.h" +#include "bflb_sflash.h" +#include "bflb_sf_ctrl.h" /** @addtogroup BL702_Peripheral_Driver * @{ @@ -69,10 +69,11 @@ /** @defgroup SF_CFG_EXT_Public_Functions * @{ */ -void SF_Cfg_Init_Internal_Flash_Gpio(void); -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg); -uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg); +void bflb_sf_cfg_init_internal_flash_gpio(void); +int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank); +uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, + spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank); /*@} end of group SF_CFG_EXT_Public_Functions */ diff --git a/drivers/soc/bl702/std/include/bl702_sf_ctrl.h b/drivers/soc/bl702/std/include/bl702_sf_ctrl.h deleted file mode 100644 index 756e2600..00000000 --- a/drivers/soc/bl702/std/include/bl702_sf_ctrl.h +++ /dev/null @@ -1,410 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_sf_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL702_SF_CTRL_H__ -#define __BL702_SF_CTRL_H__ - -#include "sf_ctrl_reg.h" -#include "bl702_common.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Serial flash pad select type definition - */ -typedef enum { - SF_CTRL_PAD_SEL_SF1, /*!< SF Ctrl pad select sf1, flash use GPIO 17-22, no psram */ - SF_CTRL_PAD_SEL_SF2, /*!< SF Ctrl pad select sf2, flash use GPIO 23-28, no psram, embedded flash */ - SF_CTRL_PAD_SEL_SF3, /*!< SF Ctrl pad select sf3, flash use GPIO 32-37, no psram */ - SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2, /*!< SF Ctrl pad select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */ - SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3, /*!< SF Ctrl pad select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */ - SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1, /*!< SF Ctrl pad select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */ - SF_CTRL_PAD_SEL_DUAL_CS_SF2, /*!< SF Ctrl pad select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */ - SF_CTRL_PAD_SEL_DUAL_CS_SF3, /*!< SF Ctrl pad select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */ -} SF_Ctrl_Pad_Select; - -/** - * @brief Serial flash system bus control type definition - */ -typedef enum { - SF_CTRL_SEL_FLASH, /*!< SF Ctrl system bus control flash */ - SF_CTRL_SEL_PSRAM, /*!< SF Ctrl system bus control psram */ -} SF_Ctrl_Select; - -/** - * @brief Serail flash controller wrap mode len type definition - */ -typedef enum { - SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */ - SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */ - SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */ - SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */ - SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */ - SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */ - SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */ - SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */ - SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */ - SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */ -} SF_Ctrl_Wrap_Len_Type; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ - SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ -} SF_Ctrl_Owner_Type; - -/** - * @brief Serial flash controller select clock type definition - */ -typedef enum { - SF_CTRL_SAHB_CLOCK, /*!< Serial flash controller select default sahb clock */ - SF_CTRL_FLASH_CLOCK, /*!< Serial flash controller select flash clock */ -} SF_Ctrl_Sahb_Type; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - HIGH_SPEED_MODE_CLOCK, /*!< Serial flash controller high speed mode clk_ahb>clk_sf */ - REMOVE_CLOCK_CONSTRAIN, /*!< Serial flash controller remove clock constrain */ -} SF_Ctrl_Ahb2sif_Type; - -/** - * @brief Read and write type definition - */ -typedef enum { - SF_CTRL_READ, /*!< Serail flash read command flag */ - SF_CTRL_WRITE, /*!< Serail flash write command flag */ -} SF_Ctrl_RW_Type; - -/** - * @brief Serail flash interface IO type definition - */ -typedef enum { - SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ - SF_CTRL_DO_MODE, /*!< Dual Output mode define */ - SF_CTRL_QO_MODE, /*!< Quad Output mode define */ - SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ - SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ -} SF_Ctrl_IO_Type; - -/** - * @brief Serail flash controller interface mode type definition - */ -typedef enum { - SF_CTRL_SPI_MODE, /*!< SPI mode define */ - SF_CTRL_QPI_MODE, /*!< QPI mode define */ -} SF_Ctrl_Mode_Type; - -/** - * @brief Serail flash controller command mode type definition - */ -typedef enum { - SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ - SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ -} SF_Ctrl_Cmd_Mode_Type; - -/** - * @brief Serail flash controller address mode type definition - */ -typedef enum { - SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ - SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ - SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ -} SF_Ctrl_Addr_Mode_Type; - -/** - * @brief Serail flash controller dummy mode type definition - */ -typedef enum { - SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ - SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ - SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ -} SF_Ctrl_Dmy_Mode_Type; - -/** - * @brief Serail flash controller data mode type definition - */ -typedef enum { - SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ - SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ - SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ -} SF_Ctrl_Data_Mode_Type; - -/** - * @brief Serail flash controller AES type definition - */ -typedef enum { - SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ - SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ - SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ - SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ -} SF_Ctrl_AES_Key_Type; - -/** - * @brief Serail flash controller configuration structure type definition - */ -typedef struct -{ - SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ - SF_Ctrl_Sahb_Type sahbClock; /*!< Sflash clock sahb sram select */ - SF_Ctrl_Ahb2sif_Type ahb2sifMode; /*!< Sflash ahb2sif mode */ - uint8_t clkDelay; /*!< Clock count for read due to pad delay */ - uint8_t clkInvert; /*!< Clock invert */ - uint8_t rxClkInvert; /*!< RX clock invert */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ -} SF_Ctrl_Cfg_Type; - -/** - * @brief SF Ctrl psram controller configuration structure type definition - */ -typedef struct -{ - SF_Ctrl_Owner_Type owner; /*!< Psram interface bus owner */ - SF_Ctrl_Pad_Select padSel; /*!< SF Ctrl pad select */ - SF_Ctrl_Select bankSel; /*!< SF Ctrl bank select */ - BL_Fun_Type psramRxClkInvertSrc; /*!< Select psram rx clock invert source */ - BL_Fun_Type psramRxClkInvertSel; /*!< Select inveted psram rx clock */ - BL_Fun_Type psramDelaySrc; /*!< Select psram read delay source */ - uint8_t psramClkDelay; /*!< Psram read delay cycle = n + 1 */ -} SF_Ctrl_Psram_Cfg; - -/** - * @brief SF Ctrl cmds configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */ - BL_Fun_Type burstToggleEn; /*!< SF Ctrl burst toggle mode enable */ - BL_Fun_Type wrapModeEn; /*!< SF Ctrl wrap mode cmd enable */ - SF_Ctrl_Wrap_Len_Type wrapLen; /*!< SF Ctrl wrap length */ -} SF_Ctrl_Cmds_Cfg; - -/** - * @brief Serail flash command configuration structure type definition - */ -typedef struct -{ - uint8_t rwFlag; /*!< Read write flag */ - SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ - SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ - uint8_t addrSize; /*!< Address size */ - uint8_t dummyClks; /*!< Dummy clocks */ - SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ - SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ - uint8_t rsv[1]; /*!< */ - uint32_t nbData; /*!< Transfer number of bytes */ - uint32_t cmdBuf[2]; /*!< Command buffer */ -} SF_Ctrl_Cmd_Cfg_Type; - -/*@} end of group SF_CTRL_Public_Types */ - -/** @defgroup SF_CTRL_Public_Constants - * @{ - */ - -/** @defgroup SF_CTRL_PAD_SELECT - * @{ - */ -#define IS_SF_CTRL_PAD_SELECT(type) (((type) == SF_CTRL_PAD_SEL_SF1) || \ - ((type) == SF_CTRL_PAD_SEL_SF2) || \ - ((type) == SF_CTRL_PAD_SEL_SF3) || \ - ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2) || \ - ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF2_SF3) || \ - ((type) == SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) || \ - ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF2) || \ - ((type) == SF_CTRL_PAD_SEL_DUAL_CS_SF3)) - -/** @defgroup SF_CTRL_SELECT - * @{ - */ -#define IS_SF_CTRL_SELECT(type) (((type) == SF_CTRL_SEL_FLASH) || \ - ((type) == SF_CTRL_SEL_PSRAM)) - -/** @defgroup SF_CTRL_WRAP_LEN_TYPE - * @{ - */ -#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \ - ((type) == SF_CTRL_WRAP_LEN_16) || \ - ((type) == SF_CTRL_WRAP_LEN_32) || \ - ((type) == SF_CTRL_WRAP_LEN_64) || \ - ((type) == SF_CTRL_WRAP_LEN_128) || \ - ((type) == SF_CTRL_WRAP_LEN_256) || \ - ((type) == SF_CTRL_WRAP_LEN_512) || \ - ((type) == SF_CTRL_WRAP_LEN_1024) || \ - ((type) == SF_CTRL_WRAP_LEN_2048) || \ - ((type) == SF_CTRL_WRAP_LEN_4096)) - -/** @defgroup SF_CTRL_OWNER_TYPE - * @{ - */ -#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ - ((type) == SF_CTRL_OWNER_IAHB)) - -/** @defgroup SF_CTRL_SAHB_TYPE - * @{ - */ -#define IS_SF_CTRL_SAHB_TYPE(type) (((type) == SF_CTRL_SAHB_CLOCK) || \ - ((type) == SF_CTRL_FLASH_CLOCK)) - -/** @defgroup SF_CTRL_AHB2SIF_TYPE - * @{ - */ -#define IS_SF_CTRL_AHB2SIF_TYPE(type) (((type) == HIGH_SPEED_MODE_CLOCK) || \ - ((type) == REMOVE_CLOCK_CONSTRAIN)) - -/** @defgroup SF_CTRL_RW_TYPE - * @{ - */ -#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ - ((type) == SF_CTRL_WRITE)) - -/** @defgroup SF_CTRL_IO_TYPE - * @{ - */ -#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ - ((type) == SF_CTRL_DO_MODE) || \ - ((type) == SF_CTRL_QO_MODE) || \ - ((type) == SF_CTRL_DIO_MODE) || \ - ((type) == SF_CTRL_QIO_MODE)) - -/** @defgroup SF_CTRL_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ - ((type) == SF_CTRL_QPI_MODE)) - -/** @defgroup SF_CTRL_CMD_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ - ((type) == SF_CTRL_CMD_4_LINES)) - -/** @defgroup SF_CTRL_ADDR_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ - ((type) == SF_CTRL_ADDR_2_LINES) || \ - ((type) == SF_CTRL_ADDR_4_LINES)) - -/** @defgroup SF_CTRL_DMY_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ - ((type) == SF_CTRL_DUMMY_2_LINES) || \ - ((type) == SF_CTRL_DUMMY_4_LINES)) - -/** @defgroup SF_CTRL_DATA_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ - ((type) == SF_CTRL_DATA_2_LINES) || \ - ((type) == SF_CTRL_DATA_4_LINES)) - -/** @defgroup SF_CTRL_AES_KEY_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ - ((type) == SF_CTRL_AES_256BITS) || \ - ((type) == SF_CTRL_AES_192BITS) || \ - ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) - -/*@} end of group SF_CTRL_Public_Constants */ - -/** @defgroup SF_CTRL_Public_Macros - * @{ - */ -#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF -#define FLASH_CTRL_BUF_SIZE 256 - -/*@} end of group SF_CTRL_Public_Macros */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void); -#endif -void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); -void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *psramCfg); -uint8_t SF_Ctrl_Get_Clock_Delay(void); -void SF_Ctrl_Set_Clock_Delay(uint8_t delay); -void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg); -void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel); -void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel); -void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); -void SF_Ctrl_Disable(void); -void SF_Ctrl_AES_Enable_BE(void); -void SF_Ctrl_AES_Enable_LE(void); -void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, - uint32_t endAddr, - uint8_t locked); -void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Enable(void); -void SF_Ctrl_AES_Disable(void); -uint8_t SF_Ctrl_Is_AES_Enable(void); -void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset); -uint32_t SF_Ctrl_Get_Flash_Image_Offset(void); -void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType); -void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); -void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -BL_Sts_Type SF_Ctrl_GetBusyState(void); - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL702_Peripheral_Driver */ - -#endif /* __BL702_SF_CTRL_H__ */ diff --git a/drivers/soc/bl702/std/include/bl702_sflash.h b/drivers/soc/bl702/std/include/bl702_sflash.h deleted file mode 100644 index a907b4d2..00000000 --- a/drivers/soc/bl702/std/include/bl702_sflash.h +++ /dev/null @@ -1,197 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_sflah.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL702_SFLAH_H__ -#define __BL702_SFLAH_H__ - -#include "bl702_common.h" -#include "bl702_sf_ctrl.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLAH - * @{ - */ - -/** @defgroup SFLAH_Public_Types - * @{ - */ - -/** - * @brief Serial flash configuration structure type definition - */ -typedef struct -{ - uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */ - uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - uint8_t resetEnCmd; /*!< Flash enable reset command */ - uint8_t resetCmd; /*!< Flash reset command */ - uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ - uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ - uint8_t jedecIdCmd; /*!< JEDEC ID command */ - uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ - uint8_t qpiJedecIdCmd; /*!< QPI JEDEC ID comamnd */ - uint8_t qpiJedecIdCmdDmyClk; /*!< QPI JEDEC ID command dummy clock */ - uint8_t sectorSize; /*!< *1024bytes */ - uint8_t mid; /*!< Manufacturer ID */ - uint16_t pageSize; /*!< Page size */ - uint8_t chipEraseCmd; /*!< Chip erase cmd */ - uint8_t sectorEraseCmd; /*!< Sector erase command */ - uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ - uint8_t blk64EraseCmd; /*!< Block 64K erase command */ - uint8_t writeEnableCmd; /*!< Need before every erase or program */ - uint8_t pageProgramCmd; /*!< Page program cmd */ - uint8_t qpageProgramCmd; /*!< QIO page program cmd */ - uint8_t qppAddrMode; /*!< QIO page program address mode */ - uint8_t fastReadCmd; /*!< Fast read command */ - uint8_t frDmyClk; /*!< Fast read command dummy clock */ - uint8_t qpiFastReadCmd; /*!< QPI fast read command */ - uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ - uint8_t fastReadDoCmd; /*!< Fast read dual output command */ - uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ - uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ - uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ - uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ - uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ - uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ - uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ - uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ - uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ - uint8_t qpiPageProgramCmd; /*!< QPI program command */ - uint8_t writeVregEnableCmd; /*!< Enable write reg */ - uint8_t wrEnableIndex; /*!< Write enable register index */ - uint8_t qeIndex; /*!< Quad mode enable register index */ - uint8_t busyIndex; /*!< Busy status register index */ - uint8_t wrEnableBit; /*!< Write enable bit pos */ - uint8_t qeBit; /*!< Quad enable bit pos */ - uint8_t busyBit; /*!< Busy status bit pos */ - uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ - uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ - uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ - uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ - uint8_t releasePowerDown; /*!< Release power down command */ - uint8_t busyReadRegLen; /*!< Register length of contain busy status */ - uint8_t readRegCmd[4]; /*!< Read register command buffer */ - uint8_t writeRegCmd[4]; /*!< Write register command buffer */ - uint8_t enterQpi; /*!< Enter qpi command */ - uint8_t exitQpi; /*!< Exit qpi command */ - uint8_t cReadMode; /*!< Config data for continuous read mode */ - uint8_t cRExit; /*!< Config data for exit continuous read mode */ - uint8_t burstWrapCmd; /*!< Enable burst wrap command */ - uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ - uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t burstWrapData; /*!< Data to enable burst wrap */ - uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ - uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ - uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ - uint16_t timeEsector; /*!< 4K erase time */ - uint16_t timeE32k; /*!< 32K erase time */ - uint16_t timeE64k; /*!< 64K erase time */ - uint16_t timePagePgm; /*!< Page program time */ - uint16_t timeCe; /*!< Chip erase time in ms */ - uint8_t pdDelay; /*!< Release power down command delay time for wake up */ - uint8_t qeData; /*!< QE set data */ -} __attribute__((packed)) SPI_Flash_Cfg_Type; - -/*@} end of group SFLAH_Public_Types */ - -/** @defgroup SFLAH_Public_Constants - * @{ - */ - -/*@} end of group SFLAH_Public_Constants */ - -/** @defgroup SFLAH_Public_Macros - * @{ - */ -#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) -#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) -#define BFLB_SPIFLASH_CMD_INVALID 0xff - -/*@} end of group SFLAH_Public_Macros */ - -/** @defgroup SFLAH_Public_Functions - * @{ - */ -void SFlash_Init(const SF_Ctrl_Cfg_Type *sfCtrlCfg); -BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); -BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum); -BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr); -BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); -void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen); -void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data); -void SFlash_GetDeviceId(uint8_t *data); -void SFlash_Powerdown(void); -void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead); -void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, - uint32_t len); -BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead); -BL_Err_Type SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - uint8_t wayDisable); -void SFlash_Cache_Read_Disable(void); -BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead); -BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, - uint32_t len); - -/*@} end of group SFLAH_Public_Functions */ - -/*@} end of group SFLAH */ - -/*@} end of group BL702_Peripheral_Driver */ - -#endif /* __BL702_SFLAH_H__ */ diff --git a/drivers/soc/bl702/std/include/bl702_sflash_ext.h b/drivers/soc/bl702/std/include/bl702_sflash_ext.h index 6c93f3f4..6897e253 100644 --- a/drivers/soc/bl702/std/include/bl702_sflash_ext.h +++ b/drivers/soc/bl702/std/include/bl702_sflash_ext.h @@ -36,7 +36,7 @@ #ifndef __BL702_SFLAH_EXT_H__ #define __BL702_SFLAH_EXT_H__ -#include "bl702_sflash.h" +#include "bflb_sflash.h" #include "bl702_common.h" /** @addtogroup BL702_Peripheral_Driver @@ -54,13 +54,11 @@ /** * @brief Serail flash protect KH25V40 type definition */ -typedef enum { - SFLASH_KH25V40_PROTECT_NONE, /*!< SFlash no protect KH25V40 */ - SFLASH_KH25V40_PROTECT_448KTO512K, /*!< SFlash protect KH25V40 448K to 512K */ - SFLASH_KH25V40_PROTECT_384KTO512K, /*!< SFlash protect KH25V40 384K to 512K */ - SFLASH_KH25V40_PROTECT_256KTO512K, /*!< SFlash protect KH25V40 256K to 512K */ - SFLASH_KH25V40_PROTECT_ALL, /*!< SFlash protect KH25V40 0K to 512K */ -} SFlash_Protect_Kh25v40_Type; +#define SFLASH_KH25V40_PROTECT_NONE 0 /*!< SFlash no protect KH25V40 */ +#define SFLASH_KH25V40_PROTECT_448KTO512K 1 /*!< SFlash protect KH25V40 448K to 512K */ +#define SFLASH_KH25V40_PROTECT_384KTO512K 2 /*!< SFlash protect KH25V40 384K to 512K */ +#define SFLASH_KH25V40_PROTECT_256KTO512K 3 /*!< SFlash protect KH25V40 256K to 512K */ +#define SFLASH_KH25V40_PROTECT_ALL 4 /*!< SFlash protect KH25V40 0K to 512K */ /*@} end of group SFLAH_EXT_Public_Types */ @@ -68,15 +66,6 @@ typedef enum { * @{ */ -/** @defgroup SFLASH_PROTECT_KH25V40_TYPE - * @{ - */ -#define IS_SFLASH_PROTECT_KH25V40_TYPE(type) (((type) == SFLASH_KH25V40_PROTECT_NONE) || \ - ((type) == SFLASH_KH25V40_PROTECT_448KTO512K) || \ - ((type) == SFLASH_KH25V40_PROTECT_384KTO512K) || \ - ((type) == SFLASH_KH25V40_PROTECT_256KTO512K) || \ - ((type) == SFLASH_KH25V40_PROTECT_ALL)) - /*@} end of group SFLAH_EXT_Public_Constants */ /** @defgroup SFLAH_EXT_Public_Macros @@ -88,12 +77,12 @@ typedef enum { /** @defgroup SFLAH_EXT_Public_Functions * @{ */ -BL_Err_Type SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect); -BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg); +int bflb_sflash_kh25v40_write_protect(spi_flash_cfg_type *flash_cfg, uint8_t protect); +int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, + uint8_t reg_len); +int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, + uint8_t reg_len); +int bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg); /*@} end of group SFLAH_EXT_Public_Functions */ diff --git a/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h b/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h index b8d55e1c..7362f8de 100644 --- a/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h +++ b/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h @@ -37,11 +37,10 @@ #define __BL702_XIP_SFLASH_EXT_H__ #include "bl702_common.h" -#include "bl702_sflash.h" -#include "bl702_xip_sflash.h" -#include "bl702_sflash.h" +#include "bflb_xip_sflash.h" +#include "bflb_sflash.h" #include "bl702_sflash_ext.h" -#include "bl702_sf_cfg.h" +#include "bflb_sf_cfg.h" #include "bl702_sf_cfg_ext.h" /** @addtogroup BL702_Peripheral_Driver @@ -74,8 +73,11 @@ * @{ */ -BL_Err_Type XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect); -BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg); +void bflb_xip_sflash_opt_enter(uint8_t *aes_enable); +void bflb_xip_sflash_opt_exit(uint8_t aes_enable); +int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr,uint8_t *data, uint32_t len, uint8_t group, uint8_t bank); +int bflb_xip_sflash_kh25v40_write_protect_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t protect); +int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank); /*@} end of group XIP_SFLASH_EXT_Public_Functions */ diff --git a/drivers/soc/bl702/std/include/hardware/ef_data_0_reg.h b/drivers/soc/bl702/std/include/hardware/ef_data_0_reg.h deleted file mode 100644 index 84dec1d3..00000000 --- a/drivers/soc/bl702/std/include/hardware/ef_data_0_reg.h +++ /dev/null @@ -1,762 +0,0 @@ -/** - ****************************************************************************** - * @file ef_data_0_reg.h - * @version V1.2 - * @date 2020-04-30 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __EF_DATA_0_REG_H__ -#define __EF_DATA_0_REG_H__ - -#include "bl702.h" - -/* 0x0 : ef_cfg_0 */ -#define EF_DATA_0_EF_CFG_0_OFFSET (0x0) -#define EF_DATA_0_EF_SF_AES_MODE EF_DATA_0_EF_SF_AES_MODE -#define EF_DATA_0_EF_SF_AES_MODE_POS (0U) -#define EF_DATA_0_EF_SF_AES_MODE_LEN (2U) -#define EF_DATA_0_EF_SF_AES_MODE_MSK (((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS) -#define EF_DATA_0_EF_SF_AES_MODE_UMSK (~(((1U << EF_DATA_0_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_0_EF_SF_AES_MODE_POS)) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE EF_DATA_0_EF_SBOOT_SIGN_MODE -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_POS (2U) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN (2U) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK (((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) -#define EF_DATA_0_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_0_EF_SBOOT_SIGN_MODE_POS)) -#define EF_DATA_0_EF_SBOOT_EN EF_DATA_0_EF_SBOOT_EN -#define EF_DATA_0_EF_SBOOT_EN_POS (4U) -#define EF_DATA_0_EF_SBOOT_EN_LEN (2U) -#define EF_DATA_0_EF_SBOOT_EN_MSK (((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS) -#define EF_DATA_0_EF_SBOOT_EN_UMSK (~(((1U << EF_DATA_0_EF_SBOOT_EN_LEN) - 1) << EF_DATA_0_EF_SBOOT_EN_POS)) -#define EF_DATA_0_EF_CPU0_ENC_EN EF_DATA_0_EF_CPU0_ENC_EN -#define EF_DATA_0_EF_CPU0_ENC_EN_POS (7U) -#define EF_DATA_0_EF_CPU0_ENC_EN_LEN (1U) -#define EF_DATA_0_EF_CPU0_ENC_EN_MSK (((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS) -#define EF_DATA_0_EF_CPU0_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_0_EF_CPU0_ENC_EN_POS)) -#define EF_DATA_0_EF_BOOT_SEL EF_DATA_0_EF_BOOT_SEL -#define EF_DATA_0_EF_BOOT_SEL_POS (8U) -#define EF_DATA_0_EF_BOOT_SEL_LEN (4U) -#define EF_DATA_0_EF_BOOT_SEL_MSK (((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS) -#define EF_DATA_0_EF_BOOT_SEL_UMSK (~(((1U << EF_DATA_0_EF_BOOT_SEL_LEN) - 1) << EF_DATA_0_EF_BOOT_SEL_POS)) -#define EF_DATA_0_EF_SF_KEY_0_SEL EF_DATA_0_EF_SF_KEY_0_SEL -#define EF_DATA_0_EF_SF_KEY_0_SEL_POS (12U) -#define EF_DATA_0_EF_SF_KEY_0_SEL_LEN (2U) -#define EF_DATA_0_EF_SF_KEY_0_SEL_MSK (((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS) -#define EF_DATA_0_EF_SF_KEY_0_SEL_UMSK (~(((1U << EF_DATA_0_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_0_EF_SF_KEY_0_SEL_POS)) -#define EF_DATA_0_EF_0_KEY_ENC_EN EF_DATA_0_EF_0_KEY_ENC_EN -#define EF_DATA_0_EF_0_KEY_ENC_EN_POS (17U) -#define EF_DATA_0_EF_0_KEY_ENC_EN_LEN (1U) -#define EF_DATA_0_EF_0_KEY_ENC_EN_MSK (((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS) -#define EF_DATA_0_EF_0_KEY_ENC_EN_UMSK (~(((1U << EF_DATA_0_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_0_EF_0_KEY_ENC_EN_POS)) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS EF_DATA_0_EF_DBG_JTAG_0_DIS -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_POS (26U) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN (2U) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_MSK (((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS) -#define EF_DATA_0_EF_DBG_JTAG_0_DIS_UMSK (~(((1U << EF_DATA_0_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_0_EF_DBG_JTAG_0_DIS_POS)) -#define EF_DATA_0_EF_DBG_MODE EF_DATA_0_EF_DBG_MODE -#define EF_DATA_0_EF_DBG_MODE_POS (28U) -#define EF_DATA_0_EF_DBG_MODE_LEN (4U) -#define EF_DATA_0_EF_DBG_MODE_MSK (((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS) -#define EF_DATA_0_EF_DBG_MODE_UMSK (~(((1U << EF_DATA_0_EF_DBG_MODE_LEN) - 1) << EF_DATA_0_EF_DBG_MODE_POS)) - -/* 0x4 : ef_dbg_pwd_low */ -#define EF_DATA_0_EF_DBG_PWD_LOW_OFFSET (0x4) -#define EF_DATA_0_EF_DBG_PWD_LOW EF_DATA_0_EF_DBG_PWD_LOW -#define EF_DATA_0_EF_DBG_PWD_LOW_POS (0U) -#define EF_DATA_0_EF_DBG_PWD_LOW_LEN (32U) -#define EF_DATA_0_EF_DBG_PWD_LOW_MSK (((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS) -#define EF_DATA_0_EF_DBG_PWD_LOW_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_LOW_POS)) - -/* 0x8 : ef_dbg_pwd_high */ -#define EF_DATA_0_EF_DBG_PWD_HIGH_OFFSET (0x8) -#define EF_DATA_0_EF_DBG_PWD_HIGH EF_DATA_0_EF_DBG_PWD_HIGH -#define EF_DATA_0_EF_DBG_PWD_HIGH_POS (0U) -#define EF_DATA_0_EF_DBG_PWD_HIGH_LEN (32U) -#define EF_DATA_0_EF_DBG_PWD_HIGH_MSK (((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS) -#define EF_DATA_0_EF_DBG_PWD_HIGH_UMSK (~(((1U << EF_DATA_0_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_0_EF_DBG_PWD_HIGH_POS)) - -/* 0xC : ef_ana_trim_0 */ -#define EF_DATA_0_EF_ANA_TRIM_0_OFFSET (0xC) -#define EF_DATA_0_EF_ANA_TRIM_0 EF_DATA_0_EF_ANA_TRIM_0 -#define EF_DATA_0_EF_ANA_TRIM_0_POS (0U) -#define EF_DATA_0_EF_ANA_TRIM_0_LEN (32U) -#define EF_DATA_0_EF_ANA_TRIM_0_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS) -#define EF_DATA_0_EF_ANA_TRIM_0_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_0_POS)) - -/* 0x10 : ef_sw_usage_0 */ -#define EF_DATA_0_EF_SW_USAGE_0_OFFSET (0x10) -#define EF_DATA_0_EF_SW_USAGE_0 EF_DATA_0_EF_SW_USAGE_0 -#define EF_DATA_0_EF_SW_USAGE_0_POS (0U) -#define EF_DATA_0_EF_SW_USAGE_0_LEN (32U) -#define EF_DATA_0_EF_SW_USAGE_0_MSK (((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS) -#define EF_DATA_0_EF_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_0_EF_SW_USAGE_0_POS)) - -/* 0x14 : ef_wifi_mac_low */ -#define EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET (0x14) -#define EF_DATA_0_EF_WIFI_MAC_LOW EF_DATA_0_EF_WIFI_MAC_LOW -#define EF_DATA_0_EF_WIFI_MAC_LOW_POS (0U) -#define EF_DATA_0_EF_WIFI_MAC_LOW_LEN (32U) -#define EF_DATA_0_EF_WIFI_MAC_LOW_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS) -#define EF_DATA_0_EF_WIFI_MAC_LOW_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_LOW_POS)) - -/* 0x18 : ef_wifi_mac_high */ -#define EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET (0x18) -#define EF_DATA_0_EF_WIFI_MAC_HIGH EF_DATA_0_EF_WIFI_MAC_HIGH -#define EF_DATA_0_EF_WIFI_MAC_HIGH_POS (0U) -#define EF_DATA_0_EF_WIFI_MAC_HIGH_LEN (32U) -#define EF_DATA_0_EF_WIFI_MAC_HIGH_MSK (((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS) -#define EF_DATA_0_EF_WIFI_MAC_HIGH_UMSK (~(((1U << EF_DATA_0_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_0_EF_WIFI_MAC_HIGH_POS)) - -/* 0x1C : ef_key_slot_0_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W0_OFFSET (0x1C) -#define EF_DATA_0_EF_KEY_SLOT_0_W0 EF_DATA_0_EF_KEY_SLOT_0_W0 -#define EF_DATA_0_EF_KEY_SLOT_0_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W0_POS)) - -/* 0x20 : ef_key_slot_0_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W1_OFFSET (0x20) -#define EF_DATA_0_EF_KEY_SLOT_0_W1 EF_DATA_0_EF_KEY_SLOT_0_W1 -#define EF_DATA_0_EF_KEY_SLOT_0_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W1_POS)) - -/* 0x24 : ef_key_slot_0_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W2_OFFSET (0x24) -#define EF_DATA_0_EF_KEY_SLOT_0_W2 EF_DATA_0_EF_KEY_SLOT_0_W2 -#define EF_DATA_0_EF_KEY_SLOT_0_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W2_POS)) - -/* 0x28 : ef_key_slot_0_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_0_W3_OFFSET (0x28) -#define EF_DATA_0_EF_KEY_SLOT_0_W3 EF_DATA_0_EF_KEY_SLOT_0_W3 -#define EF_DATA_0_EF_KEY_SLOT_0_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_0_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_0_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_0_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_0_W3_POS)) - -/* 0x2C : ef_key_slot_1_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W0_OFFSET (0x2C) -#define EF_DATA_0_EF_KEY_SLOT_1_W0 EF_DATA_0_EF_KEY_SLOT_1_W0 -#define EF_DATA_0_EF_KEY_SLOT_1_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W0_POS)) - -/* 0x30 : ef_key_slot_1_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W1_OFFSET (0x30) -#define EF_DATA_0_EF_KEY_SLOT_1_W1 EF_DATA_0_EF_KEY_SLOT_1_W1 -#define EF_DATA_0_EF_KEY_SLOT_1_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W1_POS)) - -/* 0x34 : ef_key_slot_1_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W2_OFFSET (0x34) -#define EF_DATA_0_EF_KEY_SLOT_1_W2 EF_DATA_0_EF_KEY_SLOT_1_W2 -#define EF_DATA_0_EF_KEY_SLOT_1_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W2_POS)) - -/* 0x38 : ef_key_slot_1_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_1_W3_OFFSET (0x38) -#define EF_DATA_0_EF_KEY_SLOT_1_W3 EF_DATA_0_EF_KEY_SLOT_1_W3 -#define EF_DATA_0_EF_KEY_SLOT_1_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_1_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_1_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_1_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_1_W3_POS)) - -/* 0x3C : ef_key_slot_2_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W0_OFFSET (0x3C) -#define EF_DATA_0_EF_KEY_SLOT_2_W0 EF_DATA_0_EF_KEY_SLOT_2_W0 -#define EF_DATA_0_EF_KEY_SLOT_2_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W0_POS)) - -/* 0x40 : ef_key_slot_2_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W1_OFFSET (0x40) -#define EF_DATA_0_EF_KEY_SLOT_2_W1 EF_DATA_0_EF_KEY_SLOT_2_W1 -#define EF_DATA_0_EF_KEY_SLOT_2_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W1_POS)) - -/* 0x44 : ef_key_slot_2_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W2_OFFSET (0x44) -#define EF_DATA_0_EF_KEY_SLOT_2_W2 EF_DATA_0_EF_KEY_SLOT_2_W2 -#define EF_DATA_0_EF_KEY_SLOT_2_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W2_POS)) - -/* 0x48 : ef_key_slot_2_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_2_W3_OFFSET (0x48) -#define EF_DATA_0_EF_KEY_SLOT_2_W3 EF_DATA_0_EF_KEY_SLOT_2_W3 -#define EF_DATA_0_EF_KEY_SLOT_2_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_2_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_2_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_2_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_2_W3_POS)) - -/* 0x4C : ef_key_slot_3_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W0_OFFSET (0x4C) -#define EF_DATA_0_EF_KEY_SLOT_3_W0 EF_DATA_0_EF_KEY_SLOT_3_W0 -#define EF_DATA_0_EF_KEY_SLOT_3_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W0_POS)) - -/* 0x50 : ef_key_slot_3_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W1_OFFSET (0x50) -#define EF_DATA_0_EF_KEY_SLOT_3_W1 EF_DATA_0_EF_KEY_SLOT_3_W1 -#define EF_DATA_0_EF_KEY_SLOT_3_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W1_POS)) - -/* 0x54 : ef_key_slot_3_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W2_OFFSET (0x54) -#define EF_DATA_0_EF_KEY_SLOT_3_W2 EF_DATA_0_EF_KEY_SLOT_3_W2 -#define EF_DATA_0_EF_KEY_SLOT_3_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W2_POS)) - -/* 0x58 : ef_key_slot_3_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_3_W3_OFFSET (0x58) -#define EF_DATA_0_EF_KEY_SLOT_3_W3 EF_DATA_0_EF_KEY_SLOT_3_W3 -#define EF_DATA_0_EF_KEY_SLOT_3_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_3_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_3_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_3_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_3_W3_POS)) - -/* 0x5C : ef_key_slot_4_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W0_OFFSET (0x5C) -#define EF_DATA_0_EF_KEY_SLOT_4_W0 EF_DATA_0_EF_KEY_SLOT_4_W0 -#define EF_DATA_0_EF_KEY_SLOT_4_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W0_POS)) - -/* 0x60 : ef_key_slot_4_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W1_OFFSET (0x60) -#define EF_DATA_0_EF_KEY_SLOT_4_W1 EF_DATA_0_EF_KEY_SLOT_4_W1 -#define EF_DATA_0_EF_KEY_SLOT_4_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W1_POS)) - -/* 0x64 : ef_key_slot_4_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W2_OFFSET (0x64) -#define EF_DATA_0_EF_KEY_SLOT_4_W2 EF_DATA_0_EF_KEY_SLOT_4_W2 -#define EF_DATA_0_EF_KEY_SLOT_4_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W2_POS)) - -/* 0x68 : ef_key_slot_4_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_4_W3_OFFSET (0x68) -#define EF_DATA_0_EF_KEY_SLOT_4_W3 EF_DATA_0_EF_KEY_SLOT_4_W3 -#define EF_DATA_0_EF_KEY_SLOT_4_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_4_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_4_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_4_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_4_W3_POS)) - -/* 0x6C : ef_key_slot_5_w0 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W0_OFFSET (0x6C) -#define EF_DATA_0_EF_KEY_SLOT_5_W0 EF_DATA_0_EF_KEY_SLOT_5_W0 -#define EF_DATA_0_EF_KEY_SLOT_5_W0_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W0_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W0_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W0_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W0_POS)) - -/* 0x70 : ef_key_slot_5_w1 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W1_OFFSET (0x70) -#define EF_DATA_0_EF_KEY_SLOT_5_W1 EF_DATA_0_EF_KEY_SLOT_5_W1 -#define EF_DATA_0_EF_KEY_SLOT_5_W1_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W1_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W1_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W1_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W1_POS)) - -/* 0x74 : ef_key_slot_5_w2 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W2_OFFSET (0x74) -#define EF_DATA_0_EF_KEY_SLOT_5_W2 EF_DATA_0_EF_KEY_SLOT_5_W2 -#define EF_DATA_0_EF_KEY_SLOT_5_W2_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W2_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W2_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W2_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W2_POS)) - -/* 0x78 : ef_key_slot_5_w3 */ -#define EF_DATA_0_EF_KEY_SLOT_5_W3_OFFSET (0x78) -#define EF_DATA_0_EF_KEY_SLOT_5_W3 EF_DATA_0_EF_KEY_SLOT_5_W3 -#define EF_DATA_0_EF_KEY_SLOT_5_W3_POS (0U) -#define EF_DATA_0_EF_KEY_SLOT_5_W3_LEN (32U) -#define EF_DATA_0_EF_KEY_SLOT_5_W3_MSK (((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS) -#define EF_DATA_0_EF_KEY_SLOT_5_W3_UMSK (~(((1U << EF_DATA_0_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_0_EF_KEY_SLOT_5_W3_POS)) - -/* 0x7C : ef_data_0_lock */ -#define EF_DATA_0_LOCK_OFFSET (0x7C) -#define EF_DATA_0_EF_ANA_TRIM_1 EF_DATA_0_EF_ANA_TRIM_1 -#define EF_DATA_0_EF_ANA_TRIM_1_POS (0U) -#define EF_DATA_0_EF_ANA_TRIM_1_LEN (13U) -#define EF_DATA_0_EF_ANA_TRIM_1_MSK (((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS) -#define EF_DATA_0_EF_ANA_TRIM_1_UMSK (~(((1U << EF_DATA_0_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_0_EF_ANA_TRIM_1_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L EF_DATA_0_WR_LOCK_KEY_SLOT_4_L -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS (13U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_L_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L EF_DATA_0_WR_LOCK_KEY_SLOT_5_L -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS (14U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_L_POS)) -#define EF_DATA_0_WR_LOCK_BOOT_MODE EF_DATA_0_WR_LOCK_BOOT_MODE -#define EF_DATA_0_WR_LOCK_BOOT_MODE_POS (15U) -#define EF_DATA_0_WR_LOCK_BOOT_MODE_LEN (1U) -#define EF_DATA_0_WR_LOCK_BOOT_MODE_MSK (((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS) -#define EF_DATA_0_WR_LOCK_BOOT_MODE_UMSK (~(((1U << EF_DATA_0_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_0_WR_LOCK_BOOT_MODE_POS)) -#define EF_DATA_0_WR_LOCK_DBG_PWD EF_DATA_0_WR_LOCK_DBG_PWD -#define EF_DATA_0_WR_LOCK_DBG_PWD_POS (16U) -#define EF_DATA_0_WR_LOCK_DBG_PWD_LEN (1U) -#define EF_DATA_0_WR_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS) -#define EF_DATA_0_WR_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_WR_LOCK_DBG_PWD_POS)) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0 EF_DATA_0_WR_LOCK_SW_USAGE_0 -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_POS (17U) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN (1U) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_MSK (((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS) -#define EF_DATA_0_WR_LOCK_SW_USAGE_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_0_WR_LOCK_SW_USAGE_0_POS)) -#define EF_DATA_0_WR_LOCK_WIFI_MAC EF_DATA_0_WR_LOCK_WIFI_MAC -#define EF_DATA_0_WR_LOCK_WIFI_MAC_POS (18U) -#define EF_DATA_0_WR_LOCK_WIFI_MAC_LEN (1U) -#define EF_DATA_0_WR_LOCK_WIFI_MAC_MSK (((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS) -#define EF_DATA_0_WR_LOCK_WIFI_MAC_UMSK (~(((1U << EF_DATA_0_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_0_WR_LOCK_WIFI_MAC_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0 EF_DATA_0_WR_LOCK_KEY_SLOT_0 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS (19U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_0_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1 EF_DATA_0_WR_LOCK_KEY_SLOT_1 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS (20U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_1_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2 EF_DATA_0_WR_LOCK_KEY_SLOT_2 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS (21U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_2_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3 EF_DATA_0_WR_LOCK_KEY_SLOT_3 -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS (22U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_3_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H EF_DATA_0_WR_LOCK_KEY_SLOT_4_H -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS (23U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_4_H_POS)) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H EF_DATA_0_WR_LOCK_KEY_SLOT_5_H -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS (24U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN (1U) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_MSK (((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS) -#define EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_0_WR_LOCK_KEY_SLOT_5_H_POS)) -#define EF_DATA_0_RD_LOCK_DBG_PWD EF_DATA_0_RD_LOCK_DBG_PWD -#define EF_DATA_0_RD_LOCK_DBG_PWD_POS (25U) -#define EF_DATA_0_RD_LOCK_DBG_PWD_LEN (1U) -#define EF_DATA_0_RD_LOCK_DBG_PWD_MSK (((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS) -#define EF_DATA_0_RD_LOCK_DBG_PWD_UMSK (~(((1U << EF_DATA_0_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_0_RD_LOCK_DBG_PWD_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0 EF_DATA_0_RD_LOCK_KEY_SLOT_0 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS (26U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_0_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_0_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1 EF_DATA_0_RD_LOCK_KEY_SLOT_1 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS (27U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_1_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_1_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2 EF_DATA_0_RD_LOCK_KEY_SLOT_2 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS (28U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_2_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_2_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3 EF_DATA_0_RD_LOCK_KEY_SLOT_3 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS (29U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_3_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_3_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4 EF_DATA_0_RD_LOCK_KEY_SLOT_4 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS (30U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_4_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_4_POS)) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5 EF_DATA_0_RD_LOCK_KEY_SLOT_5 -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS (31U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN (1U) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_MSK (((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS) -#define EF_DATA_0_RD_LOCK_KEY_SLOT_5_UMSK (~(((1U << EF_DATA_0_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_0_RD_LOCK_KEY_SLOT_5_POS)) - -struct ef_data_0_reg { - /* 0x0 : ef_cfg_0 */ - union { - struct - { - uint32_t ef_sf_aes_mode : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t rsvd0 : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t rsvd1 : 1; /* [ 6], r/w, 0x0 */ - uint32_t ef_cpu0_enc_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t ef_boot_sel : 4; /* [11: 8], r/w, 0x0 */ - uint32_t ef_sf_key_0_sel : 2; /* [13:12], r/w, 0x0 */ - uint32_t rsvd2 : 1; /* [ 14], r/w, 0x0 */ - uint32_t rsvd3 : 1; /* [ 15], r/w, 0x0 */ - uint32_t rsvd4 : 1; /* [ 16], r/w, 0x0 */ - uint32_t ef_0_key_enc_en : 1; /* [ 17], r/w, 0x0 */ - uint32_t rsvd5 : 1; /* [ 18], r/w, 0x0 */ - uint32_t rsvd6 : 1; /* [ 19], r/w, 0x0 */ - uint32_t rsvd7 : 1; /* [ 20], r/w, 0x0 */ - uint32_t rsvd8 : 1; /* [ 21], r/w, 0x0 */ - uint32_t rsvd9 : 1; /* [ 22], r/w, 0x0 */ - uint32_t rsvd10 : 1; /* [ 23], r/w, 0x0 */ - uint32_t rsvd11 : 2; /* [25:24], r/w, 0x0 */ - uint32_t ef_dbg_jtag_0_dis : 2; /* [27:26], r/w, 0x0 */ - uint32_t ef_dbg_mode : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_cfg_0; - - /* 0x4 : ef_dbg_pwd_low */ - union { - struct - { - uint32_t ef_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_dbg_pwd_low; - - /* 0x8 : ef_dbg_pwd_high */ - union { - struct - { - uint32_t ef_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_dbg_pwd_high; - - /* 0xC : ef_ana_trim_0 */ - union { - struct - { - uint32_t ef_ana_trim_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_ana_trim_0; - - /* 0x10 : ef_sw_usage_0 */ - union { - struct - { - uint32_t ef_sw_usage_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_sw_usage_0; - - /* 0x14 : ef_wifi_mac_low */ - union { - struct - { - uint32_t ef_wifi_mac_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_wifi_mac_low; - - /* 0x18 : ef_wifi_mac_high */ - union { - struct - { - uint32_t ef_wifi_mac_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_wifi_mac_high; - - /* 0x1C : ef_key_slot_0_w0 */ - union { - struct - { - uint32_t ef_key_slot_0_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w0; - - /* 0x20 : ef_key_slot_0_w1 */ - union { - struct - { - uint32_t ef_key_slot_0_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w1; - - /* 0x24 : ef_key_slot_0_w2 */ - union { - struct - { - uint32_t ef_key_slot_0_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w2; - - /* 0x28 : ef_key_slot_0_w3 */ - union { - struct - { - uint32_t ef_key_slot_0_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_0_w3; - - /* 0x2C : ef_key_slot_1_w0 */ - union { - struct - { - uint32_t ef_key_slot_1_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w0; - - /* 0x30 : ef_key_slot_1_w1 */ - union { - struct - { - uint32_t ef_key_slot_1_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w1; - - /* 0x34 : ef_key_slot_1_w2 */ - union { - struct - { - uint32_t ef_key_slot_1_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w2; - - /* 0x38 : ef_key_slot_1_w3 */ - union { - struct - { - uint32_t ef_key_slot_1_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_1_w3; - - /* 0x3C : ef_key_slot_2_w0 */ - union { - struct - { - uint32_t ef_key_slot_2_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w0; - - /* 0x40 : ef_key_slot_2_w1 */ - union { - struct - { - uint32_t ef_key_slot_2_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w1; - - /* 0x44 : ef_key_slot_2_w2 */ - union { - struct - { - uint32_t ef_key_slot_2_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w2; - - /* 0x48 : ef_key_slot_2_w3 */ - union { - struct - { - uint32_t ef_key_slot_2_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_2_w3; - - /* 0x4C : ef_key_slot_3_w0 */ - union { - struct - { - uint32_t ef_key_slot_3_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w0; - - /* 0x50 : ef_key_slot_3_w1 */ - union { - struct - { - uint32_t ef_key_slot_3_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w1; - - /* 0x54 : ef_key_slot_3_w2 */ - union { - struct - { - uint32_t ef_key_slot_3_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w2; - - /* 0x58 : ef_key_slot_3_w3 */ - union { - struct - { - uint32_t ef_key_slot_3_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_3_w3; - - /* 0x5C : ef_key_slot_4_w0 */ - union { - struct - { - uint32_t ef_key_slot_4_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w0; - - /* 0x60 : ef_key_slot_4_w1 */ - union { - struct - { - uint32_t ef_key_slot_4_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w1; - - /* 0x64 : ef_key_slot_4_w2 */ - union { - struct - { - uint32_t ef_key_slot_4_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w2; - - /* 0x68 : ef_key_slot_4_w3 */ - union { - struct - { - uint32_t ef_key_slot_4_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_4_w3; - - /* 0x6C : ef_key_slot_5_w0 */ - union { - struct - { - uint32_t ef_key_slot_5_w0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w0; - - /* 0x70 : ef_key_slot_5_w1 */ - union { - struct - { - uint32_t ef_key_slot_5_w1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w1; - - /* 0x74 : ef_key_slot_5_w2 */ - union { - struct - { - uint32_t ef_key_slot_5_w2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w2; - - /* 0x78 : ef_key_slot_5_w3 */ - union { - struct - { - uint32_t ef_key_slot_5_w3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_key_slot_5_w3; - - /* 0x7C : ef_data_0_lock */ - union { - struct - { - uint32_t ef_ana_trim_1 : 13; /* [12: 0], r/w, 0x0 */ - uint32_t wr_lock_key_slot_4_l : 1; /* [ 13], r/w, 0x0 */ - uint32_t wr_lock_key_slot_5_l : 1; /* [ 14], r/w, 0x0 */ - uint32_t wr_lock_boot_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t wr_lock_dbg_pwd : 1; /* [ 16], r/w, 0x0 */ - uint32_t wr_lock_sw_usage_0 : 1; /* [ 17], r/w, 0x0 */ - uint32_t wr_lock_wifi_mac : 1; /* [ 18], r/w, 0x0 */ - uint32_t wr_lock_key_slot_0 : 1; /* [ 19], r/w, 0x0 */ - uint32_t wr_lock_key_slot_1 : 1; /* [ 20], r/w, 0x0 */ - uint32_t wr_lock_key_slot_2 : 1; /* [ 21], r/w, 0x0 */ - uint32_t wr_lock_key_slot_3 : 1; /* [ 22], r/w, 0x0 */ - uint32_t wr_lock_key_slot_4_h : 1; /* [ 23], r/w, 0x0 */ - uint32_t wr_lock_key_slot_5_h : 1; /* [ 24], r/w, 0x0 */ - uint32_t rd_lock_dbg_pwd : 1; /* [ 25], r/w, 0x0 */ - uint32_t rd_lock_key_slot_0 : 1; /* [ 26], r/w, 0x0 */ - uint32_t rd_lock_key_slot_1 : 1; /* [ 27], r/w, 0x0 */ - uint32_t rd_lock_key_slot_2 : 1; /* [ 28], r/w, 0x0 */ - uint32_t rd_lock_key_slot_3 : 1; /* [ 29], r/w, 0x0 */ - uint32_t rd_lock_key_slot_4 : 1; /* [ 30], r/w, 0x0 */ - uint32_t rd_lock_key_slot_5 : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ef_data_0_lock; -}; - -typedef volatile struct ef_data_0_reg ef_data_0_reg_t; - -#endif /* __EF_DATA_0_REG_H__ */ diff --git a/drivers/soc/bl702/std/port/bl702_flash.c b/drivers/soc/bl702/std/port/bl702_flash.c deleted file mode 100644 index 69beea8f..00000000 --- a/drivers/soc/bl702/std/port/bl702_flash.c +++ /dev/null @@ -1,241 +0,0 @@ -#include "bl702_glb.h" -#include "bl702_xip_sflash.h" -#include "bl702_xip_sflash_ext.h" -#include "bl702_sf_cfg.h" -#include "bl702_sf_cfg_ext.h" -#include "bl702_ef_cfg.h" -#include "bflb_flash.h" - -static uint32_t g_jedec_id = 0; -static SPI_Flash_Cfg_Type g_flash_cfg; - -static bflb_efuse_device_info_type devInfo; - -static void ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_Qspi_Enable(p_flash_cfg); - } -} - -static void ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { - L1C_Set_Wrap(DISABLE); - } else { - L1C_Set_Wrap(ENABLE); - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(p_flash_cfg); - } - } -} - -static void ATTR_TCM_SECTION flash_sf2_gpio_init(void) -{ - uint32_t tmpVal; - - /* flash_cfg != BFLB_FLASH_CFG_SF1_EXT_17_22, flash pad use SF2 */ - if (devInfo.flash_cfg != BFLB_FLASH_CFG_SF1_EXT_17_22) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); - /* GLB_CFG_GPIO_USE_PSRAM_IO == 0, need init SF2 flash gpio */ - if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) { - SF_Cfg_Init_Ext_Flash_Gpio(1); - } - } -} - -/** - * @brief flash_config_init - * - * @return int - */ -static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) -{ - int ret = -1; - uint32_t jid = 0; - uint32_t offset = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(); - XIP_SFlash_State_Save(p_flash_cfg, &offset); - flash_sf2_gpio_init(); - SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); - arch_memcpy(jedec_id, (uint8_t *)&jid, 3); - jid &= 0xFFFFFF; - g_jedec_id = jid; - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg); - if (ret == 0) { - p_flash_cfg->mid = (jid & 0xff); - } - - /* Set flash controler from p_flash_cfg */ - flash_set_qspi_enable(p_flash_cfg); - flash_set_l1c_wrap(p_flash_cfg); - XIP_SFlash_State_Restore(p_flash_cfg, p_flash_cfg->ioMode & 0x0f, offset); - XIP_SFlash_Opt_Exit(); - bflb_irq_restore(flag); - - return ret; -} - -/** - * @brief multi flash adapter - * - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_init(void) -{ - int ret = -1; - uint8_t clkDelay = 1; - uint8_t clkInvert = 1; - uint32_t jedec_id = 0; - uintptr_t flag; - - bflb_ef_ctrl_get_device_info(&devInfo); - - flag = bflb_irq_save(); - L1C_Cache_Flush(); - SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg); - L1C_Cache_Flush(); - bflb_irq_restore(flag); - if (g_flash_cfg.mid != 0xff) { - return 0; - } - clkDelay = g_flash_cfg.clkDelay; - clkInvert = g_flash_cfg.clkInvert; - g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f; - - ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); - - g_flash_cfg.clkDelay = clkDelay; - g_flash_cfg.clkInvert = clkInvert; - - return ret; -} - -uint32_t bflb_flash_get_jedec_id(void) -{ - uint32_t jid = 0; - - jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16); - return jid; -} - -void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) -{ - *cfg_addr = (uint8_t *)&g_flash_cfg; - *len = sizeof(SPI_Flash_Cfg_Type); -} - -ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void) -{ - return SF_Ctrl_Get_Flash_Image_Offset(); -} - -void bflb_flash_set_iomode(uint8_t iomode) -{ - g_flash_cfg.ioMode &= ~0x0f; - g_flash_cfg.ioMode |= iomode; -} - -int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len) -{ - int ret = -1; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(); - ret = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, startaddr, startaddr + len - 1); - XIP_SFlash_Opt_Exit(); - bflb_irq_restore(flag); - - return ret; -} - -int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - int ret = -1; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(); - ret = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len); - XIP_SFlash_Opt_Exit(); - bflb_irq_restore(flag); - - return ret; -} - -int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - int ret = -1; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(); - ret = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len); - XIP_SFlash_Opt_Exit(); - bflb_irq_restore(flag); - - return ret; -} - -int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) -{ - uint32_t tmp[1]; - int stat; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - - XIP_SFlash_Opt_Enter(); - /* To make it simple, exit cont read anyway */ - SFlash_Reset_Continue_Read(&g_flash_cfg); - - if (g_flash_cfg.cReadSupport == 0) { - cont_read = 0; - } - - if (cont_read == 1) { - stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - - if (0 != stat) { - XIP_SFlash_Opt_Exit(); - return -1; - } - } - - /* Set default value */ - L1C_Cache_Enable_Set(0xf); - - if (cache_enable) { - SF_Ctrl_Set_Flash_Image_Offset(flash_offset); - SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable); - } - XIP_SFlash_Opt_Exit(); - - return 0; -} - -void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config) -{ - uint8_t hw_key_enable = 0; - - if (config->key == NULL) { - hw_key_enable = 1; - } - - SF_Ctrl_AES_Set_Key_BE(config->region, (uint8_t *)config->key, config->keybits); - SF_Ctrl_AES_Set_IV_BE(config->region, (uint8_t *)config->iv, config->start_addr); - SF_Ctrl_AES_Set_Region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable); -} - -void bflb_flash_aes_enable(void) -{ - SF_Ctrl_AES_Enable(); -} - -void bflb_flash_aes_disable(void) -{ - SF_Ctrl_AES_Disable(); -} \ No newline at end of file diff --git a/drivers/soc/bl702/std/src/bl702_clock.c b/drivers/soc/bl702/std/src/bl702_clock.c index b206f3d7..0ad6d871 100644 --- a/drivers/soc/bl702/std/src/bl702_clock.c +++ b/drivers/soc/bl702/std/src/bl702_clock.c @@ -84,13 +84,13 @@ * @{ */ -static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) +static inline uint32_t Clock_Xtal_Output(void) { /* 32m */ return (32 * 1000 * 1000); } -static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_XClk_Mux_Output(uint8_t sel) { if (sel == 0) { /* rc32m */ @@ -101,7 +101,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) +static inline uint8_t Clock_Get_MCU_XClk_Sel_Val(void) { uint32_t tmpVal = 0; @@ -111,7 +111,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) return (tmpVal & 0x1); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_MCU_Root_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -121,7 +121,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) return ((tmpVal >> 1) & 0x1); } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_MCU_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* pll 57.6m */ @@ -140,7 +140,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) { uint32_t tmpVal; @@ -157,7 +157,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) +static inline uint8_t Clock_Get_MCU_HClk_Div_Val(void) { uint32_t tmpVal; @@ -166,7 +166,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) +static inline uint8_t Clock_Get_Peri_BClk_Div_Val(void) { uint32_t tmpVal; @@ -175,7 +175,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) +static inline uint32_t Clock_F32k_Mux_Output(uint8_t sel) { uint32_t tmpVal; uint32_t div = 0; @@ -194,7 +194,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) +static inline uint8_t Clock_Get_F32k_Sel_Val(void) { uint32_t tmpVal; @@ -203,7 +203,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output() +static inline uint32_t Clock_Get_AUPLL_Output() { uint32_t tmpVal = 0; @@ -278,7 +278,7 @@ uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type) } } -static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* fclk */ @@ -289,7 +289,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -298,7 +298,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) +static inline uint8_t Clock_Get_UART_Div_Val(void) { uint32_t tmpVal; @@ -307,13 +307,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(void) +static inline uint32_t Clock_SPI_Clk_Mux_Output(void) { /* pbclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) +static inline uint8_t Clock_Get_SPI_Div_Val(void) { uint32_t tmpVal; @@ -322,13 +322,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output() +static inline uint32_t Clock_I2C_Clk_Mux_Output() { /* pbclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) +static inline uint8_t Clock_Get_I2C_Div_Val(void) { uint32_t tmpVal; @@ -337,13 +337,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_I2S_Clk_Mux_Output(void) +static inline uint32_t Clock_I2S_Clk_Mux_Output(void) { /* aupll clk */ return Clock_Get_AUPLL_Output(); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) +static inline uint8_t Clock_Get_GPADC_Div_Val(void) { uint32_t tmpVal; @@ -352,7 +352,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel) { if (sel == 0) { /* aupll clk */ @@ -363,7 +363,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -372,7 +372,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel) { uint32_t div = 0; @@ -385,7 +385,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -394,7 +394,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* pll 32m */ @@ -408,7 +408,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) +static inline uint8_t Clock_Get_GPDAC_Div_Val(void) { uint32_t tmpVal; @@ -417,7 +417,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -426,7 +426,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL); } -// static uint32_t ATTR_CLOCK_SECTION Clock_PWM_Clk_Mux_Output(uint8_t sel) +// static inline uint32_t Clock_PWM_Clk_Mux_Output(uint8_t sel) // { // if (sel == 0) { // /* xclk */ @@ -440,7 +440,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) // } // } -// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Div_Val(void) +// static inline uint8_t Clock_Get_PWM_Div_Val(void) // { // uint32_t tmpVal; @@ -449,7 +449,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) // return tmpVal; // } -// static uint8_t ATTR_CLOCK_SECTION Clock_Get_PWM_Clk_Sel_Val(void) +// static inline uint8_t Clock_Get_PWM_Clk_Sel_Val(void) // { // uint32_t tmpVal; @@ -458,13 +458,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) // return BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL); // } -static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void) +static inline uint32_t Clock_IR_Clk_Mux_Output(void) { /* xclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) +static inline uint8_t Clock_Get_IR_Div_Val(void) { uint32_t tmpVal; @@ -473,7 +473,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* xclk */ @@ -484,7 +484,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -493,7 +493,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void) +static inline uint8_t Clock_Get_CAM_Div_Val(void) { uint32_t tmpVal; @@ -502,7 +502,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void) { uint32_t tmpVal; @@ -511,7 +511,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* 144m */ @@ -525,7 +525,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* sf sel2 */ @@ -542,7 +542,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -551,7 +551,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) +static inline uint8_t Clock_Get_SF_Div_Val(void) { uint32_t tmpVal; @@ -560,7 +560,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_QDEC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_QDEC_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* xclk */ @@ -571,7 +571,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_QDEC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_QDEC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_QDEC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -580,7 +580,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_QDEC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_QDEC_Div_Val(void) +static inline uint8_t Clock_Get_QDEC_Div_Val(void) { uint32_t tmpVal; @@ -589,7 +589,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_QDEC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_DIV); } -// static uint32_t ATTR_CLOCK_SECTION Clock_TIMER_Clk_Mux_Output(uint8_t sel) +// static inline uint32_t Clock_TIMER_Clk_Mux_Output(uint8_t sel) // { // if (sel == 0) { // /* fclk */ @@ -606,7 +606,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_QDEC_Div_Val(void) // } // } -// static uint8_t ATTR_CLOCK_SECTION Clock_Get_TIMER0_Clk_Sel_Val(void) +// static inline uint8_t Clock_Get_TIMER0_Clk_Sel_Val(void) // { // uint32_t tmpVal; @@ -615,7 +615,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_QDEC_Div_Val(void) // return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_1); // } -// static uint8_t ATTR_CLOCK_SECTION Clock_Get_TIMER1_Clk_Sel_Val(void) +// static inline uint8_t Clock_Get_TIMER1_Clk_Sel_Val(void) // { // uint32_t tmpVal; @@ -624,7 +624,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_QDEC_Div_Val(void) // return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_2); // } -// static uint8_t ATTR_CLOCK_SECTION Clock_Get_WDT_Clk_Sel_Val(void) +// static inline uint8_t Clock_Get_WDT_Clk_Sel_Val(void) // { // uint32_t tmpVal; diff --git a/drivers/soc/bl702/std/src/bl702_ef_ctrl.c b/drivers/soc/bl702/std/src/bl702_ef_ctrl.c deleted file mode 100644 index e61de431..00000000 --- a/drivers/soc/bl702/std/src/bl702_ef_ctrl.c +++ /dev/null @@ -1,1722 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_sec_ef_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl702_ef_ctrl.h" -#include "ef_data_0_reg.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) -#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) -#define EF_CTRL_DFT_TIMEOUT_VAL (160 * 1000) -#ifndef BOOTROM -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#else -#define EF_CTRL_LOAD_BEFORE_READ_R0 -#endif -#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, EF_CTRL_EFUSE_R0_SIZE / 4) - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Switch efuse region 0 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -/* static */ void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -static void EF_Ctrl_Program_Efuse_0(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Program */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - BL702_Delay_US(4); - - /* Trigger */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} - -/*@} end of group SEC_EF_CTRL_Private_Functions */ - -/** @defgroup SEC_EF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Load efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - EF_CTRL_DATA0_CLEAR; - - /* Trigger read */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - BL702_Delay_US(10); - - /* Wait for efuse control idle*/ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - timeout--; - - if (timeout == 0) { - break; - } - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || - - (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); - - /* Switch to AHB clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse busy status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse whether finish loading - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type EF_Ctrl_AutoLoad_Done(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Efuse write debug password - * - * @param passWdLow: password low 32 bits - * @param passWdHigh: password high 32 bits - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read debug password - * - * @param passWdLow: password low 32 bits pointer to store value - * @param passWdHigh: password high 32 bits pointer to store value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh) -{ - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE); - cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS); - cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN); -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]); - - if (aes[0] != EF_CTRL_SF_AES_NONE) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN, 1); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE); - sign[0] = (EF_Ctrl_Sign_Type)(tmpVal2 & 0x01); - - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_CPU0_ENC_EN); - - if (tmpVal2) { - aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE); - } else { - aes[0] = EF_CTRL_SF_AES_NONE; - } -} - -/****************************************************************************/ /** - * @brief Analog Trim parity calculate - * - * @param val: Value of efuse trim data - * @param len: Length of bit to calculate - * - * @return Parity bit value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) -{ - uint8_t cnt = 0; - uint8_t i = 0; - - for (i = 0; i < len; i++) { - if (val & (1 << i)) { - cnt++; - } - } - - return cnt & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse write analog trim - * - * @param index: index of analog trim - * @param trim: trim value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (index == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0, trim); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read analog trim - * - * @param index: index of analog trim - * @param trim: trim value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (index == 0) { - *trim = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - } -} - -/****************************************************************************/ /** - * @brief Efuse read RC32M trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - trim->trimRc32mCodeFrExt = (tmpVal >> 10) & 0xff; - trim->trimRc32mCodeFrExtParity = (tmpVal >> 18) & 0x01; - trim->trimRc32mExtCodeEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32K trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_ANA_TRIM_0); - trim->trimRc32kCodeFrExt = (tmpVal >> 20) & 0x3ff; - trim->trimRc32kCodeFrExtParity = (tmpVal >> 30) & 0x01; - trim->trimRc32kExtCodeEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read TSEN trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - trim->tsenRefcodeCornerEn = tmpVal & 0x01; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - trim->tsenRefcodeCorner = tmpVal & 0xfff; - trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; - - trim->tsenRefcodeCornerVersion = 0; -} - -/****************************************************************************/ /** - * @brief Efuse read ADC Gain trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - trim->adcGainCoeff = (tmpVal >> 1) & 0xfff; - trim->adcGainCoeffParity = (tmpVal >> 13) & 0x01; - trim->adcGainCoeffEn = (tmpVal >> 14) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write software usage - * - * @param index: index of software usage - * @param usage: usage value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) -{ - /* switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (index == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param usage: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (index == 0) { - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param program: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index == 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write MAC address - * - * @param mac[6]: MAC address buffer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse Ctrl get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[8]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0; - uint32_t cnt = 0; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - BL_WRWD_TO_BYTEP(machigh, tmpVal); - - /* Get original parity */ - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - - /* Check parity */ - for (i = 0; i < 8; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == (tmpVal & 0x3f)) { - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[7]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - machigh[2] = (tmpVal >> 16) & 0xff; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for MAC address - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_MAC_Address(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Whether a value bits is all zero - * - * @param val: value to check - * @param start: start bit - * @param len: total length of bits to check - * - * @return 1 for all bits zero 0 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) -{ - uint32_t mask = 0; - - val = (val >> start); - - if (len >= 32) { - mask = 0xffffffff; - } else { - mask = (1 << len) - 1; - } - - if ((val & mask) == 0) { - return 1; - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief Whether MAC address slot is empty - * - * @param slot: MAC address slot - * @param reload: whether reload to check - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff; - uint32_t part1Empty = 0, part2Empty = 0; - - if (slot == 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); - } else if (slot == 2) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } - - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32)); - part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22)); - - return (part1Empty && part2Empty); -} - -/****************************************************************************/ /** - * @brief Efuse write optional MAC address - * - * @param slot: MAC address slot - * @param mac[8]: MAC address buffer - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal = 0; - uint32_t i = 0; - uint32_t cnt = 0; - - if (slot >= 3) { - return ERROR; - } - - if (slot == 2) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - } else { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - } - - /* The low 32 bits */ - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, BL_RDWD_FRM_BYTEP(maclow)); - } - - /* The high 32 bits */ - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, BL_RDWD_FRM_BYTEP(machigh)); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1, BL_RDWD_FRM_BYTEP(machigh)); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, BL_RDWD_FRM_BYTEP(machigh)); - } - - cnt = 0; - for (i = 0; i < 8; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - cnt &= 0x3f; - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - if (slot == 0) { - tmpVal |= (cnt << 0); - } else if (slot == 1) { - tmpVal |= (cnt << 6); - } else if (slot == 2) { - tmpVal |= (cnt << 12); - } - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2, tmpVal); - - if (program) { - if (slot == 2) { - EF_Ctrl_Program_Efuse_0(); - } else { - EF_Ctrl_Program_Efuse_0(); - } - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read optional MAC address - * - * @param slot: MAC address slot - * @param mac[8]: MAC address buffer - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal = 0; - uint32_t i = 0; - uint32_t cnt = 0; - uint32_t crc = 0; - - if (slot >= 3) { - return ERROR; - } - - /* Trigger read data from efuse */ - if (reload) { - if (slot == 2) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } else { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - } - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W0); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - } - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W1); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } - BL_WRWD_TO_BYTEP(machigh, tmpVal); - - /* Get original parity */ - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - if (slot == 0) { - crc = ((tmpVal >> 0) & 0x3f); - } else if (slot == 1) { - crc = ((tmpVal >> 6) & 0x3f); - } else if (slot == 2) { - crc = ((tmpVal >> 12) & 0x3f); - } - - /* Check parity */ - for (i = 0; i < 8; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - if ((cnt & 0x3f) == crc) { - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read chip ID - * - * @param chipID[8]: Chip ID buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) -{ - return EF_Ctrl_Read_MAC_Address(chipID); -} - -/****************************************************************************/ /** - * @brief Efuse get chip PID&&VID - * - * @param pid[1]: Chip PID - * @param vid[1]: Chip VID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W3); - pid[0] = (uint16_t)(tmpVal & 0xFFFF); - vid[0] = (uint16_t)(tmpVal >> 16); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse get customer PID&&VID - * - * @param pid[1]: Customer PID - * @param vid[1]: Customer VID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_4_W2); - pid[0] = (uint16_t)(tmpVal & 0xFFFF); - vid[0] = (uint16_t)(tmpVal >> 16); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read device info - * - * @param deviceInfo: Device info pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo) -{ - uint32_t tmpVal; - uint32_t *p = (uint32_t *)deviceInfo; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W2); - *p = tmpVal; -} - -/****************************************************************************/ /** - * @brief Whether Capcode is empty - * - * @param slot: Cap code slot - * @param reload: Whether reload - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp = 0xffffffff; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7)); - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - return (EF_Ctrl_Is_All_Bits_Zero(tmp, 9, 7)); - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - return (EF_Ctrl_Is_All_Bits_Zero(tmp, 25, 7)); - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief Efuse write Cap code - * - * @param slot: Cap code slot - * @param code: Cap code value - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program) -{ - uint32_t tmp; - uint8_t trim; - - if (slot >= 3) { - return ERROR; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - EF_CTRL_LOAD_BEFORE_READ_R0; - - trim = (code << 1); - trim |= (1 << 0); - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp | (trim << 25)); - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 9)); - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp | (trim << 25)); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - while (SET == EF_Ctrl_Busy()) - ; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read Cap code - * - * @param slot: Cap code slot - * @param code: Cap code pointer - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload) -{ - uint32_t tmp; - uint8_t trim = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - trim = (tmp >> 25) & 0x7f; - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - trim = (tmp >> 9) & 0x7f; - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - trim = (tmp >> 25) & 0x7f; - } - - if (trim & 0x01) { - *code = trim >> 1; - return SUCCESS; - } - return ERROR; -} - -/****************************************************************************/ /** - * @brief Whether power offset slot is empty - * - * @param slot: Power offset code slot - * @param reload: Whether reload - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp1 = 0xffffffff; - uint32_t part1Empty = 0, part2Empty = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9)); - part2Empty = 1; - } else if (slot == 1) { - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 9)); - part2Empty = 1; - } else if (slot == 2) { - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 16, 9)); - part2Empty = 1; - } - - return (part1Empty && part2Empty); -} - -/****************************************************************************/ /** - * @brief Efuse write power offset - * - * @param slot: Power offset slot - * @param pwrOffset[2]: Power offset value array - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program) -{ - uint32_t tmp = 0; - uint32_t k = 0; - uint32_t Value = 0; - - if (slot >= 3) { - return ERROR; - } - - for (k = 0; k < 2; k++) { - /* Use 4 bits as signed value */ - if (pwrOffset[k] > 7) { - pwrOffset[k] = 7; - } - if (pwrOffset[k] < -8) { - pwrOffset[k] = -8; - } - Value += (uint32_t)(pwrOffset[k] & 0x0f) << (k * 4); - } - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - tmp |= (Value << 17); - tmp |= (1 << 16); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3, tmp); - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - tmp |= (Value << 1); - tmp |= (1 << 0); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp); - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - tmp |= (Value << 17); - tmp |= (1 << 16); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3, tmp); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - - while (SET == EF_Ctrl_Busy()) - ; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read poweroffset value - * - * @param slot: Power offset slot - * @param pwrOffset[2]: Power offset array - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload) -{ - uint32_t pwrOffsetValue = 0; - uint32_t tmp = 0, k; - uint8_t en = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_5_W3); - en = (tmp >> 16) & 0x01; - pwrOffsetValue = (tmp >> 17) & 0xff; - } else if (slot == 1) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - en = (tmp >> 0) & 0x01; - pwrOffsetValue = (tmp >> 1) & 0xff; - } else if (slot == 2) { - tmp = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_3_W3); - en = (tmp >> 16) & 0x01; - pwrOffsetValue = (tmp >> 17) & 0xff; - } - - if (en) { - for (k = 0; k < 2; k++) { - tmp = (pwrOffsetValue >> (k * 4)) & 0x0f; - if (tmp >= 8) { - pwrOffset[k] = tmp - 16; - } else { - pwrOffset[k] = tmp; - } - } - return SUCCESS; - } - return ERROR; -} - -/****************************************************************************/ /** - * @brief Efuse write AES key - * - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - - if (index > 5) { - return; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Every key is 4 words len*/ - BL702_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read AES key from specified region and index - * - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - - if (index > 5) { - return; - } - - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R0; - - /* Every key is 4 words len*/ - BL702_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for aes key - * - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if (index > 5) { - return; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index <= 3) { - tmpVal |= (1 << (index + 19)); - } else { - tmpVal |= (1 << (index + 19)); - tmpVal |= (1 << (index - 4 + 13)); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for aes key - * - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if (index > 5) { - return; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 26)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Program data to efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Add delay for CLK to be stable */ - BL702_Delay_US(4); - - BL702_MemCpy4(pEfuseStart0 + index, data, len); - - EF_Ctrl_Program_Efuse_0(); -} - -/****************************************************************************/ /** - * @brief Read data from efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - BL702_MemCpy4(data, pEfuseStart0 + index, len); -} - -/****************************************************************************/ /** - * @brief Clear efuse data register - * - * @param index: index of efuse in word - * @param len: data length - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - uint32_t i = 0; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart0[index + i] = 0; - } -} -#endif - -/****************************************************************************/ /** - * @brief efuse ctrl crc enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); - BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); - BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc busy status - * - * @param None - * - * @return DISABLE or ENABLE - * -*******************************************************************************/ -BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); -} - -/****************************************************************************/ /** - * @brief efuse ctrl set golden value - * - * @param goldenValue: Crc golden value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) -{ - BL_WR_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc result - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Crc_Result(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL702_Peripheral_Driver */ diff --git a/drivers/soc/bl702/std/src/bl702_hbn.c b/drivers/soc/bl702/std/src/bl702_hbn.c index 429e2fb8..ee7fc708 100644 --- a/drivers/soc/bl702/std/src/bl702_hbn.c +++ b/drivers/soc/bl702/std/src/bl702_hbn.c @@ -36,7 +36,7 @@ #include "bl702_hbn.h" #include "bl702_glb.h" -#include "bl702_xip_sflash.h" +#include "bflb_xip_sflash.h" /** @addtogroup BL702_Peripheral_Driver * @{ @@ -198,25 +198,26 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) * @return None * *******************************************************************************/ -void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg) { - SPI_Flash_Cfg_Type bhFlashCfg; + spi_flash_cfg_type bhFlashCfg; if (flashCfg == NULL) { /* fix this some time */ /* SFlash_Cache_Flush(); */ - XIP_SFlash_Read_Via_Cache_Need_Lock(BL702_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type)); + bflb_xip_sflash_read_via_cache_need_lock(BL702_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), + sizeof(spi_flash_cfg_type), 0, 0); /* fix this some time */ /* SFlash_Cache_Flush(); */ - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - SFlash_Reset_Continue_Read(&bhFlashCfg); + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + bflb_sflash_reset_continue_read(&bhFlashCfg); } else { - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - SFlash_Reset_Continue_Read(flashCfg); + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + bflb_sflash_reset_continue_read(flashCfg); } - SFlash_Powerdown(); + bflb_sflash_powerdown(); } /****************************************************************************/ /** diff --git a/drivers/soc/bl702/std/src/bl702_psram.c b/drivers/soc/bl702/std/src/bl702_psram.c deleted file mode 100644 index 935563e3..00000000 --- a/drivers/soc/bl702/std/src/bl702_psram.c +++ /dev/null @@ -1,764 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_psram.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl702_psram.h" -#include "bl702_l1c.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup PSRAM - * @{ - */ - -/** @defgroup PSRAM_Private_Macros - * @{ - */ - -/*@} end of group PSRAM_Private_Macros */ - -/** @defgroup PSRAM_Private_Types - * @{ - */ - -/*@} end of group PSRAM_Private_Types */ - -/** @defgroup PSRAM_Private_Variables - * @{ - */ - -/*@} end of group PSRAM_Private_Variables */ - -/** @defgroup PSRAM_Global_Variables - * @{ - */ - -/*@} end of group PSRAM_Global_Variables */ - -/** @defgroup PSRAM_Private_Fun_Declaration - * @{ - */ - -/*@} end of group PSRAM_Private_Fun_Declaration */ - -/** @defgroup PSRAM_Private_Functions - * @{ - */ - -/*@} end of group PSRAM_Private_Functions */ - -/** @defgroup PSRAM_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init serial psram control interface - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param cmdsCfg: Serial Serial Flash controller configuration pointer - * @param sfCtrlPsramCfg: Serial psram controller configuration pointer - * - * @return None - * -*******************************************************************************/ -//#ifndef BFLB_USE_ROM_DRIVER -//__WEAK -void ATTR_TCM_SECTION Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) -{ - SF_Ctrl_Psram_Init(sfCtrlPsramCfg); - SF_Ctrl_Cmds_Set(cmdsCfg); - - Psram_SetDriveStrength(psramCfg); - Psram_SetBurstWrap(psramCfg); -} -//#endif - -/****************************************************************************/ /** - * @brief Read psram register - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param regValue: Register value pointer to store data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) -{ - /* Check the parameters */ - CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode)); - - uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type psramCmd; - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) { - psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - } - - psramCmd.cmdBuf[0] = (psramCfg->readRegCmd) << 24; - psramCmd.rwFlag = SF_CTRL_READ; - psramCmd.addrSize = 3; - psramCmd.dummyClks = psramCfg->readRegDmyClk; - psramCmd.nbData = 1; - - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - BL702_MemCpy(regValue, psramCtrlBuf, 1); -} -#endif - -/****************************************************************************/ /** - * @brief Write psram register - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param regValue: Register value pointer storing data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) -{ - /* Check the parameters */ - CHECK_PARAM(IS_PSRAM_CTRL_MODE(psramCfg->ctrlMode)); - - uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type psramCmd; - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - BL702_MemCpy(psramCtrlBuf, regValue, 1); - - if (psramCfg->ctrlMode == PSRAM_QPI_CTRL_MODE) { - psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - } - - psramCmd.cmdBuf[0] = (psramCfg->writeRegCmd) << 24; - psramCmd.rwFlag = SF_CTRL_WRITE; - psramCmd.addrSize = 3; - psramCmd.nbData = 1; - - SF_Ctrl_SendCmd(&psramCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set psram driver strength - * - * @param psramCfg: Serial psram parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg) -{ - uint32_t stat = 0; - /* Check the parameters */ - CHECK_PARAM(IS_PSRAM_DRIVE_STRENGTH(psramCfg->driveStrength)); - - Psram_ReadReg(psramCfg, (uint8_t *)&stat); - - if ((stat & 0x3) == psramCfg->driveStrength) { - return SUCCESS; - } - - stat &= (~0x3); - stat |= psramCfg->driveStrength; - - Psram_WriteReg(psramCfg, (uint8_t *)&stat); - /* Wait for write done */ - - Psram_ReadReg(psramCfg, (uint8_t *)&stat); - - if ((stat & 0x3) == psramCfg->driveStrength) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Set psram burst wrap size - * - * @param psramCfg: Serial psram parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg) -{ - uint32_t stat = 0; - /* Check the parameters */ - CHECK_PARAM(IS_PSRAM_BURST_LENGTH(psramCfg->burstLength)); - - Psram_ReadReg(psramCfg, (uint8_t *)&stat); - - if (((stat >> 5) & 0x3) == psramCfg->burstLength) { - return SUCCESS; - } - - stat &= (~(0x3 << 5)); - stat |= (psramCfg->burstLength << 5); - - Psram_WriteReg(psramCfg, (uint8_t *)&stat); - /* Wait for write done */ - - Psram_ReadReg(psramCfg, (uint8_t *)&stat); - - if (((stat >> 5) & 0x3) == psramCfg->burstLength) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Get psram ID - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param data: Data pointer to store read data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data) -{ - uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type psramCmd; - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - psramCmd.cmdBuf[0] = (psramCfg->readIdCmd) << 24; - psramCmd.rwFlag = SF_CTRL_READ; - psramCmd.addrSize = 3; - psramCmd.dummyClks = psramCfg->readIdDmyClk; - psramCmd.nbData = 8; - - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - BL702_MemCpy(data, psramCtrlBuf, 8); -} -#endif - -/****************************************************************************/ /** - * @brief Psram enter quad mode - * - * @param psramCfg: Serial psram parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg) -{ - SF_Ctrl_Cmd_Cfg_Type psramCmd; - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - psramCmd.cmdBuf[0] = (psramCfg->enterQuadModeCmd) << 24; - psramCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Psram exit quad mode - * - * @param psramCfg: Serial psram parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg) -{ - SF_Ctrl_Cmd_Cfg_Type psramCmd; - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - - psramCmd.cmdBuf[0] = (psramCfg->exitQuadModeCmd) << 24; - psramCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Psram toggle burst length - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param ctrlMode: Psram ctrl mode type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) -{ - SF_Ctrl_Cmd_Cfg_Type psramCmd; - /* Check the parameters */ - CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode)); - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - if (ctrlMode == PSRAM_QPI_CTRL_MODE) { - psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - } - - psramCmd.cmdBuf[0] = (psramCfg->burstToggleCmd) << 24; - psramCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Psram software reset - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param ctrlMode: Psram ctrl mode type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) -{ - SF_Ctrl_Cmd_Cfg_Type psramCmd; - /* Check the parameters */ - CHECK_PARAM(IS_PSRAM_CTRL_MODE(ctrlMode)); - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - if (ctrlMode == PSRAM_QPI_CTRL_MODE) { - psramCmd.cmdMode = SF_CTRL_CMD_4_LINES; - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - } - - /* Reset enable */ - psramCmd.cmdBuf[0] = (psramCfg->resetEnableCmd) << 24; - /* rwFlag don't care */ - psramCmd.rwFlag = SF_CTRL_READ; - /* Wait for write done */ - - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - /* Reset */ - psramCmd.cmdBuf[0] = (psramCfg->resetCmd) << 24; - /* rwFlag don't care */ - psramCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - BL702_Delay_US(50); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Psram set IDbus config - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param ioMode: Psram ctrl mode type - * @param addr: Address to read/write - * @param len: Data length to read/write - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len) -{ - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type psramCmd; - uint8_t cmdValid = 1; - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode)); - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - - /* read mode cache set */ - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = psramCfg->fReadCmd; - dummyClks = psramCfg->fReadDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = psramCfg->fReadQuadCmd; - dummyClks = psramCfg->fReadQuadDmyClk; - } else { - return ERROR; - } - - /* prepare command */ - psramCmd.rwFlag = SF_CTRL_READ; - psramCmd.addrSize = 3; - psramCmd.cmdBuf[0] = (cmd << 24) | addr; - psramCmd.dummyClks = dummyClks; - psramCmd.nbData = len; - SF_Ctrl_Psram_Read_Icache_Set(&psramCmd, cmdValid); - - /* write mode cache set */ - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = psramCfg->writeCmd; - } else if (SF_CTRL_QIO_MODE == ioMode) { - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = psramCfg->quadWriteCmd; - } else { - return ERROR; - } - - dummyClks = 0; - - /* prepare command */ - psramCmd.rwFlag = SF_CTRL_WRITE; - psramCmd.addrSize = 3; - psramCmd.cmdBuf[0] = (cmd << 24) | addr; - psramCmd.dummyClks = dummyClks; - psramCmd.nbData = len; - SF_Ctrl_Psram_Write_Icache_Set(&psramCmd, cmdValid); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Set cache write to psram with cache - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param ioMode: Psram controller interface mode - * @param wtEn: Psram cache write through enable - * @param wbEn: Psram cache write back enable - * @param waEn: Psram cache write allocate enable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, - BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) -{ - BL_Err_Type stat; - - /* Cache now only support 32 bytes read */ - stat = Psram_Set_IDbus_Cfg(psramCfg, ioMode, 0, 32); - - if (SUCCESS != stat) { - return stat; - } - - L1C_Cache_Write_Set(wtEn, wbEn, waEn); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write psram one region - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param ioMode: Write mode: SPI mode or QPI mode - * @param addr: Start address to be write - * @param data: Data pointer to be write - * @param len: Data length to be write - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_Write(SPI_Psram_Cfg_Type *psramCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t burstLen = 512; - uint8_t cmd; - SF_Ctrl_Cmd_Cfg_Type psramCmd; - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode)); - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = psramCfg->writeCmd; - } else if (SF_CTRL_QIO_MODE == ioMode) { - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = psramCfg->quadWriteCmd; - } else { - return ERROR; - } - - /* Prepare command */ - psramCmd.rwFlag = SF_CTRL_WRITE; - psramCmd.addrSize = 3; - - if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) { - burstLen = 16; - } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) { - burstLen = 32; - } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) { - burstLen = 64; - } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) { - burstLen = 512; - } - - for (i = 0; i < len;) { - /* Get current programmed length within page size */ - curLen = burstLen - addr % burstLen; - - if (curLen > len - i) { - curLen = len - i; - } - - /* Prepare command */ - BL702_MemCpy_Fast(psramCtrlBuf, data, curLen); - psramCmd.cmdBuf[0] = (cmd << 24) | (addr); - psramCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&psramCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from psram - * - * @param psramCfg: Serial psram parameter configuration pointer - * @param ioMode: IoMode: psram controller interface mode - * @param addr: Psram read start address - * @param data: Data pointer to store data read from psram - * @param len: Data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION Psram_Read(SPI_Psram_Cfg_Type *psramCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const psramCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint32_t burstLen = 512; - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type psramCmd; - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_IO_TYPE(ioMode)); - - if (((uint32_t)&psramCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&psramCmd, 0, sizeof(psramCmd) / 4); - } else { - BL702_MemSet(&psramCmd, 0, sizeof(psramCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = psramCfg->fReadCmd; - dummyClks = psramCfg->fReadDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - psramCmd.addrMode = SF_CTRL_ADDR_4_LINES; - psramCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = psramCfg->fReadQuadCmd; - dummyClks = psramCfg->fReadQuadDmyClk; - } else { - return ERROR; - } - - /* Prepare command */ - psramCmd.rwFlag = SF_CTRL_READ; - psramCmd.addrSize = 3; - psramCmd.dummyClks = dummyClks; - - if (psramCfg->burstLength == PSRAM_BURST_LENGTH_16_BYTES) { - burstLen = 16; - } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_32_BYTES) { - burstLen = 32; - } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_64_BYTES) { - burstLen = 64; - } else if (psramCfg->burstLength == PSRAM_BURST_LENGTH_512_BYTES) { - burstLen = 512; - } - - /* Read data */ - for (i = 0; i < len;) { - /* Prepare command */ - psramCmd.cmdBuf[0] = (cmd << 24) | (addr); - curLen = burstLen - addr % burstLen; - - if (curLen > len - i) { - curLen = len - i; - } - - if (curLen >= FLASH_CTRL_BUF_SIZE) { - curLen = FLASH_CTRL_BUF_SIZE; - psramCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - psramCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&psramCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - } - - BL702_MemCpy_Fast(data, psramCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} -#endif - -/*@} end of group PSRAM_Public_Functions */ - -/*@} end of group PSRAM */ - -/*@} end of group BL702_Peripheral_Driver */ diff --git a/drivers/soc/bl702/std/src/bl702_romapi.c b/drivers/soc/bl702/std/src/bl702_romapi.c index 8611946f..7372d8b7 100644 --- a/drivers/soc/bl702/std/src/bl702_romapi.c +++ b/drivers/soc/bl702/std/src/bl702_romapi.c @@ -487,283 +487,292 @@ __ALWAYS_INLINE ATTR_CLOCK_SECTION /******************************************************************************/ __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) + int + bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_State_Save(pFlashCfg, offset); + return RomDriver_XIP_SFlash_State_Save(p_flash_cfg, offset); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset) + int + bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_State_Restore(p_flash_cfg, io_mode, offset); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr) + int + bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg, ioMode, startaddr, endaddr); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_Erase_Need_Lock(p_flash_cfg, io_mode, startaddr, startaddr+len-1); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) + int + bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg, ioMode, addr, data, len); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_Write_Need_Lock(p_flash_cfg, io_mode, addr, data, len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) + int + bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg, ioMode, addr, data, len); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_Read_Need_Lock(p_flash_cfg, io_mode, addr, data, len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) + int + bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg, ioMode, data); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(p_flash_cfg, io_mode, data); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) + int + bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg, ioMode, data); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(p_flash_cfg, io_mode, data); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen) + int + bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t id_len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg, ioMode, data, idLen); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(p_flash_cfg, io_mode, data, id_len); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) + int + bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank) { + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len); } #endif -__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len) +__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_xip_sflash_read_with_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *dst, int len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Read_With_Lock(pFlashCfg, ioMode, addr, dst, len); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_Read_With_Lock(p_flash_cfg, io_mode, addr, dst, len); } -__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src, int len) +__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_xip_sflash_write_with_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *src, int len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Write_With_Lock(pFlashCfg, ioMode, addr, src, len); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_Write_With_Lock(p_flash_cfg, io_mode, addr, src, len); } -__ALWAYS_INLINE ATTR_TCM_SECTION int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len) +__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_xip_sflash_erase_with_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, int len, uint8_t group, uint8_t bank) { - return RomDriver_XIP_SFlash_Erase_With_Lock(pFlashCfg, ioMode, addr, len); + uint8_t io_mode = p_flash_cfg->io_mode & 0xf; + return RomDriver_XIP_SFlash_Erase_With_Lock(p_flash_cfg, io_mode, addr, len); } /******************************************************************************/ /******************************************************************************/ -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg) { - RomDriver_SFlash_Init(pSfCtrlCfg); + RomDriver_SFlash_Init(p_sf_ctrl_cfg); } -__ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) +__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_sflash_setspimode(uint8_t mode) { return RomDriver_SFlash_SetSPIMode(mode); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) + int + bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Read_Reg(flashCfg, regIndex, regValue, regLen); + return RomDriver_SFlash_Read_Reg(flash_cfg, reg_index, reg_value, reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) + int + bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Write_Reg(flashCfg, regIndex, regValue, regLen); + return RomDriver_SFlash_Write_Reg(flash_cfg, reg_index, reg_value, reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) + int + bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t readRegCmd, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg, readRegCmd, regValue, regLen); + return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg, readRegCmd, reg_value, reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) + int + bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t writeRegCmd, uint8_t *reg_value, uint8_t reg_len) { - return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg, writeRegCmd, regValue, regLen); + return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg, writeRegCmd, reg_value, reg_len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Sts_Type - SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) + int + bflb_sflash_busy(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Busy(flashCfg); + return RomDriver_SFlash_Busy(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) + int + bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Write_Enable(flashCfg); + return RomDriver_SFlash_Write_Enable(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) + int + bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Qspi_Enable(flashCfg); + return RomDriver_SFlash_Qspi_Enable(flash_cfg); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg) { - RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg); + RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) + int + bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Chip_Erase(flashCfg); + return RomDriver_SFlash_Chip_Erase(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) + int + bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t secNum) { - return RomDriver_SFlash_Sector_Erase(flashCfg, secNum); + return RomDriver_SFlash_Sector_Erase(flash_cfg, secNum); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) + int + bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blkNum) { - return RomDriver_SFlash_Blk32_Erase(flashCfg, blkNum); + return RomDriver_SFlash_Blk32_Erase(flash_cfg, blkNum); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) + int + bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blkNum) { - return RomDriver_SFlash_Blk64_Erase(flashCfg, blkNum); + return RomDriver_SFlash_Blk64_Erase(flash_cfg, blkNum); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) + int + bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t startaddr, uint32_t endaddr) { - return RomDriver_SFlash_Erase(flashCfg, startaddr, endaddr); + return RomDriver_SFlash_Erase(flash_cfg, startaddr, endaddr); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) + int + bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len) { - return RomDriver_SFlash_Program(flashCfg, ioMode, addr, data, len); + return RomDriver_SFlash_Program(flash_cfg, io_mode, addr, data, len); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len) { - RomDriver_SFlash_GetUniqueId(data, idLen); + RomDriver_SFlash_GetUniqueId(data, id_len); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data) { - RomDriver_SFlash_GetJedecId(flashCfg, data); + RomDriver_SFlash_GetJedecId(flash_cfg, data); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_GetDeviceId(uint8_t *data) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr) { RomDriver_SFlash_GetDeviceId(data); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Powerdown(void) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_powerdown(void) { RomDriver_SFlash_Powerdown(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg) { - RomDriver_SFlash_Releae_Powerdown(flashCfg); + RomDriver_SFlash_Releae_Powerdown(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) + int + bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flash_cont_read, uint8_t bank) { - return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg, flashContRead); + return RomDriver_SFlash_Restore_From_Powerdown(p_flash_cfg, flash_cont_read); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg) { - RomDriver_SFlash_SetBurstWrap(flashCfg); + RomDriver_SFlash_SetBurstWrap(flash_cfg); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg) { - RomDriver_SFlash_DisableBurstWrap(flashCfg); + RomDriver_SFlash_DisableBurstWrap(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) + int + bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Software_Reset(flashCfg); + return RomDriver_SFlash_Software_Reset(flash_cfg); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg) { - return RomDriver_SFlash_Reset_Continue_Read(flashCfg); + return RomDriver_SFlash_Reset_Continue_Read(flash_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) + int + bflb_sflash_set_idbus_cfg(spi_flash_cfg_type *flash_cfg, + uint8_t io_mode, uint8_t contRead, uint32_t addr, uint32_t len, uint8_t bank) { - return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, addr, len); + return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg, io_mode, contRead, addr, len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) + int + bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t contRead, uint8_t bank) { - return RomDriver_SFlash_IDbus_Read_Enable(flashCfg, ioMode, contRead); + return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg, io_mode, contRead); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) + int + bflb_sflash_cache_read_enable(spi_flash_cfg_type *flash_cfg, + uint8_t io_mode, uint8_t contRead, uint8_t wayDisable) { - return RomDriver_SFlash_Cache_Read_Enable(flashCfg, ioMode, contRead, wayDisable); + return RomDriver_SFlash_Cache_Read_Enable(flash_cfg, io_mode, contRead, wayDisable); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SFlash_Cache_Read_Disable(void) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_cache_read_disable(void) { RomDriver_SFlash_Cache_Read_Disable(); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) + int + bflb_sflash_read(spi_flash_cfg_type *flash_cfg, + uint8_t io_mode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) { - return RomDriver_SFlash_Read(flashCfg, ioMode, contRead, addr, data, len); + return RomDriver_SFlash_Read(flash_cfg, io_mode, contRead, addr, data, len); } /******************************************************************************/ @@ -775,9 +784,9 @@ __ALWAYS_INLINE ATTR_TCM_SECTION return RomDriver_L1C_Cache_Enable_Set(wayDisable); } -__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en) { - RomDriver_L1C_Cache_Write_Set(wtEn, wbEn, waEn); + RomDriver_L1C_Cache_Write_Set(wt_en, wb_en, wa_en); } #if 0 @@ -829,284 +838,288 @@ __ALWAYS_INLINE ATTR_TCM_SECTION /******************************************************************************/ /******************************************************************************/ -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg) { RomDriver_SF_Ctrl_Enable(cfg); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) +void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg) { - RomDriver_SF_Ctrl_Psram_Init(sfCtrlPsramCfg); + RomDriver_SF_Ctrl_Psram_Init(psram_cfg); } #endif __ALWAYS_INLINE ATTR_TCM_SECTION uint8_t - SF_Ctrl_Get_Clock_Delay(void) + bflb_sf_ctrl_get_clock_delay(void) { return RomDriver_SF_Ctrl_Get_Clock_Delay(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Clock_Delay(uint8_t delay) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_set_clock_delay(uint8_t delay) { RomDriver_SF_Ctrl_Set_Clock_Delay(delay); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel) { - RomDriver_SF_Ctrl_Cmds_Set(cmdsCfg); + RomDriver_SF_Ctrl_Cmds_Set(cmds_cfg); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_set_owner(uint8_t owner) { RomDriver_SF_Ctrl_Set_Owner(owner); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Disable(void) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_disable(void) { RomDriver_SF_Ctrl_Disable(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_select_pad(uint8_t sel) { RomDriver_SF_Ctrl_Select_Pad(sel); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Bank(SF_Ctrl_Select sel) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_select_bank(uint8_t sel) { RomDriver_SF_Ctrl_Select_Bank(sel); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_BE(void) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_enable_be(void) { RomDriver_SF_Ctrl_AES_Enable_BE(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable_LE(void) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_enable_le(void) { RomDriver_SF_Ctrl_AES_Enable_LE(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, - uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, + uint8_t hw_key, uint32_t start_addr, uint32_t end_addr, uint8_t locked) { - RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hwKey, startAddr, endAddr, locked); + RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hw_key, start_addr, end_addr, locked); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type) { - RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType); + RomDriver_SF_Ctrl_AES_Set_Key(region, key, key_type); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type) { - RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType); + RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, key_type); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset) { - RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addrOffset); + RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addr_offset); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset) { - RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addrOffset); + RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addr_offset); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Enable(void) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_enable(void) { RomDriver_SF_Ctrl_AES_Enable(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_AES_Disable(void) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_disable(void) { RomDriver_SF_Ctrl_AES_Disable(); } __ALWAYS_INLINE ATTR_TCM_SECTION uint8_t - SF_Ctrl_Is_AES_Enable(void) + bflb_sf_ctrl_is_aes_enable(void) { return RomDriver_SF_Ctrl_Is_AES_Enable(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank) { - RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset); + RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset); } __ALWAYS_INLINE ATTR_TCM_SECTION uint32_t - SF_Ctrl_Get_Flash_Image_Offset(void) + bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank) { return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_select_clock(uint8_t sahb_type) { - RomDriver_SF_Ctrl_Select_Clock(sahbType); + RomDriver_SF_Ctrl_Select_Clock(sahb_type); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg) { RomDriver_SF_Ctrl_SendCmd(cfg); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_flash_read_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) { - RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg, cmdValid); + RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg, cmd_valid); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_psram_write_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) { - RomDriver_SF_Ctrl_Psram_Write_Icache_Set(cfg, cmdValid); + RomDriver_SF_Ctrl_Psram_Write_Icache_Set(cfg, cmd_valid); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_psram_read_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid) { - RomDriver_SF_Ctrl_Psram_Read_Icache_Set(cfg, cmdValid); + RomDriver_SF_Ctrl_Psram_Read_Icache_Set(cfg, cmd_valid); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Sts_Type - SF_Ctrl_GetBusyState(void) + uint8_t + bflb_sf_ctrl_get_busy_state(void) { return RomDriver_SF_Ctrl_GetBusyState(); } -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) +__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin) { - RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin); + return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin); } #if 0 -__ALWAYS_INLINE ATTR_TCM_SECTION void SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin) { - RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin); + RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin); } #endif __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) + int + bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) { - return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg); + return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg); } #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -void SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) +void bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default) { - RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); + RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg, restore_default); } #endif __ALWAYS_INLINE ATTR_TCM_SECTION uint32_t - SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg) + bflb_sf_cfg_flash_identify(uint8_t callFromFlash, uint8_t flash_pin_cfg, uint8_t restore_default, + spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) { - return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg); + uint8_t auto_scan = 0; + uint8_t flash_pin = 0; + auto_scan = ((flash_pin_cfg >> 7) & 1); + flash_pin = (flash_pin_cfg & 0x7F); + return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, auto_scan, flash_pin, restore_default, p_flash_cfg); } /******************************************************************************/ /******************************************************************************/ #if 0 __ALWAYS_INLINE ATTR_TCM_SECTION -void Psram_Init(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) +void bflb_psram_Init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg, struct sf_ctrl_psram_cfg *psram_cfg) { - RomDriver_Psram_Init(psramCfg, cmdsCfg, sfCtrlPsramCfg); + RomDriver_Psram_Init(psram_cfg, cmds_cfg, psram_cfg); } #endif -__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value) { - RomDriver_Psram_ReadReg(psramCfg, regValue); + RomDriver_Psram_ReadReg(psram_cfg, reg_value); } -__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_WriteReg(SPI_Psram_Cfg_Type *psramCfg, uint8_t *regValue) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value) { - RomDriver_Psram_WriteReg(psramCfg, regValue); + RomDriver_Psram_WriteReg(psram_cfg, reg_value); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_SetDriveStrength(SPI_Psram_Cfg_Type *psramCfg) + int + bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg) { - return RomDriver_Psram_SetDriveStrength(psramCfg); + return RomDriver_Psram_SetDriveStrength(psram_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_SetBurstWrap(SPI_Psram_Cfg_Type *psramCfg) + int + bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg) { - return RomDriver_Psram_SetBurstWrap(psramCfg); + return RomDriver_Psram_SetBurstWrap(psram_cfg); } -__ALWAYS_INLINE ATTR_TCM_SECTION void Psram_ReadId(SPI_Psram_Cfg_Type *psramCfg, uint8_t *data) +__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data) { - RomDriver_Psram_ReadId(psramCfg, data); + RomDriver_Psram_ReadId(psram_cfg, data); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_EnterQuadMode(SPI_Psram_Cfg_Type *psramCfg) + int + bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg) { - return RomDriver_Psram_EnterQuadMode(psramCfg); + return RomDriver_Psram_EnterQuadMode(psram_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_ExitQuadMode(SPI_Psram_Cfg_Type *psramCfg) + int + bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg) { - return RomDriver_Psram_ExitQuadMode(psramCfg); + return RomDriver_Psram_ExitQuadMode(psram_cfg); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_ToggleBurstLength(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) + int + bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode) { - return RomDriver_Psram_ToggleBurstLength(psramCfg, ctrlMode); + return RomDriver_Psram_ToggleBurstLength(psram_cfg, ctrl_mode); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_SoftwareReset(SPI_Psram_Cfg_Type *psramCfg, PSRAM_Ctrl_Mode ctrlMode) + int + bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode) { - return RomDriver_Psram_SoftwareReset(psramCfg, ctrlMode); + return RomDriver_Psram_SoftwareReset(psram_cfg, ctrl_mode); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_Set_IDbus_Cfg(SPI_Psram_Cfg_Type *psramCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint32_t len) + int + bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, + uint8_t io_mode, uint32_t addr, uint32_t len) { - return RomDriver_Psram_Set_IDbus_Cfg(psramCfg, ioMode, addr, len); + return RomDriver_Psram_Set_IDbus_Cfg(psram_cfg, io_mode, addr, len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_Cache_Write_Set(SPI_Psram_Cfg_Type *psramCfg, SF_Ctrl_IO_Type ioMode, - BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn) + int + bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, + uint8_t wt_en, uint8_t wb_en, uint8_t wa_en) { - return RomDriver_Psram_Cache_Write_Set(psramCfg, ioMode, wtEn, wbEn, waEn); + return RomDriver_Psram_Cache_Write_Set(psram_cfg, io_mode, wt_en, wb_en, wa_en); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_Write(SPI_Psram_Cfg_Type *psramCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) + int + bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, + uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len) { - return RomDriver_Psram_Write(psramCfg, ioMode, addr, data, len); + return RomDriver_Psram_Write(psram_cfg, io_mode, addr, data, len); } __ALWAYS_INLINE ATTR_TCM_SECTION - BL_Err_Type - Psram_Read(SPI_Psram_Cfg_Type *psramCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) + int + bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, + uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len) { - return RomDriver_Psram_Read(psramCfg, ioMode, addr, data, len); + return RomDriver_Psram_Read(psram_cfg, io_mode, addr, data, len); } /******************************************************************************/ diff --git a/drivers/soc/bl702/std/src/bl702_sf_cfg.c b/drivers/soc/bl702/std/src/bl702_sf_cfg.c deleted file mode 100644 index a333638e..00000000 --- a/drivers/soc/bl702/std/src/bl702_sf_cfg.c +++ /dev/null @@ -1,2395 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_sf_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl702_glb.h" -#include "bl702_sf_cfg.h" -#include "bl702_xip_sflash.h" -#include "soft_crc.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_Private_Macros */ - -/** @defgroup SF_CFG_Private_Types - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; -#endif - -/*@} end of group SF_CFG_Private_Types */ - -/** @defgroup SF_CFG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16DV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */ - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80EW_16FW_32JW_32FW_32FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Issi = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x9d, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x00, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x06, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 5, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x51, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_DO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 32 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 8 / 8, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0x12, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32C = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_1635F = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx40 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x0B, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_DIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 6000, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Xtx = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x0B, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 6000, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q80L_Q80H_Q16H = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x85, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Puya_Q32H = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x85, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya40 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x68, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xA0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_DO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Boya = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0x68, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0x01, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FT_VQ80 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 8, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1440ef, - .name = "Winb_80DV_08_33", - .cfg = &flashCfg_Winb_80DV, - }, - { - .jedecID = 0x1540ef, - .name = "Winb_16DV_16_33", - .cfg = &flashCfg_Winb_16DV, - }, - { - .jedecID = 0x1640ef, - .name = "Winb_32FV_32_33", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1460ef, - .name = "Winb_80EW_08_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1560ef, - .name = "Winb_16FW_16_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1660ef, - .name = "Winb_32FW_32_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1860ef, - .name = "Winb_128FW_128_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x1680ef, - .name = "Winb_32JW_32_18", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x13605e, - .name = "Zbit_04_33", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x14605e, - .name = "Zbit_08_33", - .cfg = &flashCfg_Winb_80EW_16FW_32JW_32FW_32FV, - }, - { - .jedecID = 0x14609d, - .name = "ISSI_08_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x15609d, - .name = "ISSI_16_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x16609d, - .name = "ISSI_32_33", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x14709d, - .name = "ISSI_08_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x15709d, - .name = "ISSI_16_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x16709d, - .name = "ISSI_32_18", - .cfg = &flashCfg_Issi, - }, - { - .jedecID = 0x134051, - .name = "GD_MD04D_04_33", - .cfg = &flashCfg_Gd_Md_40D, - }, - { - .jedecID = 0x1440C8, - .name = "GD_Q08E_08_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1540C8, - .name = "GD_Q16E_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1640C8, - .name = "GD_Q32C_32_33", - .cfg = &flashCfg_Gd_Q32C, - }, - { - .jedecID = 0x1460C8, - .name = "GD_LQ08C_08_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1560C8, - .name = "GD_LE16C_16_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1660C8, - .name = "GD_LQ32D_32_18", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x1465C8, - .name = "GD_WQ80E_80_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1565C8, - .name = "GD_WQ16E_16_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1665C8, - .name = "GD_WQ32E_32_33", - .cfg = &flashCfg_Gd_LQ08C_LE16C_LQ32D_WQ32E, - }, - { - .jedecID = 0x3425C2, - .name = "MX_25V80_08_18", - .cfg = &flashCfg_Mxic, - }, - { - .jedecID = 0x3525C2, - .name = "MX_25U16_35_18", - .cfg = &flashCfg_Mxic_1635F, - }, - { - .jedecID = 0x3625C2, - .name = "MX_25V32_32_18", - .cfg = &flashCfg_Mxic, - }, - { - .jedecID = 0x13400B, - .name = "XT_25F04D_04_33", - .cfg = &flashCfg_Xtx40, - }, - { - .jedecID = 0x15400B, - .name = "XT_25F16B_16_33", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x16400B, - .name = "XT_25F32B_32_33", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x14600B, - .name = "XT_25Q80B_08_18", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x16600B, - .name = "XT_25Q32B_32_18", - .cfg = &flashCfg_Xtx, - }, - { - .jedecID = 0x146085, - .name = "Puya_Q80L/H_08_18/33", - .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, - }, - { - .jedecID = 0x156085, - .name = "Puya_Q16H_16_33", - .cfg = &flashCfg_Puya_Q80L_Q80H_Q16H, - }, - { - .jedecID = 0x166085, - .name = "Puya_Q32H_32_33", - .cfg = &flashCfg_Puya_Q32H, - }, - { - .jedecID = 0x134068, - .name = "Boya_Q04B_04_33", - .cfg = &flashCfg_Boya40, - }, - { - .jedecID = 0x144068, - .name = "Boya_Q08B_08_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x154068, - .name = "Boya_Q16B_16_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x164068, - .name = "Boya_Q32B_32_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x174068, - .name = "Boya_Q64A_64_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x184068, - .name = "Boya_Q128A_128_33", - .cfg = &flashCfg_Boya, - }, - { - .jedecID = 0x14605E, - .name = "FT_VQ80", - .cfg = &flashCfg_FT_VQ80, - } -}; -#endif - -/*@} end of group SF_CFG_Private_Variables */ - -/** @defgroup SF_CFG_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_Global_Variables */ - -/** @defgroup SF_CFG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return None - * -*******************************************************************************/ -__WEAK -/* static */ void ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_FLASH_PSRAM; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else if (extFlashPin == 1) { - gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; - } else { - gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - cfg.gpioMode = GPIO_MODE_AF; - - GLB_GPIO_Init(&cfg); - } -} - -/****************************************************************************/ /** - * @brief Deinit external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -/* static */ void ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_GPIO; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - - } else if (extFlashPin == 1) { - gpiopins[0] = BFLB_EXTFLASH_CLK1_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS1_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA01_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA11_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA21_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA31_GPIO; - } else { - gpiopins[0] = BFLB_EXTFLASH_CLK2_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS2_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA02_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA12_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA22_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA32_GPIO; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - GLB_GPIO_Init(&cfg); - } -} -#endif - -/*@} end of group SF_CFG_Private_Functions */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(); - SF_Ctrl_Set_Flash_Image_Offset(0); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset); - - if (BL702_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Init flash GPIO according to flash Pin config - * - * @param flashPinCfg: Specify flash Pin config - * @param restoreDefault: Wether to restore default setting - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(uint8_t flashPinCfg, uint8_t restoreDefault) -{ - uint8_t flashCfg; - uint8_t swapCfg; - uint32_t tmpVal; - - flashCfg = (flashPinCfg >> 2) & 0x03; - swapCfg = flashPinCfg & 0x03; - - if (restoreDefault) { - /* Set Default first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); - - if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) { - SF_Cfg_Init_Ext_Flash_Gpio(1); - } - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); - BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); - - SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2); - - /* Default is set, so return */ - if (flashCfg == BFLB_FLASH_CFG_SF2_EXT_23_28 && swapCfg == BFLB_SF2_SWAP_NONE) { - return; - } - } - - if (flashCfg == BFLB_FLASH_CFG_SF1_EXT_17_22) { - SF_Cfg_Init_Ext_Flash_Gpio(0); - SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF1); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO); - - if (BL_GET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO) == 0x00) { - SF_Cfg_Init_Ext_Flash_Gpio(1); - } - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM); - - if (swapCfg == BFLB_SF2_SWAP_NONE) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); - } else if (swapCfg == BFLB_SF2_SWAP_CS_IO2) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); - } else if (swapCfg == BFLB_SF2_SWAP_IO0_IO3) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3); - } - - BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal); - - SF_Ctrl_Select_Pad(SF_CTRL_PAD_SEL_SF2); - } -} - -/****************************************************************************/ /** - * @brief Identify one flash - * - * @param callFromFlash: code run at flash or ram - * @param autoScan: Auto scan all GPIO pin - * @param flashPinCfg: Specify flash GPIO config, not auto scan - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, - uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) -{ - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t offset; - BL_Err_Type stat; - - BL702_MemCpy_Fast(pFlashCfg, &flashCfg_Gd_Q80E_Q16E, sizeof(SPI_Flash_Cfg_Type)); - - if (callFromFlash == 1) { - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - return 0; - } - } - - if (autoScan) { - flashPinCfg = 0; - - do { - if (flashPinCfg > 0x0f) { - jdecId = 0; - break; - } - - SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); - SFlash_Releae_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = 0; - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - flashPinCfg++; - } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); - } else { - /* select media gpio */ - SF_Cfg_Init_Flash_Gpio(flashPinCfg, restoreDefault); - SFlash_Releae_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - } - - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - break; - } - } - - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset); - } - - return jdecId; - } else { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, pFlashCfg->ioMode, offset); - } - - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); - } -} -#endif - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL702_Peripheral_Driver */ diff --git a/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c b/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c index 01ae803f..60192827 100644 --- a/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c +++ b/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c @@ -35,9 +35,9 @@ */ #include "bl702_glb.h" -#include "bl702_sf_cfg.h" +#include "bflb_sf_cfg.h" #include "bl702_sf_cfg_ext.h" -#include "bl702_xip_sflash.h" +#include "bflb_xip_sflash.h" #include "bl702_romdriver.h" #include "soft_crc.h" @@ -61,10 +61,10 @@ */ typedef struct { - uint32_t jedecID; + uint32_t jedec_id; char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; + const spi_flash_cfg_type *cfg; +} flash_info_t; /*@} end of group SF_CFG_EXT_Private_Types */ @@ -72,488 +72,488 @@ typedef struct * @{ */ -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={ - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_gd_md_40d = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0x51, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16/8, - .cReadSupport = 0, - .cReadMode = 0xA0, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0xA0, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, + /*erase*/ + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = 0x11, - .clkDelay = 1, - .clkInvert = 0x3f, + .io_mode = 0x11, + .clk_delay = 1, + .clk_invert = 0x3f, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8/8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8/8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8/8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8/8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16/8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20*1000, - .pdDelay = 20, - .qeData = 0, + /*AC*/ + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 20 * 1000, + .pd_delay = 20, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_mx_kh25 = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xc2, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x00, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x00, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x00, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x00, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0x20, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 0, + .c_read_mode = 0x20, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = 0x11, - .clkDelay = 1, - .clkInvert = 0x01, + .io_mode = 0x11, + .clk_delay = 1, + .clk_invert = 0x01, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33000, - .pdDelay = 20, - .qeData = 0, + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33000, + .pd_delay = 20, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_Q80 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_fm_q80 = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xc8, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x02, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x01, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA0, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0xA0, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x01, + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x01, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33000, - .pdDelay = 20, - .qeData = 0, + .time_e_sector = 300, + .time_e_32k = 1200, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33000, + .pd_delay = 20, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, +static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_winb_16jv = { + .reset_c_read_cmd = 0xff, + .reset_c_read_cmd_size = 3, .mid = 0xef, - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, + .de_burst_wrap_cmd = 0x77, + .de_burst_wrap_cmd_dmy_clk = 0x3, + .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .de_burst_wrap_data = 0xF0, /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, + .write_enable_cmd = 0x06, + .wr_enable_index = 0x00, + .wr_enable_bit = 0x01, + .wr_enable_read_reg_len = 0x01, - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, + .qe_index = 1, + .qe_bit = 0x01, + .qe_write_reg_len = 0x01, + .qe_read_reg_len = 0x1, - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, + .busy_index = 0, + .busy_bit = 0x00, + .busy_read_reg_len = 0x1, + .release_powerdown = 0xab, - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, + .read_reg_cmd[0] = 0x05, + .read_reg_cmd[1] = 0x35, + .write_reg_cmd[0] = 0x01, + .write_reg_cmd[1] = 0x31, - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, + .fast_read_qio_cmd = 0xeb, + .fr_qio_dmy_clk = 16 / 8, + .c_read_support = 1, + .c_read_mode = 0x20, - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, + .burst_wrap_cmd = 0x77, + .burst_wrap_cmd_dmy_clk = 0x3, + .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES, + .burst_wrap_data = 0x40, /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, + .chip_erase_cmd = 0xc7, + .sector_erase_cmd = 0x20, + .blk32_erase_cmd = 0x52, + .blk64_erase_cmd = 0xd8, /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, + .page_program_cmd = 0x02, + .qpage_program_cmd = 0x32, + .qpp_addr_mode = SF_CTRL_ADDR_1_LINE, - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x01, + .io_mode = SF_CTRL_QIO_MODE, + .clk_delay = 1, + .clk_invert = 0x01, - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, + .reset_en_cmd = 0x66, + .reset_cmd = 0x99, + .c_rexit = 0xff, + .wr_enable_write_reg_len = 0x00, /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .qpiJedecIdCmd = 0x9f, - .qpiJedecIdCmdDmyClk = 0x00, - .sectorSize = 4, - .pageSize = 256, + .jedec_id_cmd = 0x9f, + .jedec_id_cmd_dmy_clk = 0, + .qpi_jedec_id_cmd = 0x9f, + .qpi_jedec_id_cmd_dmy_clk = 0x00, + .sector_size = 4, + .page_size = 256, /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, + .fast_read_cmd = 0x0b, + .fr_dmy_clk = 8 / 8, + .qpi_fast_read_cmd = 0x0b, + .qpi_fr_dmy_clk = 8 / 8, + .fast_read_do_cmd = 0x3b, + .fr_do_dmy_clk = 8 / 8, + .fast_read_dio_cmd = 0xbb, + .fr_dio_dmy_clk = 0, + .fast_read_qo_cmd = 0x6b, + .fr_qo_dmy_clk = 8 / 8, - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, + .qpi_fast_read_qio_cmd = 0xeb, + .qpi_fr_qio_dmy_clk = 16 / 8, + .qpi_page_program_cmd = 0x02, + .write_vreg_enable_cmd = 0x50, /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, + .enter_qpi = 0x38, + .exit_qpi = 0xff, /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33000, - .pdDelay = 3, - .qeData = 0, + .time_e_sector = 300, + .time_e_32k = 1600, + .time_e_64k = 1200, + .time_page_pgm = 5, + .time_ce = 33 * 1000, + .pd_delay = 20, + .qe_data = 0, }; -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { +static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[] = { { - .jedecID = 0x134051, + .jedec_id = 0x134051, .name = "GD_MD04D_04_33", - .cfg = &flashCfg_Gd_Md_40D, + .cfg = &flashcfg_gd_md_40d, }, { - .jedecID = 0x1320c2, + .jedec_id = 0x1320c2, .name = "MX_KH40_04_33", - .cfg = &flashCfg_MX_KH25, + .cfg = &flashcfg_mx_kh25, }, { - .jedecID = 0x1420c2, + .jedec_id = 0x1420c2, .name = "MX_KH80_08_33", - .cfg = &flashCfg_MX_KH25, + .cfg = &flashcfg_mx_kh25, }, { - .jedecID = 0x1520c2, + .jedec_id = 0x1520c2, .name = "MX_KH16_16_33", - .cfg = &flashCfg_MX_KH25, + .cfg = &flashcfg_mx_kh25, }, { - .jedecID = 0x1440A1, + .jedec_id = 0x1440A1, .name = "FM_25Q80_80_33", - .cfg = &flashCfg_FM_Q80, + .cfg = &flashcfg_fm_q80, }, { - .jedecID = 0x1570EF, + .jedec_id = 0x1570EF, .name = "Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x1870EF, + .jedec_id = 0x1870EF, .name = "Winb_128JV_128_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x15605E, + .jedec_id = 0x15605E, .name = "ZB_VQ16_16_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x144020, + .jedec_id = 0x144020, .name = "XM_25QH80_80_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x154020, + .jedec_id = 0x154020, .name = "XM_25QH16_16_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x164020, + .jedec_id = 0x164020, .name = "XM_25QH32_32_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x174020, + .jedec_id = 0x174020, .name = "XM_25QH64_64_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x13325E, + .jedec_id = 0x13325E, .name = "ZB_D40B_80_33", - .cfg = &flashCfg_MX_KH25, + .cfg = &flashcfg_mx_kh25, }, { - .jedecID = 0x14325E, + .jedec_id = 0x14325E, .name = "ZB_D80B_80_33", - .cfg = &flashCfg_MX_KH25, + .cfg = &flashcfg_mx_kh25, }, { - .jedecID = 0x15405E, + .jedec_id = 0x15405E, .name = "ZB_25Q16B_15_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x16405E, + .jedec_id = 0x16405E, .name = "ZB_25Q32B_16_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, { - .jedecID = 0x1560EB, + .jedec_id = 0x1560EB, .name = "TH_25Q16HB_16_33", - .cfg = &flashCfg_FM_Q80, + .cfg = &flashcfg_fm_q80, }, { - .jedecID = 0x15345E, + .jedec_id = 0x15345E, .name = "ZB_25Q16A_15_33", - .cfg = &flashCfg_Winb_16JV, + .cfg = &flashcfg_winb_16jv, }, }; @@ -583,7 +583,7 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { * @return None * *******************************************************************************/ -void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) +void ATTR_TCM_SECTION bflb_sf_cfg_Init_Internal_Flash_Gpio(void) { GLB_GPIO_Cfg_Type gpioCfg = { .gpioPin = GLB_GPIO_PIN_0, @@ -611,42 +611,45 @@ void ATTR_TCM_SECTION SF_Cfg_Init_Internal_Flash_Gpio(void) /****************************************************************************/ /** * @brief Get flash config according to flash ID * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer + * @param flash_id: Flash ID + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select * - * @return SUCCESS or ERROR + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, + uint8_t group, uint8_t bank) { uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; + uint8_t buf[sizeof(spi_flash_cfg_type) + 8]; uint32_t crc, *pCrc; - char flashCfgMagic[] = "FCFG"; + char flash_cfg_magic[] = "FCFG"; - if (flashID == 0) { - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); + if (flash_id == 0) { + bflb_xip_sflash_read_via_cache_need_lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank); - if (BL702_MemCmp(buf, flashCfgMagic, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); + if (BL702_MemCmp(buf, flash_cfg_magic, 4) == 0) { + crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); + pCrc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type)); if (*pCrc == crc) { - BL702_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); + BL702_MemCpy_Fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type)); return SUCCESS; } } } else { - if (SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS) { + if (bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank) == SUCCESS) { /* 0x134051 flash cfg is wrong in rom, find again */ - if ((flashID&0xFFFFFF) != 0x134051) { + if ((flash_id&0xFFFFFF) != 0x134051) { return SUCCESS; } } - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == flash_id) { + BL702_MemCpy_Fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); return SUCCESS; } } @@ -658,23 +661,25 @@ BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID /****************************************************************************/ /** * @brief Identify one flash * - * @param callFromFlash: code run at flash or ram - * @param autoScan: Auto scan all GPIO pin - * @param flashPinCfg: Specify flash GPIO config, not auto scan - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer + * @param call_from_flash: code run at flash or ram + * @param auto_scan: Auto scan all GPIO pin + * @param flash_pin_cfg: Specify flash GPIO config, not auto scan + * @param restore_default: Wether restore default flash GPIO config + * @param p_flash_cfg: Flash config pointer + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select * * @return Flash ID * *******************************************************************************/ -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, - uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg) +uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, + uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank) { - uint32_t jdecId = 0; + uint32_t jedec_id = 0; uint32_t i = 0; uint32_t ret = 0; - ret = SF_Cfg_Flash_Identify(callFromFlash, autoScan, flashPinCfg, restoreDefault, pFlashCfg); + ret = bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank); if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) { /* 0x134051 flash cfg is wrong in rom, find again */ @@ -683,19 +688,19 @@ uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, } } - jdecId = (ret & 0xffffff); + jedec_id = (ret & 0xffffff); - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - BL702_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); + for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) { + if (flash_infos[i].jedec_id == jedec_id) { + BL702_MemCpy_Fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type)); break; } } - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - return jdecId; + if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) { + return jedec_id; } else { - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); + return (jedec_id | BFLB_FLASH_ID_VALID_FLAG); } } diff --git a/drivers/soc/bl702/std/src/bl702_sf_ctrl.c b/drivers/soc/bl702/std/src/bl702_sf_ctrl.c deleted file mode 100644 index 95f01f5b..00000000 --- a/drivers/soc/bl702/std/src/bl702_sf_ctrl.c +++ /dev/null @@ -1,1449 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_sf_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl702_sf_ctrl.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Private_Macros - * @{ - */ - -/*@} end of group SF_CTRL_Private_Macros */ - -/** @defgroup SF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SF_CTRL_Private_Types */ - -/** @defgroup SF_CTRL_Private_Variables - * @{ - */ -#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) -#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100) - -/*@} end of group SF_CTRL_Private_Variables */ - -/** @defgroup SF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SF_CTRL_Global_Variables */ - -/** @defgroup SF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SF_CTRL_Private_Functions - * @{ - */ - -/*@} end of group SF_CTRL_Private_Functions */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Enable serail flash controller - * - * @param cfg: serial flash controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - if (cfg == NULL) { - return; - } - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (cfg->clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - /* Serail out inverted, so sf ctrl send on negative edge */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); - - /* Set do di and oe delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_0_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_1_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_2_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IO_3_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_4, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_0_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_1_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_2_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IO_3_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF2_IF_IO_DLY_4, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_0_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_1_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_2_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DO_DLY_SEL, cfg->doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_DI_DLY_SEL, cfg->diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF3_IO_3_OE_DLY_SEL, cfg->oeDelay); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF3_IF_IO_DLY_4, tmpVal); - - /* Enable AHB access sram buffer and enable sf interface */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); - - SF_Ctrl_Set_Owner(cfg->owner); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serail psram controller - * - * @param sfCtrlPsramCfg: serial psram controller config - * - * @return None - * -*******************************************************************************/ -//#ifndef BFLB_USE_ROM_DRIVER -//__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Psram_Init(SF_Ctrl_Psram_Cfg *sfCtrlPsramCfg) -{ - uint32_t tmpVal = 0; - - SF_Ctrl_Select_Pad(sfCtrlPsramCfg->padSel); - SF_Ctrl_Select_Bank(sfCtrlPsramCfg->bankSel); - - /* Select psram clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12); - - if (sfCtrlPsramCfg->psramRxClkInvertSrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - - if (sfCtrlPsramCfg->psramRxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - } - - if (sfCtrlPsramCfg->psramDelaySrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - - if (sfCtrlPsramCfg->psramClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, sfCtrlPsramCfg->psramClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal); - - /* Enable AHB access sram buffer and enable sf interface */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); - - SF_Ctrl_Set_Owner(sfCtrlPsramCfg->owner); -} -//#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param None - * - * @return Clock delay value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { - return 0; - } else { - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller clock delay value - * - * @param delay: Clock delay value - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (delay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set cmds config - * - * @param cmdsCfg: SF Ctrl cmds config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->wrapLen)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_EN); - } - - if (cmdsCfg->burstToggleEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_BT_EN); - } - - if (cmdsCfg->wrapModeEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_WRAP_MODE); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_WRAP_LEN, cmdsCfg->wrapLen); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl pad select - * - * @param sel: pad select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pad_Select sel) -{ - /* TODO: sf_if_bk_swap */ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_SELECT(sel)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (sel <= SF_CTRL_PAD_SEL_SF3) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel); - } else if (sel >= SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2 && sel <= SF_CTRL_PAD_SEL_DUAL_BANK_SF3_SF1) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, sel - SF_CTRL_PAD_SEL_DUAL_BANK_SF1_SF2); - } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF2) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 1); - } else if (sel == SF_CTRL_PAD_SEL_DUAL_CS_SF3) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 2); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl bank select - * - * @param sel: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Bank(SF_Ctrl_Select sel) -{ - /* TODO: sf_if_bk_swap */ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_SELECT(sel)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (sel == SF_CTRL_SEL_FLASH) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller owner:I/D AHB or system AHB - * - * @param owner: owner type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - /* Set owner */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); - - /* Set iahb to flash interface */ - if (owner == SF_CTRL_OWNER_IAHB) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash controller - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with big indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with little indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES region - * - * @param region: region number - * @param enable: enable or not - * @param hwKey: hardware key or software key - * @param startAddr: region start address - * @param endAddr: region end address - * @param locked: lock this region or not - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, - uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal; - - if (!hwKey) { - regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - } - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_CFG); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); - /* sf_aes_end =1 means 1,11,1111,1111 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_CFG, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - tmpVal -= 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - tmpVal += 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Enable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check is serial flash controller AES enable - * - * @param None - * - * @return Wether AES is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - return BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash image offset - * - * @param addrOffset: Address offset value - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset) -{ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash image offset - * - * @param None - * - * @return :Address offset value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(void) -{ - return BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); -} -#endif - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param sahbType: Serial flash controller clock sahb sram select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Clock(SF_Ctrl_Sahb_Type sahbType) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (sahbType == SF_CTRL_SAHB_CLOCK) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); - } else if (sahbType == SF_CTRL_FLASH_CLOCK) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SAHB_SRAM_SEL); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param cfg: Serial flash controller command configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { - return; - } - - /* Clear trigger */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_2, cfg->cmdBuf[1]); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); - } - - /* Configure cmd */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_CMD_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_CMD_BYTE, 0); - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_ADR_BYTE, 0); - } - - /* Configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, cfg->nbData - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_BYTE, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_0_DAT_RW, cfg->rwFlag); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); - - //switch sf_clk_sahb_sram_sel = 1 - SF_Ctrl_Select_Clock(SF_CTRL_FLASH_CLOCK); - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_TRIG); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0, tmpVal); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); - return; - } - } - - //switch sf_clk_sahb_sram_sel = 0 - SF_Ctrl_Select_Clock(SF_CTRL_SAHB_CLOCK); -} -#endif - -/****************************************************************************/ /** - * @brief Config SF controller for flash I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config psram controller for psram I/D cache write - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Psram_Write_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_4, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_5, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_2_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_3, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config psram controller for psram I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Psram_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get SF Ctrl busy state - * - * @param None - * - * @return SET for SF ctrl busy or RESET for SF ctrl not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_SAHB_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_BUSY)) { - return SET; - } else { - return RESET; - } -} -#endif - -/****************************************************************************/ /** - * @brief SF Controller interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void) -{ - /* TODO: Not implemented */ -} -#endif - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL702_Peripheral_Driver */ diff --git a/drivers/soc/bl702/std/src/bl702_sflash.c b/drivers/soc/bl702/std/src/bl702_sflash.c deleted file mode 100644 index 6d157575..00000000 --- a/drivers/soc/bl702/std/src/bl702_sflash.c +++ /dev/null @@ -1,1530 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl702_sflash.h" -#include "bl702_sf_ctrl.h" -#include "bl702_l1c.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLASH - * @{ - */ - -/** @defgroup SFLASH_Private_Macros - * @{ - */ - -/*@} end of group SFLASH_Private_Macros */ - -/** @defgroup SFLASH_Private_Types - * @{ - */ - -/*@} end of group SFLASH_Private_Types */ - -/** @defgroup SFLASH_Private_Variables - * @{ - */ -#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000) - -/*@} end of group SFLASH_Private_Variables */ - -/** @defgroup SFLASH_Global_Variables - * @{ - */ - -/*@} end of group SFLASH_Global_Variables */ - -/** @defgroup SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SFLASH_Private_Fun_Declaration */ - -/** @defgroup SFLASH_Private_Functions - * @{ - */ - -/*@} end of group SFLASH_Private_Functions */ - -/** @defgroup SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init serial flash control interface - * - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg) -{ - SF_Ctrl_Enable(pSfCtrlCfg); -} -#endif - -/****************************************************************************/ /** - * @brief Set serial flash control interface SPI or QPI mode - * - * @param mode: Serial flash interface mode - * - * @return BFLB_RET:SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) -{ - BL_Err_Type stat = SUCCESS; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - BL702_Delay_US(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - BL702_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - BL702_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register with read command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param readRegCmd: read command - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = readRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - BL702_Delay_US(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - BL702_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register with write command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param writeRegCmd: write command - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - BL702_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = writeRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Check flash busy status - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SET for busy or RESET for not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); - - if ((stat & (1 << flashCfg->busyBit)) == 0) { - return RESET; - } - - return SET; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash write function - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Write enable*/ - flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); - - if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); - } else { - stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); - stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); - } - } else { - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit % 8)); - } else { - stat = flashCfg->qeData; - } - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash volatile register write enable - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash whole chip - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeCe * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one sector - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param secNum: flash sector number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) -{ - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeEsector * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 64K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 64K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(500); - cnt++; - - if (cnt > flashCfg->timeE64k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: progran mode:SPI mode or QPI mode - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - BL_Err_Type stat; - uint8_t cmd; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - cmd = flashCfg->pageProgramCmd; - } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->qpageProgramCmd; - } else { - return ERROR; - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = flashCfg->pageSize - addr % flashCfg->pageSize; - - if (curLen > len - i) { - curLen = len - i; - } - - /* Prepare command */ - BL702_MemCpy_Fast(flashCtrlBuf, data, curLen); - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(100); - cnt++; - - if (cnt > flashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash unique ID - * - * @param data: data pointer to store read data - * @param idLen: unique ID len - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = 4; - cmd = 0x4B; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = idLen; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - BL702_MemCpy(data, flashCtrlBuf, idLen); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash jedec ID - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = flashCfg->jedecIdCmdDmyClk; - cmd = flashCfg->jedecIdCmd; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - BL702_MemCpy(data, flashCtrlBuf, 3); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash device ID - * - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t addr = 0x00000001; - uint8_t readMode = 0xFF; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - dummyClks = 2; - cmd = 0x94; - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.cmdBuf[1] = (readMode << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 4; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 2; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - BL702_MemCpy(data, flashCtrlBuf, 2); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash power down - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Powerdown(void) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - uint32_t timeOut = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = 0xB9; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Release flash power down for wake up - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Releae_Powerdown(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t cmd; - uint32_t timeOut = 0; - - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = flashCfg->releasePowerDown; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Sflash restore from power down - * - * @param pFlashCfg: Flash configuration pointer - * @param flashContRead: Whether enable continuous read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead) -{ - BL_Err_Type stat = SUCCESS; - uint32_t jdecId = 0; - uint8_t tmp[8]; - uint8_t ioMode = pFlashCfg->ioMode & 0xf; - - /* Wake flash up from power down */ - SFlash_Releae_Powerdown(pFlashCfg); - BL702_Delay_US(120); - - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - - if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { - SFlash_Qspi_Enable(pFlashCfg); - } - - if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { - /* unwrap */ - L1C_Set_Wrap(DISABLE); - } else { - /* burst wrap */ - L1C_Set_Wrap(ENABLE); - /* For command that is setting register instead of send command, we need write enable */ - SFlash_Write_Enable(pFlashCfg); - SFlash_SetBurstWrap(pFlashCfg); - } - - if (flashContRead) { - stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - } else { - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((flashCfg->ioMode >> 4) & 0x01) == 1) { - /* Disable burst wrap ,just return */ - return; - } - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; - dummyClks = flashCfg->burstWrapCmdDmyClk; - cmd = flashCfg->burstWrapCmd; - wrapData = flashCfg->burstWrapData; - BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; - dummyClks = flashCfg->deBurstWrapCmdDmyClk; - cmd = flashCfg->deBurstWrapCmd; - wrapData = flashCfg->deBurstWrapData; - BL702_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Software reset flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) -{ - uint16_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset enable */ - flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - /* Wait for write done */ - while (SET == SFlash_Busy(flashCfg)) { - BL702_Delay_US(100); - cnt++; - - if (cnt > 20) { - return ERROR; - } - } - - SF_Ctrl_SendCmd(&flashCmd); - - /* Reset */ - flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - BL702_Delay_US(50); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Reset flash continous read mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset continous read */ - BL702_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = flashCfg->resetCreadCmdSize; - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set I/D bus read flash configuration in flash controller - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: address to read/write - * @param len: data length to read/write - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len) -{ - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmdValid = 1; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - /*prepare command**/ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - flashCmd.cmdBuf[0] = (cmd << 24) | addr; - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; - cmdValid = 0; - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = len; - SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Enable I/D bus read from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead) -{ - BL_Err_Type stat; - - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 4); - - if (SUCCESS != stat) { - return stat; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Enable cache read from flash with cache - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param wayDisable: cache way disable config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Cache_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint8_t wayDisable) -{ - BL_Err_Type stat; - - /* Cache now only support 32 bytes read */ - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32); - - if (SUCCESS != stat) { - return stat; - } - - return L1C_Cache_Enable_Set(wayDisable); -} -#endif - -/****************************************************************************/ /** - * @brief Disable read from flash with cache - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Cache_Read_Disable(void) -{ - L1C_Cache_Read_Disable(); -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - - /* Read data */ - for (i = 0; i < len;) { - /* Prepare command */ - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - curLen = len - i; - - if (curLen >= FLASH_CTRL_BUF_SIZE) { - curLen = FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - BL702_MemCpy_Fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} -#endif - -/*@} end of group SFLASH_Public_Functions */ - -/*@} end of group SFLASH */ - -/*@} end of group BL702_Peripheral_Driver */ diff --git a/drivers/soc/bl702/std/src/bl702_sflash_ext.c b/drivers/soc/bl702/std/src/bl702_sflash_ext.c index aa933c5b..b38c579f 100644 --- a/drivers/soc/bl702/std/src/bl702_sflash_ext.c +++ b/drivers/soc/bl702/std/src/bl702_sflash_ext.c @@ -34,8 +34,8 @@ ****************************************************************************** */ +#include "bflb_sf_ctrl.h" #include "bl702_sflash_ext.h" -#include "bl702_sf_ctrl.h" #include "l1c_reg.h" /** @addtogroup BL702_Peripheral_Driver @@ -89,182 +89,182 @@ /****************************************************************************/ /** * @brief KH25V40 flash write protect set * - * @param flashCfg: Serial flash parameter configuration pointer + * @param flash_cfg: Serial flash parameter configuration pointer * @param protect: protect area * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_KH25V40_Write_Protect(SPI_Flash_Cfg_Type *flashCfg, SFlash_Protect_Kh25v40_Type protect) +int ATTR_TCM_SECTION bflb_sflash_kh25v40_write_protect(spi_flash_cfg_type *flash_cfg, uint8_t protect) { uint32_t stat = 0, ret; - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); + bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1); if (((stat >> 2) & 0xf) == protect) { - return SUCCESS; + return 0; } stat |= ((protect << 2) & 0xff); - ret = SFlash_Write_Enable(flashCfg); - if (SUCCESS != ret) { - return ERROR; + ret = bflb_sflash_write_enable(flash_cfg); + if (0 != ret) { + return -1; } - SFlash_Write_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); + bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)&stat, 1); + bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1); if (((stat >> 2) & 0xf) == protect) { - return SUCCESS; + return 0; } - return ERROR; + return -1; } /****************************************************************************/ /** * @brief Read flash register with read command * - * @param flashCfg: Serial flash parameter configuration pointer - * @param readRegCmd: read command - * @param regValue: register value pointer to store data - * @param regLen: register value length + * @param flash_cfg: Serial flash parameter configuration pointer + * @param read_reg_cmd: read command + * @param reg_value: register value pointer to store data + * @param reg_len: register value length * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) +int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len) { - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; + uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE; + struct sf_ctrl_cmd_cfg_type flash_cmd; uint32_t cnt = 0; - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL702_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - flashCmd.cmdBuf[0] = readRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; + flash_cmd.cmd_buf[0] = read_reg_cmd << 24; + flash_cmd.rw_flag = SF_CTRL_READ; + flash_cmd.nb_data = reg_len; - SF_Ctrl_SendCmd(&flashCmd); + bflb_sf_ctrl_sendcmd(&flash_cmd); - while (SET == SF_Ctrl_GetBusyState()) { + while (SET == bflb_sf_ctrl_get_busy_state()) { BL702_Delay_US(1); cnt++; if (cnt > 1000) { - return ERROR; + return -1; } } - BL702_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; + BL702_MemCpy(reg_value, flash_ctrl_buf, reg_len); + return 0; } /****************************************************************************/ /** * @brief Write flash register with write command * - * @param flashCfg: Serial flash parameter configuration pointer - * @param writeRegCmd: write command - * @param regValue: register value pointer storing data - * @param regLen: register value length + * @param flash_cfg: Serial flash parameter configuration pointer + * @param read_reg_cmd: write command + * @param reg_value: register value pointer storing data + * @param reg_len: register value length * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) +int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len) { - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; + uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE; uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; + struct sf_ctrl_cmd_cfg_type flash_cmd; - if (((uint32_t)&flashCmd) % 4 == 0) { - BL702_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); + if (((uint32_t)&flash_cmd) % 4 == 0) { + BL702_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4); } else { - BL702_MemSet(&flashCmd, 0, sizeof(flashCmd)); + BL702_MemSet(&flash_cmd, 0, sizeof(flash_cmd)); } - BL702_MemCpy(flashCtrlBuf, regValue, regLen); + BL702_MemCpy(flash_ctrl_buf, reg_value, reg_len); - flashCmd.cmdBuf[0] = writeRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; + flash_cmd.cmd_buf[0] = read_reg_cmd << 24; + flash_cmd.rw_flag = SF_CTRL_WRITE; + flash_cmd.nb_data = reg_len; - SF_Ctrl_SendCmd(&flashCmd); + bflb_sf_ctrl_sendcmd(&flash_cmd); /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { + while (SET == bflb_sflash_busy(flash_cfg)) { BL702_Delay_US(100); cnt++; if (cnt > 400) { - return ERROR; + return -1; } } - return SUCCESS; + return 0; } /****************************************************************************//** * @brief Clear flash status register * - * @param pFlashCfg: Flash configuration pointer + * @param p_flash_cfg: Flash configuration pointer * - * @return SUCCESS or ERROR + * @return 0 or -1 * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg) +int ATTR_TCM_SECTION bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg) { uint32_t ret = 0; - uint32_t qeValue = 0; - uint32_t regValue = 0; - uint32_t readValue = 0; - uint8_t readRegValue0 = 0; - uint8_t readRegValue1 = 0; + uint32_t qe_value = 0; + uint32_t reg_value = 0; + uint32_t read_value = 0; + uint8_t readreg_value0 = 0; + uint8_t readreg_value1 = 0; - if((pFlashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){ - qeValue = 1; + if((p_flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE){ + qe_value = 1; } - SFlash_Read_Reg(pFlashCfg, 0, (uint8_t *)&readRegValue0, 1); - SFlash_Read_Reg(pFlashCfg, 1, (uint8_t *)&readRegValue1, 1); - readValue = (readRegValue0|(readRegValue1<<8)); - if ((readValue & (~((1<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit)) | - (1<<(pFlashCfg->busyIndex*8+pFlashCfg->busyBit)) | - (1<<(pFlashCfg->wrEnableIndex*8+pFlashCfg->wrEnableBit))))) == 0){ - return SUCCESS; + bflb_sflash_read_reg(p_flash_cfg, 0, (uint8_t *)&readreg_value0, 1); + bflb_sflash_read_reg(p_flash_cfg, 1, (uint8_t *)&readreg_value1, 1); + read_value = (readreg_value0|(readreg_value1<<8)); + if ((read_value & (~((1<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit)) | + (1<<(p_flash_cfg->busy_index*8+p_flash_cfg->busy_bit)) | + (1<<(p_flash_cfg->wr_enable_index*8+p_flash_cfg->wr_enable_bit))))) == 0){ + return 0; } - ret = SFlash_Write_Enable(pFlashCfg); - if (SUCCESS != ret) { - return ERROR; + ret = bflb_sflash_write_enable(p_flash_cfg); + if (0 != ret) { + return -1; } - if (pFlashCfg->qeWriteRegLen == 2) { - regValue = (qeValue<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit)); - SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 2); + if (p_flash_cfg->qe_write_reg_len == 2) { + reg_value = (qe_value<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit)); + bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 2); } else { - if (pFlashCfg->qeIndex == 0) { - regValue = (qeValue<qeBit); + if (p_flash_cfg->qe_index == 0) { + reg_value = (qe_value<qe_bit); } else { - regValue = 0; + reg_value = 0; } - SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 1); - ret = SFlash_Write_Enable(pFlashCfg); - if (SUCCESS != ret) { - return ERROR; + bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 1); + ret = bflb_sflash_write_enable(p_flash_cfg); + if (0 != ret) { + return -1; } - if (pFlashCfg->qeIndex == 1) { - regValue = (qeValue<qeBit); + if (p_flash_cfg->qe_index == 1) { + reg_value = (qe_value<qe_bit); } else { - regValue = 0; + reg_value = 0; } - SFlash_Write_Reg(pFlashCfg, 1, (uint8_t *)®Value, 1); + bflb_sflash_write_reg(p_flash_cfg, 1, (uint8_t *)®_value, 1); } - return SUCCESS; + return 0; } /*@} end of group SFLASH_EXT_Public_Functions */ diff --git a/drivers/soc/bl702/std/src/bl702_xip_sflash.c b/drivers/soc/bl702/std/src/bl702_xip_sflash.c deleted file mode 100644 index 8b9893bf..00000000 --- a/drivers/soc/bl702/std/src/bl702_xip_sflash.c +++ /dev/null @@ -1,404 +0,0 @@ -/** - ****************************************************************************** - * @file bl702_xip_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl702_xip_sflash.h" - -/** @addtogroup BL702_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Private_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Macros */ - -/** @defgroup XIP_SFLASH_Private_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Types */ - -/** @defgroup XIP_SFLASH_Private_Variables - * @{ - */ -static uint8_t aesEnable; - -/*@} end of group XIP_SFLASH_Private_Variables */ - -/** @defgroup XIP_SFLASH_Global_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Global_Variables */ - -/** @defgroup XIP_SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ - -/** @defgroup XIP_SFLASH_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief XIP SFlash option save - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(void) -{ - aesEnable = SF_Ctrl_Is_AES_Enable(); - - if (aesEnable) { - SF_Ctrl_AES_Disable(); - } -} - -/****************************************************************************/ /** - * @brief XIP SFlash option restore - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(void) -{ - if (aesEnable) { - SF_Ctrl_AES_Enable(); - } -} - -/****************************************************************************/ /** - * @brief Save flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset) -{ - /* XIP_SFlash_Delay */ - volatile uint32_t i = 32 * 2; - - while (i--) - ; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); - /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */ - SFlash_Software_Reset(pFlashCfg); - /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); - /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); - /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); - - /* Clear offset setting*/ - *offset = SF_Ctrl_Get_Flash_Image_Offset(); - SF_Ctrl_Set_Flash_Image_Offset(0); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Restore flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param ioMode: flash controller interface mode - * @param offset: CPU XIP flash offset - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t offset) -{ - uint32_t tmp[1]; - - SF_Ctrl_Set_Flash_Image_Offset(offset); - - SFlash_SetBurstWrap(pFlashCfg); - SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); - - return SUCCESS; -} -#endif - -/*@} end of group XIP_SFLASH_Private_Functions */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param ioMode: flash controller interface mode - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t startaddr, uint32_t endaddr) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, endaddr); - XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param pFlashCfg: Flash config pointer - * @param ioMode: flash controller interface mode - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); - } else { - stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param pFlashCfg: Flash config pointer - * @param ioMode: flash controller interface mode - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); - } else { - stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Jedec ID - * - * @param pFlashCfg: Flash config pointer - * @param ioMode: flash controller interface mode - * @param data: data pointer to store Jedec ID Read from flash - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); - } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Device ID - * - * @param pFlashCfg: Flash config pointer - * @param ioMode: flash controller interface mode - * @param data: data pointer to store Device ID Read from flash - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); - } else { - SFlash_GetDeviceId(data); - XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Unique ID - * - * @param pFlashCfg: Flash config pointer - * @param ioMode: flash controller interface mode - * @param data: data pointer to store Device ID Read from flash - * @param idLen: Unique id len - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint8_t *data, uint8_t idLen) -{ - BL_Err_Type stat; - uint32_t offset; - - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); - } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash via XIP - * - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -//#ifndef BFLB_USE_ROM_DRIVER -//__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len) -{ - uint32_t offset; - addr = addr & (BL702_FLASH_XIP_END-BL702_FLASH_XIP_BASE-1); - addr |= BL702_FLASH_XIP_BASE; - - offset = SF_Ctrl_Get_Flash_Image_Offset(); - SF_Ctrl_Set_Flash_Image_Offset(0); - /* Flash read */ - BL702_MemCpy_Fast(data, (void *)(addr), len); - SF_Ctrl_Set_Flash_Image_Offset(offset); - - return SUCCESS; -} -//#endif - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL702_Peripheral_Driver */ diff --git a/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c b/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c index 241e0e40..fcd7d25e 100644 --- a/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c +++ b/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c @@ -79,27 +79,87 @@ */ /****************************************************************************//** - * @brief XIP KH25V40 flash write protect set + * @brief XIP SFlash option save * - * @param pFlashCfg: Flash config pointer - * @param protect: protect area + * @param aes_enable: AES enable status pointer * - * @return SUCCESS or ERROR + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable) +{ + *aes_enable = bflb_sf_ctrl_is_aes_enable(); + + if (*aes_enable) { + bflb_sf_ctrl_aes_disable(); + } +} + +/****************************************************************************//** + * @brief XIP SFlash option restore + * + * @param aes_enable: AES enable status + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable) +{ + if (aes_enable) { + bflb_sf_ctrl_aes_enable(); + } +} + +/****************************************************************************//** + * @brief Read data from flash via XIP + * + * @param addr: flash read start address + * @param data: data pointer to store data read from flash + * @param len: data length to read + * @param group: CPU group id 0 or 1 + * @param bank: Flash bank select + * + * @return BFLB_RET:0 means success and other value means error * *******************************************************************************/ __WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_KH25V40_Write_Protect_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Protect_Kh25v40_Type protect) +int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr,uint8_t *data, uint32_t len, + uint8_t group, uint8_t bank) { - BL_Err_Type stat; uint32_t offset; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf; - stat = XIP_SFlash_State_Save(pFlashCfg, &offset); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + if(addr>=BL702_FLASH_XIP_BASE && addrioMode&0xf; - stat=XIP_SFlash_State_Save(pFlashCfg, &offset); - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32); + stat=bflb_xip_sflash_state_save(p_flash_cfg, &offset, 0, 0); + if (stat != 0) { + bflb_sflash_set_xip_cfg(p_flash_cfg, 1, 0, 32, 0, 0); } else { - stat=SFlash_Clear_Status_Register(pFlashCfg); - XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset); + stat=bflb_sflash_clear_status_register(p_flash_cfg); + bflb_xip_sflash_state_restore(p_flash_cfg, offset, 0, 0); } return stat; diff --git a/drivers/soc/bl808/std/CMakeLists.txt b/drivers/soc/bl808/std/CMakeLists.txt index 3bc9f464..73ccc4de 100644 --- a/drivers/soc/bl808/std/CMakeLists.txt +++ b/drivers/soc/bl808/std/CMakeLists.txt @@ -22,13 +22,7 @@ sdk_library_add_sources(src/bl808_tzc_sec.c) sdk_library_add_sources(src/bl808_psram_uhs.c) sdk_library_add_sources(src/bl808_uhs_phy.c) -sdk_library_add_sources(src/bl808_sf_cfg.c) -sdk_library_add_sources(src/bl808_sf_ctrl.c) -sdk_library_add_sources(src/bl808_sflash.c) -sdk_library_add_sources(src/bl808_xip_sflash.c) - sdk_library_add_sources(port/bl808_clock.c) -sdk_library_add_sources(port/bl808_flash.c) sdk_add_include_directories( include diff --git a/drivers/soc/bl808/std/include/bl808_glb.h b/drivers/soc/bl808/std/include/bl808_glb.h index d9f30327..156335ad 100644 --- a/drivers/soc/bl808/std/include/bl808_glb.h +++ b/drivers/soc/bl808/std/include/bl808_glb.h @@ -42,11 +42,11 @@ #include "pds_reg.h" #include "bl808_gpio.h" #include "bl808_hbn.h" -#include "bl808_sf_ctrl.h" -#include "bl808_sf_cfg.h" #include "bl808_aon.h" #include "bl808_pds.h" #include "bl808_common.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" /** @addtogroup BL808_Peripheral_Driver * @{ diff --git a/drivers/soc/bl808/std/include/bl808_glb_gpio.h b/drivers/soc/bl808/std/include/bl808_glb_gpio.h index ab65ef25..40eed3fa 100644 --- a/drivers/soc/bl808/std/include/bl808_glb_gpio.h +++ b/drivers/soc/bl808/std/include/bl808_glb_gpio.h @@ -41,11 +41,11 @@ #include "pds_reg.h" #include "bl808_gpio.h" #include "bl808_hbn.h" -#include "bl808_sf_ctrl.h" -#include "bl808_sf_cfg.h" #include "bl808_aon.h" #include "bl808_pds.h" #include "bl808_common.h" +#include "bflb_sf_ctrl.h" +#include "bflb_sf_cfg.h" /** @addtogroup BL808_Peripheral_Driver * @{ diff --git a/drivers/soc/bl808/std/include/bl808_hbn.h b/drivers/soc/bl808/std/include/bl808_hbn.h index ece53d49..6f151ee2 100644 --- a/drivers/soc/bl808/std/include/bl808_hbn.h +++ b/drivers/soc/bl808/std/include/bl808_hbn.h @@ -39,8 +39,8 @@ #include "hbn_reg.h" #include "bl808_aon.h" #include "bl808_l1c.h" -#include "bl808_sflash.h" #include "bl808_common.h" +#include "bflb_sflash.h" /** @addtogroup BL808_Peripheral_Driver * @{ @@ -323,7 +323,7 @@ typedef struct uint32_t sleepTime; /*!< HBN sleep time */ uint8_t gpioWakeupSrc; /*!< GPIO Wakeup source */ HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ HBN_LEVEL_Type hbnLevel; /*!< HBN level */ HBN_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ uint8_t dcdcPuSeq; /*!< power on dcdc sequence */ @@ -571,7 +571,7 @@ void HBN_OUT1_IRQHandler(void); #endif /*----------*/ void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg); -void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg); +void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg); void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq); BL_Err_Type HBN_Reset(void); /*----------*/ diff --git a/drivers/soc/bl808/std/include/bl808_pds.h b/drivers/soc/bl808/std/include/bl808_pds.h index 70654009..6dd9acc9 100644 --- a/drivers/soc/bl808/std/include/bl808_pds.h +++ b/drivers/soc/bl808/std/include/bl808_pds.h @@ -41,9 +41,9 @@ #include "bl808_clock.h" #include "bl808_aon.h" #include "bl808_hbn.h" -#include "bl808_sflash.h" -#include "bl808_sf_ctrl.h" #include "bl808_common.h" +#include "bflb_sflash.h" +#include "bflb_sf_ctrl.h" /** @addtogroup BL808_Peripheral_Driver * @{ @@ -372,7 +372,7 @@ typedef struct uint8_t xtalType; /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */ uint8_t flashContRead; /*!< Whether enable flash continue read */ uint32_t sleepTime; /*!< PDS sleep time */ - SPI_Flash_Cfg_Type *flashCfg; /*!< Flash config pointer, used when power down flash */ + spi_flash_cfg_type *flashCfg; /*!< Flash config pointer, used when power down flash */ PDS_LDO_LEVEL_Type ldoLevel; /*!< LDO level */ void (*preCbFun)(void); /*!< Pre callback function */ void (*postCbFun)(void); /*!< Post callback function */ @@ -473,8 +473,8 @@ BL_Err_Type PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask); BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig); BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set); BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad); -BL_Err_Type PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg); -BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg); +BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg); +BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg); BL_Err_Type PDS_Set_MCU0_Clock_Enable(void); BL_Err_Type PDS_Set_MCU0_Clock_Disable(void); BL_Err_Type PDS_Set_MCU0_Reset_Address(uint32_t addr); diff --git a/drivers/soc/bl808/std/include/bl808_sf_cfg.h b/drivers/soc/bl808/std/include/bl808_sf_cfg.h deleted file mode 100644 index ee315f7f..00000000 --- a/drivers/soc/bl808/std/include/bl808_sf_cfg.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SF_CFG_H__ -#define __BL808_SF_CFG_H__ - -#include "string.h" -#include "bl808_glb.h" -#include "bl808_glb_gpio.h" -#include "bl808_sflash.h" -#include "bl808_sf_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Public_Types - * @{ - */ - -/*@} end of group SF_CFG_Public_Types */ - -/** @defgroup SF_CFG_Public_Constants - * @{ - */ - -/*@} end of group SF_CFG_Public_Constants */ - -/** @defgroup SF_CFG_Public_Macros - * @{ - */ -/* Flash option sf2 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_34 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_35 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_36 -#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_37 -#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_38 -#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_39 -#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 -#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF - -/*@} end of group SF_CFG_Public_Macros */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault); -BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); -BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); -uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); -BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SF_CFG_H__ */ diff --git a/drivers/soc/bl808/std/include/bl808_sf_ctrl.h b/drivers/soc/bl808/std/include/bl808_sf_ctrl.h deleted file mode 100644 index eea942a1..00000000 --- a/drivers/soc/bl808/std/include/bl808_sf_ctrl.h +++ /dev/null @@ -1,470 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SF_CTRL_H__ -#define __BL808_SF_CTRL_H__ - -#include "sf_ctrl_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Serial flash pad type definition - */ -typedef enum { - SF_CTRL_PAD1, /*!< SF Ctrl pad 1 */ - SF_CTRL_PAD2, /*!< SF Ctrl pad 2 */ - SF_CTRL_PAD3, /*!< SF Ctrl pad 3 */ -} SF_Ctrl_Pad_Type; - -/** - * @brief Serial flash config pin select type definition - */ -typedef enum { - SF_IO_EMB_SWAP_IO0_IO3 = 0x0, /*!< SF select embedded flash swap io0 with io3 */ - SF_IO_EMB_SWAP_DUAL_IO0_IO3 = 0x1, /*!< SF select embedded flash swap dual io0 with io3 */ - SF_IO_EMB_SWAP_NONE = 0x2, /*!< SF select embedded flash no swap */ - SF_IO_EMB_SWAP_NONE_DUAL_IO0 = 0x3, /*!< SF select embedded flash no swap and use dual io0 */ - SF_IO_EXT_SF2 = 0x4, /*!< SF select external flash SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 = 0x14, /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 = 0x15, /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 = 0x16, /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 = 0x17, /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */ -} SF_Ctrl_Pin_Select; - -/** - * @brief Serial flash select bank control type definition - */ -typedef enum { - SF_CTRL_FLASH_BANK0, /*!< SF Ctrl select flash bank0 */ - SF_CTRL_FLASH_BANK1, /*!< SF Ctrl select flash bank1 */ -} SF_Ctrl_Bank_Select; - -/** - * @brief Serial flash controller wrap mode type definition - */ -typedef enum { - SF_CTRL_WRAP_MODE_0, /*!< Cmds bypass wrap commands to macro, original mode */ - SF_CTRL_WRAP_MODE_1, /*!< Cmds handle wrap commands, original mode */ - SF_CTRL_WRAP_MODE_2, /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */ - SF_CTRL_WRAP_MODE_3, /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */ -} SF_Ctrl_Wrap_Mode; - -/** - * @brief Serail flash controller wrap mode len type definition - */ -typedef enum { - SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */ - SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */ - SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */ - SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */ - SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */ - SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */ - SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */ - SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */ - SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */ - SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */ -} SF_Ctrl_Wrap_Len_Type; - -/** - * @brief Serail flash controller memory remap type define - */ -typedef enum { - SF_CTRL_ORIGINAL_MEMORY_MAP, /*!< Remap none, use two addr map when use dual flash */ - SF_CTRL_REMAP_16MB, /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */ - SF_CTRL_REMAP_8MB, /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */ - SF_CTRL_REMAP_4MB, /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */ -} SF_Ctrl_Remap_Type; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ - SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ -} SF_Ctrl_Owner_Type; - -/** - * @brief Read and write type definition - */ -typedef enum { - SF_CTRL_READ, /*!< Serail flash read command flag */ - SF_CTRL_WRITE, /*!< Serail flash write command flag */ -} SF_Ctrl_RW_Type; - -/** - * @brief Serail flash interface IO type definition - */ -typedef enum { - SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ - SF_CTRL_DO_MODE, /*!< Dual Output mode define */ - SF_CTRL_QO_MODE, /*!< Quad Output mode define */ - SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ - SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ -} SF_Ctrl_IO_Type; - -/** - * @brief Serail flash controller interface mode type definition - */ -typedef enum { - SF_CTRL_SPI_MODE, /*!< SPI mode define */ - SF_CTRL_QPI_MODE, /*!< QPI mode define */ -} SF_Ctrl_Mode_Type; - -/** - * @brief Serail flash controller command mode type definition - */ -typedef enum { - SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ - SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ -} SF_Ctrl_Cmd_Mode_Type; - -/** - * @brief Serail flash controller address mode type definition - */ -typedef enum { - SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ - SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ - SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ -} SF_Ctrl_Addr_Mode_Type; - -/** - * @brief Serail flash controller dummy mode type definition - */ -typedef enum { - SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ - SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ - SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ -} SF_Ctrl_Dmy_Mode_Type; - -/** - * @brief Serail flash controller data mode type definition - */ -typedef enum { - SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ - SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ - SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ -} SF_Ctrl_Data_Mode_Type; - -/** - * @brief Serail flash controller AES mode type definition - */ -typedef enum { - SF_CTRL_AES_CTR_MODE, /*!< Serail flash AES CTR mode */ - SF_CTRL_AES_XTS_MODE, /*!< Serail flash AES XTS mode */ -} SF_Ctrl_AES_Mode_Type; - -/** - * @brief Serail flash controller AES key len type definition - */ -typedef enum { - SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ - SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ - SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ - SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ -} SF_Ctrl_AES_Key_Type; - -/** - * @brief Serail flash controller configuration structure type definition - */ -typedef struct -{ - SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ - BL_Fun_Type en32bAddr; /*!< Sflash enable 32-bits address */ - uint8_t clkDelay; /*!< Clock count for read due to pad delay */ - uint8_t clkInvert; /*!< Clock invert */ - uint8_t rxClkInvert; /*!< RX clock invert */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ -} SF_Ctrl_Cfg_Type; - -/** - * @brief SF Ctrl bank2 controller configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type sbus2Select; /*!< Select sbus2 as 2nd flash controller */ - BL_Fun_Type bank2RxClkInvertSrc; /*!< Select bank2 rx clock invert source */ - BL_Fun_Type bank2RxClkInvertSel; /*!< Select inveted bank2 rx clock */ - BL_Fun_Type bank2DelaySrc; /*!< Select bank2 read delay source */ - uint8_t bank2ClkDelay; /*!< Bank2 read delay cycle = n + 1 */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ - SF_Ctrl_Remap_Type remap; /*!< Select dual flash memory remap set */ - uint8_t remapLock; /*!< Select memory remap lock */ -} SF_Ctrl_Bank2_Cfg; - -/** - * @brief SF Ctrl cmds configuration structure type definition - */ -typedef struct -{ - uint8_t ackLatency; /*!< SF Ctrl ack latency cycles */ - BL_Fun_Type cmdsCoreEn; /*!< SF Ctrl cmds core enable */ - BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */ - SF_Ctrl_Wrap_Mode cmdsWrapMode; /*!< SF Ctrl cmds wrap mode */ - SF_Ctrl_Wrap_Len_Type cmdsWrapLen; /*!< SF Ctrl cmds wrap length */ -} SF_Ctrl_Cmds_Cfg; - -/** - * @brief Serail flash command configuration structure type definition - */ -typedef struct -{ - uint8_t rwFlag; /*!< Read write flag */ - SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ - SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ - uint8_t addrSize; /*!< Address size */ - uint8_t dummyClks; /*!< Dummy clocks */ - SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ - SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ - uint8_t rsv[1]; /*!< */ - uint32_t nbData; /*!< Transfer number of bytes */ - uint32_t cmdBuf[2]; /*!< Command buffer */ -} SF_Ctrl_Cmd_Cfg_Type; - -/*@} end of group SF_CTRL_Public_Types */ - -/** @defgroup SF_CTRL_Public_Constants - * @{ - */ - -/** @defgroup SF_CTRL_PAD_TYPE - * @{ - */ -#define IS_SF_CTRL_PAD_TYPE(type) (((type) == SF_CTRL_PAD1) || \ - ((type) == SF_CTRL_PAD2) || \ - ((type) == SF_CTRL_PAD3)) - -/** @defgroup SF_CTRL_PIN_SELECT - * @{ - */ -#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \ - ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \ - ((type) == SF_IO_EMB_SWAP_NONE) || \ - ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \ - ((type) == SF_IO_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2)) - -/** @defgroup SF_CTRL_BANK_SELECT - * @{ - */ -#define IS_SF_CTRL_BANK_SELECT(type) (((type) == SF_CTRL_FLASH_BANK0) || \ - ((type) == SF_CTRL_FLASH_BANK1)) - -/** @defgroup SF_CTRL_WRAP_MODE - * @{ - */ -#define IS_SF_CTRL_WRAP_MODE(type) (((type) == SF_CTRL_WRAP_MODE_0) || \ - ((type) == SF_CTRL_WRAP_MODE_1) || \ - ((type) == SF_CTRL_WRAP_MODE_2) || \ - ((type) == SF_CTRL_WRAP_MODE_3)) - -/** @defgroup SF_CTRL_WRAP_LEN_TYPE - * @{ - */ -#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \ - ((type) == SF_CTRL_WRAP_LEN_16) || \ - ((type) == SF_CTRL_WRAP_LEN_32) || \ - ((type) == SF_CTRL_WRAP_LEN_64) || \ - ((type) == SF_CTRL_WRAP_LEN_128) || \ - ((type) == SF_CTRL_WRAP_LEN_256) || \ - ((type) == SF_CTRL_WRAP_LEN_512) || \ - ((type) == SF_CTRL_WRAP_LEN_1024) || \ - ((type) == SF_CTRL_WRAP_LEN_2048) || \ - ((type) == SF_CTRL_WRAP_LEN_4096)) - -/** @defgroup SF_CTRL_REMAP_TYPE - * @{ - */ -#define IS_SF_CTRL_REMAP_TYPE(type) (((type) == SF_CTRL_ORIGINAL_MEMORY_MAP) || \ - ((type) == SF_CTRL_REMAP_16MB) || \ - ((type) == SF_CTRL_REMAP_8MB) || \ - ((type) == SF_CTRL_REMAP_4MB)) - -/** @defgroup SF_CTRL_OWNER_TYPE - * @{ - */ -#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ - ((type) == SF_CTRL_OWNER_IAHB)) - -/** @defgroup SF_CTRL_RW_TYPE - * @{ - */ -#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ - ((type) == SF_CTRL_WRITE)) - -/** @defgroup SF_CTRL_IO_TYPE - * @{ - */ -#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ - ((type) == SF_CTRL_DO_MODE) || \ - ((type) == SF_CTRL_QO_MODE) || \ - ((type) == SF_CTRL_DIO_MODE) || \ - ((type) == SF_CTRL_QIO_MODE)) - -/** @defgroup SF_CTRL_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ - ((type) == SF_CTRL_QPI_MODE)) - -/** @defgroup SF_CTRL_CMD_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ - ((type) == SF_CTRL_CMD_4_LINES)) - -/** @defgroup SF_CTRL_ADDR_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ - ((type) == SF_CTRL_ADDR_2_LINES) || \ - ((type) == SF_CTRL_ADDR_4_LINES)) - -/** @defgroup SF_CTRL_DMY_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ - ((type) == SF_CTRL_DUMMY_2_LINES) || \ - ((type) == SF_CTRL_DUMMY_4_LINES)) - -/** @defgroup SF_CTRL_DATA_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ - ((type) == SF_CTRL_DATA_2_LINES) || \ - ((type) == SF_CTRL_DATA_4_LINES)) - -/** @defgroup SF_CTRL_AES_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_MODE_TYPE(type) (((type) == SF_CTRL_AES_CTR_MODE) || \ - ((type) == SF_CTRL_AES_XTS_MODE)) - -/** @defgroup SF_CTRL_AES_KEY_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ - ((type) == SF_CTRL_AES_256BITS) || \ - ((type) == SF_CTRL_AES_192BITS) || \ - ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) - -/*@} end of group SF_CTRL_Public_Constants */ - -/** @defgroup SF_CTRL_Public_Macros - * @{ - */ -#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF -#define NOR_FLASH_CTRL_BUF_SIZE 256 -#define NAND_FLASH_CTRL_BUF_SIZE 512 - -/*@} end of group SF_CTRL_Public_Macros */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void); -#endif -void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); -void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg); -void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay); -void SF_Ctrl_Sbus2_Hold_Sram(void); -void SF_Ctrl_Sbus2_Release_Sram(void); -BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void); -void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad); -void SF_Ctrl_Sbus2_Revoke_replace(void); -void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert); -void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr); -uint8_t SF_Ctrl_Get_Clock_Delay(void); -void SF_Ctrl_Set_Clock_Delay(uint8_t delay); -uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void); -void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock); -void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel); -void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); -void SF_Ctrl_Disable(void); -void SF_Ctrl_AES_Enable_BE(void); -void SF_Ctrl_AES_Enable_LE(void); -void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, - uint8_t locked); -void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode); -void SF_Ctrl_AES_Enable(void); -void SF_Ctrl_AES_Disable(void); -BL_Sts_Type SF_Ctrl_Is_AES_Enable(void); -void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock); -void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); -void SF_Ctrl_Disable_Wrap_Access(uint8_t disable); -void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -BL_Sts_Type SF_Ctrl_GetBusyState(void); - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SF_CTRL_H__ */ diff --git a/drivers/soc/bl808/std/include/bl808_sflash.h b/drivers/soc/bl808/std/include/bl808_sflash.h deleted file mode 100644 index 51f9bc2e..00000000 --- a/drivers/soc/bl808/std/include/bl808_sflash.h +++ /dev/null @@ -1,218 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sflah.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SFLAH_H__ -#define __BL808_SFLAH_H__ - -#include "bl808_common.h" -#include "bl808_sf_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLAH - * @{ - */ - -/** @defgroup SFLAH_Public_Types - * @{ - */ - -/** - * @brief Serial flash configuration structure type definition - */ -typedef struct -{ - uint8_t ioMode; /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */ - uint8_t cReadSupport; /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */ - uint8_t clkDelay; /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */ - uint8_t clkInvert; /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */ - uint8_t resetEnCmd; /*!< Flash enable reset command */ - uint8_t resetCmd; /*!< Flash reset command */ - uint8_t resetCreadCmd; /*!< Flash reset continuous read command */ - uint8_t resetCreadCmdSize; /*!< Flash reset continuous read command size */ - uint8_t jedecIdCmd; /*!< JEDEC ID command */ - uint8_t jedecIdCmdDmyClk; /*!< JEDEC ID command dummy clock */ - uint8_t enter32BitsAddrCmd; /*!< Enter 32-bits addr command */ - uint8_t exit32BitsAddrCmd; /*!< Exit 32-bits addr command */ - uint8_t sectorSize; /*!< *1024bytes */ - uint8_t mid; /*!< Manufacturer ID */ - uint16_t pageSize; /*!< Page size */ - uint8_t chipEraseCmd; /*!< Chip erase cmd */ - uint8_t sectorEraseCmd; /*!< Sector erase command */ - uint8_t blk32EraseCmd; /*!< Block 32K erase command,some Micron not support */ - uint8_t blk64EraseCmd; /*!< Block 64K erase command */ - uint8_t writeEnableCmd; /*!< Need before every erase or program */ - uint8_t pageProgramCmd; /*!< Page program cmd */ - uint8_t qpageProgramCmd; /*!< QIO page program cmd */ - uint8_t qppAddrMode; /*!< QIO page program address mode */ - uint8_t fastReadCmd; /*!< Fast read command */ - uint8_t frDmyClk; /*!< Fast read command dummy clock */ - uint8_t qpiFastReadCmd; /*!< QPI fast read command */ - uint8_t qpiFrDmyClk; /*!< QPI fast read command dummy clock */ - uint8_t fastReadDoCmd; /*!< Fast read dual output command */ - uint8_t frDoDmyClk; /*!< Fast read dual output command dummy clock */ - uint8_t fastReadDioCmd; /*!< Fast read dual io comamnd */ - uint8_t frDioDmyClk; /*!< Fast read dual io command dummy clock */ - uint8_t fastReadQoCmd; /*!< Fast read quad output comamnd */ - uint8_t frQoDmyClk; /*!< Fast read quad output comamnd dummy clock */ - uint8_t fastReadQioCmd; /*!< Fast read quad io comamnd */ - uint8_t frQioDmyClk; /*!< Fast read quad io comamnd dummy clock */ - uint8_t qpiFastReadQioCmd; /*!< QPI fast read quad io comamnd */ - uint8_t qpiFrQioDmyClk; /*!< QPI fast read QIO dummy clock */ - uint8_t qpiPageProgramCmd; /*!< QPI program command */ - uint8_t writeVregEnableCmd; /*!< Enable write reg */ - uint8_t wrEnableIndex; /*!< Write enable register index */ - uint8_t qeIndex; /*!< Quad mode enable register index */ - uint8_t busyIndex; /*!< Busy status register index */ - uint8_t wrEnableBit; /*!< Write enable bit pos */ - uint8_t qeBit; /*!< Quad enable bit pos */ - uint8_t busyBit; /*!< Busy status bit pos */ - uint8_t wrEnableWriteRegLen; /*!< Register length of write enable */ - uint8_t wrEnableReadRegLen; /*!< Register length of write enable status */ - uint8_t qeWriteRegLen; /*!< Register length of contain quad enable */ - uint8_t qeReadRegLen; /*!< Register length of contain quad enable status */ - uint8_t releasePowerDown; /*!< Release power down command */ - uint8_t busyReadRegLen; /*!< Register length of contain busy status */ - uint8_t readRegCmd[4]; /*!< Read register command buffer */ - uint8_t writeRegCmd[4]; /*!< Write register command buffer */ - uint8_t enterQpi; /*!< Enter qpi command */ - uint8_t exitQpi; /*!< Exit qpi command */ - uint8_t cReadMode; /*!< Config data for continuous read mode */ - uint8_t cRExit; /*!< Config data for exit continuous read mode */ - uint8_t burstWrapCmd; /*!< Enable burst wrap command */ - uint8_t burstWrapCmdDmyClk; /*!< Enable burst wrap command dummy clock */ - uint8_t burstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t burstWrapData; /*!< Data to enable burst wrap */ - uint8_t deBurstWrapCmd; /*!< Disable burst wrap command */ - uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */ - uint8_t deBurstWrapDataMode; /*!< Data and address mode for this command */ - uint8_t deBurstWrapData; /*!< Data to disable burst wrap */ - uint16_t timeEsector; /*!< 4K erase time */ - uint16_t timeE32k; /*!< 32K erase time */ - uint16_t timeE64k; /*!< 64K erase time */ - uint16_t timePagePgm; /*!< Page program time */ - uint16_t timeCe; /*!< Chip erase time in ms */ - uint8_t pdDelay; /*!< Release power down command delay time for wake up */ - uint8_t qeData; /*!< QE set data */ -} __attribute__((packed)) SPI_Flash_Cfg_Type; - -/** - * @brief Serial flash security register configuration - */ -typedef struct -{ - uint8_t eraseCmd; /*!< Erase security register command */ - uint8_t programCmd; /*!< Program security register command */ - uint8_t readCmd; /*!< Read security register command */ - uint8_t enterSecOptCmd; /*!< Enter security register option mode command */ - uint8_t exitSecOptCmd; /*!< Exit security register option mode command */ - uint8_t blockNum; /*!< Security register block number */ - uint8_t *data; /*!< Data pointer to be program/read */ - uint32_t addr; /*!< Start address to be program/read */ - uint32_t len; /*!< Data length to be program/read */ -} SFlash_Sec_Reg_Cfg; -/*@} end of group SFLAH_Public_Types */ - -/** @defgroup SFLAH_Public_Constants - * @{ - */ - -/*@} end of group SFLAH_Public_Constants */ - -/** @defgroup SFLAH_Public_Macros - * @{ - */ -#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024) -#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024) -#define BFLB_SPIFLASH_CMD_INVALID 0xff - -/*@} end of group SFLAH_Public_Macros */ - -/** @defgroup SFLAH_Public_Functions - * @{ - */ -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); -BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode); -BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen); -BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, - uint8_t regLen); -BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum); -BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum); -BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr); -void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen); -void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data); -void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr); -void SFlash_Powerdown(void); -void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, - SF_Ctrl_Bank_Select bank); -void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr); -BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg); -void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg); -BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, - uint32_t len, SF_Ctrl_Bank_Select bank); -BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - SF_Ctrl_Bank_Select bank); -void SFlash_IDbus_Read_Disable(void); -BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos); -BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, - SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg); -BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, - uint32_t len); -BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len); - -/*@} end of group SFLAH_Public_Functions */ - -/*@} end of group SFLAH */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SFLAH_H__ */ diff --git a/drivers/soc/bl808/std/include/bl808_xip_sflash.h b/drivers/soc/bl808/std/include/bl808_xip_sflash.h deleted file mode 100644 index fe9918e4..00000000 --- a/drivers/soc/bl808/std/include/bl808_xip_sflash.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_xip_sflash.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_XIP_SFLASH_H__ -#define __BL808_XIP_SFLASH_H__ - -#include "bl808_common.h" -#include "bl808_sflash.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Public_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Types */ - -/** @defgroup XIP_SFLASH_Public_Constants - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Constants */ - -/** @defgroup XIP_SFLASH_Public_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Public_Macros */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ -BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, - int len, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, - uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, - uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, - BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank); -void XIP_SFlash_Opt_Enter(uint8_t *aesEnable); -void XIP_SFlash_Opt_Exit(uint8_t aesEnable); - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_XIP_SFLASH_H__ */ diff --git a/drivers/soc/bl808/std/include/hardware/dtsrc_reg.h b/drivers/soc/bl808/std/include/hardware/dtsrc_reg.h deleted file mode 100644 index 879e0ebb..00000000 --- a/drivers/soc/bl808/std/include/hardware/dtsrc_reg.h +++ /dev/null @@ -1,505 +0,0 @@ -/** - ****************************************************************************** - * @file dtsrc_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DTSRC_REG_H__ -#define __DTSRC_REG_H__ - -#include "bl808.h" - -/* 0x0 : config */ -#define DTSRC_CONFIG_OFFSET (0x0) -#define DTSRC_CR_ENABLE DTSRC_CR_ENABLE -#define DTSRC_CR_ENABLE_POS (0U) -#define DTSRC_CR_ENABLE_LEN (1U) -#define DTSRC_CR_ENABLE_MSK (((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS) -#define DTSRC_CR_ENABLE_UMSK (~(((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS)) -#define DTSRC_CR_AXI_EN DTSRC_CR_AXI_EN -#define DTSRC_CR_AXI_EN_POS (1U) -#define DTSRC_CR_AXI_EN_LEN (1U) -#define DTSRC_CR_AXI_EN_MSK (((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS) -#define DTSRC_CR_AXI_EN_UMSK (~(((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS)) -#define DTSRC_CR_MODE_CEA_861 DTSRC_CR_MODE_CEA_861 -#define DTSRC_CR_MODE_CEA_861_POS (2U) -#define DTSRC_CR_MODE_CEA_861_LEN (1U) -#define DTSRC_CR_MODE_CEA_861_MSK (((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS) -#define DTSRC_CR_MODE_CEA_861_UMSK (~(((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS)) -#define DTSRC_CR_SNSR_EN DTSRC_CR_SNSR_EN -#define DTSRC_CR_SNSR_EN_POS (3U) -#define DTSRC_CR_SNSR_EN_LEN (1U) -#define DTSRC_CR_SNSR_EN_MSK (((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS) -#define DTSRC_CR_SNSR_EN_UMSK (~(((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS)) -#define DTSRC_CR_SNSR_HSYNC_INV DTSRC_CR_SNSR_HSYNC_INV -#define DTSRC_CR_SNSR_HSYNC_INV_POS (4U) -#define DTSRC_CR_SNSR_HSYNC_INV_LEN (1U) -#define DTSRC_CR_SNSR_HSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS) -#define DTSRC_CR_SNSR_HSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS)) -#define DTSRC_CR_SNSR_VSYNC_INV DTSRC_CR_SNSR_VSYNC_INV -#define DTSRC_CR_SNSR_VSYNC_INV_POS (5U) -#define DTSRC_CR_SNSR_VSYNC_INV_LEN (1U) -#define DTSRC_CR_SNSR_VSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS) -#define DTSRC_CR_SNSR_VSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS)) -#define DTSRC_CR_AXI_SWAP_MODE DTSRC_CR_AXI_SWAP_MODE -#define DTSRC_CR_AXI_SWAP_MODE_POS (7U) -#define DTSRC_CR_AXI_SWAP_MODE_LEN (1U) -#define DTSRC_CR_AXI_SWAP_MODE_MSK (((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS) -#define DTSRC_CR_AXI_SWAP_MODE_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SEL DTSRC_CR_AXI_SWAP_IDX_SEL -#define DTSRC_CR_AXI_SWAP_IDX_SEL_POS (8U) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_LEN (4U) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SWM DTSRC_CR_AXI_SWAP_IDX_SWM -#define DTSRC_CR_AXI_SWAP_IDX_SWM_POS (12U) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_LEN (1U) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SWV DTSRC_CR_AXI_SWAP_IDX_SWV -#define DTSRC_CR_AXI_SWAP_IDX_SWV_POS (13U) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_LEN (1U) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS)) -#define DTSRC_CR_AXI_DVP_DATA_MODE DTSRC_CR_AXI_DVP_DATA_MODE -#define DTSRC_CR_AXI_DVP_DATA_MODE_POS (16U) -#define DTSRC_CR_AXI_DVP_DATA_MODE_LEN (3U) -#define DTSRC_CR_AXI_DVP_DATA_MODE_MSK (((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS) -#define DTSRC_CR_AXI_DVP_DATA_MODE_UMSK (~(((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS)) -#define DTSRC_CR_AXI_B0_SEL DTSRC_CR_AXI_B0_SEL -#define DTSRC_CR_AXI_B0_SEL_POS (20U) -#define DTSRC_CR_AXI_B0_SEL_LEN (2U) -#define DTSRC_CR_AXI_B0_SEL_MSK (((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS) -#define DTSRC_CR_AXI_B0_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS)) -#define DTSRC_CR_AXI_B1_SEL DTSRC_CR_AXI_B1_SEL -#define DTSRC_CR_AXI_B1_SEL_POS (22U) -#define DTSRC_CR_AXI_B1_SEL_LEN (2U) -#define DTSRC_CR_AXI_B1_SEL_MSK (((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS) -#define DTSRC_CR_AXI_B1_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS)) -#define DTSRC_CR_AXI_B2_SEL DTSRC_CR_AXI_B2_SEL -#define DTSRC_CR_AXI_B2_SEL_POS (24U) -#define DTSRC_CR_AXI_B2_SEL_LEN (2U) -#define DTSRC_CR_AXI_B2_SEL_MSK (((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS) -#define DTSRC_CR_AXI_B2_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS)) - -/* 0x4 : frame_size_h */ -#define DTSRC_FRAME_SIZE_H_OFFSET (0x4) -#define DTSRC_CR_TOTAL_H DTSRC_CR_TOTAL_H -#define DTSRC_CR_TOTAL_H_POS (0U) -#define DTSRC_CR_TOTAL_H_LEN (12U) -#define DTSRC_CR_TOTAL_H_MSK (((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS) -#define DTSRC_CR_TOTAL_H_UMSK (~(((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS)) -#define DTSRC_CR_BLANK_H DTSRC_CR_BLANK_H -#define DTSRC_CR_BLANK_H_POS (16U) -#define DTSRC_CR_BLANK_H_LEN (12U) -#define DTSRC_CR_BLANK_H_MSK (((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS) -#define DTSRC_CR_BLANK_H_UMSK (~(((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS)) - -/* 0x8 : frame_size_v */ -#define DTSRC_FRAME_SIZE_V_OFFSET (0x8) -#define DTSRC_CR_TOTAL_V DTSRC_CR_TOTAL_V -#define DTSRC_CR_TOTAL_V_POS (0U) -#define DTSRC_CR_TOTAL_V_LEN (12U) -#define DTSRC_CR_TOTAL_V_MSK (((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS) -#define DTSRC_CR_TOTAL_V_UMSK (~(((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS)) -#define DTSRC_CR_BLANK_V DTSRC_CR_BLANK_V -#define DTSRC_CR_BLANK_V_POS (16U) -#define DTSRC_CR_BLANK_V_LEN (12U) -#define DTSRC_CR_BLANK_V_MSK (((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS) -#define DTSRC_CR_BLANK_V_UMSK (~(((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS)) - -/* 0xC : frame_size_cea_861 */ -#define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC) -#define DTSRC_CR_H_DURATION DTSRC_CR_H_DURATION -#define DTSRC_CR_H_DURATION_POS (0U) -#define DTSRC_CR_H_DURATION_LEN (8U) -#define DTSRC_CR_H_DURATION_MSK (((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS) -#define DTSRC_CR_H_DURATION_UMSK (~(((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS)) -#define DTSRC_CR_H_PLACEMENT DTSRC_CR_H_PLACEMENT -#define DTSRC_CR_H_PLACEMENT_POS (8U) -#define DTSRC_CR_H_PLACEMENT_LEN (8U) -#define DTSRC_CR_H_PLACEMENT_MSK (((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS) -#define DTSRC_CR_H_PLACEMENT_UMSK (~(((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS)) -#define DTSRC_CR_V_DURATION DTSRC_CR_V_DURATION -#define DTSRC_CR_V_DURATION_POS (16U) -#define DTSRC_CR_V_DURATION_LEN (8U) -#define DTSRC_CR_V_DURATION_MSK (((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS) -#define DTSRC_CR_V_DURATION_UMSK (~(((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS)) -#define DTSRC_CR_V_PLACEMENT DTSRC_CR_V_PLACEMENT -#define DTSRC_CR_V_PLACEMENT_POS (24U) -#define DTSRC_CR_V_PLACEMENT_LEN (8U) -#define DTSRC_CR_V_PLACEMENT_MSK (((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS) -#define DTSRC_CR_V_PLACEMENT_UMSK (~(((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS)) - -/* 0x10 : pix_data_range */ -#define DTSRC_PIX_DATA_RANGE_OFFSET (0x10) -#define DTSRC_CR_DATA_MIN DTSRC_CR_DATA_MIN -#define DTSRC_CR_DATA_MIN_POS (0U) -#define DTSRC_CR_DATA_MIN_LEN (16U) -#define DTSRC_CR_DATA_MIN_MSK (((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS) -#define DTSRC_CR_DATA_MIN_UMSK (~(((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS)) -#define DTSRC_CR_DATA_MAX DTSRC_CR_DATA_MAX -#define DTSRC_CR_DATA_MAX_POS (16U) -#define DTSRC_CR_DATA_MAX_LEN (16U) -#define DTSRC_CR_DATA_MAX_MSK (((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS) -#define DTSRC_CR_DATA_MAX_UMSK (~(((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS)) - -/* 0x14 : pix_data_step */ -#define DTSRC_PIX_DATA_STEP_OFFSET (0x14) -#define DTSRC_CR_DATA_STEP DTSRC_CR_DATA_STEP -#define DTSRC_CR_DATA_STEP_POS (0U) -#define DTSRC_CR_DATA_STEP_LEN (8U) -#define DTSRC_CR_DATA_STEP_MSK (((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS) -#define DTSRC_CR_DATA_STEP_UMSK (~(((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS)) - -/* 0x20 : axi2dvp_setting */ -#define DTSRC_AXI2DVP_SETTING_OFFSET (0x20) -#define DTSRC_CR_AXI_XLEN DTSRC_CR_AXI_XLEN -#define DTSRC_CR_AXI_XLEN_POS (0U) -#define DTSRC_CR_AXI_XLEN_LEN (3U) -#define DTSRC_CR_AXI_XLEN_MSK (((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS) -#define DTSRC_CR_AXI_XLEN_UMSK (~(((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS)) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR DTSRC_CR_AXI_DRAIN_ERR_CLR -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_POS (4U) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN (1U) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_MSK (((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_UMSK (~(((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS)) -#define DTSRC_CR_AXI_420_MODE DTSRC_CR_AXI_420_MODE -#define DTSRC_CR_AXI_420_MODE_POS (8U) -#define DTSRC_CR_AXI_420_MODE_LEN (1U) -#define DTSRC_CR_AXI_420_MODE_MSK (((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS) -#define DTSRC_CR_AXI_420_MODE_UMSK (~(((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS)) -#define DTSRC_CR_AXI_420_UD_SEL DTSRC_CR_AXI_420_UD_SEL -#define DTSRC_CR_AXI_420_UD_SEL_POS (9U) -#define DTSRC_CR_AXI_420_UD_SEL_LEN (1U) -#define DTSRC_CR_AXI_420_UD_SEL_MSK (((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS) -#define DTSRC_CR_AXI_420_UD_SEL_UMSK (~(((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS)) -#define DTSRC_CR_QOS_SW_MODE DTSRC_CR_QOS_SW_MODE -#define DTSRC_CR_QOS_SW_MODE_POS (10U) -#define DTSRC_CR_QOS_SW_MODE_LEN (1U) -#define DTSRC_CR_QOS_SW_MODE_MSK (((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS) -#define DTSRC_CR_QOS_SW_MODE_UMSK (~(((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS)) -#define DTSRC_CR_QOS_SW DTSRC_CR_QOS_SW -#define DTSRC_CR_QOS_SW_POS (11U) -#define DTSRC_CR_QOS_SW_LEN (1U) -#define DTSRC_CR_QOS_SW_MSK (((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS) -#define DTSRC_CR_QOS_SW_UMSK (~(((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS)) - -/* 0x24 : axi2dvp_start_addr_by */ -#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24) -#define DTSRC_CR_AXI_ADDR_START_BY DTSRC_CR_AXI_ADDR_START_BY -#define DTSRC_CR_AXI_ADDR_START_BY_POS (0U) -#define DTSRC_CR_AXI_ADDR_START_BY_LEN (32U) -#define DTSRC_CR_AXI_ADDR_START_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS) -#define DTSRC_CR_AXI_ADDR_START_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS)) - -/* 0x28 : axi2dvp_burst_cnt */ -#define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28) -#define DTSRC_CR_AXI_FRAME_BC DTSRC_CR_AXI_FRAME_BC -#define DTSRC_CR_AXI_FRAME_BC_POS (0U) -#define DTSRC_CR_AXI_FRAME_BC_LEN (32U) -#define DTSRC_CR_AXI_FRAME_BC_MSK (((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS) -#define DTSRC_CR_AXI_FRAME_BC_UMSK (~(((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS)) - -/* 0x2C : axi2dvp_status */ -#define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C) -#define DTSRC_ST_AXI_FIFO_CNT_BY DTSRC_ST_AXI_FIFO_CNT_BY -#define DTSRC_ST_AXI_FIFO_CNT_BY_POS (0U) -#define DTSRC_ST_AXI_FIFO_CNT_BY_LEN (7U) -#define DTSRC_ST_AXI_FIFO_CNT_BY_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS) -#define DTSRC_ST_AXI_FIFO_CNT_BY_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS)) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY DTSRC_ST_AXI_DRAIN_ERROR_BY -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_POS (7U) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN (1U) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS)) -#define DTSRC_ST_AXI_STATE_IDLE_BY DTSRC_ST_AXI_STATE_IDLE_BY -#define DTSRC_ST_AXI_STATE_IDLE_BY_POS (8U) -#define DTSRC_ST_AXI_STATE_IDLE_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_IDLE_BY_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS) -#define DTSRC_ST_AXI_STATE_IDLE_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS)) -#define DTSRC_ST_AXI_STATE_FUNC_BY DTSRC_ST_AXI_STATE_FUNC_BY -#define DTSRC_ST_AXI_STATE_FUNC_BY_POS (9U) -#define DTSRC_ST_AXI_STATE_FUNC_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_FUNC_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS) -#define DTSRC_ST_AXI_STATE_FUNC_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS)) -#define DTSRC_ST_AXI_STATE_FLSH_BY DTSRC_ST_AXI_STATE_FLSH_BY -#define DTSRC_ST_AXI_STATE_FLSH_BY_POS (10U) -#define DTSRC_ST_AXI_STATE_FLSH_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_FLSH_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS) -#define DTSRC_ST_AXI_STATE_FLSH_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS)) -#define DTSRC_ST_AXI_FIFO_CNT_UV DTSRC_ST_AXI_FIFO_CNT_UV -#define DTSRC_ST_AXI_FIFO_CNT_UV_POS (16U) -#define DTSRC_ST_AXI_FIFO_CNT_UV_LEN (7U) -#define DTSRC_ST_AXI_FIFO_CNT_UV_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS) -#define DTSRC_ST_AXI_FIFO_CNT_UV_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS)) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV DTSRC_ST_AXI_DRAIN_ERROR_UV -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_POS (23U) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN (1U) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS)) -#define DTSRC_ST_AXI_STATE_IDLE_UV DTSRC_ST_AXI_STATE_IDLE_UV -#define DTSRC_ST_AXI_STATE_IDLE_UV_POS (24U) -#define DTSRC_ST_AXI_STATE_IDLE_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_IDLE_UV_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS) -#define DTSRC_ST_AXI_STATE_IDLE_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS)) -#define DTSRC_ST_AXI_STATE_FUNC_UV DTSRC_ST_AXI_STATE_FUNC_UV -#define DTSRC_ST_AXI_STATE_FUNC_UV_POS (25U) -#define DTSRC_ST_AXI_STATE_FUNC_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_FUNC_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS) -#define DTSRC_ST_AXI_STATE_FUNC_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS)) -#define DTSRC_ST_AXI_STATE_FLSH_UV DTSRC_ST_AXI_STATE_FLSH_UV -#define DTSRC_ST_AXI_STATE_FLSH_UV_POS (26U) -#define DTSRC_ST_AXI_STATE_FLSH_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_FLSH_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS) -#define DTSRC_ST_AXI_STATE_FLSH_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS)) - -/* 0x30 : axi2dvp_swap_addr_by */ -#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30) -#define DTSRC_CR_AXI_ADDR_SWAP_BY DTSRC_CR_AXI_ADDR_SWAP_BY -#define DTSRC_CR_AXI_ADDR_SWAP_BY_POS (0U) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_LEN (32U) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS)) - -/* 0x34 : axi2dvp_prefetch */ -#define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34) -#define DTSRC_CR_PREFETCH_V DTSRC_CR_PREFETCH_V -#define DTSRC_CR_PREFETCH_V_POS (0U) -#define DTSRC_CR_PREFETCH_V_LEN (12U) -#define DTSRC_CR_PREFETCH_V_MSK (((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS) -#define DTSRC_CR_PREFETCH_V_UMSK (~(((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS)) - -/* 0x38 : snsr2dvp_wait_pos */ -#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38) -#define DTSRC_CR_SNSR_FIFO_TH DTSRC_CR_SNSR_FIFO_TH -#define DTSRC_CR_SNSR_FIFO_TH_POS (0U) -#define DTSRC_CR_SNSR_FIFO_TH_LEN (11U) -#define DTSRC_CR_SNSR_FIFO_TH_MSK (((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS) -#define DTSRC_CR_SNSR_FIFO_TH_UMSK (~(((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS)) - -/* 0x40 : axi2dvp_start_addr_uv */ -#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40) -#define DTSRC_CR_AXI_ADDR_START_UV DTSRC_CR_AXI_ADDR_START_UV -#define DTSRC_CR_AXI_ADDR_START_UV_POS (0U) -#define DTSRC_CR_AXI_ADDR_START_UV_LEN (32U) -#define DTSRC_CR_AXI_ADDR_START_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS) -#define DTSRC_CR_AXI_ADDR_START_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS)) - -/* 0x44 : axi2dvp_swap_addr_uv */ -#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44) -#define DTSRC_CR_AXI_ADDR_SWAP_UV DTSRC_CR_AXI_ADDR_SWAP_UV -#define DTSRC_CR_AXI_ADDR_SWAP_UV_POS (0U) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_LEN (32U) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS)) - -struct dtsrc_reg { - /* 0x0 : config */ - union { - struct { - uint32_t cr_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_axi_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_mode_cea_861 : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_snsr_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_snsr_hsync_inv : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_snsr_vsync_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t cr_axi_swap_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_sel : 4; /* [11: 8], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_swm : 1; /* [ 12], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_swv : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_axi_dvp_data_mode : 3; /* [18:16], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t cr_axi_b0_sel : 2; /* [21:20], r/w, 0x0 */ - uint32_t cr_axi_b1_sel : 2; /* [23:22], r/w, 0x1 */ - uint32_t cr_axi_b2_sel : 2; /* [25:24], r/w, 0x2 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } config; - - /* 0x4 : frame_size_h */ - union { - struct { - uint32_t cr_total_h : 12; /* [11: 0], r/w, 0x897 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_blank_h : 12; /* [27:16], r/w, 0x117 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } frame_size_h; - - /* 0x8 : frame_size_v */ - union { - struct { - uint32_t cr_total_v : 12; /* [11: 0], r/w, 0x464 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_blank_v : 12; /* [27:16], r/w, 0x2c */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } frame_size_v; - - /* 0xC : frame_size_cea_861 */ - union { - struct { - uint32_t cr_h_duration : 8; /* [ 7: 0], r/w, 0x83 */ - uint32_t cr_h_placement : 8; /* [15: 8], r/w, 0x57 */ - uint32_t cr_v_duration : 8; /* [23:16], r/w, 0x8 */ - uint32_t cr_v_placement : 8; /* [31:24], r/w, 0x3 */ - } BF; - uint32_t WORD; - } frame_size_cea_861; - - /* 0x10 : pix_data_range */ - union { - struct { - uint32_t cr_data_min : 16; /* [15: 0], r/w, 0x0 */ - uint32_t cr_data_max : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } pix_data_range; - - /* 0x14 : pix_data_step */ - union { - struct { - uint32_t cr_data_step : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pix_data_step; - - /* 0x18 reserved */ - uint8_t RESERVED0x18[8]; - - /* 0x20 : axi2dvp_setting */ - union { - struct { - uint32_t cr_axi_xlen : 3; /* [ 2: 0], r/w, 0x3 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_axi_drain_err_clr : 1; /* [ 4], w1p, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cr_axi_420_mode : 1; /* [ 8], r/w, 0x0 */ - uint32_t cr_axi_420_ud_sel : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_qos_sw_mode : 1; /* [ 10], r/w, 0x0 */ - uint32_t cr_qos_sw : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_setting; - - /* 0x24 : axi2dvp_start_addr_by */ - union { - struct { - uint32_t cr_axi_addr_start_by : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_start_addr_by; - - /* 0x28 : axi2dvp_burst_cnt */ - union { - struct { - uint32_t cr_axi_frame_bc : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_burst_cnt; - - /* 0x2C : axi2dvp_status */ - union { - struct { - uint32_t st_axi_fifo_cnt_by : 7; /* [ 6: 0], r, 0x0 */ - uint32_t st_axi_drain_error_by : 1; /* [ 7], r, 0x0 */ - uint32_t st_axi_state_idle_by : 1; /* [ 8], r, 0x0 */ - uint32_t st_axi_state_func_by : 1; /* [ 9], r, 0x0 */ - uint32_t st_axi_state_flsh_by : 1; /* [ 10], r, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t st_axi_fifo_cnt_uv : 7; /* [22:16], r, 0x0 */ - uint32_t st_axi_drain_error_uv : 1; /* [ 23], r, 0x0 */ - uint32_t st_axi_state_idle_uv : 1; /* [ 24], r, 0x0 */ - uint32_t st_axi_state_func_uv : 1; /* [ 25], r, 0x0 */ - uint32_t st_axi_state_flsh_uv : 1; /* [ 26], r, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_status; - - /* 0x30 : axi2dvp_swap_addr_by */ - union { - struct { - uint32_t cr_axi_addr_swap_by : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_swap_addr_by; - - /* 0x34 : axi2dvp_prefetch */ - union { - struct { - uint32_t cr_prefetch_v : 12; /* [11: 0], r/w, 0x28 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_prefetch; - - /* 0x38 : snsr2dvp_wait_pos */ - union { - struct { - uint32_t cr_snsr_fifo_th : 11; /* [10: 0], r/w, 0x8b */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } snsr2dvp_wait_pos; - - /* 0x3c reserved */ - uint8_t RESERVED0x3c[4]; - - /* 0x40 : axi2dvp_start_addr_uv */ - union { - struct { - uint32_t cr_axi_addr_start_uv : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_start_addr_uv; - - /* 0x44 : axi2dvp_swap_addr_uv */ - union { - struct { - uint32_t cr_axi_addr_swap_uv : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_swap_addr_uv; -}; - -typedef volatile struct dtsrc_reg dtsrc_reg_t; - -#endif /* __DTSRC_REG_H__ */ diff --git a/drivers/soc/bl808/std/port/bl808_flash.c b/drivers/soc/bl808/std/port/bl808_flash.c deleted file mode 100644 index 3f8be629..00000000 --- a/drivers/soc/bl808/std/port/bl808_flash.c +++ /dev/null @@ -1,283 +0,0 @@ -#include "bl808_glb.h" -#include "bl808_xip_sflash.h" -#include "bl808_sf_cfg.h" -#include "bflb_flash.h" - -static uint32_t g_jedec_id = 0; -static SPI_Flash_Cfg_Type g_flash_cfg; - -/** - * @brief flash_get_clock_delay - * - * @return int - */ -static int flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - /* bit0-3 for clk delay */ - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN)) { - cfg->clkDelay = BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } else { - cfg->clkDelay = 0; - } - cfg->clkInvert = 0; - /* bit0 for clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL) & 1) << 0); - /* bit1 for rx clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL) & 1) << 1); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); - /* bit4-6 for do delay */ - cfg->clkDelay |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL) & 7) << 4); - /* bit2-4 for di delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL) & 7) << 2); - /* bit5-7 for oe delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL) & 7) << 5); - - return 0; -} - -/** - * @brief flash_set_qspi_enable - * - * @return int - */ -static int ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_Qspi_Enable(p_flash_cfg); - } - - return 0; -} - -/** - * @brief flash_set_l1c_wrap - * - * @return int - */ -static int ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { - L1C_Set_Wrap(DISABLE); - } else { - L1C_Set_Wrap(ENABLE); - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(p_flash_cfg); - } - } - - return 0; -} - -/** - * @brief flash_config_init - * - * @return int - */ -static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) -{ - int ret = -1; - uint8_t isAesEnable = 0; - uint32_t jid = 0; - uint32_t offset = 0; - uintptr_t flag; - - flag = bflb_irq_save(); - XIP_SFlash_Opt_Enter(&isAesEnable); - XIP_SFlash_State_Save(p_flash_cfg, &offset, 0, 0); - SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); - arch_memcpy(jedec_id, (uint8_t *)&jid, 3); - jid &= 0xFFFFFF; - g_jedec_id = jid; - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg, 0, 0); - if (ret == 0) { - p_flash_cfg->mid = (jid & 0xff); - } - - /* Set flash controler from p_flash_cfg */ - flash_set_qspi_enable(p_flash_cfg); - flash_set_l1c_wrap(p_flash_cfg); - XIP_SFlash_State_Restore(p_flash_cfg, offset, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - bflb_irq_restore(flag); - - return ret; -} - -/** - * @brief multi flash adapter - * - * @return int - */ -int ATTR_TCM_SECTION bflb_flash_init(void) -{ - int ret = -1; - uint32_t jedec_id = 0; - uintptr_t flag; - - jedec_id = GLB_Get_Flash_Id_Value(); - if (jedec_id != 0) { - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jedec_id, &g_flash_cfg, 0, 0); - if (ret == 0) { - g_jedec_id = jedec_id; - flash_get_clock_delay(&g_flash_cfg); - return 0; - } - } - - flag = bflb_irq_save(); - L1C_ICache_Invalid_All(); - SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg, 0, 0); - L1C_ICache_Invalid_All(); - bflb_irq_restore(flag); - if (g_flash_cfg.mid != 0xff) { - flash_get_clock_delay(&g_flash_cfg); - return 0; - } - - ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); - - flash_get_clock_delay(&g_flash_cfg); - GLB_Set_Flash_Id_Value(g_jedec_id); - - return ret; -} - -uint32_t bflb_flash_get_jedec_id(void) -{ - uint32_t jid = 0; - - jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16); - return jid; -} - -void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) -{ - *cfg_addr = (uint8_t *)&g_flash_cfg; - *len = sizeof(SPI_Flash_Cfg_Type); -} - -ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void) -{ - return SF_Ctrl_Get_Flash_Image_Offset(0, 0); -} - -void bflb_flash_set_iomode(uint8_t iomode) -{ - g_flash_cfg.ioMode &= ~0x1f; - if (iomode == 4) { - g_flash_cfg.ioMode |= iomode; - } else { - g_flash_cfg.ioMode |= 0x10; - g_flash_cfg.ioMode |= iomode; - } -} - -int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len) -{ - int stat; - uintptr_t flag; - - if (startaddr >= BL808_FLASH_XIP_END - BL808_FLASH_XIP_BASE) { - return -ENOMEM; - } - - flag = bflb_irq_save(); - stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, len, 0, 0); - bflb_irq_restore(flag); - - return stat; -} - -int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - int stat; - uintptr_t flag; - - if (addr >= BL808_FLASH_XIP_END - BL808_FLASH_XIP_BASE) { - return -ENOMEM; - } - - flag = bflb_irq_save(); - stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - bflb_irq_restore(flag); - - return stat; -} - -int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - int stat; - uintptr_t flag; - - if (addr >= BL808_FLASH_XIP_END - BL808_FLASH_XIP_BASE) { - return -ENOMEM; - } - - flag = bflb_irq_save(); - stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - bflb_irq_restore(flag); - - return stat; -} - -int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) -{ - uint8_t isAesEnable = 0; - uint32_t tmp[1]; - int stat; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - - XIP_SFlash_Opt_Enter(&isAesEnable); - /* To make it simple, exit cont read anyway */ - SFlash_Reset_Continue_Read(&g_flash_cfg); - - if (g_flash_cfg.cReadSupport == 0) { - cont_read = 0; - } - - if (cont_read == 1) { - stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - - if (0 != stat) { - XIP_SFlash_Opt_Exit(isAesEnable); - return -1; - } - } - - /* TODO: Set default value */ - - SF_Ctrl_Set_Flash_Image_Offset(flash_offset, 0, 0); - SFlash_IDbus_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, SF_CTRL_FLASH_BANK0); - - XIP_SFlash_Opt_Exit(isAesEnable); - - return 0; -} - -void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config) -{ - uint8_t hw_key_enable = 0; - - if (config->key == NULL) { - hw_key_enable = 1; - } - - SF_Ctrl_AES_Set_Key_BE(config->region, (uint8_t *)config->key, config->keybits); - SF_Ctrl_AES_Set_IV_BE(config->region, (uint8_t *)config->iv, config->start_addr); - SF_Ctrl_AES_Set_Region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable); -} - -void bflb_flash_aes_enable(void) -{ - SF_Ctrl_AES_Enable(); -} - -void bflb_flash_aes_disable(void) -{ - SF_Ctrl_AES_Disable(); -} \ No newline at end of file diff --git a/drivers/soc/bl808/std/src/bl808_clock.c b/drivers/soc/bl808/std/src/bl808_clock.c index 5099784f..46b94265 100644 --- a/drivers/soc/bl808/std/src/bl808_clock.c +++ b/drivers/soc/bl808/std/src/bl808_clock.c @@ -275,7 +275,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clock } } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output() +static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output() { uint32_t tmpVal = 0; @@ -420,22 +420,22 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output() } } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Get_WIFI_PLL_Output(uint32_t pllOut) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Get_WIFI_PLL_Output(uint32_t pllOut) { return Clock_Get_WIFI_PLL_Output(pllOut); } -static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_WIFI_PLL_Output(uint32_t pllOut) +static inline uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_WIFI_PLL_Output(uint32_t pllOut) { return Clock_Get_WIFI_PLL_Output(pllOut); } -static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_CPU_PLL_Output(uint32_t pllOut) +static inline uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_CPU_PLL_Output(uint32_t pllOut) { return Clock_Get_CPU_PLL_Output(pllOut); } -static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) +static inline uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) { uint8_t xtalType = 0; @@ -463,7 +463,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void) } } -static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) { if (sel == 0) { /* rc32m */ @@ -476,7 +476,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) { uint32_t tmpVal; uint32_t div = 0; @@ -495,7 +495,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) { uint32_t tmpVal; @@ -504,7 +504,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm wifi pll 320m */ @@ -517,7 +517,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(void) { uint32_t tmpVal; @@ -526,7 +526,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm wifi pll 240m */ @@ -539,7 +539,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(void) { uint32_t tmpVal; @@ -548,7 +548,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm wifi pll 160m */ @@ -561,7 +561,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(void) { uint32_t tmpVal; @@ -570,7 +570,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 160m */ @@ -589,7 +589,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void) { uint32_t tmpVal; @@ -598,7 +598,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 80m */ @@ -617,7 +617,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void) { uint32_t tmpVal; @@ -626,7 +626,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* cpu pll 400m */ @@ -645,7 +645,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) { uint32_t tmpVal; @@ -655,7 +655,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void) return (tmpVal & 0x1); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -665,7 +665,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void) return ((tmpVal >> 1) & 0x1); } -static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) { uint32_t tmpVal; @@ -682,7 +682,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) { uint32_t tmpVal; @@ -691,7 +691,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) { uint32_t tmpVal; @@ -700,7 +700,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void) { uint32_t tmpVal; @@ -709,7 +709,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t sel) { if (sel == 0) { /* rc32m */ @@ -722,7 +722,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void) { uint32_t tmpVal; @@ -731,7 +731,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -740,7 +740,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm mux 240m */ @@ -756,7 +756,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint8_t sel) { uint32_t tmpVal; @@ -773,7 +773,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void) { uint32_t tmpVal; @@ -782,7 +782,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void) { uint32_t tmpVal; @@ -791,7 +791,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void) { uint32_t tmpVal; @@ -800,7 +800,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void) +static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void) { uint32_t tmpVal; @@ -809,7 +809,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_MM_BCLK_Mux_Output(uint8_t sel) +static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_MM_BCLK_Mux_Output(uint8_t sel) { if (sel == 0 || sel == 1) { /* mm xclk */ @@ -906,7 +906,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type) } } -static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_EMI_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mcu pbclk */ @@ -928,7 +928,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Div_Val(void) +static inline uint8_t Clock_Get_EMI_Clk_Div_Val(void) { uint32_t tmpVal; @@ -937,7 +937,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_EMI_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -946,7 +946,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk(void) +static inline uint32_t Clock_Get_EMI_Clk(void) { uint32_t div = 0; @@ -955,7 +955,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk(void) return Clock_EMI_Clk_Mux_Output(Clock_Get_EMI_Clk_Sel_Val()) / (div + 1); } -static uint32_t ATTR_CLOCK_SECTION Clock_PARAMB_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_PARAMB_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* emi cpu pll 400m */ @@ -971,7 +971,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_PARAMB_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Div_Val(void) +static inline uint8_t Clock_Get_PSRAMB_Clk_Div_Val(void) { uint32_t tmpVal; @@ -980,7 +980,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_PSRAMB_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -989,7 +989,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk(void) +static inline uint32_t Clock_Get_PSRAMB_Clk(void) { uint32_t div = 0; @@ -998,7 +998,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk(void) return Clock_PARAMB_Clk_Mux_Output(Clock_Get_PSRAMB_Clk_Sel_Val()) / (div + 1); } -static uint32_t ATTR_CLOCK_SECTION Clock_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm mux 160m */ @@ -1018,7 +1018,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Clk_Div_Val(void) +static inline uint8_t Clock_Get_Clk_Div_Val(void) { uint32_t tmpVal; @@ -1027,7 +1027,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1036,7 +1036,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_Clk(void) +static inline uint32_t Clock_Get_Clk(void) { uint32_t div = 0; @@ -1045,7 +1045,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Clk(void) return Clock_Clk_Mux_Output(Clock_Get_Clk_Sel_Val()) / (div + 1); } -static uint32_t ATTR_CLOCK_SECTION Clock_H264_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_H264_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm mux 160m */ @@ -1061,7 +1061,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_H264_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Div_Val(void) +static inline uint8_t Clock_Get_H264_Clk_Div_Val(void) { uint32_t tmpVal; @@ -1070,7 +1070,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_H264_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1079,7 +1079,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk(void) +static inline uint32_t Clock_Get_H264_Clk(void) { uint32_t div = 0; @@ -1088,7 +1088,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk(void) return Clock_H264_Clk_Mux_Output(Clock_Get_H264_Clk_Sel_Val()) / (div + 1); } -static uint32_t ATTR_CLOCK_SECTION Clock_BLAI_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_BLAI_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm mux 160m */ @@ -1104,7 +1104,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_BLAI_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Div_Val(void) +static inline uint8_t Clock_Get_BLAI_Clk_Div_Val(void) { uint32_t tmpVal; @@ -1113,7 +1113,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_BLAI_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1122,7 +1122,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk(void) +static inline uint32_t Clock_Get_BLAI_Clk(void) { uint32_t div = 0; @@ -1131,7 +1131,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk(void) return Clock_BLAI_Clk_Mux_Output(Clock_Get_BLAI_Clk_Sel_Val()) / (div + 1); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_MIPI_Div_Val(void) +static inline uint8_t Clock_Get_MIPI_Div_Val(void) { uint32_t tmpVal; @@ -1140,12 +1140,12 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MIPI_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO); } -static uint32_t ATTR_CLOCK_SECTION Clock_MIPI_Clk_Mux_Output(void) +static inline uint32_t Clock_MIPI_Clk_Mux_Output(void) { return Clock_Get_MIPI_PLL_Output(); } -static uint32_t ATTR_CLOCK_SECTION Clock_Display_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_Display_Clk_Mux_Output(uint8_t sel) { uint32_t div = 0; @@ -1161,7 +1161,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Display_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Div_Val(void) +static inline uint8_t Clock_Get_Display_Clk_Div_Val(void) { uint32_t tmpVal; @@ -1170,7 +1170,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_Display_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1179,7 +1179,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk(void) +static inline uint32_t Clock_Get_Display_Clk(void) { uint32_t div = 0; @@ -1188,7 +1188,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk(void) return Clock_Display_Clk_Mux_Output(Clock_Get_Display_Clk_Sel_Val()) / (div + 1); } -static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mcu pbclk */ @@ -1202,7 +1202,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1211,7 +1211,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void) return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL)); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) +static inline uint8_t Clock_Get_UART_Div_Val(void) { uint32_t tmpVal; @@ -1220,7 +1220,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_UART_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_DSP_UART_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm pbclk */ @@ -1236,7 +1236,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_UART_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_DSP_UART_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1245,7 +1245,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART0_Div_Val(void) +static inline uint8_t Clock_Get_DSP_UART0_Div_Val(void) { uint32_t tmpVal; @@ -1254,7 +1254,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART0_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART1_Div_Val(void) +static inline uint8_t Clock_Get_DSP_UART1_Div_Val(void) { uint32_t tmpVal; @@ -1263,7 +1263,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART1_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_PKA_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_PKA_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mcu pbclk */ @@ -1276,7 +1276,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_PKA_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PKA_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_PKA_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1285,13 +1285,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PKA_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void) +static inline uint32_t Clock_IR_Clk_Mux_Output(void) { /* xclk */ return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) +static inline uint8_t Clock_Get_IR_Div_Val(void) { uint32_t tmpVal; @@ -1300,7 +1300,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void) { uint32_t tmpVal; @@ -1309,7 +1309,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2); } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 120m */ @@ -1326,7 +1326,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* sf sel2 */ @@ -1343,7 +1343,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1352,7 +1352,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) +static inline uint8_t Clock_Get_SF_Div_Val(void) { uint32_t tmpVal; @@ -1361,7 +1361,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SPI_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mux 160Mkz */ @@ -1372,7 +1372,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SPI_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1381,7 +1381,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) +static inline uint8_t Clock_Get_SPI_Div_Val(void) { uint32_t tmpVal; @@ -1390,7 +1390,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_SPI_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_DSP_SPI_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm mux 160m */ @@ -1403,7 +1403,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_SPI_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_DSP_SPI_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1412,7 +1412,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Div_Val(void) +static inline uint8_t Clock_Get_DSP_SPI_Div_Val(void) { uint32_t tmpVal; @@ -1421,7 +1421,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_I2C_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mcu pbclk */ @@ -1434,7 +1434,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_I2C_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1443,7 +1443,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) +static inline uint8_t Clock_Get_I2C_Div_Val(void) { uint32_t tmpVal; @@ -1452,7 +1452,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_DSP_I2C_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_DSP_I2C_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* mm pbclk */ @@ -1463,7 +1463,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_I2C_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_DSP_I2C_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1472,7 +1472,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C0_Div_Val(void) +static inline uint8_t Clock_Get_DSP_I2C0_Div_Val(void) { uint32_t tmpVal; @@ -1481,7 +1481,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C0_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C1_Div_Val(void) +static inline uint8_t Clock_Get_DSP_I2C1_Div_Val(void) { uint32_t tmpVal; @@ -1490,7 +1490,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C1_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel) { if (sel == 0) { /* audio pll clk */ @@ -1501,7 +1501,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1510,7 +1510,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) +static inline uint8_t Clock_Get_GPADC_Div_Val(void) { uint32_t tmpVal; @@ -1519,7 +1519,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel) { uint32_t div = 0; @@ -1532,13 +1532,13 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel) } } -static uint32_t ATTR_CLOCK_SECTION Clock_PDM_Clk_Mux_Output(void) +static inline uint32_t Clock_PDM_Clk_Mux_Output(void) { /* audio pll clk */ return Clock_Get_Audio_PLL_Output(); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_PDM_Div_Val(void) +static inline uint8_t Clock_Get_PDM_Div_Val(void) { uint32_t tmpVal; @@ -1547,13 +1547,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PDM_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_I2S_Clk_Mux_Output(void) +static inline uint32_t Clock_I2S_Clk_Mux_Output(void) { /* audio pll clk */ return Clock_Get_Audio_PLL_Output(); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2S_Div_Val(void) +static inline uint8_t Clock_Get_I2S_Div_Val(void) { uint32_t tmpVal; @@ -1562,13 +1562,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2S_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_ADC_Clk_Mux_Output(void) +static inline uint32_t Clock_ADC_Clk_Mux_Output(void) { /* audio pll clk */ return Clock_Get_Audio_PLL_Output(); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_ADC_Div_Val(void) +static inline uint8_t Clock_Get_ADC_Div_Val(void) { uint32_t tmpVal; @@ -1577,7 +1577,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_ADC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1586,7 +1586,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS); } -static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 32m */ @@ -1600,7 +1600,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) +static inline uint8_t Clock_Get_GPDAC_Div_Val(void) { uint32_t tmpVal; @@ -1609,7 +1609,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1618,13 +1618,13 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL); } -static uint32_t ATTR_CLOCK_SECTION Clock_DAC_Clk_Mux_Output(void) +static inline uint32_t Clock_DAC_Clk_Mux_Output(void) { /* audio pll clk */ return Clock_Get_Audio_PLL_Output(); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_DAC_Div_Val(void) +static inline uint8_t Clock_Get_DAC_Div_Val(void) { uint32_t tmpVal; @@ -1633,7 +1633,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DAC_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_SDH_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_SDH_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* wifi pll 96m */ @@ -1644,7 +1644,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_SDH_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_SDH_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1653,7 +1653,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Div_Val(void) +static inline uint8_t Clock_Get_SDH_Div_Val(void) { uint32_t tmpVal; @@ -1662,7 +1662,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Div_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV); } -static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel) +static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel) { if (sel == 0) { /* xclk */ @@ -1678,7 +1678,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel) } } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void) +static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void) { uint32_t tmpVal; @@ -1687,7 +1687,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void) return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL); } -static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void) +static inline uint8_t Clock_Get_CAM_Div_Val(void) { uint32_t tmpVal; @@ -1703,7 +1703,7 @@ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void) * @return Audio ADC clock value * *******************************************************************************/ -static uint32_t ATTR_CLOCK_SECTION Clock_Audio_ADC_Clock_Get(void) +static inline uint32_t Clock_Audio_ADC_Clock_Get(void) { uint32_t clock = 0; uint32_t div = 0; @@ -1721,7 +1721,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_ADC_Clock_Get(void) * @return Audio DAC clock value * *******************************************************************************/ -static uint32_t ATTR_CLOCK_SECTION Clock_Audio_DAC_Clock_Get(void) +static inline uint32_t Clock_Audio_DAC_Clock_Get(void) { uint32_t clock = 0; uint32_t div = 0; @@ -1741,7 +1741,7 @@ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_DAC_Clock_Get(void) * @return Peripheral1 clock value * *******************************************************************************/ -uint32_t ATTR_CLOCK_SECTION Clock_Peripheral_Clock_Get(BL_Peripheral_Type type) +uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type) { uint32_t clock = 0; uint32_t div = 0; diff --git a/drivers/soc/bl808/std/src/bl808_ef_ctrl.c b/drivers/soc/bl808/std/src/bl808_ef_ctrl.c deleted file mode 100644 index 7d9987d6..00000000 --- a/drivers/soc/bl808/std/src/bl808_ef_ctrl.c +++ /dev/null @@ -1,1698 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ef_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_ef_ctrl.h" -#include "ef_data_0_reg.h" -#include "ef_data_1_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) -#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) -#define EF_CTRL_DFT_TIMEOUT_VAL (320 * 1000) -#ifndef BOOTROM -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1() -#else -#define EF_CTRL_LOAD_BEFORE_READ_R0 -#define EF_CTRL_LOAD_BEFORE_READ_R1 -#endif -#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, 0, EF_CTRL_EFUSE_R0_SIZE / 4) -#define EF_CTRL_DATA1_CLEAR EF_Ctrl_Clear(1, 0, EF_CTRL_EFUSE_R1_SIZE / 4) - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief get custom USB PID VID - * - * @param PID - * - * @param VID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) -{ - uint32_t tmpVal; - - EF_Ctrl_Read_Sw_Usage(4, &tmpVal); - - pid[0] = (uint16_t)(tmpVal & 0xFFFF); - vid[0] = (uint16_t)(tmpVal >> 16); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Switch efuse region 0 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Switch efuse region 1 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_1(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Program */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - arch_delay_us(4); - - /* Trigger */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 1 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_1(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - /* Program */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - arch_delay_us(4); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_1_RW_POS) | - (1 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Load efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - EF_CTRL_DATA0_CLEAR; - - /* Trigger read */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - arch_delay_us(10); - - /* Wait for efuse control idle */ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - timeout--; - - if (timeout == 0) { - break; - } - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || - - (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); - - /* Switch to AHB clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Load efuse region 1 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void EF_Ctrl_Load_Efuse_R1(void) -{ - uint32_t tmpVal; - - EF_CTRL_DATA1_CLEAR; - - /* Trigger read */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (1 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - arch_delay_us(10); - - /* Wait for efuse control idle */ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1); - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_1_BUSY)); - - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - } while (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)); - - /* Switch to AHB clock since often read efuse data after load */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse busy status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) -{ - if (BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0), EF_CTRL_EF_IF_0_BUSY) || - BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1), EF_CTRL_EF_IF_1_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse whether finish loading - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { - return SET; - } else { - return RESET; - } -} -#endif - -/****************************************************************************/ /** - * @brief Efuse write debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits - * @param passWdHigh: password high 32 bits - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH, passWdHigh); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits pointer to store value - * @param passWdHigh: password high 32 bits pointer to store value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh) -{ - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (slot == 0) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } else if (slot == 1) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS, cfg->ef_dbg_jtag_1_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE); - cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS); - cfg->ef_dbg_jtag_1_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS); - cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN); -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (aes[0] != EF_CTRL_SF_AES_NONE) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - } - - if (EF_CTRL_SIGN_NONE != sign[0]) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, tmpVal); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param aes[2]: AES configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2]) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - aes[1] = aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE); -} - -/****************************************************************************/ /** - * @brief Efuse read xtal trim rc32m configuration - * - * @param forceNoTrim: force no trim - * @param noXtal: no xtal - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Trim_RC32M(uint8_t *forceNoTrim, uint8_t *noXtal) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - *forceNoTrim = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_FORCE_NO_TRIM); - *noXtal = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_NO_XTAL); -} - -/****************************************************************************/ /** - * @brief Efuse Set sf key re sel - * - * @param ef_sf_key_re_sel: Efuse sf key re sel - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_KEY_RE_SEL, ef_sf_key_re_sel); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Analog Trim parity calculate - * - * @param val: Value of efuse trim data - * @param len: Length of bit to calculate - * - * @return Parity bit value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) -{ - uint8_t cnt = 0; - uint8_t i = 0; - - for (i = 0; i < len; i++) { - if (val & (1 << i)) { - cnt++; - } - } - - return cnt & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC11 trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC11_Trim(Efuse_Ana_DCDC11_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimDcdc11VoutAon = (tmpVal >> 26) & 0x0f; - trim->trimDcdc11VoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimDcdc11VoutAonEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC18 trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC18_Trim(Efuse_Ana_DCDC18_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimDcdc18VoutAon = (tmpVal >> 20) & 0x0f; - trim->trimDcdc18VoutAonParity = (tmpVal >> 24) & 0x01; - trim->trimDcdc18VoutAonEn = (tmpVal >> 25) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO18FLASH trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18FLASH_Trim(Efuse_Ana_LDO18FLASH_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimLdo18flashVoutAon = (tmpVal >> 26) & 0x0f; - trim->trimLdo18flashVoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimLdo18flashVoutAonEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read USB20RCAL trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_USB20RCAL_Trim(Efuse_Ana_USB20RCAL_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2); - trim->trimUsb20rcalAon = (tmpVal >> 8) & 0x3f; - trim->trimUsb20rcalAonParity = (tmpVal >> 14) & 0x01; - trim->trimUsb20rcalAonEn = (tmpVal >> 15) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32M trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - trim->trimRc32mCodeFrExt = (tmpVal >> 4) & 0xff; - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimRc32mCodeFrExtParity = (tmpVal >> 0) & 0x01; - trim->trimRc32mExtCodeEn = (tmpVal >> 1) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32K trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimRc32kCodeFrExt = (tmpVal >> 8) & 0x3ff; - trim->trimRc32kCodeFrExtParity = (tmpVal >> 18) & 0x01; - trim->trimRc32kExtCodeEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief - * - * @param - * - * @return - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18IO_Vout_Trim(Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimLdo18ioVoutVal = (tmpVal >> 14) & 0x0f; - trim->trimLdo18ioVoutParity = (tmpVal >> 18) & 0x01; - trim->trimLdo18ioVoutEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read TSEN trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->tsenRefcodeCorner = (tmpVal >> 0) & 0xfff; - trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; - trim->tsenRefcodeCornerEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read ADC Gain trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->adcGainCoeff = (tmpVal >> 14) & 0xfff; - trim->adcGainCoeffParity = (tmpVal >> 26) & 0x01; - trim->adcGainCoeffEn = (tmpVal >> 27) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write software usage - * - * @param index: index of software usage - * @param usage: usage value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) -{ - /* switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - switch (index) { - case 0: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage); - break; - - case 1: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1, usage); - break; - - case 2: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, usage); - break; - - case 3: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, usage); - break; - - case 4: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0, usage); - break; - - default: - break; - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param usage: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - switch (index) { - case 0: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - break; - - case 1: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1); - break; - - case 2: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2); - break; - - case 3: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - break; - - case 4: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param program: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index == 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0); - } else if (index == 1) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_1); - } else if (index == 2) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_2); - } else if (index == 3) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_3); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write MAC address - * - * @param mac[6]: MAC address buffer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse Ctrl get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[6]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0; - uint32_t cnt = 0; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[7]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - machigh[2] = (tmpVal >> 16) & 0xff; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for MAC address - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_MAC_Address(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Whether a value bits is all zero - * - * @param val: value to check - * @param start: start bit - * @param len: total length of bits to check - * - * @return 1 for all bits zero 0 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) -{ - uint32_t mask = 0; - - val = (val >> start); - - if (len >= 32) { - mask = 0xffffffff; - } else { - mask = (1 << len) - 1; - } - - if ((val & mask) == 0) { - return 1; - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief Efuse read chip ID - * - * @param chipID[8]: Chip ID buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) -{ - chipID[6] = 0; - chipID[7] = 0; - return EF_Ctrl_Read_MAC_Address_Raw(chipID); -} - -/****************************************************************************/ /** - * @brief Efuse write AES key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - /* slot_w0~slot_w3,slot_w11 in ef_data0 - slot_w4~slot_w10,in ef_data1 */ - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - - ARCH_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - /* Every key is 4 words len*/ - ARCH_MemCpy4(pAESKeyStart1 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Efuse read AES key from specified region and index - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - if ((index <= 3) || (index == 11)) { - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R0; - - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); - } else if ((index < 11) && (index > 3)) { - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R1; - index = index - 4; - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart1 + index * 4, len); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for aes key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 8 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 17)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 15)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for aes key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 4 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 27)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 25)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} -/****************************************************************************/ /** - * @brief Program data to efuse - * - * @param offset: offset of efuse address to program - * @param pword: data pointer to buffer which is aligned to word - * @param count: count of data in words to program - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct(uint32_t offset, uint32_t *pword, uint32_t count) -{ - uint32_t *pEfuseStart = (uint32_t *)(EF_DATA_BASE); - uint32_t region0_count = 0, region1_count = 0; - - if (offset > 0x100 || (offset + count * 4) > 0x100) { - return; - } - - if (offset < 0x80) { - if (offset + count * 4 <= 0x80) { - region0_count = count; - } else { - region0_count = (0x80 - offset) / 4; - region1_count = (offset + count * 4 - 0x80) / 4; - } - } else { - region1_count = count; - } - - if (region0_count > 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Add delay for CLK to be stable */ - arch_delay_us(4); - - if (pword != NULL) { - ARCH_MemCpy4(pEfuseStart, pword, region0_count); - pEfuseStart += region0_count; - pword += region0_count; - } - - EF_Ctrl_Program_Efuse_0(); - arch_delay_us(100); - } - if (region1_count > 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - /* Add delay for CLK to be stable */ - arch_delay_us(4); - - if (pword != NULL) { - ARCH_MemCpy4(pEfuseStart, pword, region1_count); - } - - EF_Ctrl_Program_Efuse_1(); - arch_delay_us(100); - } -} - -/****************************************************************************/ /** - * @brief Read data from efuse - * - * @param offset: offset of efuse address to read - * @param pword: data pointer to buffer which is aligned to word - * @param count: count of data in words to read - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct(uint32_t offset, uint32_t *pword, uint32_t count) -{ - uint32_t *pEfuseStart = (uint32_t *)(EF_DATA_BASE); - uint32_t region0_count = 0, region1_count = 0; - - if (offset > 0x100 || (offset + count * 4) > 0x100) { - return; - } - - if (offset < 0x80) { - if (offset + count * 4 <= 0x80) { - region0_count = count; - } else { - region0_count = (0x80 - offset) / 4; - region1_count = (offset + count * 4 - 0x80) / 4; - } - } else { - region1_count = count; - } - - if (region0_count > 0) { - EF_CTRL_LOAD_BEFORE_READ_R0; - ARCH_MemCpy4(pword, pEfuseStart, region0_count); - pword += region0_count; - pEfuseStart += region0_count; - } - if (region1_count > 0) { - EF_CTRL_LOAD_BEFORE_READ_R1; - ARCH_MemCpy4(pword, pEfuseStart, region0_count); - } -} - -/****************************************************************************/ /** - * @brief Clear efuse data register - * - * @param region: index efuse region - * @param index: index of efuse in word - * @param len: data length - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - uint32_t i = 0; - - if (region == 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart0[index + i] = 0; - } - } else if (region == 1) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart1[index + i] = 0; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief efuse ctrl crc enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc busy status - * - * @param None - * - * @return DISABLE or ENABLE - * -*******************************************************************************/ -BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); -} - -/****************************************************************************/ /** - * @brief efuse ctrl set golden value - * - * @param goldenValue: Crc golden value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) -{ - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc result - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Crc_Result(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/drivers/soc/bl808/std/src/bl808_glb.c b/drivers/soc/bl808/std/src/bl808_glb.c index 652f674b..239ba7d1 100644 --- a/drivers/soc/bl808/std/src/bl808_glb.c +++ b/drivers/soc/bl808/std/src/bl808_glb.c @@ -81,8 +81,6 @@ static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *b * @{ */ - - /* WiFi PLL Config*/ const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = { .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ @@ -305,42 +303,42 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX /* uhs PLL 2100 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ + { NULL, 0x0 }, /*!< XTAL is None */ { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */ { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */ { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */ @@ -351,39 +349,39 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] /* uhs PLL 1400 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = { { NULL, 0x0 }, /*!< XTAL is None */ @@ -397,39 +395,39 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] /* uhs PLL 1500 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = { { NULL, 0x0 }, /*!< XTAL is None */ @@ -443,42 +441,42 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] /* uhs PLL 1600 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ + { NULL, 0x0 }, /*!< XTAL is None */ { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */ { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */ @@ -489,180 +487,180 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] /* uhs PLL 400 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll400BasicCfg_24M, 0x19000 }, /*!< XTAL is 24M */ - { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */ - { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &uhsPll400BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */ - { &uhsPll400BasicCfg_26M, 0x1713B }, /*!< XTAL is 26M */ - { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */ + { NULL, 0x0 }, /*!< XTAL is None */ + { &uhsPll400BasicCfg_24M, 0x19000 }, /*!< XTAL is 24M */ + { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */ + { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */ + { &uhsPll400BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */ + { &uhsPll400BasicCfg_26M, 0x1713B }, /*!< XTAL is 26M */ + { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */ }; /* uhs PLL 667 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll667BasicCfg_24M, 0x29B00 }, /*!< XTAL is 24M */ - { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is 32M */ - { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */ - { &uhsPll667BasicCfg_40M, 0x21599 }, /*!< XTAL is 40M */ - { &uhsPll667BasicCfg_26M, 0x267B1 }, /*!< XTAL is 26M */ - { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is RC32M */ + { NULL, 0x0 }, /*!< XTAL is None */ + { &uhsPll667BasicCfg_24M, 0x29B00 }, /*!< XTAL is 24M */ + { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is 32M */ + { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */ + { &uhsPll667BasicCfg_40M, 0x21599 }, /*!< XTAL is 40M */ + { &uhsPll667BasicCfg_26M, 0x267B1 }, /*!< XTAL is 26M */ + { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is RC32M */ }; /* uhs PLL 800 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll800BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ - { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is 32M */ - { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */ - { &uhsPll800BasicCfg_40M, 0x1E000 }, /*!< XTAL is 40M */ - { &uhsPll800BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ - { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is RC32M */ + { NULL, 0x0 }, /*!< XTAL is None */ + { &uhsPll800BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ + { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is 32M */ + { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */ + { &uhsPll800BasicCfg_40M, 0x1E000 }, /*!< XTAL is 40M */ + { &uhsPll800BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ + { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is RC32M */ }; /* uhs PLL 1066 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ + { NULL, 0x0 }, /*!< XTAL is None */ { &uhsPll1066BasicCfg_24M, 0x2C6AA }, /*!< XTAL is 24M */ { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is 32M */ { &uhsPll1066BasicCfg_38P4M, 0x29A40 }, /*!< XTAL is 38.4M */ @@ -673,42 +671,42 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] /* uhs PLL 2000 Config*/ const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ + .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ + .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ + .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ + .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ + .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */ }; const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ + { NULL, 0x0 }, /*!< XTAL is None */ { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */ { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */ { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */ @@ -1264,7 +1262,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, co /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */ if (GLB_WAC_PLL_AUPLL == pllType) { tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((cfg->clkpllSdmin==0x12D0E)||(cfg->clkpllSdmin==0x1C395)||(cfg->clkpllSdmin==0x17851)||(cfg->clkpllSdmin==0x16944)||(cfg->clkpllSdmin==0x115E5)) { + if ((cfg->clkpllSdmin == 0x12D0E) || (cfg->clkpllSdmin == 0x1C395) || (cfg->clkpllSdmin == 0x17851) || (cfg->clkpllSdmin == 0x16944) || (cfg->clkpllSdmin == 0x115E5)) { /* 451.548 */ tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14); } else { @@ -1577,9 +1575,9 @@ BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_ } tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - if(enable){ + if (enable) { tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - }else{ + } else { tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); } tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum); @@ -1622,23 +1620,23 @@ BL_Err_Type GLB_Set_EMAC_CLK(uint8_t enable) *******************************************************************************/ BL_Err_Type GLB_Output_EMAC_CLK(uint8_t gpio) { - uint32_t regAddr=GLB_BASE+GLB_GPIO_CFG0_OFFSET+(gpio<<2); - uint32_t regVal=0x00040F03; + uint32_t regAddr = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpio << 2); + uint32_t regVal = 0x00040F03; - if( ( gpio != GLB_GPIO_PIN_6 ) && \ - ( gpio != GLB_GPIO_PIN_14 ) && \ - ( gpio != GLB_GPIO_PIN_12 ) && \ - ( gpio != GLB_GPIO_PIN_30 ) ){ + if ((gpio != GLB_GPIO_PIN_6) && + (gpio != GLB_GPIO_PIN_14) && + (gpio != GLB_GPIO_PIN_12) && + (gpio != GLB_GPIO_PIN_30)) { return ERROR; } /* set gpio in debug function */ - BL_WR_WORD(regAddr,regVal); + BL_WR_WORD(regAddr, regVal); /* select signal */ - BL_WR_WORD(0x200002E0+((gpio-6)/8)*4,0x80000010); + BL_WR_WORD(0x200002E0 + ((gpio - 6) / 8) * 4, 0x80000010); /* output */ - BL_WR_WORD(0x200002F0,0x01); + BL_WR_WORD(0x200002F0, 0x01); return SUCCESS; } @@ -5149,9 +5147,9 @@ BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType) * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) +BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue) { - BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue|BFLB_FLASH_ID_VALID_FLAG)); + BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue | BFLB_FLASH_ID_VALID_FLAG)); return SUCCESS; } @@ -5164,13 +5162,13 @@ BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) * @return flash id * *******************************************************************************/ -uint32_t GLB_Get_Flash_Id_Value(void) +uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void) { uint32_t tmpVal = 0; tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1); - if ((tmpVal&BFLB_FLASH_ID_VALID_FLAG) != 0) { - return (tmpVal&BFLB_FLASH_ID_VALID_MASK); + if ((tmpVal & BFLB_FLASH_ID_VALID_FLAG) != 0) { + return (tmpVal & BFLB_FLASH_ID_VALID_MASK); } return 0x00000000; @@ -5869,7 +5867,7 @@ BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Typ * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) +BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList) { GLB_PLL_REF_CLK_Type refClk; @@ -5895,7 +5893,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) +BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList) { GLB_PLL_REF_CLK_Type refClk; @@ -5921,7 +5919,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, cons * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) +BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList) { GLB_PLL_REF_CLK_Type refClk; @@ -5947,7 +5945,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) +BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type *pllCfgList) { GLB_PLL_REF_CLK_Type refClk; @@ -5997,7 +5995,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t di * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) +BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type *pllCfgList) { GLB_PLL_REF_CLK_Type refClk; diff --git a/drivers/soc/bl808/std/src/bl808_hbn.c b/drivers/soc/bl808/std/src/bl808_hbn.c index f77cf0b4..8baba502 100644 --- a/drivers/soc/bl808/std/src/bl808_hbn.c +++ b/drivers/soc/bl808/std/src/bl808_hbn.c @@ -36,7 +36,7 @@ #include "bl808_hbn.h" #include "bl808_glb.h" -#include "bl808_xip_sflash.h" +#include "bflb_xip_sflash.h" /** @addtogroup BL808_Peripheral_Driver * @{ @@ -157,24 +157,24 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg) * @return None * *******************************************************************************/ -void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg) +void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg) { - SPI_Flash_Cfg_Type bhFlashCfg; + spi_flash_cfg_type bhFlashCfg; if (flashCfg == NULL) { - L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type)); - XIP_SFlash_Read_Via_Cache_Need_Lock(BL808_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), - sizeof(SPI_Flash_Cfg_Type), 0, 0); - L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type)); + L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(spi_flash_cfg_type)); + bflb_xip_sflash_read_via_cache_need_lock(BL808_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), + sizeof(spi_flash_cfg_type), 0, 0); + L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(spi_flash_cfg_type)); - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - SFlash_Reset_Continue_Read(&bhFlashCfg); + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + bflb_sflash_reset_continue_read(&bhFlashCfg); } else { - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - SFlash_Reset_Continue_Read(flashCfg); + bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB); + bflb_sflash_reset_continue_read(flashCfg); } - SFlash_Powerdown(); + bflb_sflash_powerdown(); } /****************************************************************************/ /** diff --git a/drivers/soc/bl808/std/src/bl808_pds.c b/drivers/soc/bl808/std/src/bl808_pds.c index 4a8f3d85..a2c24c81 100644 --- a/drivers/soc/bl808/std/src/bl808_pds.c +++ b/drivers/soc/bl808/std/src/bl808_pds.c @@ -335,7 +335,7 @@ BL_Sts_Type ATTR_TCM_SECTION PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad) * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg) +BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg) { switch (pinCfg) { case SF_IO_EXT_SF2: @@ -360,7 +360,7 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinC * @return SUCCESS or ERROR * *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg) +BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg) { uint32_t tmpVal; diff --git a/drivers/soc/bl808/std/src/bl808_sf_cfg.c b/drivers/soc/bl808/std/src/bl808_sf_cfg.c deleted file mode 100644 index ef5d29e7..00000000 --- a/drivers/soc/bl808/std/src/bl808_sf_cfg.c +++ /dev/null @@ -1,1673 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_sf_cfg.h" -#include "bl808_xip_sflash.h" -#include "soft_crc.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_Private_Macros */ - -/** @defgroup SF_CFG_Private_Types - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; -#endif - -/*@} end of group SF_CFG_Private_Types */ - -/** @defgroup SF_CFG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JW = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xf0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x24, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 32 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 8 / 8, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0x12, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_128 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x15, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = (SF_CTRL_QIO_MODE | 0x20), - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1440ef, - //.name="Winb_80DV_08_33", - .cfg = &flashCfg_Winb_80DV, - }, - { - .jedecID = 0x1540ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1640ef, - //.name="Winb_32FV_32_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1840ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1940ef, - //.name="Winb_256FV_128_33", - .cfg = &flashCfg_Winb_256FV, - }, - { - .jedecID = 0x1460ef, - //.name="Winb_80EW_08_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1560ef, - //.name="Winb_16FW_16_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1660ef, - //.name="Winb_32FW_32_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1760ef, - //.name="WB_64JW_64_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1860ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1570ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1870ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1680ef, - //.name="Winb_32JW_32_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1880ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1440C8, - //.name="GD_Q08E_08_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1540C8, - //.name="GD_Q16E_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1640C8, - //.name="GD_Q32C_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1740C8, - //.name="GD_Q64E_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1840C8, - //.name="GD_Q128E_128_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1460C8, - //.name="GD_LQ08C_08_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1560C8, - //.name="GD_LE16C_16_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1660C8, - //.name="GD_LQ32D_32_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1860c8, - //.name="GD_LQ128E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1465C8, - //.name="GD_WQ80E_80_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1565C8, - //.name="GD_WQ16E_16_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1665C8, - //.name="GD_WQ32E_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x15345e, - //.name="ZB_WQ16A_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15405e, - //.name="ZB_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x16405e, - //.name="ZB_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x17405e, - //.name="ZB_Q64B_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x14605E, - //.name="ZB_VQ80", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15605E, - //.name="ZB_VQ16", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1820C2, - //.name="MX_25L128_128_33", - .cfg = &flashCfg_Mxic_128, - }, - { - .jedecID = 0x1920C2, - //.name="MX_25L256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID = 0x3925C2, - //.name="MX_25U256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID=0x144020, - //.name="XM_25QH80_80_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x154020, - //.name="XM_25QH16_16_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x164020, - //.name="XM_25QH32_32_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x174020, - //.name="XM_25QH64_64_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID = 0x15400B, - //.name="XT_25F16B_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x16400B, - //.name="XT_25F32B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x17400B, - //.name="XT_25F64B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x18400B, - //.name="XT_25F128B_128_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x14600B, - //.name="XT_25Q80B_08_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x16600B, - //.name="XT_25Q32B_32_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x144068, - //.name="Boya_Q08B_08_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x154068, - //.name="Boya_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x164068, - //.name="Boya_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x174068, - //.name="Boya_Q64A_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x184068, - //.name="Boya_Q128A_128_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - } -}; -#endif - -/*@} end of group SF_CFG_Private_Variables */ - -/** @defgroup SF_CFG_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_Global_Variables */ - -/** @defgroup SF_CFG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 2; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_FLASH; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - - if (i == 0 || i == 1) { - /* flash clk and cs is output */ - cfg.gpioMode = GPIO_MODE_OUTPUT; - } else { - /* data are bidir */ - cfg.gpioMode = GPIO_MODE_AF; - } - - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Deinit external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_GPIO; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Private_Functions */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8, group, bank); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, group, bank); - - if (ARCH_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - arch_memcpy_fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - return SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg, group, bank); -} -#endif - -/****************************************************************************/ /** - * @brief Init flash GPIO according to flash Pin config - * - * @param flashPinCfg: Specify flash Pin config - * @param restoreDefault: Wether to restore default setting - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault) -{ - uint8_t selEmbedded = 0; - uint8_t swap = 0; - - if ((flashPinCfg&(1<<3)) > 0) { - return ERROR; - } - - if (restoreDefault) { - /* Set Default first */ - GLB_Set_Flash_IO_PARM(1, 1); - SF_Ctrl_Select_Pad(SF_IO_EMB_SWAP_IO0_IO3); - - /* Default is set, so return */ - if (flashPinCfg == SF_IO_EMB_SWAP_IO0_IO3) { - return SUCCESS; - } - } - - if (flashPinCfg & (1 << 2)) { - /* Init sf2 gpio */ - SF_Cfg_Init_Ext_Flash_Gpio(0); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* if pin select dual flash, embedded is default */ - if ((flashPinCfg & (1 << 4))) { - selEmbedded = 1; - } - - swap = ((flashPinCfg >> 1) & 1); - swap = (!swap); - GLB_Set_Flash_IO_PARM(selEmbedded, swap); - SF_Ctrl_Select_Pad(flashPinCfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint8_t autoScan = 0; - uint8_t flashPin = 0; - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t offset; - BL_Err_Type stat; - - autoScan = ((flashPinCfg >> 7) & 1); - flashPin = (flashPinCfg & 0x7F); - - arch_memcpy_fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type)); - - if (callFromFlash == 1) { - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - return 0; - } - } - - if (autoScan) { - flashPin = 0; - - do { - if (flashPin > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - jdecId = 0; - break; - } - - if (!IS_SF_CTRL_PIN_SELECT(flashPin) || (flashPin&(1<<3)) > 0) { - flashPin++; - continue; - } - - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = 0; - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - flashPin++; - } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); - } else { - /* select media gpio */ - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - } - - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - arch_memcpy_fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - break; - } - } - - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return jdecId; - } else { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); - } -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - return SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg flash init - * - * @param sel: SF pin select - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t selEmbedded = 0; - uint8_t swap = 0; - - if ((sel&(1<<3)) > 0) { - return ERROR; - } - - if (sel & (1 << 2)) { - SF_Cfg_Init_Ext_Flash_Gpio(0); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* If pin select dual flash, embedded is default */ - if ((sel & (1 << 4))) { - selEmbedded = 1; - } - - swap = ((sel >> 1) & 1); - swap = (!swap); - GLB_Set_Flash_IO_PARM(selEmbedded, swap); - SF_Ctrl_Select_Pad(sel); - - if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { - /* Embedded pad1 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } else if (sel <= SF_IO_EXT_SF2) { - /* Pad2 or pad3 io delay set */ - SF_Ctrl_Set_IO_Delay((sel >> 2), pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Dual flash mode, embedded pad1 and pad2 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - } - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - } - } - - SFlash_Init(pSfCtrlCfg, pBank2Cfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg system bus 2 flash init - * - * @param sel: SF pin select - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - if (sel < SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 || sel > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - return ERROR; - } - - /* Init flash2 gpio */ - if (sel & (1 << 2)) { - SF_Cfg_Init_Ext_Flash_Gpio(0); - } - - /* Set remap for flash2 xip mode */ - SF_Ctrl_Remap_Set(pBank2Cfg->remap, pBank2Cfg->remapLock); - - /* Dual flash mode, pad2 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - - if (pBank2Cfg->sbus2Select) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - - SFlash_Init(NULL, pBank2Cfg); - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/drivers/soc/bl808/std/src/bl808_sf_ctrl.c b/drivers/soc/bl808/std/src/bl808_sf_ctrl.c deleted file mode 100644 index 4b2c1942..00000000 --- a/drivers/soc/bl808/std/src/bl808_sf_ctrl.c +++ /dev/null @@ -1,1870 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_sf_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Private_Macros - * @{ - */ - -/*@} end of group SF_CTRL_Private_Macros */ - -/** @defgroup SF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SF_CTRL_Private_Types */ - -/** @defgroup SF_CTRL_Private_Variables - * @{ - */ -#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) -#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80) - -/*@} end of group SF_CTRL_Private_Variables */ - -/** @defgroup SF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SF_CTRL_Global_Variables */ - -/** @defgroup SF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SF_CTRL_Private_Functions - * @{ - */ - -/*@} end of group SF_CTRL_Private_Functions */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Enable serail flash controller - * - * @param cfg: serial flash controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - if (cfg == NULL) { - return; - } - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (cfg->en32bAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - if (cfg->clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - /* Serail out inverted, so sf ctrl send on negative edge */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); - - /* Enable AHB access sram buffer and enable sf interface */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); - - SF_Ctrl_Set_Owner(cfg->owner); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serail bank2 controller - * - * @param bank2Cfg: serial bank2 controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg) -{ - uint32_t tmpVal = 0; - - if (bank2Cfg == NULL) { - return; - } - - /* Select if1 bank2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12); - - if (bank2Cfg->bank2RxClkInvertSrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - } - - if (bank2Cfg->bank2DelaySrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal); - - /* Select sbus2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set io delay - * - * @param pad: Pad select - * @param doDelay: DO delay select - * @param diDelay: DI delay select - * @param oeDelay: OE delay select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay) -{ - uint32_t tmpVal = 0; - uint32_t offset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - if (pad == SF_CTRL_PAD1) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET; - } else if (pad == SF_CTRL_PAD2) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET; - } else { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET; - } - - /* Set do di and oe delay */ - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_4, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 hold sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Hold_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 hold sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 release sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Release_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 release sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller sbus2 status - * - * @param None - * - * @return Wether if2 is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_Sbus2_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_EN)) { - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_FN_SEL)) { - return SET; - } else { - return RESET; - } - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 repalce - * - * @param pad: SF pad to replace - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - /* Sbus2 enable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); - - SF_Ctrl_Sbus2_Hold_Sram(); - - /* Sbus2 repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - - if (pad == SF_CTRL_PAD1) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - } else if (pad == SF_CTRL_PAD2) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_PAD_SEL, pad); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl sbus2 revoke replace - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Revoke_replace(void) -{ - uint32_t tmpVal = 0; - - SF_Ctrl_Sbus2_Release_Sram(); - - /* Sbus2 clear repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Sbus2 disable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 clock delay - * - * @param clkDelay: Sbus2 clock delay - * @param rxClkInvert: Sbus2 rx clock invert - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL, rxClkInvert); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (en32BitsAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param None - * - * @return Clock delay value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { - return 0; - } else { - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller clock delay value - * - * @param delay: Clock delay value - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (delay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl get wrap queue value - * - * @param None - * - * @return Wrap queue value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Wrap_Queue_Value(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_Q); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set cmds config - * - * @param cmdsCfg: SF Ctrl cmds config - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_WRAP_MODE(cmdsCfg->cmdsWrapMode)); - CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->cmdsWrapLen)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - if (cmdsCfg->ackLatency) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } - - if (cmdsCfg->cmdsCoreEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } - - if (bank == SF_CTRL_FLASH_BANK1) { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } else { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl pad select - * - * @param sel: Pin select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PIN_SELECT(sel)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (sel <= SF_IO_EXT_SF2) { - /* Single flash mode, disable bank2 */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - - if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { - /* Select embedded pad1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } else { - /* Select pad2 or pad3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, ((sel&0xf) >> 2)); - } - } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl dual flash memory remap set - * - * @param remap: Memory remap set type - * @param lock: Memory remap lock - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_REMAP_TYPE(remap)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP, remap); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl select bank on system bus - * - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank) -{ - /* TODO: sf_if_bk_swap */ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller owner:I/D AHB or system AHB - * - * @param owner: owner type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - /* Set owner */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); - - /* Set iahb to flash interface */ - if (owner == SF_CTRL_OWNER_IAHB) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash controller - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with big indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with little indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES region - * - * @param region: region number - * @param enable: enable or not - * @param hwKey: hardware key or software key - * @param startAddr: region start address - * @param endAddr: region end address - * @param locked: lock this region or not - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, - uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal; - - if (!hwKey) { - regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - } - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_END); - /* sf_aes_end =1 means 1,11,1111,1111 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_END, tmpVal); - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_START); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_START, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - tmpVal -= 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W1_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, (BL_RDWD_FRM_BYTEP(iv))); - tmpVal += 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - tmpVal += 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W2_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - tmpVal -= 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif -#ifndef BFLB_USE_ROM_DRIVER - -/****************************************************************************/ /** - * @brief Set serial flash controller AES mode - * - * @param mode: AES mode select - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_MODE_TYPE(mode)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (mode == SF_CTRL_AES_CTR_MODE) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check is serial flash controller AES enable - * - * @param None - * - * @return Wether AES is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash image offset - * - * @param addrOffset: Address offset value - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET, addrOffset); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET, addrOffset); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Get flash image offset - * - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return :Address offset value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET); - } - } - - return tmpVal; -} -#endif - -/****************************************************************************/ /** - * @brief Lock/unlock sf_id0/sf_id1/sf_bk2_id0/sf_bk2_id1 offset - * - * @param lock: lock or unlock - * - * @return :None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param cfg: Serial flash controller command configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - uint32_t cmdOffset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { - return; - } - - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - /* Clear trigger */ - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Copy command buffer */ - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); - } - - /* Configure cmd */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_CMD_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_CMD_BYTE, 0); - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, 0); - } - - /* Configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, cfg->nbData - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_RW, cfg->rwFlag); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl disable iahb to flash wrap access for XTS mode - * - * @param disable: Disable for 1 and enable for 0 - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable_Wrap_Access(uint8_t disable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (disable) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config SF controller for flash I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config bank2 controller for flash2 I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get SF Ctrl busy state - * - * @param None - * - * @return SET for SF ctrl busy or RESET for SF ctrl not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) -{ - uint32_t tmpVal = 0; - uint32_t cmdOffset = 0; - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_IF_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Controller interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void) -{ - /* TODO: Not implemented */ -} -#endif - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/drivers/soc/bl808/std/src/bl808_sflash.c b/drivers/soc/bl808/std/src/bl808_sflash.c deleted file mode 100644 index 68040c7b..00000000 --- a/drivers/soc/bl808/std/src/bl808_sflash.c +++ /dev/null @@ -1,2164 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_sflash.h" -#include "bl808_sf_ctrl.h" -#include "bl808_l1c.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLASH - * @{ - */ - -/** @defgroup SFLASH_Private_Macros - * @{ - */ - -/*@} end of group SFLASH_Private_Macros */ - -/** @defgroup SFLASH_Private_Types - * @{ - */ - -/*@} end of group SFLASH_Private_Types */ - -/** @defgroup SFLASH_Private_Variables - * @{ - */ -#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) - -/*@} end of group SFLASH_Private_Variables */ - -/** @defgroup SFLASH_Global_Variables - * @{ - */ - -/*@} end of group SFLASH_Global_Variables */ - -/** @defgroup SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SFLASH_Private_Fun_Declaration */ - -/** @defgroup SFLASH_Private_Functions - * @{ - */ - -/*@} end of group SFLASH_Private_Functions */ - -/** @defgroup SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init serial flash control interface - * - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t clkDelay = 0; - uint8_t rxClkInvert = 0; - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if (pBank2Cfg->bank2DelaySrc) { - clkDelay = pBank2Cfg->bank2ClkDelay; - } else { - if (pSfCtrlCfg != NULL) { - clkDelay = pSfCtrlCfg->clkDelay; - } else { - clkDelay = 1; - } - } - - if (pBank2Cfg->bank2RxClkInvertSrc) { - rxClkInvert = pBank2Cfg->bank2RxClkInvertSel; - } else { - if (pSfCtrlCfg != NULL) { - rxClkInvert = pSfCtrlCfg->rxClkInvert; - } else { - rxClkInvert = 0; - } - } - - SF_Ctrl_Sbus2_Set_Delay(clkDelay, rxClkInvert); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - SF_Ctrl_Bank2_Enable(pBank2Cfg); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - if (pSfCtrlCfg != NULL) { - SF_Ctrl_Enable(pSfCtrlCfg); - } -} -#endif - -/****************************************************************************/ /** - * @brief Set serial flash control interface SPI or QPI mode - * - * @param mode: Serial flash interface mode - * - * @return BFLB_RET:SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) -{ - BL_Err_Type stat = SUCCESS; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register with read command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param readRegCmd: read command - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = readRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register with write command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param writeRegCmd: write command - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = writeRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Check flash busy status - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SET for busy or RESET for not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); - - if ((stat & (1 << flashCfg->busyBit)) == 0) { - return RESET; - } - - return SET; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash write function - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Write enable*/ - flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); - - if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); - } else { - stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); - stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); - } - } else { - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit % 8)); - } else { - stat = flashCfg->qeData; - } - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - stat &= (~(1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex))); - } else { - stat &= (~(1 << (flashCfg->qeBit % 8))); - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash volatile register write enable - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash whole chip - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint32_t timeout = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - timeout = flashCfg->timeCe; - - if ((timeout >> 15) > 0) { - timeout = (timeout & 0x7FFF) * 1000; - } - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > timeout * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one sector - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param secNum: flash sector number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | ((flashCfg->sectorSize * 1024 * secNum) >> 8); - flashCmd.cmdBuf[1] = ((flashCfg->sectorSize * 1024 * secNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeEsector * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 64K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 64K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE64k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash unique ID - * - * @param data: data pointer to store read data - * @param idLen: unique ID len - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = 4; - cmd = 0x4B; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = idLen; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, idLen); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash jedec ID - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = flashCfg->jedecIdCmdDmyClk; - cmd = flashCfg->jedecIdCmd; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 3); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash device ID - * - * @param data: data pointer to store read data - * @param is32BitsAddr: Is flash addr mode in 32-bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t addr = 0x00000001; - uint8_t readMode = 0xFF; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - dummyClks = 2; - cmd = 0x94; - flashCmd.addrSize = 4; - - if (is32BitsAddr) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24) | (readMode << 16); - flashCmd.addrSize++; - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.cmdBuf[1] = (readMode << 24); - } - - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 2; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 2); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash power down - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Powerdown(void) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - uint32_t timeOut = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = 0xB9; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Release flash power down for wake up - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t cmd; - uint32_t timeOut = 0; - - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = flashCfg->releasePowerDown; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Sflash restore from power down - * - * @param pFlashCfg: Flash configuration pointer - * @param flashContRead: Whether enable continuous read - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, - SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat = SUCCESS; - uint32_t jdecId = 0; - uint8_t tmp[8]; - uint8_t ioMode = pFlashCfg->ioMode & 0xf; - - /* Wake flash up from power down */ - SFlash_Release_Powerdown(pFlashCfg); - arch_delay_us(120); - - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - - if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { - SFlash_Qspi_Enable(pFlashCfg); - } - - if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { - /* unwrap */ - L1C_Set_Wrap(DISABLE); - } else { - /* burst wrap */ - L1C_Set_Wrap(ENABLE); - /* For command that is setting register instead of send command, we need write enable */ - SFlash_Write_Enable(pFlashCfg); - SFlash_SetBurstWrap(pFlashCfg); - } - - if (flashContRead) { - stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32, bank); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((flashCfg->ioMode >> 4) & 0x01) == 1) { - /* Disable burst wrap ,just return */ - return; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; - dummyClks = flashCfg->burstWrapCmdDmyClk; - cmd = flashCfg->burstWrapCmd; - wrapData = flashCfg->burstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; - dummyClks = flashCfg->deBurstWrapCmdDmyClk; - cmd = flashCfg->deBurstWrapCmd; - wrapData = flashCfg->deBurstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash 24-bits or 32-bits addr mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - - if ((flashCfg->ioMode & 0x20) == 0) { - return ERROR; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_32bits_Addr_En(en32BitsAddr); - - if (en32BitsAddr) { - cmd = flashCfg->enter32BitsAddrCmd; - } else { - cmd = flashCfg->exit32BitsAddrCmd; - } - - flashCmd.cmdBuf[0] = (cmd << 24); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Software reset flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) -{ - uint16_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset enable */ - flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - /* Wait for write done */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 20) { - return ERROR; - } - } - - SF_Ctrl_SendCmd(&flashCmd); - - /* Reset */ - flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - arch_delay_us(50); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Reset flash continous read mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset continous read */ - ARCH_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = flashCfg->resetCreadCmdSize; - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set I/D bus read flash configuration in flash controller - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: address to read/write - * @param len: data length to read/write - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank) -{ - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmdValid = 1; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /*prepare command**/ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | addr; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = addr; - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; - } - - cmdValid = 0; - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = len; - if (bank == SF_CTRL_FLASH_BANK0) { - SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid); - } else { - SF_Ctrl_Flash2_Read_Icache_Set(&flashCmd, cmdValid); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Enable I/D bus read from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, - uint8_t contRead, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32, bank); - - if (SUCCESS != stat) { - return stat; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Disable read from flash with IDbus - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_IDbus_Read_Disable(void) -{ - //L1C_Cache_Read_Disable(); -} -#endif - -/****************************************************************************/ /** - * @brief Sflash enable RCV mode to recovery for erase while power drop - * - * @param pFlashCfg: Flash configuration pointer - * @param rCmd: Read RCV register cmd - * @param wCmd: Write RCV register cmd - * @param bitPos: RCV register bit pos - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) -{ - BL_Err_Type stat; - uint32_t cnt = 0; - uint32_t tempVal = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) > 0) { - return SUCCESS; - } - - tempVal |= (uint32_t)(1 << bitPos); - stat = SFlash_Write_Enable(pFlashCfg); - - if (SUCCESS != stat) { - stat = ERROR; - } - - stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - return stat; - } - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) <= 0) { - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint32_t cnt = 0; - uint8_t cmd = 0; - uint8_t secOptMode = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = pSecRegCfg->eraseCmd; - flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > pFlashCfg->timeEsector * 3) { - return ERROR; - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Program flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - BL_Err_Type stat; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - cmd = pSecRegCfg->programCmd; - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = 256 - addr % 256; - - if (curLen > len - i) { - curLen = len - i; - } - - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - - /* Prepare command */ - arch_memcpy_fast(flashCtrlBuf, data, curLen); - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > pFlashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash security register one block - * - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - flashCmd.dummyClks = 1; - cmd = pSecRegCfg->readCmd; - - /* Read data */ - for (i = 0; i < len;) { - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - /* Prepare command */ - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - arch_memcpy_fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - - /* Read data */ - for (i = 0; i < len;) { - /* Prepare command */ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] |= (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - arch_memcpy_fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: progran mode:SPI mode or QPI mode - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat; - uint8_t cmd; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - cmd = flashCfg->pageProgramCmd; - } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->qpageProgramCmd; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = flashCfg->pageSize - addr % flashCfg->pageSize; - - if (curLen > len - i) { - curLen = len - i; - } - - /* Prepare command */ - arch_memcpy_fast(flashCtrlBuf, data, curLen); - - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > flashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - return SUCCESS; -} -#endif - -/*@} end of group SFLASH_Public_Functions */ - -/*@} end of group SFLASH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/drivers/soc/bl808/std/src/bl808_xip_sflash.c b/drivers/soc/bl808/std/src/bl808_xip_sflash.c deleted file mode 100644 index 240fd520..00000000 --- a/drivers/soc/bl808/std/src/bl808_xip_sflash.c +++ /dev/null @@ -1,469 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_xip_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_xip_sflash.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Private_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Macros */ - -/** @defgroup XIP_SFLASH_Private_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Types */ - -/** @defgroup XIP_SFLASH_Private_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Variables */ - -/** @defgroup XIP_SFLASH_Global_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Global_Variables */ - -/** @defgroup XIP_SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ - -/** @defgroup XIP_SFLASH_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Save flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* XIP_SFlash_Delay */ - volatile uint32_t i = 32 * 2; - - while (i--) - ; - - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); - /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); - /* Enable 32Bits addr mode again in case reset command make it reset */ - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); - } - /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); - - /* Clear offset setting*/ - *offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Restore flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmp[1]; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank); - - if(((pFlashCfg->ioMode>>4)&0x01) == 0) { - if((pFlashCfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(pFlashCfg); - } - } - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return SUCCESS; -} -#endif - -/*@} end of group XIP_SFLASH_Private_Functions */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase - * @param len: data length to erase - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param pFlashCfg: Flash config pointer - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param pFlashCfg: Flash config pointer - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Jedec ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Jedec ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Device ID - * - * @param pFlashCfg: Flash config pointer - * @param is32BitsAddr: Is flash addr mode in 32-bits - * @param data: data pointer to store Device ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetDeviceId(data, is32BitsAddr); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Unique ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Device ID Read from flash - * @param idLen: Unique id len - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash via XIP - * - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t offset; - - addr = addr & (BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE-1); - addr |= BL808_FLASH_XIP_BASE; - - offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - /* Flash read */ - arch_memcpy_fast(data, (void *)(uintptr_t)(addr), len); - SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief XIP SFlash option save - * - * @param aesEnable: AES enable status pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) -{ - *aesEnable = SF_Ctrl_Is_AES_Enable(); - - if (*aesEnable) { - SF_Ctrl_AES_Disable(); - } -} - -/****************************************************************************/ /** - * @brief XIP SFlash option restore - * - * @param aesEnable: AES enable status - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) -{ - if (aesEnable) { - SF_Ctrl_AES_Enable(); - } -} - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/drivers/soc/bl808/std/startup/d0/interrupt.c b/drivers/soc/bl808/std/startup/d0/interrupt.c index f08b02e2..6a594133 100644 --- a/drivers/soc/bl808/std/startup/d0/interrupt.c +++ b/drivers/soc/bl808/std/startup/d0/interrupt.c @@ -45,7 +45,7 @@ const char *mcause_str[] = { if ((cause & 0xf)) printf("%s\r\n\r\n", mcause_str[cause & 0xf]); -#ifndef CONFIG_ERR_NOT_DUMP_ALL_REGS +#ifdef CONFIG_TRAP_DUMP_ALL_REGS printf("ra = 0x%16llx ", regs[REG_RA]); printf("sp = 0x%16llx ", regs[REG_SP]); printf("gp = 0x%16llx ", regs[REG_GP]); printf("tp = 0x%16llx ", regs[REG_TP]); printf("\n\r"); diff --git a/drivers/soc/bl808/std/startup/m0/interrupt.c b/drivers/soc/bl808/std/startup/m0/interrupt.c index f7087409..a9a4275d 100644 --- a/drivers/soc/bl808/std/startup/m0/interrupt.c +++ b/drivers/soc/bl808/std/startup/m0/interrupt.c @@ -153,7 +153,7 @@ void exception_entry(uintptr_t *regs) printf("%s\r\n", mcause_str[cause & 0xf]); // clang-format off -#ifndef CONFIG_ERR_NOT_DUMP_ALL_REGS +#ifdef CONFIG_TRAP_DUMP_ALL_REGS printf("ra = 0x%08x ", regs[REG_RA]); printf("sp = 0x%08x ", regs[REG_SP]); printf("gp = 0x%08x ", regs[REG_GP]); printf("tp = 0x%08x ", regs[REG_TP]); printf("\n\r"); diff --git a/examples/bflb_block_pool/FreeRTOSConfig.h b/examples/bflb_block_pool/FreeRTOSConfig.h index 6b521a6a..635083f0 100644 --- a/examples/bflb_block_pool/FreeRTOSConfig.h +++ b/examples/bflb_block_pool/FreeRTOSConfig.h @@ -24,10 +24,8 @@ * * 1 tab == 4 spaces! */ - #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H - /*----------------------------------------------------------- * Application specific definitions. * @@ -39,17 +37,19 @@ * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -#include "stdio.h" - -#ifdef BL702 +#if defined(BL602) || defined(BL702) || defined(BL702L) #define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) #define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) #else -#define configMTIME_BASE_ADDRESS (0xE0000000UL + 0xBFF8UL) -#define configMTIMECMP_BASE_ADDRESS (0xE0000000UL + 0x4000UL) +#if __riscv_xlen == 64 +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) #endif - -// #define configSUPPORT_STATIC_ALLOCATION 1 +#endif +#define configSUPPORT_STATIC_ALLOCATION 1 #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 #define configUSE_TICK_HOOK 0 @@ -57,7 +57,7 @@ #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ -#define configTOTAL_HEAP_SIZE ((size_t)12 * 1024) +#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024) #define configMAX_TASK_NAME_LEN (16) #define configUSE_TRACE_FACILITY 1 #define configUSE_STATS_FORMATTING_FUNCTIONS 1 @@ -68,27 +68,24 @@ #define configCHECK_FOR_STACK_OVERFLOW 2 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_APPLICATION_TASK_TAG 1 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_TICKLESS_IDLE 0 - +#define configUSE_POSIX_ERRNO 1 /* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES (2) - +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) /* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) -#define configTIMER_QUEUE_LENGTH 4 -#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) - +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) /* Task priorities. Allow these to be overridden. */ #ifndef uartPRIMARY_PRIORITY #define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) #endif - /* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ #define INCLUDE_vTaskPrioritySet 1 @@ -103,11 +100,11 @@ to exclude the API function. */ #define INCLUDE_xTaskAbortDelay 1 #define INCLUDE_xTaskGetHandle 1 #define INCLUDE_xSemaphoreGetMutexHolder 1 - /* Normal assert() semantics without relying on the provision of an assert.h header file. */ void vApplicationMallocFailedHook(void); void vAssertCalled(void); +extern int printf(const char *fmt, ...); #define configASSERT(x) \ if ((x) == 0) { \ printf("file [%s]\r\n", __FILE__); \ @@ -116,12 +113,9 @@ void vAssertCalled(void); printf("%s\r\n", (const char *)(#x)); \ vAssertCalled(); \ } - #if (configUSE_TICKLESS_IDLE != 0) void vApplicationSleep(uint32_t xExpectedIdleTime); #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime) #endif - // #define portUSING_MPU_WRAPPERS - -#endif /* FREERTOS_CONFIG_H */ +#endif /* FREERTOS_CONFIG_H */ \ No newline at end of file diff --git a/examples/bflb_block_pool/Makefile b/examples/bflb_block_pool/Makefile index 34b2f3fa..af13d05d 100644 --- a/examples/bflb_block_pool/Makefile +++ b/examples/bflb_block_pool/Makefile @@ -3,6 +3,7 @@ BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../.. export BL_SDK_BASE +CPU_ID ?= m0 CHIP ?= bl616 BOARD ?= bl616dk CROSS_COMPILE ?= riscv64-unknown-elf- diff --git a/examples/bflb_block_pool/README.md b/examples/bflb_block_pool/README.md new file mode 100644 index 00000000..2bb67cab --- /dev/null +++ b/examples/bflb_block_pool/README.md @@ -0,0 +1,44 @@ +# bflb_block_pool + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/bflb_block_pool/flash_prog_cfg.ini b/examples/bflb_block_pool/flash_prog_cfg.ini new file mode 100644 index 00000000..80ccfb32 --- /dev/null +++ b/examples/bflb_block_pool/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/bflb_block_pool_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/bflb_block_pool/main.c b/examples/bflb_block_pool/main.c index e4ec96e2..7dc03816 100644 --- a/examples/bflb_block_pool/main.c +++ b/examples/bflb_block_pool/main.c @@ -1,25 +1,22 @@ +#define DBG_TAG "MAIN" + +#include #include "bflb_mtimer.h" #include #include "semphr.h" +#include "board.h" #include "log.h" #include "bflb_block_pool.h" -#include "stdlib.h" -extern void board_init(void); +BFLOG_DEFINE_TAG(MAIN, DBG_TAG, true); +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(MAIN) #define BLK_SIZE 128 #define BLK_MEMORY_SIZE 16 * (BLK_SIZE + sizeof(void *)) static bflb_block_pool_t block_pool; __attribute__((aligned(8))) static uint8_t block_pool_memory[BLK_MEMORY_SIZE]; -static uint8_t freertos_heap[configTOTAL_HEAP_SIZE]; - -static HeapRegion_t xHeapRegions[] = { - { (uint8_t *)freertos_heap, 0 }, - { NULL, 0 }, /* Terminates the array. */ - { NULL, 0 } /* Terminates the array. */ -}; - static TaskHandle_t consumer_handle; static TaskHandle_t producer_handle; @@ -122,8 +119,6 @@ int main(void) uint32_t block_count; board_init(); - xHeapRegions[0].xSizeInBytes = configTOTAL_HEAP_SIZE; - vPortDefineHeapRegions(xHeapRegions); configASSERT((configMAX_PRIORITIES > 4)); @@ -149,6 +144,10 @@ int main(void) LOG_I("Starting producer task...\r\n"); xTaskCreate(producer_task, (char *)"producer_task", 512, NULL, configMAX_PRIORITIES - 3, &producer_handle); +#ifdef CONFIG_BFLOG + log_restart(); +#endif + vTaskStartScheduler(); while (1) { diff --git a/examples/bflb_block_pool/proj.conf b/examples/bflb_block_pool/proj.conf index c205ee54..2ec8c4a6 100644 --- a/examples/bflb_block_pool/proj.conf +++ b/examples/bflb_block_pool/proj.conf @@ -1,6 +1,14 @@ -set(CONFIG_VLIBC 1) -set(CONFIG_BFLOG 1) +set(CONFIG_BFLOG 1) -set(CONFIG_FREERTOS 1) +set(CONFIG_VSNPRINTF_FLOAT 1) +set(CONFIG_VSNPRINTF_FLOAT_EX 1) +set(CONFIG_VSNPRINTF_LONG_LONG 1) + +set(CONFIG_LOG_DISABLE 0) +set(CONFIG_ASSERT_DISABLE 0) +set(CONFIG_LOG_LEVEL 3) +set(CONFIG_BFLOG_POOL_SIZE 1024) + +set(CONFIG_FREERTOS 1) set(CONFIG_BFLB_BLOCK_POOL_DEBUG 1) \ No newline at end of file diff --git a/examples/bflog/CMakeLists.txt b/examples/bflog/barebone_sync/CMakeLists.txt similarity index 84% rename from examples/bflog/CMakeLists.txt rename to examples/bflog/barebone_sync/CMakeLists.txt index 5c96c3ab..b70f8ffa 100644 --- a/examples/bflog/CMakeLists.txt +++ b/examples/bflog/barebone_sync/CMakeLists.txt @@ -4,13 +4,12 @@ include(proj.conf) find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) +sdk_add_include_directories(.) target_sources(app PRIVATE - + log_test.c ) -sdk_add_include_directories(.) - sdk_set_main_file(main.c) -project(bflog) +project(barebone_sync) diff --git a/examples/bflog/barebone_sync/Makefile b/examples/bflog/barebone_sync/Makefile new file mode 100644 index 00000000..9b01b7fe --- /dev/null +++ b/examples/bflog/barebone_sync/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/bflog/barebone_sync/README.md b/examples/bflog/barebone_sync/README.md new file mode 100644 index 00000000..594d89b6 --- /dev/null +++ b/examples/bflog/barebone_sync/README.md @@ -0,0 +1,44 @@ +# bflog barebone sync + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/bflog/barebone_sync/bflog_user.h b/examples/bflog/barebone_sync/bflog_user.h new file mode 100644 index 00000000..af39f9b4 --- /dev/null +++ b/examples/bflog/barebone_sync/bflog_user.h @@ -0,0 +1,174 @@ +/** + * @file bflog_default.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef _BFLOG_USER_H +#define _BFLOG_USER_H + +#include "bflog.h" + +/*!< 启用LOG, 禁用将使LOG内容不参与编译 */ +/*!< log enable */ +#define BFLOG_ENABLE + +/*!< 全局启用的LOG等级, 小于此等级的LOG内容不参与编译 */ +/*!< log enable level */ +#define BFLOG_LEVEL_ENABLE BFLOG_LEVEL_TRACE + +/*!< 默认LOG记录器配置的LOG等级, 小于此等级的LOG将不被记录 */ +/*!< 可以动态调节LOG记录器等级来调整记录内容 */ +/*!< default log record level */ +#define BFLOG_LEVEL_DEFAULT BFLOG_LEVEL_TRACE + +/*!< 默认LOG输出器配置的LOG等级, 小于此等级的LOG将不被输出 */ +/*!< 可以动态调节LOG输出器等级来调整某个输出器输出的内容 */ +/*!< default direct print level */ +#define BFLOG_DIRECT_LEVEL_DEFAULT BFLOG_LEVEL_TRACE + +/*!< 使能时间戳 */ +/*!< enable timestamp to time */ +#define BFLOG_TIMESTAMP_ENABLE + +/*!< 使能BUFFER输出器, 未完成配置无效果 */ +/*!< enable buffer directed output */ +#define BFLOG_DIRECT_BUFFER_ENABLE + +/*!< 使能流输出器 */ +/*!< enable stream directed output */ +#define BFLOG_DIRECT_STREAM_ENABLE + +/*!< 使能文件输出器 */ +/*!< enable file directed output */ +#define BFLOG_DIRECT_FILE_ENABLE + +/*!< 使能按时间分割的文件输出器 */ +/*!< enable file time directed output */ +#define BFLOG_DIRECT_FILE_TIME_ENABLE + +/*!< 使能按文件大小分割的文件输出器 */ +/*!< enable file size directed output */ +#define BFLOG_DIRECT_FILE_SIZE_ENABLE + +/*!< 使能短文件名 */ +/*!< enable short file name */ +#define BFLOG_SHORT_FILENAME + +/*!< 使能文件名记录, 占用flash高 */ +/*!< enable file name record, flash use high */ +#define BFLOG_FILENAME_ENABLE + +/*!< 使能函数名记录, 占用flash中等 */ +/*!< enable function name record, flash use medium */ +#define BFLOG_FUNCTION_ENABLE + +/*!< 使能文件行数记录, 占用flash低 */ +/*!< enable line record, flash use low */ +#define BFLOG_LINE_ENABLE + +/*!< 行缓冲大小, 使用的是栈上空间, 请确保栈空间足够 */ +/*!< 行缓冲设置大小不足时, 一次长LOG输出可能不完整 */ +/*!< line buffer size (in stack) */ +/*!< flush use 4xline buffer size in stack */ +/*!< log use 2xline buffer size in stack */ +/*!< pay attention to prevent stack overflow */ +#define BFLOG_LINE_BUFFER_SIZE 256 + +/*!< 最小文件尺寸分割大小 */ +/*!< file size rotate min size */ +#define BFLOG_FILE_SIZE_MIN (1024) + +/*!< 最小时间分割大小 */ +/*!< file time rotate min interval */ +#define BFLOG_FILE_INTERVAL_MIN (60) + +/*!< 默认记录器配置的记录功能 */ +/*!< 可以动态修改记录器配置调节记录功能, 提高速度 */ +/*!< default record flag config */ +/*!< | item | time occupancy | */ +/*!< | level | low | */ +/*!< | tag | low | */ +/*!< | func | medium | */ +/*!< | line | low | */ +/*!< | file | very high | */ +/*!< | clock | medium | */ +/*!< | time | high | */ +/*!< |thread | medium | */ +#define BFLOG_FLAG_DEFAULT ( \ + (0xff & BFLOG_FLAG_LEVEL) | \ + (0xff & BFLOG_FLAG_TAG) | \ + (0xff & BFLOG_FLAG_FUNC) | \ + (0xff & BFLOG_FLAG_LINE) | \ + (0xff & BFLOG_FLAG_FILE) | \ + (0xff & BFLOG_FLAG_CLK) | \ + (0xff & BFLOG_FLAG_TIME) | \ + (0x00 & BFLOG_FLAG_THREAD)) + +/*!< 不同日志等级颜色配置 */ +/*!< color config */ +#define BFLOG_COLOR_FATAL BFLOG_COLOR_FG_MAGENTA BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL +#define BFLOG_COLOR_ERROR BFLOG_COLOR_FG_RED BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL +#define BFLOG_COLOR_WARN BFLOG_COLOR_FG_YELLOW BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL +// #define BFLOG_COLOR_INFO BFLOG_COLOR_FG_GREEN BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL +#define BFLOG_COLOR_INFO BFLOG_COLOR_FG_NONE BFLOG_COLOR_BG_NONE BFLOG_SGR_RESET +#define BFLOG_COLOR_DEBUG BFLOG_COLOR_FG_WHITE BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL +#define BFLOG_COLOR_TRACE BFLOG_COLOR_FG_WHITE BFLOG_COLOR_BG_NONE BFLOG_SGR_FAINT + +/*!< 简易排版的格式 */ +/*!< simple layout */ +#if 1 +#define BFLOG_SIMPLE_LAYOUT_STRING(_color, _level, _tag, _tm, _msg) \ + "%s" \ + "[%s][%10lu][%d-%02d-%02d %02d:%02d:%02d]" \ + "[%s:%s:%d]" \ + "<%s> %s", \ + (_color), \ + (_level), \ + ((_msg)->clkl), \ + (_tm)->year, (_tm)->mon, (_tm)->mday, \ + (_tm)->hour, (_tm)->min, (_tm)->sec, \ + ((_msg)->file), ((_msg)->func), ((_msg)->line), \ + (_tag), \ + ((_msg)->string) +#else +#define BFLOG_SIMPLE_LAYOUT_STRING(_color, _level, _tag, _tm, _msg) \ + "%s" \ + "[%s][%10lu][%d-%02d-%02d %02d:%02d:%02d]" \ + "<%s> %s", \ + (_color), \ + (_level), \ + ((_msg)->clkl), \ + (_tm)->year, (_tm)->mon, (_tm)->mday, \ + (_tm)->hour, (_tm)->min, (_tm)->sec, \ + (_tag), \ + ((_msg)->string) +#endif + +/*!< 不同日志等级提示信息配置 */ +/*!< level string config */ +#define BFLOG_LEVEL_FATAL_STRING "FATL" +#define BFLOG_LEVEL_ERROR_STRING "ERRO" +#define BFLOG_LEVEL_WARN_STRING "WARN" +#define BFLOG_LEVEL_INFO_STRING "INFO" +#define BFLOG_LEVEL_DEBUG_STRING "DBUG" +#define BFLOG_LEVEL_TRACE_STRING "TRAC" + +#endif diff --git a/examples/bflog/barebone_sync/flash_prog_cfg.ini b/examples/bflog/barebone_sync/flash_prog_cfg.ini new file mode 100644 index 00000000..392eeaed --- /dev/null +++ b/examples/bflog/barebone_sync/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/barebone_sync_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/bflog/barebone_sync/log_test.c b/examples/bflog/barebone_sync/log_test.c new file mode 100644 index 00000000..e4c73911 --- /dev/null +++ b/examples/bflog/barebone_sync/log_test.c @@ -0,0 +1,19 @@ +#define DBG_TAG "TEST" + +#include "bflog.h" + +BFLOG_DEFINE_TAG(TEST, DBG_TAG, true); +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(TEST) + +extern bflog_t example_recorder; + +void test_log(void) +{ + BFLOG_F(&example_recorder, "hello test this is fatal error\r\n"); + BFLOG_E(&example_recorder, "hello test this is error\r\n"); + BFLOG_W(&example_recorder, "hello test this is warning\r\n"); + BFLOG_I(&example_recorder, "hello test this is information\r\n"); + BFLOG_D(&example_recorder, "hello test this is degug information\r\n"); + BFLOG_T(&example_recorder, "hello test this is trace information\r\n"); +} \ No newline at end of file diff --git a/examples/bflog/barebone_sync/main.c b/examples/bflog/barebone_sync/main.c new file mode 100644 index 00000000..7f857b4d --- /dev/null +++ b/examples/bflog/barebone_sync/main.c @@ -0,0 +1,139 @@ +#define DBG_TAG "MAIN" + +#include "bflb_mtimer.h" +#include "bflb_uart.h" +#include "bflb_rtc.h" +#include "board.h" +#include "bflog.h" + +/*!< 添加BFLOG 标签可以使用标签过滤功能 */ +/*!< 不添加则标签仍然能显示, 但标签过滤无效 */ + +/*!< 定义一个 BFLOG 标签 */ +BFLOG_DEFINE_TAG(MAIN, DBG_TAG, true); + +/*!< 取消之前的BFLOG 标签 */ +#undef BFLOG_TAG + +/*!< 将BFLOG 标签定义为新的标签 */ +#define BFLOG_TAG BFLOG_GET_TAG(MAIN) + +/*!< bflog 裸机同步例程 */ +/*!< bflog barebone sync example */ + +struct bflb_device_s *uart0 = NULL; +static struct bflb_device_s *rtc = NULL; + +/*!< 当前的UTC时间戳 2022-12-16 17:52 */ +uint32_t timestamp_base = 1671184300; + +/** @defgroup example_bflog_port port +----------------------------------------------------------------------------- +* @{ +----------------------------------------------------------------------------*/ +uint64_t bflog_clock(void) +{ + return bflb_mtimer_get_time_us(); +} + +uint32_t bflog_time(void) +{ + return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + timestamp_base; +} + +char *bflog_thread(void) +{ + return ""; +} +/*--------------------------------------------------------------------------- +* @} example_bflog_port port +----------------------------------------------------------------------------*/ + +#define EXAMPLE_LOG_POOL_SIZE 4096 + +bflog_t example_recorder; +static uint32_t example_pool[EXAMPLE_LOG_POOL_SIZE / 4]; +bflog_direct_stream_t example_uart_stream; + +uint16_t example_uart_stream_output(void *ptr, uint16_t size) +{ + for (size_t i = 0; i < size; i++) { + bflb_uart_putchar(uart0, ((char *)ptr)[i]); + } + return size; +} + +void example_log_init(void) +{ + void *record = (void *)&example_recorder; + void *direct = (void *)&example_uart_stream; + + /*!< 创建一个记录器, 配置内存池, 内存池大小, 模式为同步 */ + /*!< create recorder */ + if (0 != bflog_create(record, example_pool, EXAMPLE_LOG_POOL_SIZE, BFLOG_MODE_SYNC)) { + printf("bflog_create faild\r\n"); + } + + /*!< 创建输出器, 类型为流输出器, 使能颜色输出, 互斥锁设为NULL */ + /*!< create stream direct */ + bflog_direct_create(direct, BFLOG_DIRECT_TYPE_STREAM, BFLOG_DIRECT_COLOR_ENABLE, NULL, NULL); + /*!< 配置流输出的输出函数 */ + bflog_direct_init_stream((void *)direct, example_uart_stream_output); + + /*!< 添加输出器到记录器 */ + /*!< connect direct and recorder */ + bflog_append(record, direct); + + /*!< 恢复输出器到工作模式 */ + /*!< resume direct */ + bflog_direct_resume(direct); + + /*!< 恢复记录器到工作模式 */ + /*!< resume record */ + bflog_resume(record); +} + +extern void test_log(void); + +int main(void) +{ + board_init(); + + /*!< uart0 already initialized in bsp/board */ + uart0 = bflb_device_get_by_name("uart0"); + rtc = bflb_device_get_by_name("rtc"); + bflb_rtc_set_time(rtc, 0); + + example_log_init(); + + uint8_t test = 0; + + while (1) { + if (test == 0) { + bflog_global_filter("MAIN", true); + bflog_global_filter("TEST", true); + printf("\r\n============================== enable all output\r\n\r\n"); + } else if (test == 1) { + bflog_global_filter("MAIN", false); + bflog_global_filter("TEST", true); + printf("\r\n============================== enable only MAIN output\r\n\r\n"); + } else if (test == 2) { + bflog_global_filter("MAIN", false); + bflog_global_filter("TEST", false); + printf("\r\n============================== disable all output\r\n\r\n"); + } + + if (++test >= 3) { + test = 0; + } + + BFLOG_F(&example_recorder, "hello world this is fatal error\r\n"); + BFLOG_E(&example_recorder, "hello world this is error\r\n"); + BFLOG_W(&example_recorder, "hello world this is warning\r\n"); + BFLOG_I(&example_recorder, "hello world this is information\r\n"); + BFLOG_D(&example_recorder, "hello world this is degug information\r\n"); + BFLOG_T(&example_recorder, "hello world this is trace information\r\n"); + test_log(); + bflb_mtimer_delay_ms(1000); + } +} diff --git a/examples/bflog/barebone_sync/proj.conf b/examples/bflog/barebone_sync/proj.conf new file mode 100644 index 00000000..a0e64c90 --- /dev/null +++ b/examples/bflog/barebone_sync/proj.conf @@ -0,0 +1,19 @@ +set(CONFIG_VLIBC 0) +set(CONFIG_VLIBC_FATFS 0) + +set(CONFIG_BFLOG 1) +set(CONFIG_BFLOG_USER 1) + +set(CONFIG_VSNPRINTF_FLOAT 1) +set(CONFIG_VSNPRINTF_FLOAT_EX 1) +set(CONFIG_VSNPRINTF_LONG_LONG 1) + +set(CONFIG_LOG_DISABLE 0) +set(CONFIG_ASSERT_DISABLE 0) +set(CONFIG_LOG_LEVEL 3) +set(CONFIG_BFLOG_POOL_SIZE 1024) + +set(CONFIG_FATFS 0) + +set(CONFIG_BSP_SDH_SDCARD 0) +set(CONFIG_FATFS_SDH_SDCARD 0) diff --git a/examples/bflog/freertos_async/CMakeLists.txt b/examples/bflog/freertos_async/CMakeLists.txt new file mode 100644 index 00000000..0a7482dc --- /dev/null +++ b/examples/bflog/freertos_async/CMakeLists.txt @@ -0,0 +1,17 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_add_include_directories(.) + +target_sources(app PRIVATE + thread_log.c + thread_consumer.c + thread_producer.c +) + +sdk_set_main_file(main.c) + +project(freertos_async) diff --git a/examples/bflog/freertos_async/FreeRTOSConfig.h b/examples/bflog/freertos_async/FreeRTOSConfig.h new file mode 100644 index 00000000..c471a037 --- /dev/null +++ b/examples/bflog/freertos_async/FreeRTOSConfig.h @@ -0,0 +1,125 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ +#if defined(BL602) || defined(BL702) || defined(BL702L) +#define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) +#else +#if __riscv_xlen == 64 +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) +#endif +#endif +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ((uint32_t)(1 * 1000 * 1000)) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES (15) +#define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ +#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024) +#define configMAX_TASK_NAME_LEN (16) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configUSE_POSIX_ERRNO 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) +/* Task priorities. Allow these to be overridden. */ +#ifndef uartPRIMARY_PRIORITY +#define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) +#endif +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vApplicationMallocFailedHook(void); +void vAssertCalled(void); + +#include + +#define configASSERT(x) \ + if ((x) == 0) { \ + printf("file [%s]\r\n", __FILE__); \ + printf("func [%s]\r\n", __FUNCTION__); \ + printf("line [%d]\r\n", __LINE__); \ + printf("%s\r\n", (const char *)(#x)); \ + vAssertCalled(); \ + } +#if (configUSE_TICKLESS_IDLE != 0) +void vApplicationSleep(uint32_t xExpectedIdleTime); +#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime) +#endif +// #define portUSING_MPU_WRAPPERS +#endif /* FREERTOS_CONFIG_H */ \ No newline at end of file diff --git a/examples/bflog/freertos_async/Makefile b/examples/bflog/freertos_async/Makefile new file mode 100644 index 00000000..9b01b7fe --- /dev/null +++ b/examples/bflog/freertos_async/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/bflog/freertos_async/README.md b/examples/bflog/freertos_async/README.md new file mode 100644 index 00000000..8af4e739 --- /dev/null +++ b/examples/bflog/freertos_async/README.md @@ -0,0 +1,44 @@ +# bflog freertos async + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/bflog/bflog_user.h b/examples/bflog/freertos_async/bflog_user.h similarity index 56% rename from examples/bflog/bflog_user.h rename to examples/bflog/freertos_async/bflog_user.h index 61133a9d..d36d3fc5 100644 --- a/examples/bflog/bflog_user.h +++ b/examples/bflog/freertos_async/bflog_user.h @@ -24,66 +24,84 @@ #ifndef _BFLOG_USER_H #define _BFLOG_USER_H -#include "vlibc_stdio.h" #include "bflog.h" -/*!< param check enable */ -#define CONFIG_BFLOG_DEBUG - +/*!< 启用LOG, 禁用将使LOG内容不参与编译 */ /*!< log enable */ #define BFLOG_ENABLE +/*!< 全局启用的LOG等级, 小于此等级的LOG内容不参与编译 */ /*!< log enable level */ #define BFLOG_LEVEL_ENABLE BFLOG_LEVEL_TRACE +/*!< 默认LOG记录器配置的LOG等级, 小于此等级的LOG将不被记录 */ +/*!< 可以动态调节LOG记录器等级来调整记录内容 */ /*!< default log record level */ #define BFLOG_LEVEL_DEFAULT BFLOG_LEVEL_TRACE +/*!< 默认LOG输出器配置的LOG等级, 小于此等级的LOG将不被输出 */ +/*!< 可以动态调节LOG输出器等级来调整某个输出器输出的内容 */ /*!< default direct print level */ #define BFLOG_DIRECT_LEVEL_DEFAULT BFLOG_LEVEL_TRACE +/*!< 使能时间戳 */ /*!< enable timestamp to time */ #define BFLOG_TIMESTAMP_ENABLE +/*!< 使能BUFFER输出器, 未完成配置无效果 */ /*!< enable buffer directed output */ #define BFLOG_DIRECT_BUFFER_ENABLE +/*!< 使能流输出器 */ /*!< enable stream directed output */ #define BFLOG_DIRECT_STREAM_ENABLE +/*!< 使能文件输出器 */ /*!< enable file directed output */ #define BFLOG_DIRECT_FILE_ENABLE +/*!< 使能按时间分割的文件输出器 */ /*!< enable file time directed output */ #define BFLOG_DIRECT_FILE_TIME_ENABLE +/*!< 使能按文件大小分割的文件输出器 */ /*!< enable file size directed output */ #define BFLOG_DIRECT_FILE_SIZE_ENABLE +/*!< 使能短文件名 */ /*!< enable short file name */ #define BFLOG_SHORT_FILENAME +/*!< 使能文件名记录, 占用flash高 */ /*!< enable file name record, flash use high */ #define BFLOG_FILENAME_ENABLE +/*!< 使能函数名记录, 占用flash中等 */ /*!< enable function name record, flash use medium */ #define BFLOG_FUNCTION_ENABLE +/*!< 使能文件行数记录, 占用flash低 */ /*!< enable line record, flash use low */ #define BFLOG_LINE_ENABLE +/*!< 行缓冲大小, 使用的是栈上空间, 请确保栈空间足够 */ +/*!< 行缓冲设置大小不足时, 一次长LOG输出可能不完整 */ /*!< line buffer size (in stack) */ /*!< flush use 4xline buffer size in stack */ /*!< log use 2xline buffer size in stack */ /*!< pay attention to prevent stack overflow */ #define BFLOG_LINE_BUFFER_SIZE 256 +/*!< 最小文件尺寸分割大小 */ /*!< file size rotate min size */ #define BFLOG_FILE_SIZE_MIN (1024) +/*!< 最小时间分割大小 */ /*!< file time rotate min interval */ #define BFLOG_FILE_INTERVAL_MIN (60) +/*!< 默认记录器配置的记录功能 */ +/*!< 可以动态修改记录器配置调节记录功能, 提高速度 */ /*!< default record flag config */ /*!< | item | time occupancy | */ /*!< | level | low | */ @@ -104,54 +122,45 @@ (0xff & BFLOG_FLAG_TIME) | \ (0x00 & BFLOG_FLAG_THREAD)) +/*!< 不同日志等级颜色配置 */ /*!< color config */ #define BFLOG_COLOR_FATAL BFLOG_COLOR_FG_MAGENTA BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL #define BFLOG_COLOR_ERROR BFLOG_COLOR_FG_RED BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL #define BFLOG_COLOR_WARN BFLOG_COLOR_FG_YELLOW BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL -#define BFLOG_COLOR_INFO BFLOG_COLOR_FG_GREEN BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL +#define BFLOG_COLOR_INFO BFLOG_COLOR_FG_NONE BFLOG_COLOR_BG_NONE BFLOG_SGR_RESET #define BFLOG_COLOR_DEBUG BFLOG_COLOR_FG_WHITE BFLOG_COLOR_BG_NONE BFLOG_SGR_NORMAL #define BFLOG_COLOR_TRACE BFLOG_COLOR_FG_WHITE BFLOG_COLOR_BG_NONE BFLOG_SGR_FAINT +/*!< 简易排版的格式 */ /*!< simple layout */ -#define LAYOUT_USE 1 - -#if (LAYOUT_USE == 0) -#define BFLOG_SIMPLE_LAYOUT_STRING(_color, _level, _tm, _msg) \ - "%s" \ - "[%s][%10lu][%d-%02d-%02d %02d:%02d:%02d]" \ - "[%s:%s:%d]" \ - "<%s> %s", \ - (_color), \ - (_level), \ - ((_msg)->clkl), \ - (_tm)->year, (_tm)->mon, (_tm)->mday, \ - (_tm)->hour, (_tm)->min, (_tm)->sec, \ - ((_msg)->file), ((_msg)->func), ((_msg)->line), \ - ((_msg)->tag), \ - ((_msg)->string) -#elif (LAYOUT_USE == 1) -#define BFLOG_SIMPLE_LAYOUT_STRING(_color, _level, _tm, _msg) \ - "%s" \ - "[%s][%10lu][%d-%02d-%02d %02d:%02d:%02d]" \ - "<%s> %s", \ - (_color), \ - (_level), \ - ((_msg)->clkl), \ - (_tm)->year, (_tm)->mon, (_tm)->mday, \ - (_tm)->hour, (_tm)->min, (_tm)->sec, \ - ((_msg)->tag), \ +#if 1 +#define BFLOG_SIMPLE_LAYOUT_STRING(_color, _level, _tag, _tm, _msg) \ + "%s" \ + "[%s][%10lu][%d-%02d-%02d %02d:%02d:%02d]" \ + "[%s:%s:%d]" \ + "<%s> %s", \ + (_color), \ + (_level), \ + ((_msg)->clkl), \ + (_tm)->year, (_tm)->mon, (_tm)->mday, \ + (_tm)->hour, (_tm)->min, (_tm)->sec, \ + ((_msg)->file), ((_msg)->func), ((_msg)->line), \ + (_tag), \ ((_msg)->string) #else -#define BFLOG_SIMPLE_LAYOUT_STRING(_color, _level, _tm, _msg) \ - "%s" \ - "[%s][%lu]" \ - " %s", \ - (_color), \ - (_level), \ - ((_msg)->clkl), \ +#define BFLOG_SIMPLE_LAYOUT_STRING(_color, _level, _tag, _tm, _msg) \ + "%s" \ + "[%s][%10lu][%02d:%02d:%02d]" \ + "<%s> %s", \ + (_color), \ + (_level), \ + ((_msg)->clkl), \ + (_tm)->hour, (_tm)->min, (_tm)->sec, \ + (_tag), \ ((_msg)->string) #endif +/*!< 不同日志等级提示信息配置 */ /*!< level string config */ #define BFLOG_LEVEL_FATAL_STRING "FATL" #define BFLOG_LEVEL_ERROR_STRING "ERRO" @@ -160,16 +169,4 @@ #define BFLOG_LEVEL_DEBUG_STRING "DBUG" #define BFLOG_LEVEL_TRACE_STRING "TRAC" -#define bflog_fopen vlibc_fopen -#define bflog_fclose vlibc_fclose -#define bflog_fwrite vlibc_fwrite -#define bflog_ftell vlibc_ftell -#define bflog_fflush vlibc_fflush -#define bflog_snprintf vlibc_snprintf -#define bflog_vsnprintf vlibc_vsnprintf -#define bflog_remove vlibc_remove -#define bflog_rename vlibc_rename - -#define bflog_memcpy memcpy - #endif diff --git a/examples/bflog/freertos_async/example_log.h b/examples/bflog/freertos_async/example_log.h new file mode 100644 index 00000000..1e544dd3 --- /dev/null +++ b/examples/bflog/freertos_async/example_log.h @@ -0,0 +1,59 @@ +#ifndef _EXAMPLE_LOG_H +#define _EXAMPLE_LOG_H + +#include +#include +#include "bflog.h" + +extern bflog_t example_recorder; + +#define LOG_F(...) BFLOG_F((void *)&example_recorder, __VA_ARGS__) +#define LOG_E(...) BFLOG_E((void *)&example_recorder, __VA_ARGS__) +#define LOG_W(...) BFLOG_W((void *)&example_recorder, __VA_ARGS__) +#define LOG_I(...) BFLOG_I((void *)&example_recorder, __VA_ARGS__) +#define LOG_D(...) BFLOG_D((void *)&example_recorder, __VA_ARGS__) +#define LOG_T(...) BFLOG_T((void *)&example_recorder, __VA_ARGS__) +#define LOG_FLUSH() bflog_flush(&example_recorder) + +extern void error_handler(void); + +#ifdef CONFIG_ASSERT_DISABLE + +#define _ASSERT_PARAM(x) ((void)(0)) +#define _ASSERT_FUNC(x) ((void)(x)) +#define _CALL_ERROR() error_handler() + +#else + +#define _CALL_ERROR() \ + do { \ + printf("(Call Error Handler)\r\n"); \ + LOG_F("Call Error Handler\r\n"); \ + LOG_FLUSH(); \ + error_handler(); \ + } while (0) + +#define _ASSERT_PARAM(x) \ + if ((uint32_t)(x) == 0) { \ + printf("(Assertion Faild)\r\n"); \ + printf("(%s)\r\n", (const char *)(#x)); \ + LOG_F("Assertion Faild\r\n"); \ + LOG_F("%s\r\n", (const char *)(#x)); \ + LOG_FLUSH(); \ + error_handler(); \ + } + +#define _ASSERT_FUNC(x) \ + do { \ + if ((uint32_t)(x) == 0) { \ + printf("(Assertion Faild)\r\n"); \ + printf("(%s)\r\n", (const char *)(#x)); \ + LOG_F("Assertion Faild\r\n"); \ + LOG_F("%s\r\n", (const char *)(#x)); \ + LOG_FLUSH(); \ + error_handler(); \ + } \ + } while (0) +#endif + +#endif diff --git a/examples/bflog/freertos_async/flash_prog_cfg.ini b/examples/bflog/freertos_async/flash_prog_cfg.ini new file mode 100644 index 00000000..4df2a737 --- /dev/null +++ b/examples/bflog/freertos_async/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/freertos_async_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/bflog/freertos_async/main.c b/examples/bflog/freertos_async/main.c new file mode 100644 index 00000000..479f3877 --- /dev/null +++ b/examples/bflog/freertos_async/main.c @@ -0,0 +1,282 @@ +#include "bflb_mtimer.h" +#include "bflb_uart.h" +#include "bflb_rtc.h" +#include "board.h" +#include "bflog.h" +#include "example_log.h" + +/*!< 定义INLINE tag标签, 默认禁用输出 */ +BFLOG_DEFINE_TAG(INLINE, "inline func", false); + +/*!< 定义MAIN tag标签, 默认使能输出 */ +BFLOG_DEFINE_TAG(MAIN, "main", true); + +/*!< 设置此文件使用的tag标签 */ +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(MAIN) + +/*!< bflog 多线程异步例程 */ +/*!< bflog multithread async example */ +/*!< 多线程建议在未开始RTOS调度之前配置为同步模式, 开始RTOS调度后再切换为异步模式 + 此时不管RTOS能否正常工作, LOG工作都不会异常导致无LOG输出 */ + +struct bflb_device_s *uart0 = NULL; +static struct bflb_device_s *rtc = NULL; + +/*!< 当前的UTC时间戳 2022-12-16 17:52 */ +uint32_t timestamp_base = 1671184300; + +/** @defgroup example_bflog_port port +----------------------------------------------------------------------------- +* @{ +----------------------------------------------------------------------------*/ +uint64_t bflog_clock(void) +{ + return bflb_mtimer_get_time_us(); +} + +uint32_t bflog_time(void) +{ + return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + timestamp_base; +} + +char *bflog_thread(void) +{ + return ""; +} +/*--------------------------------------------------------------------------- +* @} example_bflog_port port +----------------------------------------------------------------------------*/ + +#define EXAMPLE_LOG_POOL_SIZE 4096 + +bflog_t example_recorder; +void *example_recorder_pointer = &example_recorder; +static uint32_t example_pool[EXAMPLE_LOG_POOL_SIZE / 4]; +bflog_direct_stream_t example_uart_stream; + +/***************************************************************************** +* @brief 流输出 +* +* @param[in] ptr 输出信息的指针 +* @param[in] size 输出信息的大小（byte） +* +* @retval uint16_t +*****************************************************************************/ +uint16_t example_uart_stream_output(void *ptr, uint16_t size) +{ + for (size_t i = 0; i < size; i++) { + bflb_uart_putchar(uart0, ((char *)ptr)[i]); + } + return size; +} + +/***************************************************************************** +* @brief 进入多线程调度前初始化 +* +* +*****************************************************************************/ +void example_log_init_before_enter(void) +{ + void *record = (void *)&example_recorder; + void *direct = (void *)&example_uart_stream; + + /*!< 创建一个记录器, 配置内存池, 内存池大小, 模式为同步 */ + /*!< create recorder */ + if (0 != bflog_create(record, example_pool, EXAMPLE_LOG_POOL_SIZE, BFLOG_MODE_SYNC)) { + printf("bflog_create faild\r\n"); + } + + /*!< 创建输出器, 类型为流输出器, 使能颜色输出, 互斥锁设为NULL */ + /*!< create stream direct */ + bflog_direct_create(direct, BFLOG_DIRECT_TYPE_STREAM, BFLOG_DIRECT_COLOR_ENABLE, NULL, NULL); + /*!< 配置流输出的输出函数 */ + bflog_direct_init_stream((void *)direct, example_uart_stream_output); + + /*!< 添加输出器到记录器 */ + /*!< connect direct and recorder */ + bflog_append(record, direct); + + /*!< 恢复输出器到工作模式 */ + /*!< resume direct */ + bflog_direct_resume(direct); + + /*!< 恢复记录器到工作模式 */ + /*!< resume record */ + bflog_resume(record); +} + +/** @defgroup freertos_base +----------------------------------------------------------------------------- +* @{ +----------------------------------------------------------------------------*/ +#include +#include "task.h" +#include "queue.h" +#include "semphr.h" +#include "timers.h" +#include "event_groups.h" + +void vApplicationTickHook(void) +{ +} + +void vApplicationIdleHook(void) +{ +} + +void vAssertCalled(void) +{ + LOG_F("vAssertCalled\r\n"); + _CALL_ERROR(); +} + +void vApplicationStackOverflowHook(TaskHandle_t xTask, char *pcTaskName) +{ + LOG_F("vApplicationStackOverflowHook\r\n"); + LOG_F("Taskname [%s]\r\n", pcTaskName); + _CALL_ERROR(); +} + +void vApplicationMallocFailedHook(void) +{ + LOG_F("vApplicationMallocFailedHook\r\n"); + _CALL_ERROR(); +} + +/*--------------------------------------------------------------------------- +* @} freertos_base +----------------------------------------------------------------------------*/ + +/** @defgroup thread_start +----------------------------------------------------------------------------- +* @{ +----------------------------------------------------------------------------*/ +#include "shell.h" +extern void shell_init_with_task(struct bflb_device_s *shell); + +extern void app_server_log_init(void); + +extern TaskHandle_t consumer_handle; +extern TaskHandle_t producer_handle; +extern void consumer_task(void *pvParameters); +extern void producer_task(void *pvParameters); + +static TaskHandle_t task_start; +static void +task_function_start(void *param) +{ + LOG_I("start start task\r\n"); + + app_server_log_init(); + + shell_init_with_task(uart0); + + xTaskCreate(consumer_task, (char *)"consumer_task", 512, NULL, 4, &consumer_handle); + xTaskCreate(producer_task, (char *)"producer_task", 512, NULL, 5, &producer_handle); + + LOG_I("delete start task\r\n"); + vTaskDelete(NULL); +} + +/*--------------------------------------------------------------------------- +* @} thread_start +----------------------------------------------------------------------------*/ + +QueueHandle_t queue; + +int main(void) +{ + board_init(); + + /*!< uart0 already initialized in bsp/board */ + uart0 = bflb_device_get_by_name("uart0"); + rtc = bflb_device_get_by_name("rtc"); + bflb_rtc_set_time(rtc, 0); + + example_log_init_before_enter(); + + LOG_I("app start init\r\n"); + + _ASSERT_PARAM(configMAX_PRIORITIES >= 7); + + queue = xQueueCreate(32, sizeof(void *)); + _ASSERT_PARAM(NULL != queue); + + _ASSERT_FUNC(pdPASS == xTaskCreate( + /*!< task function */ task_function_start, + /*!< task name */ "START", + /*!< stack size */ 1024, + /*!< task param */ NULL, + /*!< task priority */ 6, + /*!< task handle */ &task_start)); + + LOG_I("app start init success\r\n"); + + vTaskStartScheduler(); + + while (1) { + bflb_mtimer_delay_ms(200); + } +} + +void error_handler(void) +{ + volatile unsigned char dummy = 0; + + printf("(enter error handler)\r\n"); + LOG_F("enter error handler\r\n"); + LOG_FLUSH(); + + uint32_t flag = bflb_irq_save(); + + while (dummy == 0) { + } + + bflb_irq_restore(flag); +} + +static int tag_config(int argc, char **argv) +{ + int ret = 0; + + if (argc < 3) { + LOG_I("tag_config 1\r\n"); + LOG_I("tag_config 0\r\n"); + return 0; + } + + LOG_I("exec bflog_global_filter(\"%s\",%d)\r\n", argv[1], atoi(argv[2])); + ret = bflog_global_filter(argv[1], atoi(argv[2])); + if (ret) { + LOG_E("exec result faild, %d\r\n", ret); + } else { + LOG_I("exec success\r\n"); + } + + return 0; +} + +static int level_config(int argc, char **argv) +{ + int ret = 0; + + if (argc < 2) { + LOG_I("level_config \r\n"); + return 0; + } + + LOG_I("exec bflog_control(&example_recorder,BFLOG_CMD_LEVEL,%d)\r\n", atoi(argv[1])); + ret = bflog_control(&example_recorder, BFLOG_CMD_LEVEL, atoi(argv[1])); + + if (ret) { + LOG_E("exec result faild, %d\r\n", ret); + } else { + LOG_I("exec success\r\n"); + } + + return 0; +} + +SHELL_CMD_EXPORT(tag_config, tag config); +SHELL_CMD_EXPORT(level_config, level config); \ No newline at end of file diff --git a/examples/bflog/freertos_async/proj.conf b/examples/bflog/freertos_async/proj.conf new file mode 100644 index 00000000..b82c00d9 --- /dev/null +++ b/examples/bflog/freertos_async/proj.conf @@ -0,0 +1,23 @@ +set(CONFIG_VLIBC 0) +set(CONFIG_VLIBC_FATFS 0) + +set(CONFIG_SHELL 1) + +set(CONFIG_BFLOG 1) +set(CONFIG_BFLOG_USER 1) + +set(CONFIG_FREERTOS 1) + +set(CONFIG_FATFS 0) + +set(CONFIG_BSP_SDH_SDCARD 0) +set(CONFIG_FATFS_SDH_SDCARD 0) + +set(CONFIG_VSNPRINTF_FLOAT 1) +set(CONFIG_VSNPRINTF_FLOAT_EX 1) +set(CONFIG_VSNPRINTF_LONG_LONG 1) + +set(CONFIG_LOG_DISABLE 0) +set(CONFIG_ASSERT_DISABLE 0) +set(CONFIG_LOG_LEVEL 3) +set(CONFIG_BFLOG_POOL_SIZE 1024) \ No newline at end of file diff --git a/examples/bflog/freertos_async/static_inline.h b/examples/bflog/freertos_async/static_inline.h new file mode 100644 index 00000000..5aa6e29b --- /dev/null +++ b/examples/bflog/freertos_async/static_inline.h @@ -0,0 +1,19 @@ +#include "example_log.h" + +#ifndef __STATIC_INLINE_H__ +#define __STATIC_INLINE_H__ + +/*!< 只能在不被include的c文件中定义tag标签 */ +/*!< 头文件中可以使用extern将标签导出 */ +BFLOG_EXTERN_TAG(INLINE); + +/*!< 设置此文件使用的tag标签 */ +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(INLINE) + +static inline void test_log_static_inline(void) +{ + LOG_I("static inline\r\n"); +} + +#endif \ No newline at end of file diff --git a/examples/bflog/freertos_async/thread_consumer.c b/examples/bflog/freertos_async/thread_consumer.c new file mode 100644 index 00000000..559d26b0 --- /dev/null +++ b/examples/bflog/freertos_async/thread_consumer.c @@ -0,0 +1,45 @@ +#include +#include "task.h" +#include "queue.h" +#include "semphr.h" +#include "timers.h" +#include "event_groups.h" +#include "example_log.h" +#include "static_inline.h" + +BFLOG_DEFINE_TAG(RX, "rx", false); + +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(RX) + +TaskHandle_t consumer_handle; + +extern QueueHandle_t queue; + +void consumer_task(void *pvParameters) +{ + uint8_t time = 200; + + LOG_I("Consumer task enter \r\n"); + vTaskDelay(1000); + LOG_I("Consumer task start \r\n"); + + uint32_t count; + + while (1) { + time += 20; + time %= 64; + if (pdTRUE != xQueueReceive(queue, &count, portMAX_DELAY)) { + LOG_E("queue recv faild\r\n"); + } else { + LOG_I("Consumer recv << %d\r\n", count); + LOG_D("Consumer recv << %d\r\n", count); + LOG_T("Consumer recv << %d\r\n", count); + test_log_static_inline(); + } + + vTaskDelay(time); + } + + vTaskDelete(NULL); +} \ No newline at end of file diff --git a/examples/bflog/freertos_async/thread_log.c b/examples/bflog/freertos_async/thread_log.c new file mode 100644 index 00000000..ec8d13bb --- /dev/null +++ b/examples/bflog/freertos_async/thread_log.c @@ -0,0 +1,160 @@ +#include +#include "task.h" +#include "queue.h" +#include "semphr.h" +#include "timers.h" +#include "event_groups.h" +#include "example_log.h" + +BFLOG_DEFINE_TAG(LOG, "log", true); + +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(LOG) + +/* flush notice ------------------------------------------------------------------*/ + +static EventGroupHandle_t event_group_server_log_flush_notice; +static int +log_flush_notice(void) +{ + xEventGroupSetBits(event_group_server_log_flush_notice, 0x00000001); + return 0; +} + +/* Task Function ------------------------------------------------------------------*/ + +TaskHandle_t task_server_log; +void task_function_server_log(void *param) +{ + LOG_I("start server log task\r\n"); + + while (1) { + xEventGroupWaitBits(event_group_server_log_flush_notice, 0x00000001, pdTRUE, pdFALSE, portMAX_DELAY); + LOG_FLUSH(); + } + + LOG_E("delete server_log task\r\n"); + vTaskDelete(NULL); +} + +/* BFLOG Varibale ------------------------------------------------------------------*/ + +extern bflog_t example_recorder; +extern bflog_direct_stream_t example_uart_stream; + +#ifdef EXAMPLE_ENABLE_FILESYSTEM +static bflog_direct_file_time_t bflog_direct_filetime; +static bflog_direct_file_size_t bflog_direct_filesize; +#endif + +/* BFLOG Mutex ------------------------------------------------------------------*/ +static SemaphoreHandle_t sem_server_log; + +static int +bflog_enter_critical(void) +{ + if (pdTRUE == xSemaphoreTake(sem_server_log, (TickType_t)200)) { + return 0; + } else { + return -1; + } +} + +static int +bflog_exit_critical(void) +{ + xSemaphoreGive(sem_server_log); + return 0; +} + +/* BFLOG Stream Mutex ------------------------------------------------------------------*/ +SemaphoreHandle_t sem_server_uart0; + +static int +bflog_direct_stream_lock(void) +{ + if (pdTRUE == xSemaphoreTake(sem_server_uart0, (TickType_t)200)) { + return 0; + } else { + return -1; + } +} + +static int +bflog_direct_stream_unlock(void) +{ + xSemaphoreGive(sem_server_uart0); + return 0; +} + +/* APP init ------------------------------------------------------------------*/ + +void app_server_log_init(void) +{ + LOG_I("app server log start init\r\n"); + + LOG_FLUSH(); + + sem_server_uart0 = xSemaphoreCreateMutex(); + _ASSERT_PARAM(NULL != sem_server_uart0); + + /*!< create event flag */ + event_group_server_log_flush_notice = xEventGroupCreate(); + _ASSERT_PARAM(NULL != event_group_server_log_flush_notice); + + /*!< create mutex */ + sem_server_log = xSemaphoreCreateMutex(); + _ASSERT_PARAM(NULL != sem_server_log); + + /*!< suspen recorder */ + _ASSERT_FUNC(0 == bflog_suspend(&example_recorder)); + + /*!< reconfig async mode */ + _ASSERT_FUNC(0 == bflog_control(&example_recorder, BFLOG_CMD_FLUSH_NOTICE, (uint32_t)log_flush_notice)); + _ASSERT_FUNC(0 == bflog_control(&example_recorder, BFLOG_CMD_MODE, BFLOG_MODE_ASYNC)); + + /*!< recofig uart0 direct stream, set lock unlock function */ + _ASSERT_FUNC(0 == bflog_direct_suspend((void *)&example_uart_stream)); + _ASSERT_FUNC(0 == bflog_direct_control((void *)&example_uart_stream, BFLOG_DIRECT_CMD_LOCK, (uint32_t)bflog_direct_stream_lock)); + _ASSERT_FUNC(0 == bflog_direct_control((void *)&example_uart_stream, BFLOG_DIRECT_CMD_UNLOCK, (uint32_t)bflog_direct_stream_unlock)); + _ASSERT_FUNC(0 == bflog_direct_resume((void *)&example_uart_stream)); + +#ifdef EXAMPLE_ENABLE_FILESYSTEM + /*!< create and config file time direct, keep common log info */ + /*!< lock unlcok function not need, fatfs support re-entrancy mode */ + _ASSERT_FUNC(0 == bflog_direct_create((void *)&bflog_direct_filetime, BFLOG_DIRECT_TYPE_FILE_TIME, BFLOG_DIRECT_COLOR_DISABLE, NULL, NULL)); + /*!< 6 * 60 * 60 second create a file */ + /*!< keep max 120 files */ + _ASSERT_FUNC(0 == bflog_direct_init_file_time((void *)&bflog_direct_filetime, "sd:/log/common", 6 * 60 * 60, 120)); + _ASSERT_FUNC(0 == bflog_append(&example_recorder, (void *)&bflog_direct_filetime)); + _ASSERT_FUNC(0 == bflog_direct_resume((void *)&bflog_direct_filetime)); + + /*!< create and config file time direct, only keep error and warning log info */ + /*!< lock unlcok function not need, fatfs support re-entrancy mode */ + _ASSERT_FUNC(0 == bflog_direct_create((void *)&bflog_direct_filesize, BFLOG_DIRECT_TYPE_FILE_SIZE, BFLOG_DIRECT_COLOR_DISABLE, NULL, NULL)); + /*!< 128 * 1024 bytes create a file */ + /*!< keep max 16 files */ + _ASSERT_FUNC(0 == bflog_direct_init_file_size((void *)&bflog_direct_filesize, "sd:/log/error", 128 * 1024, 16)); + _ASSERT_FUNC(0 == bflog_direct_control((void *)&bflog_direct_filesize, BFLOG_DIRECT_CMD_LEVEL, BFLOG_LEVEL_WARN)); + _ASSERT_FUNC(0 == bflog_append(&example_recorder, (void *)&bflog_direct_filesize)); + _ASSERT_FUNC(0 == bflog_direct_resume((void *)&bflog_direct_filesize)); +#endif + + /*!< config mutex */ + _ASSERT_FUNC(0 == bflog_control(&example_recorder, BFLOG_CMD_ENTER_CRITICAL, (uint32_t)bflog_enter_critical)); + _ASSERT_FUNC(0 == bflog_control(&example_recorder, BFLOG_CMD_EXIT_CRITICAL, (uint32_t)bflog_exit_critical)); + + /*!< resume recorder */ + _ASSERT_FUNC(0 == bflog_resume(&example_recorder)); + + /*!< create flush task */ + _ASSERT_FUNC(pdPASS == xTaskCreate( + /*!< task function */ task_function_server_log, + /*!< task name */ "LOG", + /*!< stack size */ 1024, + /*!< task param */ NULL, + /*!< task priority */ 3, + /*!< task handle */ &task_server_log)); + + LOG_I("app server log init success\r\n"); +} diff --git a/examples/bflog/freertos_async/thread_producer.c b/examples/bflog/freertos_async/thread_producer.c new file mode 100644 index 00000000..c0c88e0f --- /dev/null +++ b/examples/bflog/freertos_async/thread_producer.c @@ -0,0 +1,45 @@ +#include +#include "task.h" +#include "queue.h" +#include "semphr.h" +#include "timers.h" +#include "event_groups.h" +#include "example_log.h" +#include "static_inline.h" + +BFLOG_DEFINE_TAG(TX, "tx", false); + +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(TX) + +TaskHandle_t producer_handle; + +extern QueueHandle_t queue; + +void producer_task(void *pvParameters) +{ + uint8_t time = 100; + + LOG_I("Producer task enter \r\n"); + vTaskDelay(1000); + LOG_I("Producer task start \r\n"); + + uint32_t count = 0; + + while (1) { + time = rand() % 255; + + count++; + LOG_I("Producer send >> %d\r\n", count); + LOG_D("Producer send >> %d\r\n", count); + LOG_T("Producer send >> %d\r\n", count); + test_log_static_inline(); + if (pdTRUE != xQueueSend(queue, (void *)&count, 1000)) { + LOG_E("queue send faild\r\n"); + } + + vTaskDelay(time); + } + + vTaskDelete(NULL); +} \ No newline at end of file diff --git a/examples/bflog/main.c b/examples/bflog/main.c deleted file mode 100644 index b3a5bef4..00000000 --- a/examples/bflog/main.c +++ /dev/null @@ -1,104 +0,0 @@ -#include "bflb_mtimer.h" -#include "board.h" -#include "ff.h" -#include "log.h" - -FATFS fs; -__attribute((aligned(8))) static uint32_t workbuf[4096]; - -MKFS_PARM fs_para = { - .fmt = FM_FAT32, /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */ - .n_fat = 1, /* Number of FATs */ - .align = 0, /* Data area alignment (sector) */ - .n_root = 1, /* Number of root directory entries */ - .au_size = 512 * 32, /* Cluster size (byte) */ -}; - -void filesystem_init(void) -{ - FRESULT ret; - - board_sdh_gpio_init(); - - extern void fatfs_sdh_driver_register(void); - fatfs_sdh_driver_register(); - - ret = f_mount(&fs, "sd:/", 1); - - if (ret == FR_NO_FILESYSTEM) { - LOG_W("No filesystem yet, try to be formatted...\r\n"); - - ret = f_mkfs("sd:/", &fs_para, workbuf, sizeof(workbuf)); - - if (ret != FR_OK) { - LOG_F("fail to make filesystem\r\n"); - _CALL_ERROR(); - } - - if (ret == FR_OK) { - LOG_I("done with formatting.\r\n"); - LOG_I("first start to unmount.\r\n"); - ret = f_mount(NULL, "sd:/", 1); - LOG_I("then start to remount.\r\n"); - } - } else if (ret != FR_OK) { - LOG_F("fail to mount filesystem,error= %d\r\n", ret); - LOG_F("SD card might fail to initialise.\r\n"); - _CALL_ERROR(); - } else { - LOG_D("Succeed to mount filesystem\r\n"); - } - - if (ret == FR_OK) { - LOG_I("FileSystem cluster size:%d-sectors (%d-Byte)\r\n", fs.csize, fs.csize * 512); - } -} - -static bflog_direct_file_time_t bflog_direct_filetime; -static bflog_direct_file_size_t bflog_direct_filesize; - -void bflog_restart(void) -{ - void *record = (void *)&__bflog_recorder; - - void *direct0 = (void *)&bflog_direct_filetime; - void *direct1 = (void *)&bflog_direct_filesize; - - bflog_direct_create(direct0, BFLOG_DIRECT_TYPE_FILE_TIME, BFLOG_DIRECT_COLOR_DISABLE, NULL, NULL); - bflog_direct_init_file_time_s(direct0, "sd:/log/common", 60, 42); - - bflog_direct_create(direct1, BFLOG_DIRECT_TYPE_FILE_SIZE, BFLOG_DIRECT_COLOR_DISABLE, NULL, NULL); - bflog_direct_init_file_size_s(direct1, "sd:/log/error", 128 * 1024, 16); - bflog_direct_control_s(direct1, BFLOG_DIRECT_CMD_LEVEL, BFLOG_LEVEL_WARN); - - /*!< suspend record */ - bflog_suspend_s(record); - - bflog_append_s(record, direct0); - bflog_append_s(record, direct1); - - bflog_direct_resume_s(direct0); - bflog_direct_resume_s(direct1); - - /*!< resume record */ - bflog_resume_s(record); -} - -int main(void) -{ - board_init(); - - filesystem_init(); - - bflog_restart(); - - while (1) { - LOG_F("hello world\r\n"); - LOG_E("hello world\r\n"); - LOG_W("hello world\r\n"); - LOG_I("hello world\r\n"); - LOG_D("hello world\r\n"); - LOG_T("hello world\r\n"); - bflb_mtimer_delay_ms(200); - } -} diff --git a/examples/bflog/proj.conf b/examples/bflog/proj.conf deleted file mode 100644 index a42bdc6c..00000000 --- a/examples/bflog/proj.conf +++ /dev/null @@ -1,9 +0,0 @@ -set(CONFIG_VLIBC 1) -set(CONFIG_VLIBC_FATFS 1) - -set(CONFIG_BFLOG 1) -set(CONFIG_BFLOG_USER 1) -set(CONFIG_FATFS 1) - -set(CONFIG_BSP_SDH_SDCARD 1) -set(CONFIG_BSP_FATFS_SDH_SDCARD 1) \ No newline at end of file diff --git a/examples/bl808_dualcore/helloworld_d0/README.md b/examples/bl808_dualcore/helloworld_d0/README.md new file mode 100644 index 00000000..92b485c6 --- /dev/null +++ b/examples/bl808_dualcore/helloworld_d0/README.md @@ -0,0 +1,22 @@ +# bl808_dualcore + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL808 | Only for D0 CPU | + +## Compile + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/bl808_dualcore/helloworld_d0/flash_prog_cfg.ini b/examples/bl808_dualcore/helloworld_d0/flash_prog_cfg.ini new file mode 100644 index 00000000..9bbaac9a --- /dev/null +++ b/examples/bl808_dualcore/helloworld_d0/flash_prog_cfg.ini @@ -0,0 +1,12 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/helloworld*_$(CHIPNAME).bin +# since D0 is boot by M0，this address should consistent with m0's board_init in board.c +address = 0x100000 \ No newline at end of file diff --git a/examples/bl808_dualcore/helloworld_d0/main.c b/examples/bl808_dualcore/helloworld_d0/main.c index a24ee1f6..7182df38 100644 --- a/examples/bl808_dualcore/helloworld_d0/main.c +++ b/examples/bl808_dualcore/helloworld_d0/main.c @@ -1,5 +1,7 @@ #include "bflb_mtimer.h" #include "board.h" + +#define DBG_TAG "MAIN" #include "log.h" int main(void) diff --git a/examples/bl808_dualcore/helloworld_m0/README.md b/examples/bl808_dualcore/helloworld_m0/README.md new file mode 100644 index 00000000..f29ca294 --- /dev/null +++ b/examples/bl808_dualcore/helloworld_m0/README.md @@ -0,0 +1,22 @@ +# bl808_dualcore + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL808 | Only for M0 CPU | + +## Compile + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/bl808_dualcore/helloworld_m0/flash_prog_cfg.ini b/examples/bl808_dualcore/helloworld_m0/flash_prog_cfg.ini new file mode 100644 index 00000000..93766fff --- /dev/null +++ b/examples/bl808_dualcore/helloworld_m0/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/helloworld*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/bl808_dualcore/helloworld_m0/main.c b/examples/bl808_dualcore/helloworld_m0/main.c index 6b2c26ca..8d5aff81 100644 --- a/examples/bl808_dualcore/helloworld_m0/main.c +++ b/examples/bl808_dualcore/helloworld_m0/main.c @@ -1,5 +1,7 @@ #include "bflb_mtimer.h" #include "board.h" + +#define DBG_TAG "MAIN" #include "log.h" int main(void) diff --git a/examples/boot2_isp/README.md b/examples/boot2_isp/README.md new file mode 100644 index 00000000..ecaa10a3 --- /dev/null +++ b/examples/boot2_isp/README.md @@ -0,0 +1,43 @@ +# boot2_isp + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | Only for m0 CPU | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/boot2_isp/bflb_eflash_loader_cmds.c b/examples/boot2_isp/bflb_eflash_loader_cmds.c index 15572974..09ea61d6 100644 --- a/examples/boot2_isp/bflb_eflash_loader_cmds.c +++ b/examples/boot2_isp/bflb_eflash_loader_cmds.c @@ -48,6 +48,8 @@ #define BFLB_EFLASH_LOADER_CHECK_LEN 2048 #define BFLB_EFLASH_MAX_SIZE 2 * 1024 * 1024 +// 4bytes、32bit数据大小端转化 +#define L2B32(Little) (((Little & 0xff) << 24) | (((Little) & 0xff00) << 8) | (((Little) & 0xff0000) >> 8) | ((Little >> 24) & 0xff)) #if BLSP_BOOT2_SUPPORT_EFLASH_LOADER_RAM static struct image_cfg_t image_cfg; @@ -479,9 +481,12 @@ static int32_t bflb_eflash_loader_cmd_read_jedec_id(uint16_t cmd, uint8_t *data, /*ack read jedec ID */ tmp_buf[2] = 4; tmp_buf[3] = 0; - ackdata[0] = bflb_flash_get_jedec_id(); + ackdata[1] = bflb_flash_get_jedec_id(); ackdata[1] &= 0x00ffffff; ackdata[1] |= 0x80000000; + ackdata[1] = (ackdata[1]) << 8; + ackdata[1] |= 0x80; + ackdata[1] = L2B32(ackdata[1]); bflb_eflash_loader_if_write((uint32_t *)ackdata, 4 + 4); return BFLB_EFLASH_LOADER_SUCCESS; } diff --git a/examples/boot2_isp/bflb_eflash_loader_cmds.h b/examples/boot2_isp/bflb_eflash_loader_cmds.h index d19a57b0..14611be0 100644 --- a/examples/boot2_isp/bflb_eflash_loader_cmds.h +++ b/examples/boot2_isp/bflb_eflash_loader_cmds.h @@ -120,7 +120,7 @@ struct eflash_loader_cmd_cfg_t { __PACKED_STRUCT boot_flash_cfg_t { uint32_t magiccode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; + spi_flash_cfg_type cfg; uint32_t crc32; }; diff --git a/examples/boot2_isp/bflb_eflash_loader_uart.c b/examples/boot2_isp/bflb_eflash_loader_uart.c index 94a15340..3e67f860 100644 --- a/examples/boot2_isp/bflb_eflash_loader_uart.c +++ b/examples/boot2_isp/bflb_eflash_loader_uart.c @@ -39,6 +39,7 @@ #include "partition.h" #include "bflb_uart.h" #include "bflb_port_boot2.h" +#include "bflb_uart.h" static uint32_t g_detected_baudrate; struct bflb_device_s *uartx; @@ -53,10 +54,39 @@ void bflb_dump_data(uint8_t *buf, uint32_t size) } LOG_F("\r\n"); } + +static uint32_t uart_read_all_data(uint8_t *buf,uint32_t maxlen) +{ + return bflb_uart_get(uartx, buf, maxlen); +} + void ATTR_TCM_SECTION uart0_irq_callback(struct device *dev, void *args, uint32_t size, uint32_t state) { } +void ATTR_TCM_SECTION uart_isr(int irq, void *arg) +{ + uint32_t intstatus = bflb_uart_get_intstatus(uartx); + + if (intstatus & UART_INTSTS_RX_FIFO) { + + uint8_t *buf=(uint8_t *)g_eflash_loader_readbuf[g_rx_buf_index]; + + g_rx_buf_len+=uart_read_all_data(buf+g_rx_buf_len, + BFLB_EFLASH_LOADER_READBUF_SIZE-g_rx_buf_len); + bflb_uart_int_clear(uartx, UART_INTSTS_RX_FIFO); + + } + if (intstatus & UART_INTSTS_RTO) { + uint8_t *buf=(uint8_t *)g_eflash_loader_readbuf[g_rx_buf_index]; + + g_rx_buf_len+=uart_read_all_data(buf+g_rx_buf_len, + BFLB_EFLASH_LOADER_READBUF_SIZE-g_rx_buf_len); + bflb_uart_int_clear(uartx, UART_INTCLR_RTO); + } + +} + static void bflb_eflash_loader_usart_if_init(uint32_t bdrate) { struct bflb_uart_config_s cfg; @@ -68,8 +98,8 @@ static void bflb_eflash_loader_usart_if_init(uint32_t bdrate) cfg.stop_bits = UART_STOP_BITS_1; cfg.parity = UART_PARITY_NONE; cfg.flow_ctrl = 0; - cfg.tx_fifo_threshold = 7; - cfg.rx_fifo_threshold = 7; + cfg.tx_fifo_threshold = 16; + cfg.rx_fifo_threshold = 16; bflb_uart_init(uartx, &cfg); } @@ -80,7 +110,7 @@ void bflb_eflash_loader_usart_if_enable_int(void) void bflb_eflash_loader_usart_if_send(uint8_t *data, uint32_t len) { - uartx = bflb_device_get_by_name("uart0"); + //uartx = bflb_device_get_by_name("uart0"); bflb_uart_put(uartx, data, len); } @@ -94,6 +124,35 @@ int32_t bflb_eflash_loader_usart_if_wait_tx_idle(uint32_t timeout) static uint32_t *bflb_eflash_loader_usart_if_receive(uint32_t *recv_len, uint16_t maxlen, uint16_t timeout) { + uint8_t *buf = (uint8_t *)g_eflash_loader_readbuf[g_rx_buf_index]; + uint16_t datalen = 0; + uint64_t time_now; + + time_now = bflb_mtimer_get_time_ms(); + + do { + if (g_rx_buf_len >= 4) { + /* receive cmd id and data len*/ + datalen = buf[2] + (buf[3] << 8); + + if (g_rx_buf_len == datalen + 4) { + /*receive all the payload,return */ + /* move on to next buffer */ + g_rx_buf_index = (g_rx_buf_index + 1) % 2; + g_rx_buf_len = 0; + + if (datalen <= BFLB_EFLASH_LOADER_CMD_DATA_MAX_LEN) { + *recv_len = datalen + 4; + return (uint32_t *)buf; + } else { + *recv_len = 0; + return NULL; + } + } + } + } while (bflb_mtimer_get_time_ms() - time_now < timeout); + + *recv_len = 0; return NULL; } @@ -118,7 +177,7 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout) uint32_t handshake_count = 0; uint32_t rcv_buf_len = 0; //rcv_buf_len = UART_ReceiveData(g_uart_if_id,buf,128); - uartx = bflb_device_get_by_name("uart0"); + //uartx = bflb_device_get_by_name("uart0"); rcv_buf_len = bflb_uart_get(uartx, buf, UART_FIFO_LEN); //while(1) @@ -167,7 +226,7 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout) } } while (bflb_mtimer_get_time_ms() - nowtime < BFLB_EFLASH_LAODER_COMSUME_55_TIMEOUT); - bflb_eflash_loader_usart_if_send((uint8_t *)"Boot2 ISP Ready", strlen("Boot2 ISP Ready")); + /*init rx info */ g_rx_buf_index = 0; @@ -180,7 +239,10 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout) arch_memset(g_eflash_loader_readbuf[0], 0, BFLB_EFLASH_LOADER_READBUF_SIZE); arch_memset(g_eflash_loader_readbuf[1], 0, BFLB_EFLASH_LOADER_READBUF_SIZE); + bflb_irq_attach(uartx->irq_num, uart_isr, NULL); bflb_eflash_loader_usart_if_enable_int(); + bflb_irq_enable(uartx->irq_num); + bflb_eflash_loader_usart_if_send((uint8_t *)"Boot2 ISP Ready", strlen("Boot2 ISP Ready")); #endif diff --git a/examples/boot2_isp/blsp_common.c b/examples/boot2_isp/blsp_common.c index 9870edbf..df3b4928 100644 --- a/examples/boot2_isp/blsp_common.c +++ b/examples/boot2_isp/blsp_common.c @@ -43,6 +43,7 @@ #include "blsp_media_boot.h" #include "bflb_flash.h" #include "bflb_eflash_loader.h" +#include "bflb_uart.h" ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t g_malloc_buf[BFLB_BOOT2_XZ_MALLOC_BUF_SIZE]; @@ -88,7 +89,7 @@ int32_t blsp_mediaboot_pre_jump(void) /* reinit mtimer clock */ //system_mtimer_clock_reinit(); - + bflb_uart_deinit(uartx); /* deinit uart */ hal_boot2_debug_uart_gpio_deinit(); diff --git a/examples/boot2_isp/blsp_port.c b/examples/boot2_isp/blsp_port.c index 80f4d6dd..0da3210d 100644 --- a/examples/boot2_isp/blsp_port.c +++ b/examples/boot2_isp/blsp_port.c @@ -184,10 +184,10 @@ int32_t ATTR_TCM_SECTION blsp_boot2_set_encrypt(uint8_t index, boot2_image_confi len = g_boot_img_cfg->basic_cfg.img_len_cnt; if (len != 0) { - SF_Ctrl_AES_Set_Key_BE(index, NULL, (SF_Ctrl_AES_Key_Type)(g_boot_img_cfg->basic_cfg.encrypt_type - 1)); - SF_Ctrl_AES_Set_IV_BE(index, g_boot_img_cfg->aes_iv, g_boot_img_cfg->basic_cfg.group_image_offset); + bflb_sf_ctrl_aes_set_key_be(index, NULL, (g_boot_img_cfg->basic_cfg.encrypt_type - 1)); + bflb_sf_ctrl_aes_set_iv_be(index, g_boot_img_cfg->aes_iv, g_boot_img_cfg->basic_cfg.group_image_offset); - SF_Ctrl_AES_Set_Region(index, 1 /*enable this region*/, 1 /*hardware key*/, + bflb_sf_ctrl_aes_set_region(index, 1 /*enable this region*/, 1 /*hardware key*/, g_boot_img_cfg->basic_cfg.group_image_offset, g_boot_img_cfg->basic_cfg.group_image_offset + len - 1, g_boot_img_cfg->basic_cfg.aes_region_lock /*lock*/); @@ -196,8 +196,8 @@ int32_t ATTR_TCM_SECTION blsp_boot2_set_encrypt(uint8_t index, boot2_image_confi } if (aes_enabled) { - SF_Ctrl_AES_Enable_BE(); - SF_Ctrl_AES_Enable(); + bflb_sf_ctrl_aes_enable_be(); + bflb_sf_ctrl_aes_enable(); } return BFLB_BOOT2_SUCCESS; diff --git a/examples/boot2_isp/blsp_version.h b/examples/boot2_isp/blsp_version.h deleted file mode 100644 index 9027dc07..00000000 --- a/examples/boot2_isp/blsp_version.h +++ /dev/null @@ -1,41 +0,0 @@ -/** - ****************************************************************************** - * @file blsp_version.h - * @version V1.2 - * @date - * @brief This file is the peripheral case header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __MCU_SDK_VERSION_H__ -#define __MCU_SDK_VERSION_H__ - -#define BL_SDK_VER "1.0.0" - -#endif diff --git a/examples/boot2_isp/flash_prog_cfg.ini b/examples/boot2_isp/flash_prog_cfg.ini new file mode 100644 index 00000000..ba5d6a76 --- /dev/null +++ b/examples/boot2_isp/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/boot2_isp_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/boot2_isp/main.c b/examples/boot2_isp/main.c index 2d6158b0..f0900a46 100644 --- a/examples/boot2_isp/main.c +++ b/examples/boot2_isp/main.c @@ -362,7 +362,7 @@ int main(void) #endif uint8_t mfg_mode_flag = 0; //boot_clk_config clk_cfg; - uint8_t flash_cfg_buf[4 + sizeof(SPI_Flash_Cfg_Type) + 4] = { 0 }; + uint8_t flash_cfg_buf[4 + sizeof(spi_flash_cfg_type) + 4] = { 0 }; uint32_t crc; uint8_t *flash_cfg = NULL; uint32_t flash_cfg_len = 0; diff --git a/examples/boot2_isp/port/bl602/bflb_port_boot2.c b/examples/boot2_isp/port/bl602/bflb_port_boot2.c index 6e4c8dad..ac780f3f 100644 --- a/examples/boot2_isp/port/bl602/bflb_port_boot2.c +++ b/examples/boot2_isp/port/bl602/bflb_port_boot2.c @@ -3,8 +3,6 @@ #include "bl602_glb.h" #include "bl602_ef_ctrl.h" #include "bl602_hbn.h" -#include "bl602_xip_sflash.h" -#include "bl602_sf_cfg.h" #include "bl602_sf_cfg_ext.h" #include "bl602_glb.h" #include "bl602_xip_sflash_ext.h" @@ -502,7 +500,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) *******************************************************************************/ uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) { - uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(); + uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0,0); if (flash_addr >= img_offset) { return BL602_FLASH_XIP_BASE + (flash_addr - img_offset); } else { diff --git a/examples/boot2_isp/port/bl602/bflb_port_boot2.h b/examples/boot2_isp/port/bl602/bflb_port_boot2.h index b1e64dc2..c4173061 100644 --- a/examples/boot2_isp/port/bl602/bflb_port_boot2.h +++ b/examples/boot2_isp/port/bl602/bflb_port_boot2.h @@ -36,7 +36,6 @@ #ifndef __BFLB_PORT_BOOT2_H__ #define __BFLB_PORT_BOOT2_H__ -#include "bl602_sflash.h" #include "bl602_glb.h" #define BL_TCM_BASE BL602_TCM_BASE @@ -101,7 +100,7 @@ typedef struct struct __attribute__((packed, aligned(4))) hal_flash_config { uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; + spi_flash_cfg_type cfg; uint32_t crc32; }; diff --git a/examples/boot2_isp/port/bl606p/bflb_port_boot2.c b/examples/boot2_isp/port/bl606p/bflb_port_boot2.c index ef6405c8..a84fcaa3 100644 --- a/examples/boot2_isp/port/bl606p/bflb_port_boot2.c +++ b/examples/boot2_isp/port/bl606p/bflb_port_boot2.c @@ -5,7 +5,6 @@ #include "bl606p_hbn.h" #include "bl606p_glb.h" #include "bl606p_pds.h" -#include "bl606p_xip_sflash.h" #include "bl606p_tzc_sec.h" #include "bflb_gpio.h" #include "softcrc.h" @@ -195,7 +194,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num) LOG_F("r ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg); before_ef = g_efuse_cfg.psram_dqs_cfg; - if ((g_efuse_cfg.psram_dqs_cfg & (0x1000)) && (g_efuse_cfg.psram_dqs_cfg != 0xffff)) { + if (g_efuse_cfg.psram_dqs_cfg != 0xffff) { left_flag = ((g_efuse_cfg.psram_dqs_cfg & (0xf0)) >> 0x4); right_flag = (g_efuse_cfg.psram_dqs_cfg & (0xf)); c_val = ((left_flag + right_flag) >> 0x1); @@ -225,11 +224,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num) c_val = ((left_flag + right_flag) >> 1); g_efuse_cfg.psram_dqs_cfg = (((left_flag << 0x4) | (right_flag)) & (0xff)); - if (bflb_ef_ctrl_get_trim_parity(g_efuse_cfg.psram_dqs_cfg, 11)) { - g_efuse_cfg.psram_dqs_cfg = ((0x1800) | (g_efuse_cfg.psram_dqs_cfg)); - } else { - g_efuse_cfg.psram_dqs_cfg = ((0x1000) | (g_efuse_cfg.psram_dqs_cfg)); - } + LOG_F("c ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg); *psram_dqs_win_num = right_flag - left_flag; if (((*psram_dqs_win_num) <= 4) || ((*psram_dqs_win_num) > 0xf)) { @@ -364,11 +359,11 @@ uint32_t hal_boot2_custom(void *custom_param) ret = hal_boot2_x8_psram_calibration(&psram_dqs_win_num); if (ret == ERROR) { while (1) { - printf("psram:%d\r\n", (int)psram_dqs_win_num); + LOG_F("psram:%d\r\n", (int)psram_dqs_win_num); arch_delay_ms(500); } } - printf("psram:%d \r\n", (int)psram_dqs_win_num); + LOG_F("psram:%d \r\n", (int)psram_dqs_win_num); /* Flush i-cache in case branch prediction logic is wrong when psram is not inited by hal_boot2_custom but cpu has already prefetch psram */ @@ -449,7 +444,7 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) } /* get device info */ - //EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info); + bflb_ef_ctrl_get_device_info((bflb_efuse_device_info_type *)&efuse_cfg->dev_info); /* get chip id */ bflb_efuse_get_chipid(efuse_cfg->chip_id); @@ -858,7 +853,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) *******************************************************************************/ uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) { - uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); + uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0); if (flash_addr >= img_offset) { return BL606P_FLASH_XIP_BASE + (flash_addr - img_offset); } else { diff --git a/examples/boot2_isp/port/bl606p/bflb_port_boot2.h b/examples/boot2_isp/port/bl606p/bflb_port_boot2.h index 7d1c3811..6c2d4b71 100644 --- a/examples/boot2_isp/port/bl606p/bflb_port_boot2.h +++ b/examples/boot2_isp/port/bl606p/bflb_port_boot2.h @@ -36,7 +36,6 @@ #ifndef __BFLB_PORT_BOOT2_H__ #define __BFLB_PORT_BOOT2_H__ -#include "bl606p_sflash.h" #include "bl606p_glb.h" #include "bl606p_pm.h" @@ -167,13 +166,13 @@ typedef struct struct __attribute__((packed, aligned(4))) hal_flash_config { uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; + spi_flash_cfg_type cfg; uint32_t crc32; }; struct hal_psram_config { uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; + spi_flash_cfg_type cfg; uint32_t crc32; }; diff --git a/examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld b/examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld index 2e6b9db0..77f47653 100644 --- a/examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld +++ b/examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld @@ -23,7 +23,7 @@ HeapMinSize = 0x1000; /* 4KB */ PROVIDE(__boot2_pass_param_addr = 0x62047E00);/* 0x62030000+96*1024-512 */ MEMORY { - xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 48K + xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 58K itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 48K dtcm_memory (rx) : ORIGIN = 0x6202C000, LENGTH = 4K nocache_ram_memory (!rx) : ORIGIN = 0x2202D000, LENGTH = 84K diff --git a/examples/boot2_isp/port/bl616/bflb_port_boot2.c b/examples/boot2_isp/port/bl616/bflb_port_boot2.c index 31182e6d..d4c07987 100644 --- a/examples/boot2_isp/port/bl616/bflb_port_boot2.c +++ b/examples/boot2_isp/port/bl616/bflb_port_boot2.c @@ -38,11 +38,11 @@ #include "bl616_ef_ctrl.h" #include "bl616_hbn.h" #include "bl616_glb.h" -#include "bl616_xip_sflash.h" #include "bl616_tzc_sec.h" #include "softcrc.h" #include "bl616_psram.h" #include "bflb_flash.h" +#include "log.h" /****************************************************************************/ /** * @brief init boot2 system clock @@ -228,8 +228,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num) printf("r ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg); #endif before_ef = g_efuse_cfg.psram_dqs_cfg; - if ((g_efuse_cfg.psram_dqs_cfg & (0x1000)) && - (((g_efuse_cfg.psram_dqs_cfg & 0x800) >> 11) == EF_Ctrl_Get_Trim_Parity(g_efuse_cfg.psram_dqs_cfg, 11))) { + if (g_efuse_cfg.psram_dqs_cfg != 0xffff) { left_flag = ((g_efuse_cfg.psram_dqs_cfg & (0xf0)) >> 0x4); right_flag = (g_efuse_cfg.psram_dqs_cfg & (0xf)); c_val = ((left_flag + right_flag) >> 0x1); @@ -263,11 +262,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num) // printf("window: 0x%02x ~ 0x%02x; c_val: 0x%02x; dqs:0x%04x; code num:%d\r\n", left_flag, right_flag, c_val, dqs_val[c_val], (right_flag - left_flag)); g_efuse_cfg.psram_dqs_cfg = (((left_flag << 0x4) | (right_flag)) & (0xff)); - if (EF_Ctrl_Get_Trim_Parity(g_efuse_cfg.psram_dqs_cfg, 11)) { - g_efuse_cfg.psram_dqs_cfg = ((0x1800) | (g_efuse_cfg.psram_dqs_cfg)); - } else { - g_efuse_cfg.psram_dqs_cfg = ((0x1000) | (g_efuse_cfg.psram_dqs_cfg)); - } + #ifdef CONFIG_DEBUG printf("c ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg); /* printf("window: 0x%02x ~ 0x%02x; c_val: 0x%02x; dqs:0x%08x; code num:%d\r\n", left_flag, right_flag, c_val, dqs_val[c_val], (right_flag - left_flag)); */ @@ -282,7 +277,7 @@ static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num) } /* to do write efuse psram dqs delay */ if (!(before_ef & 0x1fff)) { - // EF_Ctrl_Write_Psram_Trim((Efuse_Psram_Trim_Type *)&g_efuse_cfg.psram_dqs_cfg, ENABLE); + bflb_ef_ctrl_write_common_trim(NULL,"psram",g_efuse_cfg.psram_dqs_cfg,1); } } return psram_id; @@ -314,11 +309,11 @@ uint32_t hal_boot2_custom(void *custom_param) __ISB(); if (ret == ERROR) { while (1) { - printf("psram error:%d\r\n", (int)psram_dqs_win_num); + LOG_F("psram error:%d\r\n", (int)psram_dqs_win_num); arch_delay_ms(500); } } - printf("psram suss:%d \r\n", (int)psram_dqs_win_num); + LOG_F("psram suss:%d \r\n", (int)psram_dqs_win_num); } return ret; @@ -790,7 +785,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) *******************************************************************************/ uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) { - uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); + uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0); if (flash_addr >= img_offset) { return BL616_FLASH_XIP_BASE + (flash_addr - img_offset); } else { diff --git a/examples/boot2_isp/port/bl616/bflb_port_boot2.h b/examples/boot2_isp/port/bl616/bflb_port_boot2.h index 809b1eef..b9226339 100644 --- a/examples/boot2_isp/port/bl616/bflb_port_boot2.h +++ b/examples/boot2_isp/port/bl616/bflb_port_boot2.h @@ -36,7 +36,6 @@ #ifndef __BFLB_PORT_BOOT2_H__ #define __BFLB_PORT_BOOT2_H__ -#include "bl616_sflash.h" #include "bl616_glb.h" #include "bl616_common.h" @@ -165,7 +164,7 @@ typedef struct struct __attribute__((packed, aligned(4))) hal_flash_config { uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; + spi_flash_cfg_type cfg; uint32_t crc32; }; diff --git a/examples/boot2_isp/port/bl702/bflb_port_boot2.c b/examples/boot2_isp/port/bl702/bflb_port_boot2.c index e9810c89..100c7019 100644 --- a/examples/boot2_isp/port/bl702/bflb_port_boot2.c +++ b/examples/boot2_isp/port/bl702/bflb_port_boot2.c @@ -3,7 +3,6 @@ #include "bl702_ef_ctrl.h" #include "bl702_hbn.h" #include "bl702_glb.h" -#include "bl702_xip_sflash.h" #include "bflb_gpio.h" #include "softcrc.h" #include "bl702_clock.h" @@ -492,7 +491,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) *******************************************************************************/ uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) { - uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(); + uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0,0); if (flash_addr >= img_offset) { return BL702_FLASH_XIP_BASE + (flash_addr - img_offset); } else { diff --git a/examples/boot2_isp/port/bl702/bflb_port_boot2.h b/examples/boot2_isp/port/bl702/bflb_port_boot2.h index f70d37d8..1f04a302 100644 --- a/examples/boot2_isp/port/bl702/bflb_port_boot2.h +++ b/examples/boot2_isp/port/bl702/bflb_port_boot2.h @@ -40,7 +40,6 @@ extern "C" { #endif -#include "bl702_sflash.h" #include "bl702_glb.h" #define BL_TCM_BASE BL702_TCM_BASE @@ -105,7 +104,7 @@ typedef struct struct __attribute__((packed, aligned(4))) hal_flash_config { uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; + spi_flash_cfg_type cfg; uint32_t crc32; }; diff --git a/examples/boot2_isp/port/bl808/bflb_port_boot2.c b/examples/boot2_isp/port/bl808/bflb_port_boot2.c index f97a2637..d89c01b3 100644 --- a/examples/boot2_isp/port/bl808/bflb_port_boot2.c +++ b/examples/boot2_isp/port/bl808/bflb_port_boot2.c @@ -4,12 +4,12 @@ #include "bl808_ef_cfg.h" #include "bl808_hbn.h" #include "bl808_glb.h" -#include "bl808_xip_sflash.h" #include "bl808_tzc_sec.h" #include "bflb_gpio.h" #include "softcrc.h" #include "bl808_psram_uhs.h" #include "bflb_efuse.h" +#include "bl808_uhs_phy.h" /****************************************************************************/ /** * @brief init clock @@ -38,17 +38,55 @@ void hal_boot2_init_clock(void) *******************************************************************************/ uint32_t hal_boot2_custom(void *custom_param) { + extern uhs_phy_cal_res_struct* uhs_phy_cal_res; + PSRAM_UHS_Cfg_Type psramDefaultCfg = { + 2000, + PSRAM_MEM_SIZE_32MB, + PSRAM_PAGE_SIZE_2KB, + PSRAM_UHS_NORMAL_TEMP, + }; + bflb_efuse_device_info_type chip_info; + //EF_Ctrl_Trim_DCDC_And_LDO(); AON_Trim_USB20_RCAL(); //GLB_Readjust_LDO18IO_Vout(); if (((g_efuse_cfg.dev_info & HAL_BOOT2_PSRAM_INFO_MASK) >> HAL_BOOT2_PSRAM_INFO_POS) != 0) { - GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); - Psram_UHS_x16_Init(2000); - Tzc_Sec_PSRAMA_Access_Release(); + + bflb_ef_ctrl_get_device_info(&chip_info); + if (chip_info.psramInfo == UHS_32MB_PSRAM) { + psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB; + } else if (chip_info.psramInfo == UHS_64MB_PSRAM) { + psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB; + } else { + return 2; + } - /* Flush i-cache in case branch prediction logic is wrong when - psram is not inited by hal_boot2_custom but cpu has already prefetch psram */ - __ISB(); + //init uhs PLL; Must open uhs pll first, and then initialize uhs psram + GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); + //init uhs psram ; + // Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000); + Psram_UHS_x16_Init_Override(&psramDefaultCfg); + Tzc_Sec_PSRAMA_Access_Release(); +#if 0 + // example: 2000Mbps typical cal values + uhs_phy_cal_res->rl = 39; + uhs_phy_cal_res->rdqs = 3; + uhs_phy_cal_res->rdq = 0; + uhs_phy_cal_res->wl = 13; + uhs_phy_cal_res->wdqs = 4; + uhs_phy_cal_res->wdq = 5; + uhs_phy_cal_res->ck = 9; + /* TODO: use uhs psram trim update */ + set_uhs_latency_r(uhs_phy_cal_res->rl); + cfg_dqs_rx(uhs_phy_cal_res->rdqs); + cfg_dq_rx(uhs_phy_cal_res->rdq); + set_uhs_latency_w(uhs_phy_cal_res->wl); + cfg_dq_drv(uhs_phy_cal_res->wdq); + cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1); + cfg_dqs_drv(uhs_phy_cal_res->wdqs); + // set_odt_en(); + mr_read_back(); +#endif } return 0; } @@ -99,9 +137,8 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) efuse_cfg->keep_dbg_port_closed = (uint8_t)(sw_cfg0.keep_dbg_port_closed); efuse_cfg->boot_pin_cfg = (uint8_t)(sw_cfg0.boot_pin_cfg); - /* get device info */ //FixZc - //EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info); - + /* get device info */ + bflb_ef_ctrl_get_device_info((bflb_efuse_device_info_type *)&efuse_cfg->dev_info); /* get chip id */ //EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id); bflb_efuse_get_chipid(efuse_cfg->chip_id); @@ -542,7 +579,7 @@ void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) *******************************************************************************/ uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) { - uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); + uint32_t img_offset = bflb_sf_ctrl_get_flash_image_offset(0, SF_CTRL_FLASH_BANK0); if (flash_addr >= img_offset) { return BL808_FLASH_XIP_BASE + (flash_addr - img_offset); } else { diff --git a/examples/boot2_isp/port/bl808/bflb_port_boot2.h b/examples/boot2_isp/port/bl808/bflb_port_boot2.h index eadb683e..7abd0b2e 100644 --- a/examples/boot2_isp/port/bl808/bflb_port_boot2.h +++ b/examples/boot2_isp/port/bl808/bflb_port_boot2.h @@ -36,7 +36,6 @@ #ifndef __BFLB_PORT_BOOT2_H__ #define __BFLB_PORT_BOOT2_H__ -#include "bl808_sflash.h" #include "bl808_glb.h" #define HAL_PLL_CFG_MAGICCODE "PCFG" @@ -69,6 +68,12 @@ #define HAL_BOOT2_PSRAM_INFO_MASK (0xff0000) #define HAL_BOOT2_PSRAM_INFO_POS (16) +#define WB_4MB_PSRAM (1) +#define UHS_32MB_PSRAM (2) +#define UHS_64MB_PSRAM (3) +#define WB_32MB_PSRAM (4) +#define NONE_UHS_PSRAM (-1) + typedef enum { HAL_REBOOT_AS_BOOTPIN, /*!< reboot as bootpin level */ HAL_REBOOT_FROM_INTERFACE, /*!< reboot from interface, download mode */ @@ -160,7 +165,7 @@ typedef struct struct __attribute__((packed, aligned(4))) hal_flash_config { uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; + spi_flash_cfg_type cfg; uint32_t crc32; }; diff --git a/examples/coremark_v1.01/CMakeLists.txt b/examples/coremark_v1.01/CMakeLists.txt index 89fdf0f5..2b5210e2 100644 --- a/examples/coremark_v1.01/CMakeLists.txt +++ b/examples/coremark_v1.01/CMakeLists.txt @@ -23,11 +23,11 @@ sdk_add_compile_definitions( ) sdk_add_compile_options( - # -O3 + -O3 -falign-functions=2 - # -fno-code-hoisting - # -finline-limit=500 - # -funroll-all-loops + -fno-code-hoisting + -finline-limit=500 + -funroll-all-loops ) project(coremark) diff --git a/examples/coremark_v1.01/README.md b/examples/coremark_v1.01/README.md new file mode 100644 index 00000000..1eeeaaad --- /dev/null +++ b/examples/coremark_v1.01/README.md @@ -0,0 +1,44 @@ +# coremark + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/coremark_v1.01/flash_prog_cfg.ini b/examples/coremark_v1.01/flash_prog_cfg.ini new file mode 100644 index 00000000..7421703a --- /dev/null +++ b/examples/coremark_v1.01/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/coremark*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/coremark_v1.01/proj.conf b/examples/coremark_v1.01/proj.conf index 75cf0407..31d37f40 100644 --- a/examples/coremark_v1.01/proj.conf +++ b/examples/coremark_v1.01/proj.conf @@ -1,2 +1,6 @@ set(CONFIG_VLIBC 0) -set(CONFIG_BFLOG 0) \ No newline at end of file +set(CONFIG_BFLOG 0) + +set(CONFIG_VSNPRINTF_FLOAT 1) +set(CONFIG_VSNPRINTF_FLOAT_EX 1) +set(CONFIG_VSNPRINTF_LONG_LONG 1) \ No newline at end of file diff --git a/examples/fatfs/README.md b/examples/fatfs/README.md new file mode 100644 index 00000000..ff293fe5 --- /dev/null +++ b/examples/fatfs/README.md @@ -0,0 +1,29 @@ +# fatfs + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | Only for M0 CPU | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/fatfs/flash_prog_cfg.ini b/examples/fatfs/flash_prog_cfg.ini new file mode 100644 index 00000000..eb42660e --- /dev/null +++ b/examples/fatfs/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/fatfs_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/freertos/FreeRTOSConfig.h b/examples/freertos/FreeRTOSConfig.h index ed82d3e5..5ef568e9 100644 --- a/examples/freertos/FreeRTOSConfig.h +++ b/examples/freertos/FreeRTOSConfig.h @@ -24,10 +24,8 @@ * * 1 tab == 4 spaces! */ - #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H - /*----------------------------------------------------------- * Application specific definitions. * @@ -39,8 +37,6 @@ * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -#include "stdio.h" - #if defined(BL602) || defined(BL702) || defined(BL702L) #define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) #define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) @@ -53,8 +49,7 @@ #define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) #endif #endif - -// #define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 #define configUSE_TICK_HOOK 0 @@ -73,27 +68,26 @@ #define configCHECK_FOR_STACK_OVERFLOW 2 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_APPLICATION_TASK_TAG 1 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_TICKLESS_IDLE 0 +#define configUSE_POSIX_ERRNO 1 /* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) /* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) -#define configTIMER_QUEUE_LENGTH 4 -#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) - +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) /* Task priorities. Allow these to be overridden. */ #ifndef uartPRIMARY_PRIORITY #define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) #endif - /* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */ #define INCLUDE_vTaskPrioritySet 1 @@ -108,11 +102,13 @@ to exclude the API function. */ #define INCLUDE_xTaskAbortDelay 1 #define INCLUDE_xTaskGetHandle 1 #define INCLUDE_xSemaphoreGetMutexHolder 1 - /* Normal assert() semantics without relying on the provision of an assert.h header file. */ void vApplicationMallocFailedHook(void); void vAssertCalled(void); + +#include + #define configASSERT(x) \ if ((x) == 0) { \ printf("file [%s]\r\n", __FILE__); \ @@ -121,12 +117,9 @@ void vAssertCalled(void); printf("%s\r\n", (const char *)(#x)); \ vAssertCalled(); \ } - #if (configUSE_TICKLESS_IDLE != 0) void vApplicationSleep(uint32_t xExpectedIdleTime); #define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime) #endif - // #define portUSING_MPU_WRAPPERS - -#endif /* FREERTOS_CONFIG_H */ +#endif /* FREERTOS_CONFIG_H */ \ No newline at end of file diff --git a/examples/freertos/README.md b/examples/freertos/README.md new file mode 100644 index 00000000..4a861c15 --- /dev/null +++ b/examples/freertos/README.md @@ -0,0 +1,44 @@ +# freertos + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/freertos/flash_prog_cfg.ini b/examples/freertos/flash_prog_cfg.ini new file mode 100644 index 00000000..ec1deeea --- /dev/null +++ b/examples/freertos/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/freertos_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/freertos/main.c b/examples/freertos/main.c index 93ad0ac7..e13c9298 100644 --- a/examples/freertos/main.c +++ b/examples/freertos/main.c @@ -1,16 +1,14 @@ +#define DBG_TAG "MAIN" + #include "bflb_mtimer.h" #include #include "semphr.h" #include "log.h" #include "board.h" -static uint8_t freertos_heap[configTOTAL_HEAP_SIZE]; - -static HeapRegion_t xHeapRegions[] = { - { (uint8_t *)freertos_heap, 0 }, - { NULL, 0 }, /* Terminates the array. */ - { NULL, 0 } /* Terminates the array. */ -}; +BFLOG_DEFINE_TAG(MAIN, DBG_TAG, true); +#undef BFLOG_TAG +#define BFLOG_TAG BFLOG_GET_TAG(MAIN) static TaskHandle_t consumer_handle; static TaskHandle_t producer_handle; @@ -69,8 +67,6 @@ static void producer_task(void *pvParameters) int main(void) { board_init(); - xHeapRegions[0].xSizeInBytes = configTOTAL_HEAP_SIZE; - vPortDefineHeapRegions(xHeapRegions); configASSERT((configMAX_PRIORITIES > 4)); @@ -88,6 +84,10 @@ int main(void) LOG_I("[OS] Starting producer task...\r\n"); xTaskCreate(producer_task, (char *)"producer_task", 512, NULL, configMAX_PRIORITIES - 3, &producer_handle); +#ifdef CONFIG_BFLOG + log_restart(); +#endif + vTaskStartScheduler(); while (1) { diff --git a/examples/freertos/proj.conf b/examples/freertos/proj.conf index a286c44a..c880e088 100644 --- a/examples/freertos/proj.conf +++ b/examples/freertos/proj.conf @@ -1,3 +1,12 @@ -set(CONFIG_VLIBC 0) -set(CONFIG_BFLOG 0) -set(CONFIG_FREERTOS 1) \ No newline at end of file +set(CONFIG_BFLOG 1) + +set(CONFIG_VSNPRINTF_FLOAT 1) +set(CONFIG_VSNPRINTF_FLOAT_EX 1) +set(CONFIG_VSNPRINTF_LONG_LONG 1) + +set(CONFIG_LOG_DISABLE 0) +set(CONFIG_ASSERT_DISABLE 0) +set(CONFIG_LOG_LEVEL 3) +set(CONFIG_BFLOG_POOL_SIZE 1024) + +set(CONFIG_FREERTOS 1) \ No newline at end of file diff --git a/examples/helloworld/README.md b/examples/helloworld/README.md new file mode 100644 index 00000000..27df441f --- /dev/null +++ b/examples/helloworld/README.md @@ -0,0 +1,44 @@ +# helloworld + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/helloworld/flash_prog_cfg.ini b/examples/helloworld/flash_prog_cfg.ini new file mode 100644 index 00000000..fbc719a3 --- /dev/null +++ b/examples/helloworld/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/helloworld_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/helloworld/main.c b/examples/helloworld/main.c index 638c024e..81616444 100644 --- a/examples/helloworld/main.c +++ b/examples/helloworld/main.c @@ -1,17 +1,26 @@ #include "bflb_mtimer.h" #include "board.h" + +#define DBG_TAG "MAIN" #include "log.h" int main(void) { board_init(); + while (1) { - LOG_F("hello world\r\n"); - LOG_E("hello world\r\n"); - LOG_W("hello world\r\n"); - LOG_I("hello world\r\n"); - LOG_D("hello world\r\n"); - LOG_T("hello world\r\n"); + LOG_F("hello world fatal\r\n"); + LOG_E("hello world error\r\n"); + LOG_W("hello world warning\r\n"); + LOG_I("hello world information\r\n"); + LOG_D("hello world debug\r\n"); + LOG_T("hello world trace\r\n"); + LOG_RF("hello world fatal raw\r\n"); + LOG_RE("hello world error raw\r\n"); + LOG_RW("hello world warning raw\r\n"); + LOG_RI("hello world information raw\r\n"); + LOG_RD("hello world debug raw\r\n"); + LOG_RT("hello world trace raw\r\n"); bflb_mtimer_delay_ms(1000); } } diff --git a/examples/helloworld/proj.conf b/examples/helloworld/proj.conf index 75cf0407..eb155024 100644 --- a/examples/helloworld/proj.conf +++ b/examples/helloworld/proj.conf @@ -1,2 +1,10 @@ -set(CONFIG_VLIBC 0) -set(CONFIG_BFLOG 0) \ No newline at end of file +set(CONFIG_BFLOG 0) + +set(CONFIG_VSNPRINTF_FLOAT 1) +set(CONFIG_VSNPRINTF_FLOAT_EX 1) +set(CONFIG_VSNPRINTF_LONG_LONG 1) + +set(CONFIG_LOG_DISABLE 0) +set(CONFIG_ASSERT_DISABLE 0) +set(CONFIG_LOG_LEVEL 3) +set(CONFIG_BFLOG_POOL_SIZE 1024) \ No newline at end of file diff --git a/examples/littlefs/CMakeLists.txt b/examples/littlefs/CMakeLists.txt new file mode 100644 index 00000000..bad952bd --- /dev/null +++ b/examples/littlefs/CMakeLists.txt @@ -0,0 +1,14 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_add_include_directories(.) +file(GLOB_RECURSE sources "${CMAKE_CURRENT_SOURCE_DIR}/kv_test/*.c") +target_sources(app PRIVATE ${sources}) +sdk_add_link_options(-ucmd_kv_test) + +sdk_set_main_file(main.c) + +project(littlefs) diff --git a/examples/littlefs/FreeRTOSConfig.h b/examples/littlefs/FreeRTOSConfig.h new file mode 100644 index 00000000..bf6fbfa9 --- /dev/null +++ b/examples/littlefs/FreeRTOSConfig.h @@ -0,0 +1,127 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ +#include "stdio.h" + +#ifdef BL702 +#define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS (0xE0000000UL + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS (0xE0000000UL + 0x4000UL) +#endif + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ((uint32_t)(1 * 1000 * 1000)) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES (32) +#define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ +#define configTOTAL_HEAP_SIZE ((size_t)100 * 1024) +#define configMAX_TASK_NAME_LEN (16) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (1024) + +/* Task priorities. Allow these to be overridden. */ +#ifndef uartPRIMARY_PRIORITY +#define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) +#endif + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vApplicationMallocFailedHook(void); +void vAssertCalled(void); +#define configASSERT(x) \ + if ((x) == 0) { \ + printf("file [%s]\r\n", __FILE__); \ + printf("func [%s]\r\n", __FUNCTION__); \ + printf("line [%d]\r\n", __LINE__); \ + printf("%s\r\n", (const char *)(#x)); \ + vAssertCalled(); \ + } + +#if (configUSE_TICKLESS_IDLE != 0) +void vApplicationSleep(uint32_t xExpectedIdleTime); +#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime) +#endif + +// #define portUSING_MPU_WRAPPERS + +#endif /* FREERTOS_CONFIG_H */ diff --git a/examples/bflog/Makefile b/examples/littlefs/Makefile similarity index 100% rename from examples/bflog/Makefile rename to examples/littlefs/Makefile diff --git a/examples/littlefs/README.md b/examples/littlefs/README.md new file mode 100644 index 00000000..b1cb8f9d --- /dev/null +++ b/examples/littlefs/README.md @@ -0,0 +1,44 @@ +# littlefs + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/littlefs/flash_prog_cfg.ini b/examples/littlefs/flash_prog_cfg.ini new file mode 100644 index 00000000..fdf03737 --- /dev/null +++ b/examples/littlefs/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/littlefs_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/littlefs/kv_test/Kconfig b/examples/littlefs/kv_test/Kconfig new file mode 100644 index 00000000..c28ce2f1 --- /dev/null +++ b/examples/littlefs/kv_test/Kconfig @@ -0,0 +1,41 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config EXAMPLES_KV_TEST + tristate "\"kv test!\" example" + default n + ---help--- + Enable the \"kv test!\" example + +if EXAMPLES_KV_TEST + +config EXAMPLES_KV_TEST_PROGNAME + string "Program name" + default "kv_test" + ---help--- + This is the name of the program that will be used when the NSH ELF + program is installed. + +config EXAMPLES_KV_TEST_PRIORITY + int "kv_test task priority" + default 100 + +config EXAMPLES_KV_TEST_STACKSIZE + int "kv_test stack size" + default 4096 + +config KV_TEST_TEST_CASE_NUM + int "kv_test case num" + default 1 + +config KV_TEST_FILE_OPER_SUM + int "kv_test file RW sum" + default 20000 + +config KV_TEST_FILE_OPER_PERIOD + int "kv_test file RW period(ms)" + default 1000 + +endif diff --git a/examples/littlefs/kv_test/arch_crypto.c b/examples/littlefs/kv_test/arch_crypto.c new file mode 100755 index 00000000..5085ee12 --- /dev/null +++ b/examples/littlefs/kv_test/arch_crypto.c @@ -0,0 +1,16 @@ +#include "arch_crypto.h" +#include "arch_dbg.h" + +#include +#include +#include + +void arch_md5(uint8_t *input, int len, uint8_t hash[16]) +{ + mbedtls_md5_context context; + + mbedtls_md5_init(&context); + mbedtls_md5_starts(&context); + mbedtls_md5_update(&context, input, len); + mbedtls_md5_finish(&context, hash); +} diff --git a/examples/littlefs/kv_test/arch_crypto.h b/examples/littlefs/kv_test/arch_crypto.h new file mode 100644 index 00000000..2a3b8ed5 --- /dev/null +++ b/examples/littlefs/kv_test/arch_crypto.h @@ -0,0 +1,8 @@ +#ifndef _ARCH_CRYPTO_H_ +#define _ARCH_CRYPTO_H_ + +#include + +void arch_md5(uint8_t *input, int len, uint8_t hash[16]); + +#endif /* _ARCH_CRYPTO_H_ */ diff --git a/examples/littlefs/kv_test/arch_dbg.h b/examples/littlefs/kv_test/arch_dbg.h new file mode 100755 index 00000000..f3e90318 --- /dev/null +++ b/examples/littlefs/kv_test/arch_dbg.h @@ -0,0 +1,57 @@ + +#ifndef __ARCH_DBG_H__ +#define __ARCH_DBG_H__ + + +#include +#include +#include +#include "arch_time.h" +#include "arch_os.h" + +#include +#ifdef LOG_INFO +#undef LOG_INFO +#endif + +#ifdef LOG_DEBUG +#undef LOG_DEBUG +#endif + +static inline char * arch_printf_time(void) +{ + struct tm *dtime; + int gmt_offset = 0; + time_t cur; + static char time[256]; + + memset(time, 0, sizeof(time)); + cur = arch_os_utc_now(); + dtime = gmtime((const time_t *)&cur); + snprintf(time, sizeof(time), "%02d:%02d:%02d.%03d ", dtime->tm_hour, dtime->tm_min, dtime->tm_sec, arch_os_ms_now() % 1000); + + return time; +} + +#define LOG_INFO_TAG(TAG, _fmt_, ...) \ + do { \ + LOG_I("[%s] %s: " _fmt_ "\r\n", arch_printf_time(), TAG, ##__VA_ARGS__); \ + } while (0) + +#define LOG_WARN_TAG(TAG, _fmt_, ...) \ + do { \ + LOG_W("[%s] %s: (%s,%d)" _fmt_ "\r\n", arch_printf_time(), TAG, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ + } while (0) + +#define LOG_ERROR_TAG(TAG, _fmt_, ...) \ + do { \ + LOG_E("[%s] %s: (%s,%d)" _fmt_ "\r\n", arch_printf_time(), TAG, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ + } while (0) + +#define LOG_DEBUG_TAG(TAG, _fmt_, ...) \ + do { \ + LOG_D("[%s] %s: " _fmt_ "\r\n", arch_printf_time(), TAG, ##__VA_ARGS__); \ + } while (0) + +#endif /* __APPLN_DBG_H__ */ + diff --git a/examples/littlefs/kv_test/arch_os.c b/examples/littlefs/kv_test/arch_os.c new file mode 100644 index 00000000..47d8e011 --- /dev/null +++ b/examples/littlefs/kv_test/arch_os.c @@ -0,0 +1,58 @@ +#include +#include +#include +#include +#include "arch_os.h" + + +/* Mutex */ +static int arch_os_mutex_create_internal(arch_os_mutex_handle_t *phandle, void *attr) +{ + *phandle = xSemaphoreCreateMutex(); + + return 0; +} + +int arch_os_mutex_create(arch_os_mutex_handle_t *phandle) +{ + arch_os_mutex_create_internal(phandle, NULL); + + return 0; +} + +int arch_os_mutex_delete(arch_os_mutex_handle_t handle) +{ + int ret = 9; + if (handle == NULL) + return -1; + + vSemaphoreDelete(handle); + + return ret; +} + +int arch_os_mutex_put(arch_os_mutex_handle_t handle) +{ + if (handle == NULL) + return -1; + + xSemaphoreGive(handle); + return 0; +} + +int arch_os_mutex_get(arch_os_mutex_handle_t handle, uint32_t wait_ms) +{ + xSemaphoreTake(handle, wait_ms); + return 0; +} + +/* Thread */ +int arch_os_thread_create(arch_os_thread_handle_t *pthread, + const char *name, void (*function)(void* arg), + uint32_t stack_size, void* arg, int priority) +{ + int ret = 0; + xTaskCreate(function, name, stack_size, arg, priority, pthread); + + return ret; +} diff --git a/examples/littlefs/kv_test/arch_os.h b/examples/littlefs/kv_test/arch_os.h new file mode 100644 index 00000000..3504237b --- /dev/null +++ b/examples/littlefs/kv_test/arch_os.h @@ -0,0 +1,39 @@ +#ifndef __ARCH_OS_H__ +#define __ARCH_OS_H__ + +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +#include "arch_time.h" + +#ifndef SCHED_NATIVE_PRIORITY_DEFAULT +#define SCHED_NATIVE_PRIORITY_DEFAULT (4) +#endif + +#define ARCH_OS_PRIORITY_DEFAULT SCHED_NATIVE_PRIORITY_DEFAULT +#define ARCH_OS_NATIVE_PRIORITY_DEFAULT SCHED_NATIVE_PRIORITY_DEFAULT + +#define ARCH_OS_WAIT_FOREVER (0xFFFFFFFF) +#define ARCH_OS_NO_WAIT (0) + +typedef SemaphoreHandle_t arch_os_mutex_handle_t; +typedef TaskHandle_t arch_os_thread_handle_t; + +#define ARCH_OS_FUNCTION_RETURN(v) ((void *)(intptr_t)v) + +arch_os_thread_handle_t arch_os_thread_current(void); +int arch_os_thread_create(arch_os_thread_handle_t *pthread, const char *name, + void (*function)(void *), uint32_t stack_size, void *arg, int priority); +int arch_os_thread_delete(arch_os_thread_handle_t thread); +void arch_os_thread_finish(void); + +void arch_os_enter_critical(void); +void arch_os_exit_critical(void); + +int arch_os_mutex_create(arch_os_mutex_handle_t *phandle); +int arch_os_mutex_delete(arch_os_mutex_handle_t handle); +int arch_os_mutex_put(arch_os_mutex_handle_t handle); +int arch_os_mutex_get(arch_os_mutex_handle_t handle, uint32_t wait_ms); + +#endif /* __ARCH_OS_H__ */ diff --git a/examples/littlefs/kv_test/arch_psm.c b/examples/littlefs/kv_test/arch_psm.c new file mode 100644 index 00000000..edc476f6 --- /dev/null +++ b/examples/littlefs/kv_test/arch_psm.c @@ -0,0 +1,136 @@ +#include "lfs.h" + +#include "arch_psm.h" + +extern lfs_t lfs; + +#ifndef CONFIG_KV_PSM_PATH +#define CONFIG_KV_PSM_PATH "" +#endif + +#ifndef CONFIG_KV_PSM_KEY_LEN +#define CONFIG_KV_PSM_KEY_LEN 64 +#endif + +#define PSM_KV_FORMAT "%s/%s.%s" +static uint8_t kvs_crc8(uint8_t *buf, uint16_t len) +{ + uint8_t crc = 0x00; + uint8_t i = 0; + while (len--) { + crc ^= *buf++; + for (i = 8; i > 0; i--) { + if (crc & 0x80) + crc = (crc << 1) ^ 0x31; + else + crc <<= 1; + } + } + return crc; +} + +int arch_psm_get_value(const char *name_space, const char *key, void *value, size_t length) +{ + char name[CONFIG_KV_PSM_KEY_LEN]; + int payload = -1; + uint8_t crc; + int fd, ret; + struct lfs_info info; + lfs_file_t file; + + snprintf(name, CONFIG_KV_PSM_KEY_LEN, PSM_KV_FORMAT, CONFIG_KV_PSM_PATH, name_space, key); + + fd = lfs_file_open(&lfs, &file, name, LFS_O_RDONLY); + if (fd < 0) + return -1; + + ret = lfs_stat(&lfs, name, &info); + if (ret < 0) + goto bail; + + payload = info.size - 1; + + if (payload > length) + goto bail; + + ret = lfs_file_read(&lfs, &file, value, payload); + if (ret != payload) + goto bail; + + ret = lfs_file_read(&lfs, &file, &crc, sizeof(uint8_t)); + if (ret != sizeof(uint8_t)) + goto bail; + + if (crc != kvs_crc8(value, payload)) + ret = -1; + +bail: + lfs_file_close(&lfs, &file); + + return ret > 0 ? payload : ret; +} + +int arch_psm_get_str(const char *name_space, const char *key, char *str, size_t str_size) +{ + return arch_psm_get_value(name_space, key, str, str_size); +} + +int arch_psm_set_value(const char *name_space, const char *key, const void *value, size_t length) +{ + char name[CONFIG_KV_PSM_KEY_LEN]; + uint8_t crc; + int fd, ret, ret_close; + int oflags; + struct lfs_info info; + lfs_file_t file; + + snprintf(name, CONFIG_KV_PSM_KEY_LEN, PSM_KV_FORMAT, CONFIG_KV_PSM_PATH, name_space, key); + + ret = lfs_stat(&lfs, name, &info); + if (ret < 0) { + oflags = LFS_O_RDWR | LFS_O_CREAT; + } else { + oflags = LFS_O_RDWR | LFS_O_TRUNC; + } + + fd = lfs_file_open(&lfs, &file, name, oflags); + if (fd < 0) + return -1; + + ret = lfs_file_write(&lfs, &file, value, length); + if (ret != length) + goto bail; + + crc = kvs_crc8((uint8_t *)value, length); + + ret = lfs_file_write(&lfs, &file, &crc, sizeof(uint8_t)); + +bail: + ret_close = lfs_file_close(&lfs, &file); + if ((ret_close < 0) && (oflags & LFS_O_CREAT)) { + lfs_remove(&lfs, name); + } + + return ret < 0 ? ret : (ret_close < 0 ? ret_close : length); +} + +int arch_psm_set_str(const char *name_space, const char *key, const char *str) +{ + return arch_psm_set_value(name_space, key, str, strlen(str) + 1); +} + +int arch_psm_erase_key(const char *name_space, const char *key) +{ + char name[CONFIG_KV_PSM_KEY_LEN]; + + snprintf(name, CONFIG_KV_PSM_KEY_LEN, PSM_KV_FORMAT, CONFIG_KV_PSM_PATH, name_space, key); + + lfs_remove(&lfs, name); + + return 0; +} + +int arch_psm_del_value(const char *name_space, const char *key) +{ + return arch_psm_erase_key(name_space, key); +} diff --git a/examples/littlefs/kv_test/arch_psm.h b/examples/littlefs/kv_test/arch_psm.h new file mode 100644 index 00000000..e1a94822 --- /dev/null +++ b/examples/littlefs/kv_test/arch_psm.h @@ -0,0 +1,14 @@ +#ifndef __ARCH_PSM_H__ +#define __ARCH_PSM_H__ + + +int arch_psm_init(void); +int arch_psm_get_value(const char* name_space, const char* key, void *value, size_t length); +int arch_psm_set_value(const char* name_space, const char* key, const void* value, size_t length); +int arch_psm_del_value(const char* name_space, const char* key); +int arch_psm_get_str(const char* name_space, const char* key, char *str, size_t str_size); +int arch_psm_set_str(const char* name_space, const char* key, const char* str); +int arch_psm_erase_key(const char* name_space, const char* key); + +#endif /* __ARCH_PSM_H__ */ + diff --git a/examples/littlefs/kv_test/arch_time.c b/examples/littlefs/kv_test/arch_time.c new file mode 100755 index 00000000..be40ecde --- /dev/null +++ b/examples/littlefs/kv_test/arch_time.c @@ -0,0 +1,99 @@ +#include "FreeRTOS.h" + +#include "arch_time.h" + +/* Time */ + +uint64_t arch_os_time_system(void) +{ + uint64_t curr; + + curr = xTaskGetTickCount(); + + return curr; +} + +uint32_t arch_os_ms_now(void) +{ + return (uint32_t)arch_os_time_system(); +} + +uint32_t arch_os_time_now(void) +{ + return arch_os_ms_now() / 1000; +} + +#if 0 +uint32_t arch_os_utc_now(void) +{ + struct timespec ts; + + clock_gettime(CLOCK_REALTIME, &ts); + + return (uint32_t)ts.tv_sec; +} + +int arch_os_utc_set(uint32_t utc) +{ + struct timespec ts; + + ts.tv_sec = utc; + ts.tv_nsec = 0; + + return clock_settime(CLOCK_REALTIME, &ts); +} +#else +/* + utc机制: + 基于time机制 和 utc_offset 本地维持一个utc时钟 + 设置utc 时间将用于校准time + +*/ +static uint32_t utc_offset = 0; + +uint32_t arch_os_utc_now(void) +{ + return utc_offset + arch_os_time_now(); +} + +//通过utc标准时间 校准系统， +//返回系统时间偏移 (正数 表示系统时间快过UTC时间值) +int arch_os_utc_set(uint32_t utc) +{ + int ret = 0; + uint32_t time_now = arch_os_time_now(); + struct timespec ts; + + if (utc_offset != 0) { //非第一次读取标准时间 + + ret = utc_offset + time_now - utc; //本地时间 和 标准时间 差 + + //暂时不调整斜率，保持简单策略 + //arch_os_time_tune(utc - utc_offset); //用标准时间间隔 调整系统时间 + + utc_offset = utc - time_now; //再一次设置标准时间 + } else + utc_offset = utc - time_now; //第一次设置标准时间 + + /* set CLOCK_REALTIME */ + + vTaskStepTick(time_now); + + return ret; +} +#endif + +uint32_t arch_os_ms_elapsed(uint32_t last_ms) +{ + uint32_t now = arch_os_ms_now(); + + if (last_ms < now) + return now - last_ms; + else + return 0xFFFFFFFF - last_ms + now + 1; +} + +void arch_os_ms_sleep(uint32_t ms) +{ + vTaskDelay(ms); +} diff --git a/examples/littlefs/kv_test/arch_time.h b/examples/littlefs/kv_test/arch_time.h new file mode 100644 index 00000000..5b685dd0 --- /dev/null +++ b/examples/littlefs/kv_test/arch_time.h @@ -0,0 +1,14 @@ +#ifndef __ARCH_TIME_H__ +#define __ARCH_TIME_H__ + +#include + +uint32_t arch_os_ms_now(void); +void arch_os_ms_sleep(uint32_t ms); +uint32_t arch_os_ms_elapsed(uint32_t last_ms); +uint32_t arch_os_time_now(void); +uint64_t arch_os_time_system(void); +int arch_os_utc_set(uint32_t utc); +uint32_t arch_os_utc_now(void); + +#endif /* __ARCH_TIME_H__ */ diff --git a/examples/littlefs/kv_test/kv_test.c b/examples/littlefs/kv_test/kv_test.c new file mode 100755 index 00000000..f0d9f837 --- /dev/null +++ b/examples/littlefs/kv_test/kv_test.c @@ -0,0 +1,1076 @@ +#include +#include + +#include "arch_os.h" +#include "arch_psm.h" +#include "arch_dbg.h" +#include "arch_crypto.h" + +#define KV_OK 0 /* There is no error */ +#define KV_ERROR (-1) /* A generic error happens */ + +arch_os_thread_handle_t kv_test_thread; +arch_os_thread_handle_t kv_test_thread2; +arch_os_thread_handle_t kv_test_thread3; +arch_os_thread_handle_t kv_test_thread5; + +static arch_os_mutex_handle_t kv_test_store_mutex; +int kv_num = 0; +unsigned int kv_w_time = 0; +unsigned int kv_w_max_time = 0; +#define KV_TEST_MAX_VALID_NUM CONFIG_KV_TEST_FILE_OPER_SUM +unsigned int kv_test_valid_num = 0; + +#undef KV_LOG_TAG +#define KV_LOG_TAG "kv_test" + +#define KV_MAX_KEY_LEN 64 +#define KV_MAX_VAL_LEN 256 + +#define PSM_MAX_KEY_LEN KV_MAX_KEY_LEN +#define PSM_MAX_VAL_LEN KV_MAX_VAL_LEN + +typedef struct st_kv_key { + uint8_t valid; + uint8_t keep; + uint8_t type; + int valuelen; + char namespace[PSM_MAX_KEY_LEN / 2]; + char key[PSM_MAX_KEY_LEN / 2]; + char hash[16]; +}; + +#define MAX_KEY_NUM 200 +struct st_kv_key store_key[MAX_KEY_NUM]; +#define KV_TEST_CHECK_NUM 60 + +#define KV_TEST_KEEP_KV 10 +char kv_keep[KV_TEST_KEEP_KV + 1] = { + 1, 8, 13, 15, 25, 36, 42, 47, 50, /*52,56,*/ 64 /*,70,75,85,95, 110, 128,147,167*/ +}; //�±꣬��Щ����ɾ����ֻ���޸� + +int kv_sector_erase_num[6] = { 0 }; +static void kv_test_print_value(char *value, int len); +int arch_get_random(uint8_t *output, size_t output_len) +{ + unsigned int random = 0; + int i, offset; + + for (i = 0, offset = 0; i < output_len; i++) { + offset = i & 0x3; + if (offset == 0) + random = rand(); + output[i] = (random >> (offset * 8)) & 0xff; + } + + return output_len; +} + +static int kv_test_get_rand_num(void) +{ + int i; + uint8_t valuestr[5]; + int value = 0; + + arch_get_random(valuestr, 2); + value = valuestr[0] << 8 | valuestr[1]; + //LOG_INFO_TAG(KV_LOG_TAG, "rand num:%d", value); + if (0 == value) { + LOG_INFO_TAG(KV_LOG_TAG, "[%x][%x]", valuestr[0], valuestr[1]); + } + return value; +} + +//ns_len=0 +//key_len = 0 +static void kv_test_create_key(char *namespace, int ns_len, char *key, int key_len) +{ + int i; + int value = 0; + int len; + + if (0 == ns_len) { + value = kv_test_get_rand_num(); + len = value % (PSM_MAX_KEY_LEN / 2); + if (0 == len % 2) + len = value % 10; + if (len == 0) + len = 1; + } else + len = ns_len; + + //LOG_INFO_TAG(KV_LOG_TAG, "namespace len:%d", len); + arch_get_random(namespace, len); + for (i = 0; i < len; i++) { + if (*(namespace + i) < 'a' || *(namespace + i) > 'z') + *(namespace + i) = *(namespace + i) % 26 + 'a'; + } + *(namespace + len) = 0; + if (0 == key_len) { + value = kv_test_get_rand_num(); + len = value % (PSM_MAX_KEY_LEN / 2); + if (0 == len % 2) + len = value % 10; + if (len == 0) + len = 1; + } else + len = key_len; + //LOG_INFO_TAG(KV_LOG_TAG, "key len:%d", len); + arch_get_random(key, len); + for (i = 0; i < len; i++) { + if (*(key + i) < 'a' || *(key + i) > 'z') + *(key + i) = *(key + i) % 26 + 'a'; + } + *(key + len) = 0; +} + +static int kv_test_create_value_len(void) +{ + int value = 0; + + value = kv_test_get_rand_num(); + value %= (PSM_MAX_VAL_LEN); + if ((value % 2) == 0) + value %= 64; + //if(0 == value)value = 16; + //LOG_INFO_TAG(KV_LOG_TAG, " value len:%d", value); + + return value; +} + +//len=0,������� +static int kv_test_create_value(char *value, int len) +{ + int valuelen = 0; + int i; + int ret; + int flag = 0; + + if (0 == len) + valuelen = kv_test_create_value_len(); + else + valuelen = len; + //if(valuelen < 2) + //valuelen = 2; + ret = arch_get_random(value, valuelen); + if (ret != valuelen) { + LOG_ERROR_TAG(KV_LOG_TAG, "rand ret != len"); + } + for (i = 0; i < valuelen; i++) { + if (0 == *(value + i)) { + flag = 1; + *(value + i) = 0x30; + } + } + *(value + i) = 0; + if (flag) { + //printf("------------have zero-----len:%d--------\r\n", valuelen - 1); + //kv_test_print_value(value, valuelen - 1); + } + return valuelen; +} + +static int kv_test_find_invalid(void) +{ + int i; + + for (i = 0; i < MAX_KEY_NUM; i++) { + if (0 == store_key[i].valid) + break; + } + if (i >= MAX_KEY_NUM) { + return KV_ERROR; + } + + return i; +} + +static int kv_test_find_valid(void) +{ + int i; + int total = 0; +#if 0 + + int value = 0; + int valid_num = 0; +#endif + int max_long = 0; + int m_l_index = -1; + static int valid_check_flag = 0; //0ɾ���ģ�1ɾ��С�� +#if 1 //ɾ��valueֵ��� + if (1 == valid_check_flag) { + max_long = KV_MAX_VAL_LEN; + } + for (i = 0; i < MAX_KEY_NUM; i++) { + if (1 == store_key[i].valid && 0 == store_key[i].keep) { + total++; + if (0 == valid_check_flag) { + if (store_key[i].valuelen > max_long) { + max_long = store_key[i].valuelen; + m_l_index = i; + } + } else { + if (store_key[i].valuelen < max_long) { + max_long = store_key[i].valuelen; + m_l_index = i; + } + } + } + } + valid_check_flag = !valid_check_flag; + if (m_l_index >= 0) { + LOG_INFO_TAG(KV_LOG_TAG, "will del[%d]->[%d]: %s.%s, valid:%d, keep:%d,len:%d", total, m_l_index, + store_key[m_l_index].namespace, store_key[m_l_index].key, store_key[m_l_index].valid, + store_key[m_l_index].keep, store_key[m_l_index].valuelen); + return m_l_index; + } else { + LOG_ERROR_TAG(KV_LOG_TAG, "can not find valid kv"); + return KV_ERROR; + } +#else //���ɾ�� + + for (i = 0; i < MAX_KEY_NUM; i++) { + if (1 == store_key[i].valid) + total++; + } + + if (0 == total) { + LOG_ERROR_TAG(KV_LOG_TAG, "total kv:%d ", total); + return KV_ERROR; + } + value = kv_test_get_rand_num(); + + if (total > KV_TEST_KEEP_KV) + value %= (total - KV_TEST_KEEP_KV); + else + value %= 10; + value++; //�ڼ�������1��ʼ + + LOG_INFO_TAG(KV_LOG_TAG, "kv_test_find_valid total:%d, will del: %d", total, value); + + valid_num = 0; + for (i = 0; i < MAX_KEY_NUM; i++) { + if (1 == store_key[i].valid && 0 == store_key[i].keep) { + valid_num++; + if (valid_num == value) + break; + } + } + if (i >= MAX_KEY_NUM) { + LOG_ERROR_TAG(KV_LOG_TAG, "can not find valid kv"); + return KV_ERROR; + } + + LOG_INFO_TAG(KV_LOG_TAG, "will del: %s.%s, valid:%d, keep:%d", store_key[i].namespace, store_key[i].key, + store_key[i].valid, store_key[i].keep); + return i; + +#endif +} + +static int kv_test_find_keep_valid(void) +{ + int i; + + int total = 0; + int value = 0; + int valid_num = 0; + static int check_flag = 0; //0ɾ���ģ�1ɾ��С�� + +#if 1 + valid_num = -1; + if (1 == check_flag) { + value = KV_MAX_VAL_LEN; + } + for (i = 0; i < MAX_KEY_NUM; i++) { + if (1 == store_key[i].valid && 1 == store_key[i].keep) { + total++; + //printf("[%d]value len:%d\r\n",i, store_key[i].valuelen); + if (0 == check_flag) { + if (store_key[i].valuelen > value) { + value = store_key[i].valuelen; + valid_num = i; + } + } else { + if (store_key[i].valuelen < value) { + value = store_key[i].valuelen; + valid_num = i; + } + } + } + } + check_flag = !check_flag; + if (valid_num >= 0) { + LOG_INFO_TAG(KV_LOG_TAG, "will modify[%d]->[%d]: %s.%s, valid:%d, keep:%d, len:%d", total, valid_num, + store_key[valid_num].namespace, store_key[valid_num].key, store_key[valid_num].valid, + store_key[valid_num].keep, store_key[valid_num].valuelen); + return valid_num; + } else { + LOG_ERROR_TAG(KV_LOG_TAG, "can not find valid keep kv"); + return KV_ERROR; + } +#else + value = kv_test_get_rand_num(); + + for (i = 0; i < MAX_KEY_NUM; i++) { + if (1 == store_key[i].valid && 1 == store_key[i].keep) + total++; + } + + if (0 == total) { + LOG_ERROR_TAG(KV_LOG_TAG, "total keep valid kv:%d ", total); + return KV_ERROR; + } + + value %= total; + + value++; //�ڼ�������1��ʼ + + LOG_INFO_TAG(KV_LOG_TAG, "total keep:%d, will modify: %d", total, value); + + valid_num = 0; + for (i = 0; i < MAX_KEY_NUM; i++) { + if (1 == store_key[i].valid && 1 == store_key[i].keep) { + valid_num++; + if (valid_num == value) + break; + } + } + if (i >= MAX_KEY_NUM) { + LOG_ERROR_TAG(KV_LOG_TAG, "can not find valid keep kv"); + return KV_ERROR; + } + LOG_INFO_TAG(KV_LOG_TAG, "will modify: %s.%s, valid:%d, keep:%d", store_key[i].namespace, store_key[i].key, + store_key[i].valid, store_key[i].keep); + return i; +#endif +} + +static void kv_test_save_key(char *namespace, char *key, char *value, int v_len, int type) +{ + int index = MAX_KEY_NUM; + int i; + + for (i = 0; i < MAX_KEY_NUM; i++) { + if (0 == strcmp(namespace, store_key[i].namespace) && 0 == strcmp(key, store_key[i].key)) { + index = i; + break; + } + } + if (MAX_KEY_NUM == index) { + index = kv_test_find_invalid(); + + if (index < 0) { + LOG_INFO_TAG(KV_LOG_TAG, "no invalid space: %d", index); + return; + } + } + + memset(&store_key[index], 0, sizeof(struct st_kv_key)); + store_key[index].valid = 1; + store_key[index].type = type; + strcpy(store_key[index].namespace, namespace); + strcpy(store_key[index].key, key); + store_key[index].valuelen = v_len; + arch_md5(value, v_len, store_key[index].hash); + for (i = 0; i < KV_TEST_KEEP_KV; i++) { + if (kv_keep[i] == index) { + store_key[index].keep = 1; + } + } +} + +static void kv_test_del_key(void) +{ + int index; + int ret; + + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + index = kv_test_find_valid(); + if (index < 0) { + LOG_ERROR_TAG(KV_LOG_TAG, "#########del key find error:%d", index); + arch_os_mutex_put(kv_test_store_mutex); + return; + } + + ret = arch_psm_erase_key(store_key[index].namespace, store_key[index].key); + if (ret != KV_OK) { + LOG_ERROR_TAG(KV_LOG_TAG, "#########erase key error: %d", ret); + arch_os_mutex_put(kv_test_store_mutex); + return; + } else { + char *value; + LOG_ERROR_TAG(KV_LOG_TAG, "del key %s.%s success", store_key[index].namespace, store_key[index].key); + value = malloc(KV_MAX_VAL_LEN); + if (value == NULL) { + LOG_ERROR_TAG(KV_LOG_TAG, "#########malloc error"); + memset(&store_key[index], 0, sizeof(struct st_kv_key)); + arch_os_mutex_put(kv_test_store_mutex); + return; + } + if (store_key[index].type) + ret = arch_psm_get_value(store_key[index].namespace, store_key[index].key, value, KV_MAX_VAL_LEN); + else + ret = arch_psm_get_str(store_key[index].namespace, store_key[index].key, value, KV_MAX_VAL_LEN); + if (ret > 0) { + LOG_ERROR_TAG(KV_LOG_TAG, "#########read ok after erase #############"); + } + free(value); + } + memset(&store_key[index], 0, sizeof(struct st_kv_key)); + arch_os_mutex_put(kv_test_store_mutex); +} + +static void kv_test_del_key1(void) +{ + int index; + int ret; + + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + + for (int index = 0; index < MAX_KEY_NUM; index++) { + if (store_key[index].valid != 1) { + continue; + } + + ret = arch_psm_erase_key(store_key[index].namespace, store_key[index].key); + if (ret != KV_OK) { + LOG_ERROR_TAG(KV_LOG_TAG, "##erase key %s.%s error: %d", store_key[index].namespace, store_key[index].key, + ret); + } + + memset(&store_key[index], 0, sizeof(struct st_kv_key)); + } + + arch_os_mutex_put(kv_test_store_mutex); + return; +} + +static void kv_test_print_value(char *value, int len) +{ + int i; + + for (i = 0; i < len; i++) { + if (i % 32 == 0) + printf("\r\n"); + printf("[%x]", *(value + i)); + } + printf("\r\n"); +} + +static void kv_test_check_result(void) +{ + static int checknum = 1; + int i; + int ret; + char *value; + char hash[20]; + int error_no = 0; + int total_valid = 0; + int total_valid_v_len = 0; + + value = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == value) + return; + if (kv_num / KV_TEST_CHECK_NUM >= checknum) { + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + checknum++; + + for (i = 0; i < MAX_KEY_NUM; i++) { + if (store_key[i].valid) { + total_valid++; + total_valid_v_len += store_key[i].valuelen; + if (store_key[i].type) + ret = arch_psm_get_value(store_key[i].namespace, store_key[i].key, value, PSM_MAX_VAL_LEN); + else + ret = arch_psm_get_str(store_key[i].namespace, store_key[i].key, value, PSM_MAX_VAL_LEN); + if (ret >= 0) { + arch_md5(value, ret, hash); + if (memcmp(hash, store_key[i].hash, 16) != 0) { + error_no++; + + LOG_ERROR_TAG(KV_LOG_TAG, "[%d] %s.%s hash error, write len: %d, read len: %d", i, + store_key[i].namespace, store_key[i].key, store_key[i].valuelen, ret); + //kv_test_print_value(store_key[i].hash, 16); + //kv_test_print_value(value, ret); + //kv_test_print_value(hash, 16); + } + } else { + error_no++; + LOG_ERROR_TAG(KV_LOG_TAG, "[%d] %s.%s read error %d", i, store_key[i].namespace, store_key[i].key, + ret); + } + } + } + { + LOG_INFO_TAG(KV_LOG_TAG, "-----------------------------------------"); + LOG_INFO_TAG(KV_LOG_TAG, "KV test total: %d", kv_num); + LOG_INFO_TAG(KV_LOG_TAG, "KV valid num: %d", total_valid); + LOG_INFO_TAG(KV_LOG_TAG, "KV valid len: %d", total_valid_v_len); + LOG_INFO_TAG(KV_LOG_TAG, "KV Average write time: %d", kv_w_time / KV_TEST_CHECK_NUM); + LOG_INFO_TAG(KV_LOG_TAG, "KV max write time: %d", kv_w_max_time); + kv_w_time = 0; + if (0 == error_no) + LOG_INFO_TAG(KV_LOG_TAG, "^_^ OKAY"); + else + LOG_INFO_TAG(KV_LOG_TAG, "FAIL"); + LOG_INFO_TAG(KV_LOG_TAG, "KV sector erase num:"); + for (i = 0; i < 6; i++) { + printf("[%d] ", kv_sector_erase_num[i]); + } + printf("\r\n"); + LOG_INFO_TAG(KV_LOG_TAG, "========================================="); + } + arch_os_mutex_put(kv_test_store_mutex); + } + free(value); +} + +static void kv_test_check_result1(void) +{ + static int checknum = 1; + int i; + int ret; + char *value; + char hash[20]; + int error_no = 0; + int ok_no = 0; + int total_valid = 0; + int total_valid_v_len = 0; + + value = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == value) + return; + if (kv_num / KV_TEST_CHECK_NUM >= checknum) { + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + checknum++; + + for (i = 0; i < MAX_KEY_NUM; i++) { + if (store_key[i].valid) { + total_valid++; + total_valid_v_len += store_key[i].valuelen; + if (store_key[i].type) + ret = arch_psm_get_value(store_key[i].namespace, store_key[i].key, value, PSM_MAX_VAL_LEN); + else + ret = arch_psm_get_str(store_key[i].namespace, store_key[i].key, value, PSM_MAX_VAL_LEN); + + if (ret >= 0) { + arch_md5(value, ret, hash); + if (memcmp(hash, store_key[i].hash, 16) != 0) { + error_no++; + LOG_ERROR_TAG(KV_LOG_TAG, "[%d] %s.%s hash error, write len: %d, read len: %d, error num: %d", + i, store_key[i].namespace, store_key[i].key, store_key[i].valuelen, ret, + error_no); + } else { + ok_no++; + } + } else { + error_no++; + LOG_ERROR_TAG(KV_LOG_TAG, "[%d] %s.%s read error %d, error num: %d", i, store_key[i].namespace, + store_key[i].key, ret, error_no); + } + } + } + { + LOG_INFO_TAG(KV_LOG_TAG, "-----------------------------------------"); + LOG_INFO_TAG(KV_LOG_TAG, "KV test total: %d", kv_num); + LOG_INFO_TAG(KV_LOG_TAG, "KV valid num: %d, ok num: %d, err no: %d", total_valid, ok_no, error_no); + LOG_INFO_TAG(KV_LOG_TAG, "KV valid len: %d", total_valid_v_len); + LOG_INFO_TAG(KV_LOG_TAG, "KV Average write time: %d", kv_w_time / KV_TEST_CHECK_NUM); + LOG_INFO_TAG(KV_LOG_TAG, "KV max write time: %d", kv_w_max_time); + kv_w_time = 0; + if (0 == error_no) + LOG_INFO_TAG(KV_LOG_TAG, "^_^ OKAY"); + else + LOG_INFO_TAG(KV_LOG_TAG, "FAIL"); + LOG_INFO_TAG(KV_LOG_TAG, "KV sector erase num:"); + for (i = 0; i < 6; i++) { + printf("[%d] ", kv_sector_erase_num[i]); + } + printf("\r\n"); + LOG_INFO_TAG(KV_LOG_TAG, "========================================="); + } + arch_os_mutex_put(kv_test_store_mutex); + kv_test_del_key1(); + } + + free(value); +} + +#if 0 +void kv_test_check_flash_erase(uint32_t addr) +{ + uint32_t offset = 0; + int sector_no; + + offset = addr - FW_PARAM_START_ADDR; + + sector_no = offset/4096; + if(sector_no < 0 || sector_no > 6) + { + LOG_ERROR_TAG(KV_LOG_TAG, "erase addr error: %x", addr); + return; + } + + kv_sector_erase_num[sector_no] ++; +} +#endif + +static void kv_test_proc(void *arg) +{ + int ret; + bool type = 1; + int valuelen = 0; + int error_num = 0; + char kv_namespace[PSM_MAX_KEY_LEN / 2]; + char kv_key[PSM_MAX_KEY_LEN / 2]; + char *kv_value, *kv_value2; + int time; + + kv_value = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value) + return; + + kv_value2 = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value2) { + free(kv_value); + return; + } + + while (1) { + arch_os_ms_sleep(CONFIG_KV_TEST_FILE_OPER_PERIOD); + if (kv_test_valid_num > KV_TEST_MAX_VALID_NUM) + continue; + + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + + kv_test_create_key(kv_namespace, 0, kv_key, 0); + valuelen = kv_test_create_value(kv_value, 0); + type = kv_test_get_rand_num() % 2; + + LOG_INFO_TAG(KV_LOG_TAG, "1 write kv %s.%s, value: %d", kv_namespace, kv_key, valuelen); + time = arch_os_ms_now(); + + if (type) + ret = arch_psm_set_value(kv_namespace, kv_key, kv_value, valuelen); + else + ret = arch_psm_set_str(kv_namespace, kv_key, kv_value); + + if (ret == (type ? valuelen : valuelen + 1)) //write success + { + int time1 = arch_os_ms_elapsed(time); + kv_w_time += time1; + if (time1 > kv_w_max_time) { + kv_w_max_time = time1; + } + kv_test_valid_num++; + LOG_INFO_TAG(KV_LOG_TAG, "1 write kv time:%d", time1); + + kv_test_save_key(kv_namespace, kv_key, kv_value, ret, type); + kv_num++; + + LOG_INFO_TAG(KV_LOG_TAG, "1 write kv success >>>> %d <<<<", kv_num); + arch_os_mutex_put(kv_test_store_mutex); + + // kv_test_check_result(); + kv_test_check_result1(); + } else { + error_num++; + arch_os_mutex_put(kv_test_store_mutex); + LOG_ERROR_TAG(KV_LOG_TAG, "#########1 write kv fail %d", ret); + + if (error_num > 2) { + kv_test_del_key(); + arch_os_ms_sleep(10000); + error_num = 0; + } + } + } +} + +static int kv_test_gen_namespace_len(void) +{ + static int ns_len = 0; + + ns_len++; + if (ns_len >= PSM_MAX_KEY_LEN / 2) + ns_len = 1; + + return ns_len; +} + +static int kv_test_gen_key_len(void) +{ + static int k_len = 0; + + k_len++; + if (k_len >= PSM_MAX_KEY_LEN / 2) + k_len = 1; + + return k_len; +} + +static int kv_test_gen_value_len(void) +{ + static int v_len = 0; +#if 1 + v_len++; + if (v_len > PSM_MAX_VAL_LEN) + v_len = 0; +#else + v_len = KV_MAX_VAL_LEN; +#endif + return v_len; +} + +static void kv_test2_proc(void *arg) +{ + int ret; + bool type = 1; + int valuelen = 0; + int error_num = 0; + int namespace_l = 0; + int key_l = 0; + char kv_namespace[PSM_MAX_KEY_LEN / 2]; + char kv_key[PSM_MAX_KEY_LEN / 2]; + char *kv_value, *kv_value2; + int time; + + kv_value = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value) + return; + + kv_value2 = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value2) { + free(kv_value); + return; + } + + char *value_test = malloc(PSM_MAX_VAL_LEN + 1); + + while (1) { + arch_os_ms_sleep(CONFIG_KV_TEST_FILE_OPER_PERIOD); + if (kv_test_valid_num > KV_TEST_MAX_VALID_NUM) + continue; + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + namespace_l = kv_test_gen_namespace_len(); + key_l = kv_test_gen_key_len(); + kv_test_create_key(kv_namespace, namespace_l, kv_key, key_l); + + valuelen = kv_test_create_value(kv_value, kv_test_gen_value_len()); + type = kv_test_get_rand_num() % 2; + + LOG_INFO_TAG(KV_LOG_TAG, "2 write kv %s.%s, origin len: %d", kv_namespace, kv_key, valuelen); + kv_test_print_value(kv_value, valuelen); + + time = arch_os_ms_now(); + if (type) + ret = arch_psm_set_value(kv_namespace, kv_key, kv_value, valuelen); + else + ret = arch_psm_set_str(kv_namespace, kv_key, kv_value); + if (ret == (type ? valuelen : valuelen + 1)) //write success + { + int time1 = arch_os_ms_elapsed(time); + kv_w_time += time1; + if (time1 > kv_w_max_time) { + kv_w_max_time = time1; + } + kv_test_valid_num++; + LOG_INFO_TAG(KV_LOG_TAG, "2 write kv time:%d", time1); + kv_test_save_key(kv_namespace, kv_key, kv_value, ret, type); + kv_num++; + LOG_INFO_TAG(KV_LOG_TAG, "2 write kv success >>>%d<<<", kv_num); + arch_os_mutex_put(kv_test_store_mutex); + +#if 0 + memset(value_test, 0, PSM_MAX_VAL_LEN+1); + if(type) { + ret = arch_psm_get_value(kv_namespace, kv_key, value_test, PSM_MAX_VAL_LEN); + } else { + ret = arch_psm_get_str(kv_namespace, kv_key, value_test, PSM_MAX_VAL_LEN); + } + kv_test_print_value(value_test, ret); +#endif + // kv_test_check_result(); + kv_test_check_result1(); + } else { + error_num++; + arch_os_mutex_put(kv_test_store_mutex); + LOG_ERROR_TAG(KV_LOG_TAG, "#########2 write kv fail %d, num: %d", ret, error_num); +#if 1 + if (error_num > 2) { + kv_test_del_key(); + arch_os_ms_sleep(10000); + error_num = 0; + } +#endif + } + } +} + +static void kv_test3_proc(void *arg) +{ + int ret; + bool type = 1; + int valuelen = 0; + int index; + char kv_namespace[PSM_MAX_KEY_LEN / 2]; + char kv_key[PSM_MAX_KEY_LEN / 2]; + char *kv_value, *kv_value2; + int time; + + kv_value = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value) + return; + + kv_value2 = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value2) { + free(kv_value); + return; + } + + char *value_test = malloc(PSM_MAX_VAL_LEN + 1); + + while (1) { + arch_os_ms_sleep(1); + index = kv_test_find_keep_valid(); + if (index < 0) { + arch_os_ms_sleep(CONFIG_KV_TEST_FILE_OPER_PERIOD); + continue; + } + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + strcpy(kv_namespace, store_key[index].namespace); + strcpy(kv_key, store_key[index].key); + valuelen = kv_test_create_value(kv_value, 0); + + LOG_INFO_TAG(KV_LOG_TAG, "3 modify kv[%d] %s.%s, value:%d", index, store_key[index].namespace, + store_key[index].key, valuelen); + type = store_key[index].type; + time = arch_os_ms_now(); + if (type) + ret = arch_psm_set_value(kv_namespace, kv_key, kv_value, valuelen); + else + ret = arch_psm_set_str(kv_namespace, kv_key, kv_value); + if (ret == (type ? valuelen : valuelen + 1)) //write success + { + int time1; + time1 = arch_os_ms_elapsed(time); + kv_w_time += time1; + if (time1 > kv_w_max_time) { + kv_w_max_time = time1; + } + LOG_INFO_TAG(KV_LOG_TAG, "3 modify kv time:%d", time1); + if (type) + ret = arch_psm_get_value(kv_namespace, kv_key, kv_value2, PSM_MAX_VAL_LEN); + else + ret = arch_psm_get_str(kv_namespace, kv_key, kv_value2, PSM_MAX_VAL_LEN); + if (0 == memcmp(kv_value, kv_value2, ret)) { + //kv_test_save_key(kv_namespace, kv_key, kv_value, ret, type); + arch_md5(kv_value, ret, store_key[index].hash); + store_key[index].valuelen = ret; + kv_num++; + //kv_test_print_value(store_key[index].hash, 16); + //kv_test_print_value(kv_value, 16); + //kv_test_print_value(kv_value2, 16); + LOG_INFO_TAG(KV_LOG_TAG, "3 modify kv[%d] %s.%s success >>>%d<<<", index, kv_namespace, kv_key, + kv_num); + } else { + LOG_ERROR_TAG(KV_LOG_TAG, "#########3 modify kv fail %d", ret); + kv_test_print_value(kv_value, ret); + kv_test_print_value(kv_value2, ret); + } + + arch_os_mutex_put(kv_test_store_mutex); + // kv_test_check_result(); + kv_test_check_result1(); + } else { + arch_os_mutex_put(kv_test_store_mutex); + LOG_ERROR_TAG(KV_LOG_TAG, "#########3 write kv fail %d will del", ret); + + if (type) + ret = arch_psm_get_value(kv_namespace, kv_key, value_test, PSM_MAX_VAL_LEN); + else + ret = arch_psm_get_str(kv_namespace, kv_key, value_test, PSM_MAX_VAL_LEN); + LOG_ERROR_TAG(KV_LOG_TAG, "write fail value name %s.%s: len: %d", kv_namespace, kv_key, ret); + + kv_test_del_key(); + } + } +} + +static void kv_test4_proc(void *arg) +{ + int ret; + bool type = 1; + int valuelen = 0; + int error_num = 0; + char kv_namespace[PSM_MAX_KEY_LEN / 2]; + char kv_key[PSM_MAX_KEY_LEN / 2]; + char *kv_value, *kv_value2; + int time; + + kv_value = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value) + return; + + kv_value2 = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value2) { + free(kv_value); + return; + } + + while (1) { + arch_os_ms_sleep(600); + if (kv_test_valid_num > KV_TEST_MAX_VALID_NUM) + continue; + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + kv_test_create_key(kv_namespace, 0, kv_key, 0); + valuelen = kv_test_create_value(kv_value, 0); + type = kv_test_get_rand_num() % 2; + + LOG_INFO_TAG(KV_LOG_TAG, "4 write kv %s.%s, value: %d", kv_namespace, kv_key, valuelen); + time = arch_os_ms_now(); + if (type) + ret = arch_psm_set_value(kv_namespace, kv_key, kv_value, valuelen); + else + ret = arch_psm_set_str(kv_namespace, kv_key, kv_value); + if (ret == valuelen) //write success + { + int time1 = arch_os_ms_elapsed(time); + kv_w_time += time1; + if (time1 > kv_w_max_time) { + kv_w_max_time = time1; + } + kv_test_valid_num++; + LOG_INFO_TAG(KV_LOG_TAG, "4 write kv time:%d", time1); + kv_test_save_key(kv_namespace, kv_key, kv_value, ret, type); + kv_num++; + LOG_INFO_TAG(KV_LOG_TAG, "4 write kv success >>>> %d <<<<", kv_num); + arch_os_mutex_put(kv_test_store_mutex); + kv_test_check_result1(); + } else { + error_num++; + arch_os_mutex_put(kv_test_store_mutex); + LOG_ERROR_TAG(KV_LOG_TAG, "#########4 write kv fail %d", ret); + if (error_num > 2) { + kv_test_del_key(); + arch_os_ms_sleep(10000); + error_num = 0; + } + } + } +} + +void kv_test5_proc(void *arg) +{ + int ret; + bool type = 1; + int valuelen = 0; + int error_num = 0; + char kv_namespace[PSM_MAX_KEY_LEN / 2]; + char kv_key[PSM_MAX_KEY_LEN / 2]; + char *kv_value, *kv_value2; + int time; + + kv_value = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value) + return; + + kv_value2 = malloc(PSM_MAX_VAL_LEN + 1); + if (NULL == kv_value2) { + free(kv_value); + return; + } + + while (1) { + arch_os_ms_sleep(CONFIG_KV_TEST_FILE_OPER_PERIOD); + if (kv_test_valid_num > KV_TEST_MAX_VALID_NUM) + continue; + arch_os_mutex_get(kv_test_store_mutex, ARCH_OS_WAIT_FOREVER); + kv_test_create_key(kv_namespace, 0, kv_key, 0); + valuelen = kv_test_create_value(kv_value, 0); + type = 1; + + LOG_INFO_TAG(KV_LOG_TAG, "5 write kv %s.%s, value: %d", kv_namespace, kv_key, valuelen); + time = arch_os_ms_now(); + if (type) + ret = arch_psm_set_value(kv_namespace, kv_key, kv_value, valuelen); + else + ret = arch_psm_set_str(kv_namespace, kv_key, kv_value); + if (ret == (type ? valuelen : valuelen + 1)) //write success + { + int time1 = arch_os_ms_elapsed(time); + kv_w_time += time1; + if (time1 > kv_w_max_time) { + kv_w_max_time = time1; + } + kv_test_valid_num++; + LOG_INFO_TAG(KV_LOG_TAG, "5 write kv time:%d", time1); + kv_test_save_key(kv_namespace, kv_key, kv_value, ret, type); + kv_num++; + LOG_INFO_TAG(KV_LOG_TAG, "5 write kv success >>>> %d <<<<", kv_num); + arch_os_mutex_put(kv_test_store_mutex); + // kv_test_check_result(); + kv_test_check_result1(); + } else { + error_num++; + arch_os_mutex_put(kv_test_store_mutex); + LOG_ERROR_TAG(KV_LOG_TAG, "#########5 write kv fail %d", ret); + if (error_num > 2) { + kv_test_del_key(); + arch_os_ms_sleep(10000); + error_num = 0; + } + } + } + + LOG_ERROR_TAG(KV_LOG_TAG, "%s end\n", __FUNCTION__); +} + +int kv_test(void) +{ + int ret = KV_OK; + memset(&store_key, 0, sizeof(store_key)); + arch_os_mutex_create(&kv_test_store_mutex); + int num = 0; + +#if (CONFIG_KV_TEST_TEST_CASE_NUM == 1) + if (KV_OK != arch_os_thread_create(&kv_test_thread, "kv_t_Task", kv_test_proc, CONFIG_EXAMPLES_KV_TEST_STACKSIZE, + NULL, ARCH_OS_PRIORITY_DEFAULT)) { + LOG_WARN_TAG(KV_LOG_TAG, "kv test thread create failed"); + ret = KV_ERROR; + } +#endif + +#if (CONFIG_KV_TEST_TEST_CASE_NUM == 2) + if (KV_OK != arch_os_thread_create(&kv_test_thread2, "kv_t_Task_2", kv_test2_proc, + CONFIG_EXAMPLES_KV_TEST_STACKSIZE, NULL, ARCH_OS_PRIORITY_DEFAULT)) { + LOG_WARN_TAG(KV_LOG_TAG, "kv test thread2 create failed"); + ret = KV_ERROR; + } +#endif + +#if (CONFIG_KV_TEST_TEST_CASE_NUM == 3) + if (KV_OK != arch_os_thread_create(&kv_test_thread, "kv_t_Task", kv_test_proc, CONFIG_EXAMPLES_KV_TEST_STACKSIZE, + NULL, ARCH_OS_PRIORITY_DEFAULT)) { + LOG_WARN_TAG(KV_LOG_TAG, "kv test thread create failed"); + ret = KV_ERROR; + } + + if (KV_OK != arch_os_thread_create(&kv_test_thread3, "kv_t_Task_3", kv_test3_proc, + CONFIG_EXAMPLES_KV_TEST_STACKSIZE, NULL, ARCH_OS_PRIORITY_DEFAULT)) { + LOG_WARN_TAG(KV_LOG_TAG, "kv test thread3 create failed"); + ret = KV_ERROR; + } +#endif + +#if (CONFIG_KV_TEST_TEST_CASE_NUM == 5) + if (KV_OK != arch_os_thread_create(&kv_test_thread5, "kv_t_Task_5", kv_test5_proc, + CONFIG_EXAMPLES_KV_TEST_STACKSIZE, NULL, ARCH_OS_PRIORITY_DEFAULT)) { + LOG_WARN_TAG(KV_LOG_TAG, "kv test thread5 create failed"); + ret = KV_ERROR; + } +#endif + + return ret; +} diff --git a/examples/littlefs/kv_test/kv_test.h b/examples/littlefs/kv_test/kv_test.h new file mode 100644 index 00000000..1f6481ae --- /dev/null +++ b/examples/littlefs/kv_test/kv_test.h @@ -0,0 +1,7 @@ +#ifndef _KV_TEST_H_ +#define _KV_TEST_H_ + +int kv_test(void); +void kv_test5_proc(void *arg); + +#endif diff --git a/examples/littlefs/kv_test/kv_test_main.c b/examples/littlefs/kv_test/kv_test_main.c new file mode 100644 index 00000000..4ae5353c --- /dev/null +++ b/examples/littlefs/kv_test/kv_test_main.c @@ -0,0 +1,46 @@ +/**************************************************************************** + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "kv_test.h" +#include "shell.h" + +#include "log.h" +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * kv_test_main + ****************************************************************************/ + +void cmd_kv_test(int argc, char **argv) +{ + LOG_I("%s begin\n", __FUNCTION__); + int ret = 0; + int num = 0; + kv_test(); + while (1) { + arch_os_ms_sleep(20000); + num++; + } +} diff --git a/examples/littlefs/kv_test/readme.pdf b/examples/littlefs/kv_test/readme.pdf new file mode 100755 index 00000000..0b09056e Binary files /dev/null and b/examples/littlefs/kv_test/readme.pdf differ diff --git a/examples/littlefs/main.c b/examples/littlefs/main.c new file mode 100644 index 00000000..39fac5ef --- /dev/null +++ b/examples/littlefs/main.c @@ -0,0 +1,141 @@ +/**************************************************************************** + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "FreeRTOS.h" +#include "task.h" +#include "shell.h" + +#include "bflb_mtimer.h" +#include "bflb_flash.h" +#include "bflb_l1c.h" +#include "bflb_uart.h" +#include "board.h" + +#include "log.h" +#include "lfs.h" +#include "lfs_port.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/*!< use memory area after 512k */ +#define LITTLEFS_FLASH_SIZE (0x71000) +#define LITTLEFS_FLASH_BLOCK_SIZE 4096 +#define LITTLEFS_FLASH_BLOCK_COUNT (LITTLEFS_FLASH_SIZE / LITTLEFS_FLASH_BLOCK_SIZE) +#define LITTLEFS_FLASH_BLOCK_CYCLE 500 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct bflb_device_s *uart0; + +lfs_t lfs; +lfs_file_t file; + +/*!< configuration of the filesystem is provided by this struct */ +const struct lfs_config cfg = { + // block device operations + .read = lfs_xip_flash_read, + .prog = lfs_xip_flash_prog, + .erase = lfs_xip_flash_erase, + .sync = lfs_xip_flash_sync, + + // block device configuration + .read_size = 16, + .prog_size = 16, + .lookahead_size = 16, + .cache_size = 16, + + .block_size = LITTLEFS_FLASH_BLOCK_SIZE, + .block_count = LITTLEFS_FLASH_BLOCK_COUNT, + .block_cycles = LITTLEFS_FLASH_BLOCK_CYCLE, +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +extern void shell_init_with_task(struct bflb_device_s *shell); +extern void cmd_kv_test(int argc, char **argv); +SHELL_CMD_EXPORT_ALIAS(cmd_kv_test, kv_test, shell kv test); + +/**************************************************************************** + * Functions + ****************************************************************************/ + +int main(void) +{ + board_init(); + + uart0 = bflb_device_get_by_name("uart0"); + shell_init_with_task(uart0); + + // mount the filesystem + int err = lfs_mount(&lfs, &cfg); + + // reformat if we can't mount the filesystem + // this should only happen on the first boot + if (err) { + LOG_W("try to reformat \r\n"); + err = lfs_format(&lfs, &cfg); + if (err) { + LOG_F("reformat fail\r\n"); + _CALL_ERROR(); + } + + LOG_I("reformat success\r\n"); + err = lfs_mount(&lfs, &cfg); + if (err) { + LOG_F("mount fail\r\n"); + _CALL_ERROR(); + } + } + + LOG_I("mount success\r\n"); + + // read current count + uint32_t boot_count = 0; + lfs_file_open(&lfs, &file, "boot_count", LFS_O_RDWR | LFS_O_CREAT); + lfs_file_read(&lfs, &file, &boot_count, sizeof(boot_count)); + + // update boot count + boot_count += 1; + lfs_file_rewind(&lfs, &file); + lfs_file_write(&lfs, &file, &boot_count, sizeof(boot_count)); + + // remember the storage is not updated until the file is closed successfully + lfs_file_close(&lfs, &file); + + // release any resources we were using + // lfs_unmount(&lfs); + + // print the boot count + printf("boot_count: %d\n", boot_count); + + vTaskStartScheduler(); + + while (1) { + } +} diff --git a/examples/littlefs/proj.conf b/examples/littlefs/proj.conf new file mode 100644 index 00000000..93d8d9db --- /dev/null +++ b/examples/littlefs/proj.conf @@ -0,0 +1,27 @@ +set(CONFIG_VLIBC 1) +set(CONFIG_BFLOG 0) +set(CONFIG_FREERTOS 1) +set(CONFIG_MBEDTLS 1) +set(CONFIG_SHELL 1) + +set(CONFIG_LITTLEFS 1) +set(CONFIG_LITTLEFS_FLASH_ADDRESS 0x378000) + +# Config +## mbedtls +set(CONFIG_MBEDTLS_AES_USE_HW 0) +set(CONFIG_MBEDTLS_BIGNUM_USE_HW 0) +set(CONFIG_MBEDTLS_ECC_USE_HW 0) +set(CONFIG_MBEDTLS_SHA1_USE_HW 0) +set(CONFIG_MBEDTLS_SHA256_USE_HW 0) +set(CONFIG_MBEDTLS_SHA512_USE_HW 0) + +# Define +add_definitions(-DCONFIG_EXAMPLES_KV_TEST_PRIORITY=4) +add_definitions(-DCONFIG_EXAMPLES_KV_TEST_STACKSIZE=4096) +add_definitions(-DCONFIG_KV_TEST_TEST_CASE_NUM=5) +add_definitions(-DCONFIG_KV_TEST_FILE_OPER_SUM=20000) +add_definitions(-DCONFIG_KV_TEST_FILE_OPER_PERIOD=1000) +add_definitions(-DCONFIG_KV_PSM_KEY_LEN=64) +# add_definitions(-DLFS_YES_TRACE) + diff --git a/examples/lua/README.md b/examples/lua/README.md new file mode 100644 index 00000000..2a1fb39a --- /dev/null +++ b/examples/lua/README.md @@ -0,0 +1,44 @@ +# lua + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/lua/flash_prog_cfg.ini b/examples/lua/flash_prog_cfg.ini new file mode 100644 index 00000000..790978a5 --- /dev/null +++ b/examples/lua/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/lua_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/lua/proj.conf b/examples/lua/proj.conf index 5d760d5c..1cb8f082 100644 --- a/examples/lua/proj.conf +++ b/examples/lua/proj.conf @@ -7,4 +7,4 @@ set(CONFIG_LUA 1) set(CONFIG_LUA_LHAL 1) set(CONFIG_BSP_SDH_SDCARD 1) -set(CONFIG_BSP_FATFS_SDH_SDCARD 1) \ No newline at end of file +set(CONFIG_FATFS_SDH_SDCARD 1) \ No newline at end of file diff --git a/examples/lvgl/README.md b/examples/lvgl/README.md new file mode 100644 index 00000000..4120e413 --- /dev/null +++ b/examples/lvgl/README.md @@ -0,0 +1,44 @@ +# lvgl + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/lvgl/flash_prog_cfg.ini b/examples/lvgl/flash_prog_cfg.ini new file mode 100644 index 00000000..f2a4be0b --- /dev/null +++ b/examples/lvgl/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/lvgl_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/lvgl/proj.conf b/examples/lvgl/proj.conf index ddef7bae..7172295b 100644 --- a/examples/lvgl/proj.conf +++ b/examples/lvgl/proj.conf @@ -1,2 +1,3 @@ set(CONFIG_BSP_LCD 1) +set(CONFIG_BSP_TOUCH 1) set(CONFIG_LVGL 1) \ No newline at end of file diff --git a/examples/mbedtls/CMakeLists.txt b/examples/mbedtls/CMakeLists.txt new file mode 100644 index 00000000..3ba965c0 --- /dev/null +++ b/examples/mbedtls/CMakeLists.txt @@ -0,0 +1,11 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_add_include_directories(.) + +sdk_set_main_file(main.c) + +project(mbedtls) diff --git a/examples/mbedtls/Makefile b/examples/mbedtls/Makefile new file mode 100644 index 00000000..34b2f3fa --- /dev/null +++ b/examples/mbedtls/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/mbedtls/README.md b/examples/mbedtls/README.md new file mode 100644 index 00000000..2dfe9f08 --- /dev/null +++ b/examples/mbedtls/README.md @@ -0,0 +1,44 @@ +# mbedtls + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/mbedtls/flash_prog_cfg.ini b/examples/mbedtls/flash_prog_cfg.ini new file mode 100644 index 00000000..634852b5 --- /dev/null +++ b/examples/mbedtls/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/mbedtls_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/mbedtls/main.c b/examples/mbedtls/main.c new file mode 100644 index 00000000..c131b062 --- /dev/null +++ b/examples/mbedtls/main.c @@ -0,0 +1,21 @@ +#include "bflb_mtimer.h" +#include "board.h" +#include "mbedtls/aes.h" +#include "mbedtls/sha1.h" +#include "mbedtls/sha256.h" +#include "mbedtls/sha512.h" + +int main(void) +{ + board_init(); + + mbedtls_aes_self_test(1); + mbedtls_sha1_self_test(1); + mbedtls_sha256_self_test(1); + mbedtls_sha512_self_test(1); + + printf("mbedtls test success\r\n"); + while (1) { + bflb_mtimer_delay_ms(1000); + } +} diff --git a/examples/mbedtls/mbedtls_bflb_config.h b/examples/mbedtls/mbedtls_bflb_config.h new file mode 100644 index 00000000..44c13302 --- /dev/null +++ b/examples/mbedtls/mbedtls_bflb_config.h @@ -0,0 +1,3322 @@ +/** + * \file mbedtls_config.h + * + * \brief Configuration options (set of defines) + * + * This set of compile-time options may be used to enable + * or disable features selectively, and reduce the global + * memory footprint. + */ +/* + * Copyright The Mbed TLS Contributors + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * This is an optional version symbol that enables comatibility handling of + * config files. + * + * It is equal to the #MBEDTLS_VERSION_NUMBER of the Mbed TLS version that + * introduced the config format we want to be compatible with. + */ +//#define MBEDTLS_CONFIG_VERSION 0x03000000 + +/** + * \name SECTION: System support + * + * This section sets system specific settings. + * \{ + */ + +/** + * \def MBEDTLS_HAVE_ASM + * + * The compiler has support for asm(). + * + * Requires support for asm() in compiler. + * + * Used in: + * library/aria.c + * library/bn_mul.h + * + * Required by: + * MBEDTLS_AESNI_C + * MBEDTLS_PADLOCK_C + * + * Comment to disable the use of assembly code. + */ +#define MBEDTLS_HAVE_ASM + +/** + * \def MBEDTLS_NO_UDBL_DIVISION + * + * The platform lacks support for double-width integer division (64-bit + * division on a 32-bit platform, 128-bit division on a 64-bit platform). + * + * Used in: + * include/mbedtls/bignum.h + * library/bignum.c + * + * The bignum code uses double-width division to speed up some operations. + * Double-width division is often implemented in software that needs to + * be linked with the program. The presence of a double-width integer + * type is usually detected automatically through preprocessor macros, + * but the automatic detection cannot know whether the code needs to + * and can be linked with an implementation of division for that type. + * By default division is assumed to be usable if the type is present. + * Uncomment this option to prevent the use of double-width division. + * + * Note that division for the native integer type is always required. + * Furthermore, a 64-bit type is always required even on a 32-bit + * platform, but it need not support multiplication or division. In some + * cases it is also desirable to disable some double-width operations. For + * example, if double-width division is implemented in software, disabling + * it can reduce code size in some embedded targets. + */ +//#define MBEDTLS_NO_UDBL_DIVISION + +/** + * \def MBEDTLS_NO_64BIT_MULTIPLICATION + * + * The platform lacks support for 32x32 -> 64-bit multiplication. + * + * Used in: + * library/poly1305.c + * + * Some parts of the library may use multiplication of two unsigned 32-bit + * operands with a 64-bit result in order to speed up computations. On some + * platforms, this is not available in hardware and has to be implemented in + * software, usually in a library provided by the toolchain. + * + * Sometimes it is not desirable to have to link to that library. This option + * removes the dependency of that library on platforms that lack a hardware + * 64-bit multiplier by embedding a software implementation in Mbed TLS. + * + * Note that depending on the compiler, this may decrease performance compared + * to using the library function provided by the toolchain. + */ +//#define MBEDTLS_NO_64BIT_MULTIPLICATION + +/** + * \def MBEDTLS_HAVE_SSE2 + * + * CPU supports SSE2 instruction set. + * + * Uncomment if the CPU supports SSE2 (IA-32 specific). + */ +//#define MBEDTLS_HAVE_SSE2 + +/** + * \def MBEDTLS_HAVE_TIME + * + * System has time.h and time(). + * The time does not need to be correct, only time differences are used, + * by contrast with MBEDTLS_HAVE_TIME_DATE + * + * Defining MBEDTLS_HAVE_TIME allows you to specify MBEDTLS_PLATFORM_TIME_ALT, + * MBEDTLS_PLATFORM_TIME_MACRO, MBEDTLS_PLATFORM_TIME_TYPE_MACRO and + * MBEDTLS_PLATFORM_STD_TIME. + * + * Comment if your system does not support time functions + */ +#define MBEDTLS_HAVE_TIME + +/** + * \def MBEDTLS_HAVE_TIME_DATE + * + * System has time.h, time(), and an implementation for + * mbedtls_platform_gmtime_r() (see below). + * The time needs to be correct (not necessarily very accurate, but at least + * the date should be correct). This is used to verify the validity period of + * X.509 certificates. + * + * Comment if your system does not have a correct clock. + * + * \note mbedtls_platform_gmtime_r() is an abstraction in platform_util.h that + * behaves similarly to the gmtime_r() function from the C standard. Refer to + * the documentation for mbedtls_platform_gmtime_r() for more information. + * + * \note It is possible to configure an implementation for + * mbedtls_platform_gmtime_r() at compile-time by using the macro + * MBEDTLS_PLATFORM_GMTIME_R_ALT. + */ +#define MBEDTLS_HAVE_TIME_DATE + +/** + * \def MBEDTLS_PLATFORM_MEMORY + * + * Enable the memory allocation layer. + * + * By default mbed TLS uses the system-provided calloc() and free(). + * This allows different allocators (self-implemented or provided) to be + * provided to the platform abstraction layer. + * + * Enabling MBEDTLS_PLATFORM_MEMORY without the + * MBEDTLS_PLATFORM_{FREE,CALLOC}_MACROs will provide + * "mbedtls_platform_set_calloc_free()" allowing you to set an alternative calloc() and + * free() function pointer at runtime. + * + * Enabling MBEDTLS_PLATFORM_MEMORY and specifying + * MBEDTLS_PLATFORM_{CALLOC,FREE}_MACROs will allow you to specify the + * alternate function at compile time. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Enable this layer to allow use of alternative memory allocators. + */ +//#define MBEDTLS_PLATFORM_MEMORY + +/** + * \def MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + * + * Do not assign standard functions in the platform layer (e.g. calloc() to + * MBEDTLS_PLATFORM_STD_CALLOC and printf() to MBEDTLS_PLATFORM_STD_PRINTF) + * + * This makes sure there are no linking errors on platforms that do not support + * these functions. You will HAVE to provide alternatives, either at runtime + * via the platform_set_xxx() functions or at compile time by setting + * the MBEDTLS_PLATFORM_STD_XXX defines, or enabling a + * MBEDTLS_PLATFORM_XXX_MACRO. + * + * Requires: MBEDTLS_PLATFORM_C + * + * Uncomment to prevent default assignment of standard functions in the + * platform layer. + */ +//#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS + +/** + * \def MBEDTLS_PLATFORM_EXIT_ALT + * + * MBEDTLS_PLATFORM_XXX_ALT: Uncomment a macro to let mbed TLS support the + * function in the platform abstraction layer. + * + * Example: In case you uncomment MBEDTLS_PLATFORM_PRINTF_ALT, mbed TLS will + * provide a function "mbedtls_platform_set_printf()" that allows you to set an + * alternative printf function pointer. + * + * All these define require MBEDTLS_PLATFORM_C to be defined! + * + * \note MBEDTLS_PLATFORM_SNPRINTF_ALT is required on Windows; + * it will be enabled automatically by check_config.h + * + * \warning MBEDTLS_PLATFORM_XXX_ALT cannot be defined at the same time as + * MBEDTLS_PLATFORM_XXX_MACRO! + * + * Requires: MBEDTLS_PLATFORM_TIME_ALT requires MBEDTLS_HAVE_TIME + * + * Uncomment a macro to enable alternate implementation of specific base + * platform function + */ +//#define MBEDTLS_PLATFORM_EXIT_ALT +//#define MBEDTLS_PLATFORM_TIME_ALT +//#define MBEDTLS_PLATFORM_FPRINTF_ALT +//#define MBEDTLS_PLATFORM_PRINTF_ALT +//#define MBEDTLS_PLATFORM_SNPRINTF_ALT +//#define MBEDTLS_PLATFORM_VSNPRINTF_ALT +//#define MBEDTLS_PLATFORM_NV_SEED_ALT +//#define MBEDTLS_PLATFORM_SETUP_TEARDOWN_ALT + +/** + * \def MBEDTLS_DEPRECATED_WARNING + * + * Mark deprecated functions and features so that they generate a warning if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. + * + * This only works with GCC and Clang. With other compilers, you may want to + * use MBEDTLS_DEPRECATED_REMOVED + * + * Uncomment to get warnings on using deprecated functions and features. + */ +//#define MBEDTLS_DEPRECATED_WARNING + +/** + * \def MBEDTLS_DEPRECATED_REMOVED + * + * Remove deprecated functions and features so that they generate an error if + * used. Functionality deprecated in one version will usually be removed in the + * next version. You can enable this to help you prepare the transition to a + * new major version by making sure your code is not using this functionality. + * + * Uncomment to get errors on using deprecated functions and features. + */ +//#define MBEDTLS_DEPRECATED_REMOVED + +/* \} name SECTION: System support */ + +/** + * \name SECTION: mbed TLS feature support + * + * This section sets support for features that are or are not needed + * within the modules that are enabled. + * \{ + */ + +/** + * \def MBEDTLS_TIMING_ALT + * + * Uncomment to provide your own alternate implementation for + * mbedtls_timing_get_timer(), mbedtls_set_alarm(), mbedtls_set/get_delay() + * + * Only works if you have MBEDTLS_TIMING_C enabled. + * + * You will need to provide a header "timing_alt.h" and an implementation at + * compile time. + */ +//#define MBEDTLS_TIMING_ALT + +/** + * \def MBEDTLS_AES_ALT + * + * MBEDTLS__MODULE_NAME__ALT: Uncomment a macro to let mbed TLS use your + * alternate core implementation of a symmetric crypto, an arithmetic or hash + * module (e.g. platform specific assembly optimized implementations). Keep + * in mind that the function prototypes should remain the same. + * + * This replaces the whole module. If you only want to replace one of the + * functions, use one of the MBEDTLS__FUNCTION_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_AES_ALT, mbed TLS will no longer + * provide the "struct mbedtls_aes_context" definition and omit the base + * function declarations and implementations. "aes_alt.h" will be included from + * "aes.h" to include the new function definitions. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * module. + * + * \warning MD5, DES and SHA-1 are considered weak and their + * use constitutes a security risk. If possible, we recommend + * avoiding dependencies on them, and considering stronger message + * digests and ciphers instead. + * + */ +//#define MBEDTLS_AES_ALT +//#define MBEDTLS_ARIA_ALT +//#define MBEDTLS_CAMELLIA_ALT +//#define MBEDTLS_CCM_ALT +//#define MBEDTLS_CHACHA20_ALT +//#define MBEDTLS_CHACHAPOLY_ALT +//#define MBEDTLS_CMAC_ALT +//#define MBEDTLS_DES_ALT +//#define MBEDTLS_DHM_ALT +//#define MBEDTLS_ECJPAKE_ALT +//#define MBEDTLS_GCM_ALT +//#define MBEDTLS_NIST_KW_ALT +//#define MBEDTLS_MD5_ALT +//#define MBEDTLS_POLY1305_ALT +//#define MBEDTLS_RIPEMD160_ALT +//#define MBEDTLS_RSA_ALT +//#define MBEDTLS_SHA1_ALT +//#define MBEDTLS_SHA256_ALT +//#define MBEDTLS_SHA512_ALT + +/* + * When replacing the elliptic curve module, pleace consider, that it is + * implemented with two .c files: + * - ecp.c + * - ecp_curves.c + * You can replace them very much like all the other MBEDTLS__MODULE_NAME__ALT + * macros as described above. The only difference is that you have to make sure + * that you provide functionality for both .c files. + */ +//#define MBEDTLS_ECP_ALT + +/** + * \def MBEDTLS_SHA256_PROCESS_ALT + * + * MBEDTLS__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use you + * alternate core implementation of symmetric crypto or hash function. Keep in + * mind that function prototypes should remain the same. + * + * This replaces only one function. The header file from mbed TLS is still + * used, in contrast to the MBEDTLS__MODULE_NAME__ALT flags. + * + * Example: In case you uncomment MBEDTLS_SHA256_PROCESS_ALT, mbed TLS will + * no longer provide the mbedtls_sha1_process() function, but it will still provide + * the other function (using your mbedtls_sha1_process() function) and the definition + * of mbedtls_sha1_context, so your implementation of mbedtls_sha1_process must be compatible + * with this definition. + * + * \note If you use the AES_xxx_ALT macros, then it is recommended to also set + * MBEDTLS_AES_ROM_TABLES in order to help the linker garbage-collect the AES + * tables. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + * + * \warning MD5, DES and SHA-1 are considered weak and their use + * constitutes a security risk. If possible, we recommend avoiding + * dependencies on them, and considering stronger message digests + * and ciphers instead. + * + * \warning If both MBEDTLS_ECDSA_SIGN_ALT and MBEDTLS_ECDSA_DETERMINISTIC are + * enabled, then the deterministic ECDH signature functions pass the + * the static HMAC-DRBG as RNG to mbedtls_ecdsa_sign(). Therefore + * alternative implementations should use the RNG only for generating + * the ephemeral key and nothing else. If this is not possible, then + * MBEDTLS_ECDSA_DETERMINISTIC should be disabled and an alternative + * implementation should be provided for mbedtls_ecdsa_sign_det_ext(). + * + */ +//#define MBEDTLS_MD5_PROCESS_ALT +//#define MBEDTLS_RIPEMD160_PROCESS_ALT +//#define MBEDTLS_SHA1_PROCESS_ALT +//#define MBEDTLS_SHA256_PROCESS_ALT +//#define MBEDTLS_SHA512_PROCESS_ALT +//#define MBEDTLS_DES_SETKEY_ALT +//#define MBEDTLS_DES_CRYPT_ECB_ALT +//#define MBEDTLS_DES3_CRYPT_ECB_ALT +//#define MBEDTLS_AES_SETKEY_ENC_ALT +//#define MBEDTLS_AES_SETKEY_DEC_ALT +//#define MBEDTLS_AES_ENCRYPT_ALT +//#define MBEDTLS_AES_DECRYPT_ALT +//#define MBEDTLS_ECDH_GEN_PUBLIC_ALT +//#define MBEDTLS_ECDH_COMPUTE_SHARED_ALT +//#define MBEDTLS_ECDSA_VERIFY_ALT +//#define MBEDTLS_ECDSA_SIGN_ALT +//#define MBEDTLS_ECDSA_GENKEY_ALT + +/** + * \def MBEDTLS_ECP_INTERNAL_ALT + * + * Expose a part of the internal interface of the Elliptic Curve Point module. + * + * MBEDTLS_ECP__FUNCTION_NAME__ALT: Uncomment a macro to let mbed TLS use your + * alternative core implementation of elliptic curve arithmetic. Keep in mind + * that function prototypes should remain the same. + * + * This partially replaces one function. The header file from mbed TLS is still + * used, in contrast to the MBEDTLS_ECP_ALT flag. The original implementation + * is still present and it is used for group structures not supported by the + * alternative. + * + * The original implementation can in addition be removed by setting the + * MBEDTLS_ECP_NO_FALLBACK option, in which case any function for which the + * corresponding MBEDTLS_ECP__FUNCTION_NAME__ALT macro is defined will not be + * able to fallback to curves not supported by the alternative implementation. + * + * Any of these options become available by defining MBEDTLS_ECP_INTERNAL_ALT + * and implementing the following functions: + * unsigned char mbedtls_internal_ecp_grp_capable( + * const mbedtls_ecp_group *grp ) + * int mbedtls_internal_ecp_init( const mbedtls_ecp_group *grp ) + * void mbedtls_internal_ecp_free( const mbedtls_ecp_group *grp ) + * The mbedtls_internal_ecp_grp_capable function should return 1 if the + * replacement functions implement arithmetic for the given group and 0 + * otherwise. + * The functions mbedtls_internal_ecp_init and mbedtls_internal_ecp_free are + * called before and after each point operation and provide an opportunity to + * implement optimized set up and tear down instructions. + * + * Example: In case you set MBEDTLS_ECP_INTERNAL_ALT and + * MBEDTLS_ECP_DOUBLE_JAC_ALT, mbed TLS will still provide the ecp_double_jac() + * function, but will use your mbedtls_internal_ecp_double_jac() if the group + * for the operation is supported by your implementation (i.e. your + * mbedtls_internal_ecp_grp_capable() function returns 1 for this group). If the + * group is not supported by your implementation, then the original mbed TLS + * implementation of ecp_double_jac() is used instead, unless this fallback + * behaviour is disabled by setting MBEDTLS_ECP_NO_FALLBACK (in which case + * ecp_double_jac() will return MBEDTLS_ERR_ECP_FEATURE_UNAVAILABLE). + * + * The function prototypes and the definition of mbedtls_ecp_group and + * mbedtls_ecp_point will not change based on MBEDTLS_ECP_INTERNAL_ALT, so your + * implementation of mbedtls_internal_ecp__function_name__ must be compatible + * with their definitions. + * + * Uncomment a macro to enable alternate implementation of the corresponding + * function. + */ +/* Required for all the functions in this section */ +//#define MBEDTLS_ECP_INTERNAL_ALT +/* Turn off software fallback for curves not supported in hardware */ +//#define MBEDTLS_ECP_NO_FALLBACK +/* Support for Weierstrass curves with Jacobi representation */ +//#define MBEDTLS_ECP_RANDOMIZE_JAC_ALT +//#define MBEDTLS_ECP_ADD_MIXED_ALT +//#define MBEDTLS_ECP_DOUBLE_JAC_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_MANY_ALT +//#define MBEDTLS_ECP_NORMALIZE_JAC_ALT +/* Support for curves with Montgomery arithmetic */ +//#define MBEDTLS_ECP_DOUBLE_ADD_MXZ_ALT +//#define MBEDTLS_ECP_RANDOMIZE_MXZ_ALT +//#define MBEDTLS_ECP_NORMALIZE_MXZ_ALT + +/** + * \def MBEDTLS_ENTROPY_HARDWARE_ALT + * + * Uncomment this macro to let mbed TLS use your own implementation of a + * hardware entropy collector. + * + * Your function must be called \c mbedtls_hardware_poll(), have the same + * prototype as declared in library/entropy_poll.h, and accept NULL as first + * argument. + * + * Uncomment to use your own hardware entropy collector. + */ +//#define MBEDTLS_ENTROPY_HARDWARE_ALT + +/** + * \def MBEDTLS_AES_ROM_TABLES + * + * Use precomputed AES tables stored in ROM. + * + * Uncomment this macro to use precomputed AES tables stored in ROM. + * Comment this macro to generate AES tables in RAM at runtime. + * + * Tradeoff: Using precomputed ROM tables reduces RAM usage by ~8kb + * (or ~2kb if \c MBEDTLS_AES_FEWER_TABLES is used) and reduces the + * initialization time before the first AES operation can be performed. + * It comes at the cost of additional ~8kb ROM use (resp. ~2kb if \c + * MBEDTLS_AES_FEWER_TABLES below is used), and potentially degraded + * performance if ROM access is slower than RAM access. + * + * This option is independent of \c MBEDTLS_AES_FEWER_TABLES. + * + */ +//#define MBEDTLS_AES_ROM_TABLES + +/** + * \def MBEDTLS_AES_FEWER_TABLES + * + * Use less ROM/RAM for AES tables. + * + * Uncommenting this macro omits 75% of the AES tables from + * ROM / RAM (depending on the value of \c MBEDTLS_AES_ROM_TABLES) + * by computing their values on the fly during operations + * (the tables are entry-wise rotations of one another). + * + * Tradeoff: Uncommenting this reduces the RAM / ROM footprint + * by ~6kb but at the cost of more arithmetic operations during + * runtime. Specifically, one has to compare 4 accesses within + * different tables to 4 accesses with additional arithmetic + * operations within the same table. The performance gain/loss + * depends on the system and memory details. + * + * This option is independent of \c MBEDTLS_AES_ROM_TABLES. + * + */ +//#define MBEDTLS_AES_FEWER_TABLES + +/** + * \def MBEDTLS_CAMELLIA_SMALL_MEMORY + * + * Use less ROM for the Camellia implementation (saves about 768 bytes). + * + * Uncomment this macro to use less memory for Camellia. + */ +//#define MBEDTLS_CAMELLIA_SMALL_MEMORY + +/** + * \def MBEDTLS_CHECK_RETURN_WARNING + * + * If this macro is defined, emit a compile-time warning if application code + * calls a function without checking its return value, but the return value + * should generally be checked in portable applications. + * + * This is only supported on platforms where #MBEDTLS_CHECK_RETURN is + * implemented. Otherwise this option has no effect. + * + * Uncomment to get warnings on using fallible functions without checking + * their return value. + * + * \note This feature is a work in progress. + * Warnings will be added to more functions in the future. + * + * \note A few functions are considered critical, and ignoring the return + * value of these functions will trigger a warning even if this + * macro is not defined. To completely disable return value check + * warnings, define #MBEDTLS_CHECK_RETURN with an empty expansion. + */ +//#define MBEDTLS_CHECK_RETURN_WARNING + +/** + * \def MBEDTLS_CIPHER_MODE_CBC + * + * Enable Cipher Block Chaining mode (CBC) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CBC + +/** + * \def MBEDTLS_CIPHER_MODE_CFB + * + * Enable Cipher Feedback mode (CFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CFB + +/** + * \def MBEDTLS_CIPHER_MODE_CTR + * + * Enable Counter Block Cipher mode (CTR) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_CTR + +/** + * \def MBEDTLS_CIPHER_MODE_OFB + * + * Enable Output Feedback mode (OFB) for symmetric ciphers. + */ +#define MBEDTLS_CIPHER_MODE_OFB + +/** + * \def MBEDTLS_CIPHER_MODE_XTS + * + * Enable Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES. + */ +#define MBEDTLS_CIPHER_MODE_XTS + +/** + * \def MBEDTLS_CIPHER_NULL_CIPHER + * + * Enable NULL cipher. + * Warning: Only do so when you know what you are doing. This allows for + * encryption or channels without any security! + * + * To enable the following ciphersuites: + * MBEDTLS_TLS_ECDH_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_WITH_NULL_SHA + * MBEDTLS_TLS_RSA_WITH_NULL_MD5 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_NULL_SHA + * MBEDTLS_TLS_PSK_WITH_NULL_SHA384 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA256 + * MBEDTLS_TLS_PSK_WITH_NULL_SHA + * + * Uncomment this macro to enable the NULL cipher and ciphersuites + */ +//#define MBEDTLS_CIPHER_NULL_CIPHER + +/** + * \def MBEDTLS_CIPHER_PADDING_PKCS7 + * + * MBEDTLS_CIPHER_PADDING_XXX: Uncomment or comment macros to add support for + * specific padding modes in the cipher layer with cipher modes that support + * padding (e.g. CBC) + * + * If you disable all padding modes, only full blocks can be used with CBC. + * + * Enable padding modes in the cipher layer. + */ +#define MBEDTLS_CIPHER_PADDING_PKCS7 +#define MBEDTLS_CIPHER_PADDING_ONE_AND_ZEROS +#define MBEDTLS_CIPHER_PADDING_ZEROS_AND_LEN +#define MBEDTLS_CIPHER_PADDING_ZEROS + +/** \def MBEDTLS_CTR_DRBG_USE_128_BIT_KEY + * + * Uncomment this macro to use a 128-bit key in the CTR_DRBG module. + * By default, CTR_DRBG uses a 256-bit key. + */ +//#define MBEDTLS_CTR_DRBG_USE_128_BIT_KEY + +/** + * \def MBEDTLS_ECP_DP_SECP192R1_ENABLED + * + * MBEDTLS_ECP_XXXX_ENABLED: Enables specific curves within the Elliptic Curve + * module. By default all supported curves are enabled. + * + * Comment macros to disable the curve and functions for it + */ +/* Short Weierstrass curves (supporting ECP, ECDH, ECDSA) */ +#define MBEDTLS_ECP_DP_SECP192R1_ENABLED +#define MBEDTLS_ECP_DP_SECP224R1_ENABLED +#define MBEDTLS_ECP_DP_SECP256R1_ENABLED +#define MBEDTLS_ECP_DP_SECP384R1_ENABLED +#define MBEDTLS_ECP_DP_SECP521R1_ENABLED +#define MBEDTLS_ECP_DP_SECP192K1_ENABLED +#define MBEDTLS_ECP_DP_SECP224K1_ENABLED +#define MBEDTLS_ECP_DP_SECP256K1_ENABLED +#define MBEDTLS_ECP_DP_BP256R1_ENABLED +#define MBEDTLS_ECP_DP_BP384R1_ENABLED +#define MBEDTLS_ECP_DP_BP512R1_ENABLED +/* Montgomery curves (supporting ECP) */ +#define MBEDTLS_ECP_DP_CURVE25519_ENABLED +#define MBEDTLS_ECP_DP_CURVE448_ENABLED + +/** + * \def MBEDTLS_ECP_NIST_OPTIM + * + * Enable specific 'modulo p' routines for each NIST prime. + * Depending on the prime and architecture, makes operations 4 to 8 times + * faster on the corresponding curve. + * + * Comment this macro to disable NIST curves optimisation. + */ +#define MBEDTLS_ECP_NIST_OPTIM + +/** + * \def MBEDTLS_ECP_RESTARTABLE + * + * Enable "non-blocking" ECC operations that can return early and be resumed. + * + * This allows various functions to pause by returning + * #MBEDTLS_ERR_ECP_IN_PROGRESS (or, for functions in the SSL module, + * #MBEDTLS_ERR_SSL_CRYPTO_IN_PROGRESS) and then be called later again in + * order to further progress and eventually complete their operation. This is + * controlled through mbedtls_ecp_set_max_ops() which limits the maximum + * number of ECC operations a function may perform before pausing; see + * mbedtls_ecp_set_max_ops() for more information. + * + * This is useful in non-threaded environments if you want to avoid blocking + * for too long on ECC (and, hence, X.509 or SSL/TLS) operations. + * + * Uncomment this macro to enable restartable ECC computations. + * + * \note This option only works with the default software implementation of + * elliptic curve functionality. It is incompatible with + * MBEDTLS_ECP_ALT, MBEDTLS_ECDH_XXX_ALT, MBEDTLS_ECDSA_XXX_ALT. + */ +//#define MBEDTLS_ECP_RESTARTABLE + +/** + * \def MBEDTLS_ECDSA_DETERMINISTIC + * + * Enable deterministic ECDSA (RFC 6979). + * Standard ECDSA is "fragile" in the sense that lack of entropy when signing + * may result in a compromise of the long-term signing key. This is avoided by + * the deterministic variant. + * + * Requires: MBEDTLS_HMAC_DRBG_C, MBEDTLS_ECDSA_C + * + * Comment this macro to disable deterministic ECDSA. + */ +#define MBEDTLS_ECDSA_DETERMINISTIC + +/** + * \def MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + * + * Enable the PSK based ciphersuite modes in SSL / TLS. + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + * + * Enable the DHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + * + * Enable the ECDHE-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + * + * Enable the RSA-PSK based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + * + * Enable the RSA-only based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + */ +#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + * + * Enable the DHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_DHM_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + * + * Enable the ECDHE-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_PKCS1_V15, + * MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + * + * Enable the ECDHE-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C, + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + * + * Enable the ECDH-ECDSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_ECDSA_C, MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + * + * Enable the ECDH-RSA based ciphersuite modes in SSL / TLS. + * + * Requires: MBEDTLS_ECDH_C, MBEDTLS_RSA_C, MBEDTLS_X509_CRT_PARSE_C + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + */ +#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED + +/** + * \def MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + * + * Enable the ECJPAKE based ciphersuite modes in SSL / TLS. + * + * \warning This is currently experimental. EC J-PAKE support is based on the + * Thread v1.0.0 specification; incompatible changes to the specification + * might still happen. For this reason, this is disabled by default. + * + * Requires: MBEDTLS_ECJPAKE_C + * MBEDTLS_SHA256_C + * MBEDTLS_ECP_DP_SECP256R1_ENABLED + * + * This enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8 + */ +//#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED + +/** + * \def MBEDTLS_PK_PARSE_EC_EXTENDED + * + * Enhance support for reading EC keys using variants of SEC1 not allowed by + * RFC 5915 and RFC 5480. + * + * Currently this means parsing the SpecifiedECDomain choice of EC + * parameters (only known groups are supported, not arbitrary domains, to + * avoid validation issues). + * + * Disable if you only need to support RFC 5915 + 5480 key formats. + */ +#define MBEDTLS_PK_PARSE_EC_EXTENDED + +/** + * \def MBEDTLS_ERROR_STRERROR_DUMMY + * + * Enable a dummy error function to make use of mbedtls_strerror() in + * third party libraries easier when MBEDTLS_ERROR_C is disabled + * (no effect when MBEDTLS_ERROR_C is enabled). + * + * You can safely disable this if MBEDTLS_ERROR_C is enabled, or if you're + * not using mbedtls_strerror() or error_strerror() in your application. + * + * Disable if you run into name conflicts and want to really remove the + * mbedtls_strerror() + */ +#define MBEDTLS_ERROR_STRERROR_DUMMY + +/** + * \def MBEDTLS_GENPRIME + * + * Enable the prime-number generation code. + * + * Requires: MBEDTLS_BIGNUM_C + */ +#define MBEDTLS_GENPRIME + +/** + * \def MBEDTLS_FS_IO + * + * Enable functions that use the filesystem. + */ +#define MBEDTLS_FS_IO + +/** + * \def MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + * + * Do not add default entropy sources in mbedtls_entropy_init(). + * + * This is useful to have more control over the added entropy sources in an + * application. + * + * Uncomment this macro to prevent loading of default entropy functions. + */ +//#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES + +/** + * \def MBEDTLS_NO_PLATFORM_ENTROPY + * + * Do not use built-in platform entropy functions. + * This is useful if your platform does not support + * standards like the /dev/urandom or Windows CryptoAPI. + * + * Uncomment this macro to disable the built-in platform entropy functions. + */ +//#define MBEDTLS_NO_PLATFORM_ENTROPY + +/** + * \def MBEDTLS_ENTROPY_FORCE_SHA256 + * + * Force the entropy accumulator to use a SHA-256 accumulator instead of the + * default SHA-512 based one (if both are available). + * + * Requires: MBEDTLS_SHA256_C + * + * On 32-bit systems SHA-256 can be much faster than SHA-512. Use this option + * if you have performance concerns. + * + * This option is only useful if both MBEDTLS_SHA256_C and + * MBEDTLS_SHA512_C are defined. Otherwise the available hash module is used. + */ +//#define MBEDTLS_ENTROPY_FORCE_SHA256 + +/** + * \def MBEDTLS_ENTROPY_NV_SEED + * + * Enable the non-volatile (NV) seed file-based entropy source. + * (Also enables the NV seed read/write functions in the platform layer) + * + * This is crucial (if not required) on systems that do not have a + * cryptographic entropy source (in hardware or kernel) available. + * + * Requires: MBEDTLS_ENTROPY_C, MBEDTLS_PLATFORM_C + * + * \note The read/write functions that are used by the entropy source are + * determined in the platform layer, and can be modified at runtime and/or + * compile-time depending on the flags (MBEDTLS_PLATFORM_NV_SEED_*) used. + * + * \note If you use the default implementation functions that read a seedfile + * with regular fopen(), please make sure you make a seedfile with the + * proper name (defined in MBEDTLS_PLATFORM_STD_NV_SEED_FILE) and at + * least MBEDTLS_ENTROPY_BLOCK_SIZE bytes in size that can be read from + * and written to or you will get an entropy source error! The default + * implementation will only use the first MBEDTLS_ENTROPY_BLOCK_SIZE + * bytes from the file. + * + * \note The entropy collector will write to the seed file before entropy is + * given to an external source, to update it. + */ +//#define MBEDTLS_ENTROPY_NV_SEED + +/* MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER + * + * Enable key identifiers that encode a key owner identifier. + * + * The owner of a key is identified by a value of type ::mbedtls_key_owner_id_t + * which is currently hard-coded to be int32_t. + * + * Note that this option is meant for internal use only and may be removed + * without notice. It is incompatible with MBEDTLS_USE_PSA_CRYPTO. + */ +//#define MBEDTLS_PSA_CRYPTO_KEY_ID_ENCODES_OWNER + +/** + * \def MBEDTLS_MEMORY_DEBUG + * + * Enable debugging of buffer allocator memory issues. Automatically prints + * (to stderr) all (fatal) messages on memory allocation issues. Enables + * function for 'debug output' of allocated memory. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Uncomment this macro to let the buffer allocator print out error messages. + */ +//#define MBEDTLS_MEMORY_DEBUG + +/** + * \def MBEDTLS_MEMORY_BACKTRACE + * + * Include backtrace information with each allocated block. + * + * Requires: MBEDTLS_MEMORY_BUFFER_ALLOC_C + * GLIBC-compatible backtrace() an backtrace_symbols() support + * + * Uncomment this macro to include backtrace information + */ +//#define MBEDTLS_MEMORY_BACKTRACE + +/** + * \def MBEDTLS_PK_RSA_ALT_SUPPORT + * + * Support external private RSA keys (eg from a HSM) in the PK layer. + * + * Comment this macro to disable support for external private RSA keys. + */ +#define MBEDTLS_PK_RSA_ALT_SUPPORT + +/** + * \def MBEDTLS_PKCS1_V15 + * + * Enable support for PKCS#1 v1.5 encoding. + * + * Requires: MBEDTLS_RSA_C + * + * This enables support for PKCS#1 v1.5 operations. + */ +#define MBEDTLS_PKCS1_V15 + +/** + * \def MBEDTLS_PKCS1_V21 + * + * Enable support for PKCS#1 v2.1 encoding. + * + * Requires: MBEDTLS_MD_C, MBEDTLS_RSA_C + * + * This enables support for RSAES-OAEP and RSASSA-PSS operations. + */ +#define MBEDTLS_PKCS1_V21 + +/** \def MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + * + * Enable support for platform built-in keys. If you enable this feature, + * you must implement the function mbedtls_psa_platform_get_builtin_key(). + * See the documentation of that function for more information. + * + * Built-in keys are typically derived from a hardware unique key or + * stored in a secure element. + * + * Requires: MBEDTLS_PSA_CRYPTO_C. + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_BUILTIN_KEYS + +/** \def MBEDTLS_PSA_CRYPTO_CLIENT + * + * Enable support for PSA crypto client. + * + * \note This option allows to include the code necessary for a PSA + * crypto client when the PSA crypto implementation is not included in + * the library (MBEDTLS_PSA_CRYPTO_C disabled). The code included is the + * code to set and get PSA key attributes. + * The development of PSA drivers partially relying on the library to + * fulfill the hardware gaps is another possible usage of this option. + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_CLIENT + +/** \def MBEDTLS_PSA_CRYPTO_DRIVERS + * + * Enable support for the experimental PSA crypto driver interface. + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * \warning This interface is experimental and may change or be removed + * without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_DRIVERS + +/** \def MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + * + * Make the PSA Crypto module use an external random generator provided + * by a driver, instead of Mbed TLS's entropy and DRBG modules. + * + * \note This random generator must deliver random numbers with cryptographic + * quality and high performance. It must supply unpredictable numbers + * with a uniform distribution. The implementation of this function + * is responsible for ensuring that the random generator is seeded + * with sufficient entropy. If you have a hardware TRNG which is slow + * or delivers non-uniform output, declare it as an entropy source + * with mbedtls_entropy_add_source() instead of enabling this option. + * + * If you enable this option, you must configure the type + * ::mbedtls_psa_external_random_context_t in psa/crypto_platform.h + * and define a function called mbedtls_psa_external_get_random() + * with the following prototype: + * ``` + * psa_status_t mbedtls_psa_external_get_random( + * mbedtls_psa_external_random_context_t *context, + * uint8_t *output, size_t output_size, size_t *output_length); + * ); + * ``` + * The \c context value is initialized to 0 before the first call. + * The function must fill the \c output buffer with \p output_size bytes + * of random data and set \c *output_length to \p output_size. + * + * Requires: MBEDTLS_PSA_CRYPTO_C + * + * \warning If you enable this option, code that uses the PSA cryptography + * interface will not use any of the entropy sources set up for + * the entropy module, nor the NV seed that MBEDTLS_ENTROPY_NV_SEED + * enables. + * + * \note This option is experimental and may be removed without notice. + */ +//#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG + +/** + * \def MBEDTLS_PSA_CRYPTO_SPM + * + * When MBEDTLS_PSA_CRYPTO_SPM is defined, the code is built for SPM (Secure + * Partition Manager) integration which separates the code into two parts: a + * NSPE (Non-Secure Process Environment) and an SPE (Secure Process + * Environment). + * + * Module: library/psa_crypto.c + * Requires: MBEDTLS_PSA_CRYPTO_C + * + */ +//#define MBEDTLS_PSA_CRYPTO_SPM + +/** + * \def MBEDTLS_PSA_INJECT_ENTROPY + * + * Enable support for entropy injection at first boot. This feature is + * required on systems that do not have a built-in entropy source (TRNG). + * This feature is currently not supported on systems that have a built-in + * entropy source. + * + * Requires: MBEDTLS_PSA_CRYPTO_STORAGE_C, MBEDTLS_ENTROPY_NV_SEED + * + */ +//#define MBEDTLS_PSA_INJECT_ENTROPY + +/** + * \def MBEDTLS_RSA_NO_CRT + * + * Do not use the Chinese Remainder Theorem + * for the RSA private operation. + * + * Uncomment this macro to disable the use of CRT in RSA. + * + */ +//#define MBEDTLS_RSA_NO_CRT + +/** + * \def MBEDTLS_SELF_TEST + * + * Enable the checkup functions (*_self_test). + */ +#define MBEDTLS_SELF_TEST + +/** + * \def MBEDTLS_SHA256_SMALLER + * + * Enable an implementation of SHA-256 that has lower ROM footprint but also + * lower performance. + * + * The default implementation is meant to be a reasonnable compromise between + * performance and size. This version optimizes more aggressively for size at + * the expense of performance. Eg on Cortex-M4 it reduces the size of + * mbedtls_sha256_process() from ~2KB to ~0.5KB for a performance hit of about + * 30%. + * + * Uncomment to enable the smaller implementation of SHA256. + */ +//#define MBEDTLS_SHA256_SMALLER + +/** + * \def MBEDTLS_SHA512_SMALLER + * + * Enable an implementation of SHA-512 that has lower ROM footprint but also + * lower performance. + * + * Uncomment to enable the smaller implementation of SHA512. + */ +//#define MBEDTLS_SHA512_SMALLER + +/** + * \def MBEDTLS_SSL_ALL_ALERT_MESSAGES + * + * Enable sending of alert messages in case of encountered errors as per RFC. + * If you choose not to send the alert messages, mbed TLS can still communicate + * with other servers, only debugging of failures is harder. + * + * The advantage of not sending alert messages, is that no information is given + * about reasons for failures thus preventing adversaries of gaining intel. + * + * Enable sending of all alert messages + */ +#define MBEDTLS_SSL_ALL_ALERT_MESSAGES + +/** + * \def MBEDTLS_SSL_DTLS_CONNECTION_ID + * + * Enable support for the DTLS Connection ID extension + * (version draft-ietf-tls-dtls-connection-id-05, + * https://tools.ietf.org/html/draft-ietf-tls-dtls-connection-id-05) + * which allows to identify DTLS connections across changes + * in the underlying transport. + * + * Setting this option enables the SSL APIs `mbedtls_ssl_set_cid()`, + * `mbedtls_ssl_get_peer_cid()` and `mbedtls_ssl_conf_cid()`. + * See the corresponding documentation for more information. + * + * \warning The Connection ID extension is still in draft state. + * We make no stability promises for the availability + * or the shape of the API controlled by this option. + * + * The maximum lengths of outgoing and incoming CIDs can be configured + * through the options + * - MBEDTLS_SSL_CID_OUT_LEN_MAX + * - MBEDTLS_SSL_CID_IN_LEN_MAX. + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Uncomment to enable the Connection ID extension. + */ +//#define MBEDTLS_SSL_DTLS_CONNECTION_ID + +/** + * \def MBEDTLS_SSL_ASYNC_PRIVATE + * + * Enable asynchronous external private key operations in SSL. This allows + * you to configure an SSL connection to call an external cryptographic + * module to perform private key operations instead of performing the + * operation inside the library. + * + */ +//#define MBEDTLS_SSL_ASYNC_PRIVATE + +/** + * \def MBEDTLS_SSL_CONTEXT_SERIALIZATION + * + * Enable serialization of the TLS context structures, through use of the + * functions mbedtls_ssl_context_save() and mbedtls_ssl_context_load(). + * + * This pair of functions allows one side of a connection to serialize the + * context associated with the connection, then free or re-use that context + * while the serialized state is persisted elsewhere, and finally deserialize + * that state to a live context for resuming read/write operations on the + * connection. From a protocol perspective, the state of the connection is + * unaffected, in particular this is entirely transparent to the peer. + * + * Note: this is distinct from TLS session resumption, which is part of the + * protocol and fully visible by the peer. TLS session resumption enables + * establishing new connections associated to a saved session with shorter, + * lighter handshakes, while context serialization is a local optimization in + * handling a single, potentially long-lived connection. + * + * Enabling these APIs makes some SSL structures larger, as 64 extra bytes are + * saved after the handshake to allow for more efficient serialization, so if + * you don't need this feature you'll save RAM by disabling it. + * + * Comment to disable the context serialization APIs. + */ +#define MBEDTLS_SSL_CONTEXT_SERIALIZATION + +/** + * \def MBEDTLS_SSL_DEBUG_ALL + * + * Enable the debug messages in SSL module for all issues. + * Debug messages have been disabled in some places to prevent timing + * attacks due to (unbalanced) debugging function calls. + * + * If you need all error reporting you should enable this during debugging, + * but remove this for production servers that should log as well. + * + * Uncomment this macro to report all debug messages on errors introducing + * a timing side-channel. + * + */ +//#define MBEDTLS_SSL_DEBUG_ALL + +/** \def MBEDTLS_SSL_ENCRYPT_THEN_MAC + * + * Enable support for Encrypt-then-MAC, RFC 7366. + * + * This allows peers that both support it to use a more robust protection for + * ciphersuites using CBC, providing deep resistance against timing attacks + * on the padding or underlying cipher. + * + * This only affects CBC ciphersuites, and is useless if none is defined. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Encrypt-then-MAC + */ +#define MBEDTLS_SSL_ENCRYPT_THEN_MAC + +/** \def MBEDTLS_SSL_EXTENDED_MASTER_SECRET + * + * Enable support for RFC 7627: Session Hash and Extended Master Secret + * Extension. + * + * This was introduced as "the proper fix" to the Triple Handshake familiy of + * attacks, but it is recommended to always use it (even if you disable + * renegotiation), since it actually fixes a more fundamental issue in the + * original SSL/TLS design, and has implications beyond Triple Handshake. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for Extended Master Secret. + */ +#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET + +/** + * \def MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + * + * This option controls the availability of the API mbedtls_ssl_get_peer_cert() + * giving access to the peer's certificate after completion of the handshake. + * + * Unless you need mbedtls_ssl_peer_cert() in your application, it is + * recommended to disable this option for reduced RAM usage. + * + * \note If this option is disabled, mbedtls_ssl_get_peer_cert() is still + * defined, but always returns \c NULL. + * + * \note This option has no influence on the protection against the + * triple handshake attack. Even if it is disabled, Mbed TLS will + * still ensure that certificates do not change during renegotiation, + * for exaple by keeping a hash of the peer's certificate. + * + * Comment this macro to disable storing the peer's certificate + * after the handshake. + */ +#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE + +/** + * \def MBEDTLS_SSL_RENEGOTIATION + * + * Enable support for TLS renegotiation. + * + * The two main uses of renegotiation are (1) refresh keys on long-lived + * connections and (2) client authentication after the initial handshake. + * If you don't need renegotiation, it's probably better to disable it, since + * it has been associated with security issues in the past and is easy to + * misuse/misunderstand. + * + * Comment this to disable support for renegotiation. + * + * \note Even if this option is disabled, both client and server are aware + * of the Renegotiation Indication Extension (RFC 5746) used to + * prevent the SSL renegotiation attack (see RFC 5746 Sect. 1). + * (See \c mbedtls_ssl_conf_legacy_renegotiation for the + * configuration of this extension). + * + */ +#define MBEDTLS_SSL_RENEGOTIATION + +/** + * \def MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + * + * Enable support for RFC 6066 max_fragment_length extension in SSL. + * + * Comment this macro to disable support for the max_fragment_length extension + */ +#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_2 + * + * Enable support for TLS 1.2 (and DTLS 1.2 if DTLS is enabled). + * + * Requires: MBEDTLS_SHA1_C or MBEDTLS_SHA256_C or MBEDTLS_SHA512_C + * (Depends on ciphersuites) + * + * Comment this macro to disable support for TLS 1.2 / DTLS 1.2 + */ +#define MBEDTLS_SSL_PROTO_TLS1_2 + +/** + * \def MBEDTLS_SSL_PROTO_TLS1_3 + * + * Enable support for TLS 1.3. + * + * \note The support for TLS 1.3 is not comprehensive yet, in particular + * pre-shared keys are not supported. + * See docs/architecture/tls13-support.md for a description of the TLS + * 1.3 support that this option enables. + * + * Uncomment this macro to enable the support for TLS 1.3. + * + */ +//#define MBEDTLS_SSL_PROTO_TLS1_3 + +/** + * \def MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE + * + * Enable TLS 1.3 middlebox compatibility mode. + * + * As specified in Section D.4 of RFC 8446, TLS 1.3 offers a compatibility + * mode to make a TLS 1.3 connection more likely to pass through middle boxes + * expecting TLS 1.2 traffic. + * + * Turning on the compatibility mode comes at the cost of a few added bytes + * on the wire, but it doesn't affect compatibility with TLS 1.3 implementations + * that don't use it. Therefore, unless transmission bandwidth is critical and + * you know that middlebox compatibility issues won't occur, it is therefore + * recommended to set this option. + * + * Comment to disable compatibility mode for TLS 1.3. If + * MBEDTLS_SSL_PROTO_TLS1_3 is not enabled, this option does not have any + * effect on the build. + * + */ +//#define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE + +/** + * \def MBEDTLS_SSL_PROTO_DTLS + * + * Enable support for DTLS (all available versions). + * + * Enable this and MBEDTLS_SSL_PROTO_TLS1_2 to enable DTLS 1.2. + * + * Requires: MBEDTLS_SSL_PROTO_TLS1_2 + * + * Comment this macro to disable support for DTLS + */ +#define MBEDTLS_SSL_PROTO_DTLS + +/** + * \def MBEDTLS_SSL_ALPN + * + * Enable support for RFC 7301 Application Layer Protocol Negotiation. + * + * Comment this macro to disable support for ALPN. + */ +#define MBEDTLS_SSL_ALPN + +/** + * \def MBEDTLS_SSL_DTLS_ANTI_REPLAY + * + * Enable support for the anti-replay mechanism in DTLS. + * + * Requires: MBEDTLS_SSL_TLS_C + * MBEDTLS_SSL_PROTO_DTLS + * + * \warning Disabling this is often a security risk! + * See mbedtls_ssl_conf_dtls_anti_replay() for details. + * + * Comment this to disable anti-replay in DTLS. + */ +#define MBEDTLS_SSL_DTLS_ANTI_REPLAY + +/** + * \def MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Enable support for HelloVerifyRequest on DTLS servers. + * + * This feature is highly recommended to prevent DTLS servers being used as + * amplifiers in DoS attacks against other hosts. It should always be enabled + * unless you know for sure amplification cannot be a problem in the + * environment in which your server operates. + * + * \warning Disabling this can ba a security risk! (see above) + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Comment this to disable support for HelloVerifyRequest. + */ +#define MBEDTLS_SSL_DTLS_HELLO_VERIFY + +/** + * \def MBEDTLS_SSL_DTLS_SRTP + * + * Enable support for negotiation of DTLS-SRTP (RFC 5764) + * through the use_srtp extension. + * + * \note This feature provides the minimum functionality required + * to negotiate the use of DTLS-SRTP and to allow the derivation of + * the associated SRTP packet protection key material. + * In particular, the SRTP packet protection itself, as well as the + * demultiplexing of RTP and DTLS packets at the datagram layer + * (see Section 5 of RFC 5764), are not handled by this feature. + * Instead, after successful completion of a handshake negotiating + * the use of DTLS-SRTP, the extended key exporter API + * mbedtls_ssl_conf_export_keys_cb() should be used to implement + * the key exporter described in Section 4.2 of RFC 5764 and RFC 5705 + * (this is implemented in the SSL example programs). + * The resulting key should then be passed to an SRTP stack. + * + * Setting this option enables the runtime API + * mbedtls_ssl_conf_dtls_srtp_protection_profiles() + * through which the supported DTLS-SRTP protection + * profiles can be configured. You must call this API at + * runtime if you wish to negotiate the use of DTLS-SRTP. + * + * Requires: MBEDTLS_SSL_PROTO_DTLS + * + * Uncomment this to enable support for use_srtp extension. + */ +//#define MBEDTLS_SSL_DTLS_SRTP + +/** + * \def MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + * + * Enable server-side support for clients that reconnect from the same port. + * + * Some clients unexpectedly close the connection and try to reconnect using the + * same source port. This needs special support from the server to handle the + * new connection securely, as described in section 4.2.8 of RFC 6347. This + * flag enables that support. + * + * Requires: MBEDTLS_SSL_DTLS_HELLO_VERIFY + * + * Comment this to disable support for clients reusing the source port. + */ +#define MBEDTLS_SSL_DTLS_CLIENT_PORT_REUSE + +/** + * \def MBEDTLS_SSL_SESSION_TICKETS + * + * Enable support for RFC 5077 session tickets in SSL. + * Client-side, provides full support for session tickets (maintenance of a + * session store remains the responsibility of the application, though). + * Server-side, you also need to provide callbacks for writing and parsing + * tickets, including authenticated encryption and key management. Example + * callbacks are provided by MBEDTLS_SSL_TICKET_C. + * + * Comment this macro to disable support for SSL session tickets + */ +#define MBEDTLS_SSL_SESSION_TICKETS + +/** + * \def MBEDTLS_SSL_SERVER_NAME_INDICATION + * + * Enable support for RFC 6066 server name indication (SNI) in SSL. + * + * Requires: MBEDTLS_X509_CRT_PARSE_C + * + * Comment this macro to disable support for server name indication in SSL + */ +#define MBEDTLS_SSL_SERVER_NAME_INDICATION + +/** + * \def MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH + * + * When this option is enabled, the SSL buffer will be resized automatically + * based on the negotiated maximum fragment length in each direction. + * + * Requires: MBEDTLS_SSL_MAX_FRAGMENT_LENGTH + */ +//#define MBEDTLS_SSL_VARIABLE_BUFFER_LENGTH + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + * + * Enable testing of the constant-flow nature of some sensitive functions with + * clang's MemorySanitizer. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires compiling with clang -fsanitize=memory. The test + * suites can then be run normally. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_MEMSAN + +/** + * \def MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + * + * Enable testing of the constant-flow nature of some sensitive functions with + * valgrind's memcheck tool. This causes some existing tests to also test + * this non-functional property of the code under test. + * + * This setting requires valgrind headers for building, and is only useful for + * testing if the tests suites are run with valgrind's memcheck. This can be + * done for an individual test suite with 'valgrind ./test_suite_xxx', or when + * using CMake, this can be done for all test suites with 'make memcheck'. + * + * \warning This macro is only used for extended testing; it is not considered + * part of the library's API, so it may change or disappear at any time. + * + * Uncomment to enable testing of the constant-flow nature of selected code. + */ +//#define MBEDTLS_TEST_CONSTANT_FLOW_VALGRIND + +/** + * \def MBEDTLS_TEST_HOOKS + * + * Enable features for invasive testing such as introspection functions and + * hooks for fault injection. This enables additional unit tests. + * + * Merely enabling this feature should not change the behavior of the product. + * It only adds new code, and new branching points where the default behavior + * is the same as when this feature is disabled. + * However, this feature increases the attack surface: there is an added + * risk of vulnerabilities, and more gadgets that can make exploits easier. + * Therefore this feature must never be enabled in production. + * + * See `docs/architecture/testing/mbed-crypto-invasive-testing.md` for more + * information. + * + * Uncomment to enable invasive tests. + */ +//#define MBEDTLS_TEST_HOOKS + +/** + * \def MBEDTLS_THREADING_ALT + * + * Provide your own alternate threading implementation. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to allow your own alternate threading implementation. + */ +//#define MBEDTLS_THREADING_ALT + +/** + * \def MBEDTLS_THREADING_PTHREAD + * + * Enable the pthread wrapper layer for the threading layer. + * + * Requires: MBEDTLS_THREADING_C + * + * Uncomment this to enable pthread mutexes. + */ +//#define MBEDTLS_THREADING_PTHREAD + +/** + * \def MBEDTLS_USE_PSA_CRYPTO + * + * Make the X.509 and TLS library use PSA for cryptographic operations, and + * enable new APIs for using keys handled by PSA Crypto. + * + * \note Development of this option is currently in progress, and parts of Mbed + * TLS's X.509 and TLS modules are not ported to PSA yet. However, these parts + * will still continue to work as usual, so enabling this option should not + * break backwards compatibility. + * + * \note See docs/use-psa-crypto.md for a complete description of what this + * option currently does, and of parts that are not affected by it so far. + * + * \warning This option enables new Mbed TLS APIs which are currently + * considered experimental and may change in incompatible ways at any time. + * That is, the APIs enabled by this option are not covered by the usual + * promises of API stability. + * + * Requires: MBEDTLS_PSA_CRYPTO_C. + * + * Uncomment this to enable internal use of PSA Crypto and new associated APIs. + */ +//#define MBEDTLS_USE_PSA_CRYPTO + +/** + * \def MBEDTLS_PSA_CRYPTO_CONFIG + * + * This setting allows support for cryptographic mechanisms through the PSA + * API to be configured separately from support through the mbedtls API. + * + * Uncomment this to enable use of PSA Crypto configuration settings which + * can be found in include/psa/crypto_config.h. + * + * This feature is still experimental and is not ready for production since + * it is not completed. + */ +//#define MBEDTLS_PSA_CRYPTO_CONFIG + +/** + * \def MBEDTLS_VERSION_FEATURES + * + * Allow run-time checking of compile-time enabled features. Thus allowing users + * to check at run-time if the library is for instance compiled with threading + * support via mbedtls_version_check_feature(). + * + * Requires: MBEDTLS_VERSION_C + * + * Comment this to disable run-time checking and save ROM space + */ +#define MBEDTLS_VERSION_FEATURES + +/** + * \def MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK + * + * If set, this enables the X.509 API `mbedtls_x509_crt_verify_with_ca_cb()` + * and the SSL API `mbedtls_ssl_conf_ca_cb()` which allow users to configure + * the set of trusted certificates through a callback instead of a linked + * list. + * + * This is useful for example in environments where a large number of trusted + * certificates is present and storing them in a linked list isn't efficient + * enough, or when the set of trusted certificates changes frequently. + * + * See the documentation of `mbedtls_x509_crt_verify_with_ca_cb()` and + * `mbedtls_ssl_conf_ca_cb()` for more information. + * + * Uncomment to enable trusted certificate callbacks. + */ +//#define MBEDTLS_X509_TRUSTED_CERTIFICATE_CALLBACK + +/** + * \def MBEDTLS_X509_REMOVE_INFO + * + * Disable mbedtls_x509_*_info() and related APIs. + * + * Uncomment to omit mbedtls_x509_*_info(), as well as mbedtls_debug_print_crt() + * and other functions/constants only used by these functions, thus reducing + * the code footprint by several KB. + */ +//#define MBEDTLS_X509_REMOVE_INFO + +/** + * \def MBEDTLS_X509_RSASSA_PSS_SUPPORT + * + * Enable parsing and verification of X.509 certificates, CRLs and CSRS + * signed with RSASSA-PSS (aka PKCS#1 v2.1). + * + * Comment this macro to disallow using RSASSA-PSS in certificates. + */ +#define MBEDTLS_X509_RSASSA_PSS_SUPPORT +/* \} name SECTION: mbed TLS feature support */ + +/** + * \name SECTION: mbed TLS modules + * + * This section enables or disables entire modules in mbed TLS + * \{ + */ + +/** + * \def MBEDTLS_AESNI_C + * + * Enable AES-NI support on x86-64. + * + * Module: library/aesni.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM + * + * This modules adds support for the AES-NI instructions on x86-64 + */ +#define MBEDTLS_AESNI_C + +/** + * \def MBEDTLS_AES_C + * + * Enable the AES block cipher. + * + * Module: library/aes.c + * Caller: library/cipher.c + * library/pem.c + * library/ctr_drbg.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_AES_128_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_AES_256_CBC_SHA + * MBEDTLS_TLS_PSK_WITH_AES_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_AES_128_CBC_SHA + * + * PEM_PARSE uses AES for decrypting encrypted keys. + */ +#define MBEDTLS_AES_C + +/** + * \def MBEDTLS_ASN1_PARSE_C + * + * Enable the generic ASN1 parser. + * + * Module: library/asn1.c + * Caller: library/x509.c + * library/dhm.c + * library/pkcs12.c + * library/pkcs5.c + * library/pkparse.c + */ +#define MBEDTLS_ASN1_PARSE_C + +/** + * \def MBEDTLS_ASN1_WRITE_C + * + * Enable the generic ASN1 writer. + * + * Module: library/asn1write.c + * Caller: library/ecdsa.c + * library/pkwrite.c + * library/x509_create.c + * library/x509write_crt.c + * library/x509write_csr.c + */ +#define MBEDTLS_ASN1_WRITE_C + +/** + * \def MBEDTLS_BASE64_C + * + * Enable the Base64 module. + * + * Module: library/base64.c + * Caller: library/pem.c + * + * This module is required for PEM support (required by X.509). + */ +#define MBEDTLS_BASE64_C + +/** + * \def MBEDTLS_BIGNUM_C + * + * Enable the multi-precision integer library. + * + * Module: library/bignum.c + * Caller: library/dhm.c + * library/ecp.c + * library/ecdsa.c + * library/rsa.c + * library/rsa_alt_helpers.c + * library/ssl_tls.c + * + * This module is required for RSA, DHM and ECC (ECDH, ECDSA) support. + */ +#define MBEDTLS_BIGNUM_C + +/** + * \def MBEDTLS_CAMELLIA_C + * + * Enable the Camellia block cipher. + * + * Module: library/camellia.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_256_CBC_SHA + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_CAMELLIA_128_CBC_SHA + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_CAMELLIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_CAMELLIA_128_CBC_SHA256 + */ +#define MBEDTLS_CAMELLIA_C + +/** + * \def MBEDTLS_ARIA_C + * + * Enable the ARIA block cipher. + * + * Module: library/aria.c + * Caller: library/cipher.c + * + * This module enables the following ciphersuites (if other requisites are + * enabled as well): + * + * MBEDTLS_TLS_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_ECDSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDHE_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_ECDH_RSA_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_CBC_SHA384 + * MBEDTLS_TLS_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_DHE_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_128_GCM_SHA256 + * MBEDTLS_TLS_RSA_PSK_WITH_ARIA_256_GCM_SHA384 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_128_CBC_SHA256 + * MBEDTLS_TLS_ECDHE_PSK_WITH_ARIA_256_CBC_SHA384 + */ +#define MBEDTLS_ARIA_C + +/** + * \def MBEDTLS_CCM_C + * + * Enable the Counter with CBC-MAC (CCM) mode for 128-bit block cipher. + * + * Module: library/ccm.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C + * + * This module enables the AES-CCM ciphersuites, if other requisites are + * enabled as well. + */ +#define MBEDTLS_CCM_C + +/** + * \def MBEDTLS_CHACHA20_C + * + * Enable the ChaCha20 stream cipher. + * + * Module: library/chacha20.c + */ +#define MBEDTLS_CHACHA20_C + +/** + * \def MBEDTLS_CHACHAPOLY_C + * + * Enable the ChaCha20-Poly1305 AEAD algorithm. + * + * Module: library/chachapoly.c + * + * This module requires: MBEDTLS_CHACHA20_C, MBEDTLS_POLY1305_C + */ +#define MBEDTLS_CHACHAPOLY_C + +/** + * \def MBEDTLS_CIPHER_C + * + * Enable the generic cipher layer. + * + * Module: library/cipher.c + * Caller: library/ssl_tls.c + * + * Uncomment to enable generic cipher wrappers. + */ +#define MBEDTLS_CIPHER_C + +/** + * \def MBEDTLS_CMAC_C + * + * Enable the CMAC (Cipher-based Message Authentication Code) mode for block + * ciphers. + * + * \note When #MBEDTLS_CMAC_ALT is active, meaning that the underlying + * implementation of the CMAC algorithm is provided by an alternate + * implementation, that alternate implementation may opt to not support + * AES-192 or 3DES as underlying block ciphers for the CMAC operation. + * + * Module: library/cmac.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_DES_C + * + */ +#define MBEDTLS_CMAC_C + +/** + * \def MBEDTLS_CTR_DRBG_C + * + * Enable the CTR_DRBG AES-based random generator. + * The CTR_DRBG generator uses AES-256 by default. + * To use AES-128 instead, enable \c MBEDTLS_CTR_DRBG_USE_128_BIT_KEY above. + * + * \note To achieve a 256-bit security strength with CTR_DRBG, + * you must use AES-256 *and* use sufficient entropy. + * See ctr_drbg.h for more details. + * + * Module: library/ctr_drbg.c + * Caller: + * + * Requires: MBEDTLS_AES_C + * + * This module provides the CTR_DRBG AES random number generator. + */ +#define MBEDTLS_CTR_DRBG_C + +/** + * \def MBEDTLS_DEBUG_C + * + * Enable the debug functions. + * + * Module: library/debug.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * This module provides debugging functions. + */ +#define MBEDTLS_DEBUG_C + +/** + * \def MBEDTLS_DES_C + * + * Enable the DES block cipher. + * + * Module: library/des.c + * Caller: library/pem.c + * library/cipher.c + * + * PEM_PARSE uses DES/3DES for decrypting encrypted keys. + * + * \warning DES is considered a weak cipher and its use constitutes a + * security risk. We recommend considering stronger ciphers instead. + */ +#define MBEDTLS_DES_C + +/** + * \def MBEDTLS_DHM_C + * + * Enable the Diffie-Hellman-Merkle module. + * + * Module: library/dhm.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * This module is used by the following key exchanges: + * DHE-RSA, DHE-PSK + * + * \warning Using DHE constitutes a security risk as it + * is not possible to validate custom DH parameters. + * If possible, it is recommended users should consider + * preferring other methods of key exchange. + * See dhm.h for more details. + * + */ +#define MBEDTLS_DHM_C + +/** + * \def MBEDTLS_ECDH_C + * + * Enable the elliptic curve Diffie-Hellman library. + * + * Module: library/ecdh.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA, ECDHE-RSA, DHE-PSK + * + * Requires: MBEDTLS_ECP_C + */ +#define MBEDTLS_ECDH_C + +/** + * \def MBEDTLS_ECDSA_C + * + * Enable the elliptic curve DSA library. + * + * Module: library/ecdsa.c + * Caller: + * + * This module is used by the following key exchanges: + * ECDHE-ECDSA + * + * Requires: MBEDTLS_ECP_C, MBEDTLS_ASN1_WRITE_C, MBEDTLS_ASN1_PARSE_C, + * and at least one MBEDTLS_ECP_DP_XXX_ENABLED for a + * short Weierstrass curve. + */ +#define MBEDTLS_ECDSA_C + +/** + * \def MBEDTLS_ECJPAKE_C + * + * Enable the elliptic curve J-PAKE library. + * + * \note EC J-PAKE support is based on the Thread v1.0.0 specification. + * It has not been reviewed for compliance with newer standards such as + * Thread v1.1 or RFC 8236. + * + * Module: library/ecjpake.c + * Caller: + * + * This module is used by the following key exchanges: + * ECJPAKE + * + * Requires: MBEDTLS_ECP_C, MBEDTLS_MD_C + */ +#define MBEDTLS_ECJPAKE_C + +/** + * \def MBEDTLS_ECP_C + * + * Enable the elliptic curve over GF(p) library. + * + * Module: library/ecp.c + * Caller: library/ecdh.c + * library/ecdsa.c + * library/ecjpake.c + * + * Requires: MBEDTLS_BIGNUM_C and at least one MBEDTLS_ECP_DP_XXX_ENABLED + */ +#define MBEDTLS_ECP_C + +/** + * \def MBEDTLS_ENTROPY_C + * + * Enable the platform-specific entropy code. + * + * Module: library/entropy.c + * Caller: + * + * Requires: MBEDTLS_SHA512_C or MBEDTLS_SHA256_C + * + * This module provides a generic entropy pool + */ +#define MBEDTLS_ENTROPY_C + +/** + * \def MBEDTLS_ERROR_C + * + * Enable error code to error string conversion. + * + * Module: library/error.c + * Caller: + * + * This module enables mbedtls_strerror(). + */ +#define MBEDTLS_ERROR_C + +/** + * \def MBEDTLS_GCM_C + * + * Enable the Galois/Counter Mode (GCM). + * + * Module: library/gcm.c + * + * Requires: MBEDTLS_AES_C or MBEDTLS_CAMELLIA_C or MBEDTLS_ARIA_C + * + * This module enables the AES-GCM and CAMELLIA-GCM ciphersuites, if other + * requisites are enabled as well. + */ +#define MBEDTLS_GCM_C + +/** + * \def MBEDTLS_HKDF_C + * + * Enable the HKDF algorithm (RFC 5869). + * + * Module: library/hkdf.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * This module adds support for the Hashed Message Authentication Code + * (HMAC)-based key derivation function (HKDF). + */ +#define MBEDTLS_HKDF_C + +/** + * \def MBEDTLS_HMAC_DRBG_C + * + * Enable the HMAC_DRBG random generator. + * + * Module: library/hmac_drbg.c + * Caller: + * + * Requires: MBEDTLS_MD_C + * + * Uncomment to enable the HMAC_DRBG random number geerator. + */ +#define MBEDTLS_HMAC_DRBG_C + +/** + * \def MBEDTLS_NIST_KW_C + * + * Enable the Key Wrapping mode for 128-bit block ciphers, + * as defined in NIST SP 800-38F. Only KW and KWP modes + * are supported. At the moment, only AES is approved by NIST. + * + * Module: library/nist_kw.c + * + * Requires: MBEDTLS_AES_C and MBEDTLS_CIPHER_C + */ +#define MBEDTLS_NIST_KW_C + +/** + * \def MBEDTLS_MD_C + * + * Enable the generic message digest layer. + * + * Module: library/md.c + * Caller: + * + * Uncomment to enable generic message digest wrappers. + */ +#define MBEDTLS_MD_C + +/** + * \def MBEDTLS_MD5_C + * + * Enable the MD5 hash algorithm. + * + * Module: library/md5.c + * Caller: library/md.c + * library/pem.c + * library/ssl_tls.c + * + * This module is required for TLS 1.2 depending on the handshake parameters. + * Further, it is used for checking MD5-signed certificates, and for PBKDF1 + * when decrypting PEM-encoded encrypted keys. + * + * \warning MD5 is considered a weak message digest and its use constitutes a + * security risk. If possible, we recommend avoiding dependencies on + * it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_MD5_C + +/** + * \def MBEDTLS_MEMORY_BUFFER_ALLOC_C + * + * Enable the buffer allocator implementation that makes use of a (stack) + * based buffer to 'allocate' dynamic memory. (replaces calloc() and free() + * calls) + * + * Module: library/memory_buffer_alloc.c + * + * Requires: MBEDTLS_PLATFORM_C + * MBEDTLS_PLATFORM_MEMORY (to use it within mbed TLS) + * + * Enable this module to enable the buffer memory allocator. + */ +//#define MBEDTLS_MEMORY_BUFFER_ALLOC_C + +/** + * \def MBEDTLS_NET_C + * + * Enable the TCP and UDP over IPv6/IPv4 networking routines. + * + * \note This module only works on POSIX/Unix (including Linux, BSD and OS X) + * and Windows. For other platforms, you'll want to disable it, and write your + * own networking callbacks to be passed to \c mbedtls_ssl_set_bio(). + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/net_sockets.c + * + * This module provides networking routines. + */ +#define MBEDTLS_NET_C + +/** + * \def MBEDTLS_OID_C + * + * Enable the OID database. + * + * Module: library/oid.c + * Caller: library/asn1write.c + * library/pkcs5.c + * library/pkparse.c + * library/pkwrite.c + * library/rsa.c + * library/x509.c + * library/x509_create.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * This modules translates between OIDs and internal values. + */ +#define MBEDTLS_OID_C + +/** + * \def MBEDTLS_PADLOCK_C + * + * Enable VIA Padlock support on x86. + * + * Module: library/padlock.c + * Caller: library/aes.c + * + * Requires: MBEDTLS_HAVE_ASM + * + * This modules adds support for the VIA PadLock on x86. + */ +#define MBEDTLS_PADLOCK_C + +/** + * \def MBEDTLS_PEM_PARSE_C + * + * Enable PEM decoding / parsing. + * + * Module: library/pem.c + * Caller: library/dhm.c + * library/pkparse.c + * library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for decoding / parsing PEM files. + */ +#define MBEDTLS_PEM_PARSE_C + +/** + * \def MBEDTLS_PEM_WRITE_C + * + * Enable PEM encoding / writing. + * + * Module: library/pem.c + * Caller: library/pkwrite.c + * library/x509write_crt.c + * library/x509write_csr.c + * + * Requires: MBEDTLS_BASE64_C + * + * This modules adds support for encoding / writing PEM files. + */ +#define MBEDTLS_PEM_WRITE_C + +/** + * \def MBEDTLS_PK_C + * + * Enable the generic public (asymetric) key layer. + * + * Module: library/pk.c + * Caller: library/ssl_tls.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * Requires: MBEDTLS_RSA_C or MBEDTLS_ECP_C + * + * Uncomment to enable generic public key wrappers. + */ +#define MBEDTLS_PK_C + +/** + * \def MBEDTLS_PK_PARSE_C + * + * Enable the generic public (asymetric) key parser. + * + * Module: library/pkparse.c + * Caller: library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key parse functions. + */ +#define MBEDTLS_PK_PARSE_C + +/** + * \def MBEDTLS_PK_WRITE_C + * + * Enable the generic public (asymetric) key writer. + * + * Module: library/pkwrite.c + * Caller: library/x509write.c + * + * Requires: MBEDTLS_PK_C + * + * Uncomment to enable generic public key write functions. + */ +#define MBEDTLS_PK_WRITE_C + +/** + * \def MBEDTLS_PKCS5_C + * + * Enable PKCS#5 functions. + * + * Module: library/pkcs5.c + * + * Requires: MBEDTLS_MD_C + * + * This module adds support for the PKCS#5 functions. + */ +#define MBEDTLS_PKCS5_C + +/** + * \def MBEDTLS_PKCS12_C + * + * Enable PKCS#12 PBE functions. + * Adds algorithms for parsing PKCS#8 encrypted private keys + * + * Module: library/pkcs12.c + * Caller: library/pkparse.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * + * This module enables PKCS#12 functions. + */ +#define MBEDTLS_PKCS12_C + +/** + * \def MBEDTLS_PLATFORM_C + * + * Enable the platform abstraction layer that allows you to re-assign + * functions like calloc(), free(), snprintf(), printf(), fprintf(), exit(). + * + * Enabling MBEDTLS_PLATFORM_C enables to use of MBEDTLS_PLATFORM_XXX_ALT + * or MBEDTLS_PLATFORM_XXX_MACRO directives, allowing the functions mentioned + * above to be specified at runtime or compile time respectively. + * + * \note This abstraction layer must be enabled on Windows (including MSYS2) + * as other module rely on it for a fixed snprintf implementation. + * + * Module: library/platform.c + * Caller: Most other .c files + * + * This module enables abstraction of common (libc) functions. + */ +// #define MBEDTLS_PLATFORM_C + +/** + * \def MBEDTLS_POLY1305_C + * + * Enable the Poly1305 MAC algorithm. + * + * Module: library/poly1305.c + * Caller: library/chachapoly.c + */ +#define MBEDTLS_POLY1305_C + +/** + * \def MBEDTLS_PSA_CRYPTO_C + * + * Enable the Platform Security Architecture cryptography API. + * + * Module: library/psa_crypto.c + * + * Requires: either MBEDTLS_CTR_DRBG_C and MBEDTLS_ENTROPY_C, + * or MBEDTLS_HMAC_DRBG_C and MBEDTLS_ENTROPY_C, + * or MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG. + * + */ +#define MBEDTLS_PSA_CRYPTO_C + +/** + * \def MBEDTLS_PSA_CRYPTO_SE_C + * + * Enable secure element support in the Platform Security Architecture + * cryptography API. + * + * \warning This feature is not yet suitable for production. It is provided + * for API evaluation and testing purposes only. + * + * Module: library/psa_crypto_se.c + * + * Requires: MBEDTLS_PSA_CRYPTO_C, MBEDTLS_PSA_CRYPTO_STORAGE_C + * + */ +//#define MBEDTLS_PSA_CRYPTO_SE_C + +/** + * \def MBEDTLS_PSA_CRYPTO_STORAGE_C + * + * Enable the Platform Security Architecture persistent key storage. + * + * Module: library/psa_crypto_storage.c + * + * Requires: MBEDTLS_PSA_CRYPTO_C, + * either MBEDTLS_PSA_ITS_FILE_C or a native implementation of + * the PSA ITS interface + */ +#define MBEDTLS_PSA_CRYPTO_STORAGE_C + +/** + * \def MBEDTLS_PSA_ITS_FILE_C + * + * Enable the emulation of the Platform Security Architecture + * Internal Trusted Storage (PSA ITS) over files. + * + * Module: library/psa_its_file.c + * + * Requires: MBEDTLS_FS_IO + */ +#define MBEDTLS_PSA_ITS_FILE_C + +/** + * \def MBEDTLS_RIPEMD160_C + * + * Enable the RIPEMD-160 hash algorithm. + * + * Module: library/ripemd160.c + * Caller: library/md.c + * + */ +#define MBEDTLS_RIPEMD160_C + +/** + * \def MBEDTLS_RSA_C + * + * Enable the RSA public-key cryptosystem. + * + * Module: library/rsa.c + * library/rsa_alt_helpers.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509.c + * + * This module is used by the following key exchanges: + * RSA, DHE-RSA, ECDHE-RSA, RSA-PSK + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C + */ +#define MBEDTLS_RSA_C + +/** + * \def MBEDTLS_SHA1_C + * + * Enable the SHA1 cryptographic hash algorithm. + * + * Module: library/sha1.c + * Caller: library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * library/x509write_crt.c + * + * This module is required for TLS 1.2 depending on the handshake parameters, + * and for SHA1-signed certificates. + * + * \warning SHA-1 is considered a weak message digest and its use constitutes + * a security risk. If possible, we recommend avoiding dependencies + * on it, and considering stronger message digests instead. + * + */ +#define MBEDTLS_SHA1_C + +/** + * \def MBEDTLS_SHA224_C + * + * Enable the SHA-224 cryptographic hash algorithm. + * + * Requires: MBEDTLS_SHA256_C. The library does not currently support enabling + * SHA-224 without SHA-256. + * + * Module: library/sha256.c + * Caller: library/md.c + * library/ssl_cookie.c + * + * This module adds support for SHA-224. + */ +#define MBEDTLS_SHA224_C + +/** + * \def MBEDTLS_SHA256_C + * + * Enable the SHA-256 cryptographic hash algorithm. + * + * Requires: MBEDTLS_SHA224_C. The library does not currently support enabling + * SHA-256 without SHA-224. + * + * Module: library/sha256.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * This module adds support for SHA-256. + * This module is required for the SSL/TLS 1.2 PRF function. + */ +#define MBEDTLS_SHA256_C + +/** + * \def MBEDTLS_SHA384_C + * + * Enable the SHA-384 cryptographic hash algorithm. + * + * Requires: MBEDTLS_SHA512_C + * + * Module: library/sha512.c + * Caller: library/md.c + * library/ssl_cli.c + * library/ssl_srv.c + * + * Comment to disable SHA-384 + */ +#define MBEDTLS_SHA384_C + +/** + * \def MBEDTLS_SHA512_C + * + * Enable SHA-512 cryptographic hash algorithms. + * + * Module: library/sha512.c + * Caller: library/entropy.c + * library/md.c + * library/ssl_tls.c + * library/ssl_cookie.c + * + * This module adds support for SHA-512. + */ +#define MBEDTLS_SHA512_C + +/** + * \def MBEDTLS_SSL_CACHE_C + * + * Enable simple SSL cache implementation. + * + * Module: library/ssl_cache.c + * Caller: + * + * Requires: MBEDTLS_SSL_CACHE_C + */ +#define MBEDTLS_SSL_CACHE_C + +/** + * \def MBEDTLS_SSL_COOKIE_C + * + * Enable basic implementation of DTLS cookies for hello verification. + * + * Module: library/ssl_cookie.c + * Caller: + */ +#define MBEDTLS_SSL_COOKIE_C + +/** + * \def MBEDTLS_SSL_TICKET_C + * + * Enable an implementation of TLS server-side callbacks for session tickets. + * + * Module: library/ssl_ticket.c + * Caller: + * + * Requires: MBEDTLS_CIPHER_C + */ +#define MBEDTLS_SSL_TICKET_C + +/** + * \def MBEDTLS_SSL_CLI_C + * + * Enable the SSL/TLS client code. + * + * Module: library/ssl_cli.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS client support. + */ +#define MBEDTLS_SSL_CLI_C + +/** + * \def MBEDTLS_SSL_SRV_C + * + * Enable the SSL/TLS server code. + * + * Module: library/ssl_srv.c + * Caller: + * + * Requires: MBEDTLS_SSL_TLS_C + * + * This module is required for SSL/TLS server support. + */ +#define MBEDTLS_SSL_SRV_C + +/** + * \def MBEDTLS_SSL_TLS_C + * + * Enable the generic SSL/TLS code. + * + * Module: library/ssl_tls.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * + * Requires: MBEDTLS_CIPHER_C, MBEDTLS_MD_C + * and at least one of the MBEDTLS_SSL_PROTO_XXX defines + * + * This module is required for SSL/TLS. + */ +#define MBEDTLS_SSL_TLS_C + +/** + * \def MBEDTLS_THREADING_C + * + * Enable the threading abstraction layer. + * By default mbed TLS assumes it is used in a non-threaded environment or that + * contexts are not shared between threads. If you do intend to use contexts + * between threads, you will need to enable this layer to prevent race + * conditions. See also our Knowledge Base article about threading: + * https://tls.mbed.org/kb/development/thread-safety-and-multi-threading + * + * Module: library/threading.c + * + * This allows different threading implementations (self-implemented or + * provided). + * + * You will have to enable either MBEDTLS_THREADING_ALT or + * MBEDTLS_THREADING_PTHREAD. + * + * Enable this layer to allow use of mutexes within mbed TLS + */ +//#define MBEDTLS_THREADING_C + +/** + * \def MBEDTLS_TIMING_C + * + * Enable the semi-portable timing interface. + * + * \note The provided implementation only works on POSIX/Unix (including Linux, + * BSD and OS X) and Windows. On other platforms, you can either disable that + * module and provide your own implementations of the callbacks needed by + * \c mbedtls_ssl_set_timer_cb() for DTLS, or leave it enabled and provide + * your own implementation of the whole module by setting + * \c MBEDTLS_TIMING_ALT in the current file. + * + * \note See also our Knowledge Base article about porting to a new + * environment: + * https://tls.mbed.org/kb/how-to/how-do-i-port-mbed-tls-to-a-new-environment-OS + * + * Module: library/timing.c + */ +#define MBEDTLS_TIMING_C + +/** + * \def MBEDTLS_VERSION_C + * + * Enable run-time version information. + * + * Module: library/version.c + * + * This module provides run-time version information. + */ +#define MBEDTLS_VERSION_C + +/** + * \def MBEDTLS_X509_USE_C + * + * Enable X.509 core for using certificates. + * + * Module: library/x509.c + * Caller: library/x509_crl.c + * library/x509_crt.c + * library/x509_csr.c + * + * Requires: MBEDTLS_ASN1_PARSE_C, MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, + * MBEDTLS_PK_PARSE_C + * + * This module is required for the X.509 parsing modules. + */ +#define MBEDTLS_X509_USE_C + +/** + * \def MBEDTLS_X509_CRT_PARSE_C + * + * Enable X.509 certificate parsing. + * + * Module: library/x509_crt.c + * Caller: library/ssl_cli.c + * library/ssl_srv.c + * library/ssl_tls.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 certificate parsing. + */ +#define MBEDTLS_X509_CRT_PARSE_C + +/** + * \def MBEDTLS_X509_CRL_PARSE_C + * + * Enable X.509 CRL parsing. + * + * Module: library/x509_crl.c + * Caller: library/x509_crt.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is required for X.509 CRL parsing. + */ +#define MBEDTLS_X509_CRL_PARSE_C + +/** + * \def MBEDTLS_X509_CSR_PARSE_C + * + * Enable X.509 Certificate Signing Request (CSR) parsing. + * + * Module: library/x509_csr.c + * Caller: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_USE_C + * + * This module is used for reading X.509 certificate request. + */ +#define MBEDTLS_X509_CSR_PARSE_C + +/** + * \def MBEDTLS_X509_CREATE_C + * + * Enable X.509 core for creating certificates. + * + * Module: library/x509_create.c + * + * Requires: MBEDTLS_BIGNUM_C, MBEDTLS_OID_C, MBEDTLS_PK_WRITE_C + * + * This module is the basis for creating X.509 certificates and CSRs. + */ +#define MBEDTLS_X509_CREATE_C + +/** + * \def MBEDTLS_X509_CRT_WRITE_C + * + * Enable creating X.509 certificates. + * + * Module: library/x509_crt_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate creation. + */ +#define MBEDTLS_X509_CRT_WRITE_C + +/** + * \def MBEDTLS_X509_CSR_WRITE_C + * + * Enable creating X.509 Certificate Signing Requests (CSR). + * + * Module: library/x509_csr_write.c + * + * Requires: MBEDTLS_X509_CREATE_C + * + * This module is required for X.509 certificate request writing. + */ +#define MBEDTLS_X509_CSR_WRITE_C + +/* \} name SECTION: mbed TLS modules */ + +/** + * \name SECTION: Module configuration options + * + * This section allows for the setting of module specific sizes and + * configuration options. The default values are already present in the + * relevant header files and should suffice for the regular use cases. + * + * Our advice is to enable options and change their values here + * only if you have a good reason and know the consequences. + * + * Please check the respective header file for documentation on these + * parameters (to prevent duplicate documentation). + * \{ + */ + +/* MPI / BIGNUM options */ +//#define MBEDTLS_MPI_WINDOW_SIZE 6 /**< Maximum window size used. */ +//#define MBEDTLS_MPI_MAX_SIZE 1024 /**< Maximum number of bytes for usable MPIs. */ + +/* CTR_DRBG options */ +//#define MBEDTLS_CTR_DRBG_ENTROPY_LEN 48 /**< Amount of entropy used per seed by default (48 with SHA-512, 32 with SHA-256) */ +//#define MBEDTLS_CTR_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_CTR_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_CTR_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_CTR_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ + +/* HMAC_DRBG options */ +//#define MBEDTLS_HMAC_DRBG_RESEED_INTERVAL 10000 /**< Interval before reseed is performed by default */ +//#define MBEDTLS_HMAC_DRBG_MAX_INPUT 256 /**< Maximum number of additional input bytes */ +//#define MBEDTLS_HMAC_DRBG_MAX_REQUEST 1024 /**< Maximum number of requested bytes per call */ +//#define MBEDTLS_HMAC_DRBG_MAX_SEED_INPUT 384 /**< Maximum size of (re)seed buffer */ + +/* ECP options */ +//#define MBEDTLS_ECP_WINDOW_SIZE 4 /**< Maximum window size used */ +//#define MBEDTLS_ECP_FIXED_POINT_OPTIM 1 /**< Enable fixed-point speed-up */ + +/* Entropy options */ +//#define MBEDTLS_ENTROPY_MAX_SOURCES 20 /**< Maximum number of sources supported */ +//#define MBEDTLS_ENTROPY_MAX_GATHER 128 /**< Maximum amount requested from entropy sources */ +//#define MBEDTLS_ENTROPY_MIN_HARDWARE 32 /**< Default minimum number of bytes required for the hardware entropy source mbedtls_hardware_poll() before entropy is released */ + +/* Memory buffer allocator options */ +//#define MBEDTLS_MEMORY_ALIGN_MULTIPLE 4 /**< Align on multiples of this value */ + +/* Platform options */ +//#define MBEDTLS_PLATFORM_STD_MEM_HDR /**< Header to include if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS is defined. Don't define if no header is needed. */ +//#define MBEDTLS_PLATFORM_STD_CALLOC calloc /**< Default allocator to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_FREE free /**< Default free to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT exit /**< Default exit to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_TIME time /**< Default time to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_STD_FPRINTF fprintf /**< Default fprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_PRINTF printf /**< Default printf to use, can be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_STD_SNPRINTF snprintf /**< Default snprintf to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_SUCCESS 0 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_EXIT_FAILURE 1 /**< Default exit value to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_READ mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_WRITE mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_STD_NV_SEED_FILE "seedfile" /**< Seed file to read/write with default implementation */ + +/* To Use Function Macros MBEDTLS_PLATFORM_C must be enabled */ +/* MBEDTLS_PLATFORM_XXX_MACRO and MBEDTLS_PLATFORM_XXX_ALT cannot both be defined */ +//#define MBEDTLS_PLATFORM_CALLOC_MACRO calloc /**< Default allocator macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_FREE_MACRO free /**< Default free macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_EXIT_MACRO exit /**< Default exit macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_TIME_MACRO time /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_TIME_TYPE_MACRO time_t /**< Default time macro to use, can be undefined. MBEDTLS_HAVE_TIME must be enabled */ +//#define MBEDTLS_PLATFORM_FPRINTF_MACRO fprintf /**< Default fprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_PRINTF_MACRO printf /**< Default printf macro to use, can be undefined */ +/* Note: your snprintf must correctly zero-terminate the buffer! */ +//#define MBEDTLS_PLATFORM_SNPRINTF_MACRO snprintf /**< Default snprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_VSNPRINTF_MACRO vsnprintf /**< Default vsnprintf macro to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_READ_MACRO mbedtls_platform_std_nv_seed_read /**< Default nv_seed_read function to use, can be undefined */ +//#define MBEDTLS_PLATFORM_NV_SEED_WRITE_MACRO mbedtls_platform_std_nv_seed_write /**< Default nv_seed_write function to use, can be undefined */ + +/** \def MBEDTLS_CHECK_RETURN + * + * This macro is used at the beginning of the declaration of a function + * to indicate that its return value should be checked. It should + * instruct the compiler to emit a warning or an error if the function + * is called without checking its return value. + * + * There is a default implementation for popular compilers in platform_util.h. + * You can override the default implementation by defining your own here. + * + * If the implementation here is empty, this will effectively disable the + * checking of functions' return values. + */ +//#define MBEDTLS_CHECK_RETURN __attribute__((__warn_unused_result__)) + +/** \def MBEDTLS_IGNORE_RETURN + * + * This macro requires one argument, which should be a C function call. + * If that function call would cause a #MBEDTLS_CHECK_RETURN warning, this + * warning is suppressed. + */ +//#define MBEDTLS_IGNORE_RETURN( result ) ((void) !(result)) + +/* PSA options */ +/** + * Use HMAC_DRBG with the specified hash algorithm for HMAC_DRBG for the + * PSA crypto subsystem. + * + * If this option is unset: + * - If CTR_DRBG is available, the PSA subsystem uses it rather than HMAC_DRBG. + * - Otherwise, the PSA subsystem uses HMAC_DRBG with either + * #MBEDTLS_MD_SHA512 or #MBEDTLS_MD_SHA256 based on availability and + * on unspecified heuristics. + */ +//#define MBEDTLS_PSA_HMAC_DRBG_MD_TYPE MBEDTLS_MD_SHA256 + +/** \def MBEDTLS_PSA_KEY_SLOT_COUNT + * Restrict the PSA library to supporting a maximum amount of simultaneously + * loaded keys. A loaded key is a key stored by the PSA Crypto core as a + * volatile key, or a persistent key which is loaded temporarily by the + * library as part of a crypto operation in flight. + * + * If this option is unset, the library will fall back to a default value of + * 32 keys. + */ +//#define MBEDTLS_PSA_KEY_SLOT_COUNT 32 + +/* SSL Cache options */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT 86400 /**< 1 day */ +//#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES 50 /**< Maximum entries in cache */ + +/* SSL options */ + +/** \def MBEDTLS_SSL_IN_CONTENT_LEN + * + * Maximum length (in bytes) of incoming plaintext fragments. + * + * This determines the size of the incoming TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * \note When using a value less than the default of 16KB on the client, it is + * recommended to use the Maximum Fragment Length (MFL) extension to + * inform the server about this limitation. On the server, there + * is no supported, standardized way of informing the client about + * restriction on the maximum size of incoming messages, and unless + * the limitation has been communicated by other means, it is recommended + * to only change the outgoing buffer size #MBEDTLS_SSL_OUT_CONTENT_LEN + * while keeping the default value of 16KB for the incoming buffer. + * + * Uncomment to set the maximum plaintext size of the incoming I/O buffer. + */ +//#define MBEDTLS_SSL_IN_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_CID_IN_LEN_MAX + * + * The maximum length of CIDs used for incoming DTLS messages. + * + */ +//#define MBEDTLS_SSL_CID_IN_LEN_MAX 32 + +/** \def MBEDTLS_SSL_CID_OUT_LEN_MAX + * + * The maximum length of CIDs used for outgoing DTLS messages. + * + */ +//#define MBEDTLS_SSL_CID_OUT_LEN_MAX 32 + +/** \def MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY + * + * This option controls the use of record plaintext padding + * in TLS 1.3 and when using the Connection ID extension in DTLS 1.2. + * + * The padding will always be chosen so that the length of the + * padded plaintext is a multiple of the value of this option. + * + * Note: A value of \c 1 means that no padding will be used + * for outgoing records. + * + * Note: On systems lacking division instructions, + * a power of two should be preferred. + */ +//#define MBEDTLS_SSL_CID_TLS1_3_PADDING_GRANULARITY 16 + +/** \def MBEDTLS_SSL_OUT_CONTENT_LEN + * + * Maximum length (in bytes) of outgoing plaintext fragments. + * + * This determines the size of the outgoing TLS I/O buffer in such a way + * that it is capable of holding the specified amount of plaintext data, + * regardless of the protection mechanism used. + * + * It is possible to save RAM by setting a smaller outward buffer, while keeping + * the default inward 16384 byte buffer to conform to the TLS specification. + * + * The minimum required outward buffer size is determined by the handshake + * protocol's usage. Handshaking will fail if the outward buffer is too small. + * The specific size requirement depends on the configured ciphers and any + * certificate data which is sent during the handshake. + * + * Uncomment to set the maximum plaintext size of the outgoing I/O buffer. + */ +//#define MBEDTLS_SSL_OUT_CONTENT_LEN 16384 + +/** \def MBEDTLS_SSL_DTLS_MAX_BUFFERING + * + * Maximum number of heap-allocated bytes for the purpose of + * DTLS handshake message reassembly and future message buffering. + * + * This should be at least 9/8 * MBEDTLS_SSL_IN_CONTENT_LEN + * to account for a reassembled handshake message of maximum size, + * together with its reassembly bitmap. + * + * A value of 2 * MBEDTLS_SSL_IN_CONTENT_LEN (32768 by default) + * should be sufficient for all practical situations as it allows + * to reassembly a large handshake message (such as a certificate) + * while buffering multiple smaller handshake messages. + * + */ +//#define MBEDTLS_SSL_DTLS_MAX_BUFFERING 32768 + +//#define MBEDTLS_PSK_MAX_LEN 32 /**< Max size of TLS pre-shared keys, in bytes (default 256 bits) */ +//#define MBEDTLS_SSL_COOKIE_TIMEOUT 60 /**< Default expiration delay of DTLS cookies, in seconds if HAVE_TIME, or in number of cookies issued */ + +/** \def MBEDTLS_TLS_EXT_CID + * + * At the time of writing, the CID extension has not been assigned its + * final value. Set this configuration option to make Mbed TLS use a + * different value. + * + * A future minor revision of Mbed TLS may change the default value of + * this option to match evolving standards and usage. + */ +//#define MBEDTLS_TLS_EXT_CID 254 + +/** + * Complete list of ciphersuites to use, in order of preference. + * + * \warning No dependency checking is done on that field! This option can only + * be used to restrict the set of available ciphersuites. It is your + * responsibility to make sure the needed modules are active. + * + * Use this to save a few hundred bytes of ROM (default ordering of all + * available ciphersuites) and a few to a few hundred bytes of RAM. + * + * The value below is only an example, not the default. + */ +//#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 + +/* X509 options */ +//#define MBEDTLS_X509_MAX_INTERMEDIATE_CA 8 /**< Maximum number of intermediate CAs in a verification chain. */ +//#define MBEDTLS_X509_MAX_FILE_PATH_LEN 512 /**< Maximum length of a path/filename string in bytes including the null terminator character ('\0'). */ + +/** + * Uncomment the macro to let mbed TLS use your alternate implementation of + * mbedtls_platform_zeroize(). This replaces the default implementation in + * platform_util.c. + * + * mbedtls_platform_zeroize() is a widely used function across the library to + * zero a block of memory. The implementation is expected to be secure in the + * sense that it has been written to prevent the compiler from removing calls + * to mbedtls_platform_zeroize() as part of redundant code elimination + * optimizations. However, it is difficult to guarantee that calls to + * mbedtls_platform_zeroize() will not be optimized by the compiler as older + * versions of the C language standards do not provide a secure implementation + * of memset(). Therefore, MBEDTLS_PLATFORM_ZEROIZE_ALT enables users to + * configure their own implementation of mbedtls_platform_zeroize(), for + * example by using directives specific to their compiler, features from newer + * C standards (e.g using memset_s() in C11) or calling a secure memset() from + * their system (e.g explicit_bzero() in BSD). + */ +//#define MBEDTLS_PLATFORM_ZEROIZE_ALT + +/** + * Uncomment the macro to let Mbed TLS use your alternate implementation of + * mbedtls_platform_gmtime_r(). This replaces the default implementation in + * platform_util.c. + * + * gmtime() is not a thread-safe function as defined in the C standard. The + * library will try to use safer implementations of this function, such as + * gmtime_r() when available. However, if Mbed TLS cannot identify the target + * system, the implementation of mbedtls_platform_gmtime_r() will default to + * using the standard gmtime(). In this case, calls from the library to + * gmtime() will be guarded by the global mutex mbedtls_threading_gmtime_mutex + * if MBEDTLS_THREADING_C is enabled. We recommend that calls from outside the + * library are also guarded with this mutex to avoid race conditions. However, + * if the macro MBEDTLS_PLATFORM_GMTIME_R_ALT is defined, Mbed TLS will + * unconditionally use the implementation for mbedtls_platform_gmtime_r() + * supplied at compile time. + */ +//#define MBEDTLS_PLATFORM_GMTIME_R_ALT + +/** + * Enable the verified implementations of ECDH primitives from Project Everest + * (currently only Curve25519). This feature changes the layout of ECDH + * contexts and therefore is a compatibility break for applications that access + * fields of a mbedtls_ecdh_context structure directly. See also + * MBEDTLS_ECDH_LEGACY_CONTEXT in include/mbedtls/ecdh.h. + */ +//#define MBEDTLS_ECDH_VARIANT_EVEREST_ENABLED + +/* \} name SECTION: Customisation configuration options */ diff --git a/examples/mbedtls/proj.conf b/examples/mbedtls/proj.conf new file mode 100644 index 00000000..034dd7b2 --- /dev/null +++ b/examples/mbedtls/proj.conf @@ -0,0 +1,2 @@ +set(CONFIG_MBEDTLS 1) +set(CONFIG_MBEDTLS_SELF_TEST 1) diff --git a/examples/peripherals/flash/flash_xip_read_write/CMakeLists.txt b/examples/memheap/CMakeLists.txt similarity index 82% rename from examples/peripherals/flash/flash_xip_read_write/CMakeLists.txt rename to examples/memheap/CMakeLists.txt index a4b4b087..bebe5922 100644 --- a/examples/peripherals/flash/flash_xip_read_write/CMakeLists.txt +++ b/examples/memheap/CMakeLists.txt @@ -6,4 +6,4 @@ find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) sdk_set_main_file(main.c) -project(flash_xip_read_write) +project(memheap) diff --git a/examples/memheap/Makefile b/examples/memheap/Makefile new file mode 100644 index 00000000..34b2f3fa --- /dev/null +++ b/examples/memheap/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/memheap/README.md b/examples/memheap/README.md new file mode 100644 index 00000000..1f2e504e --- /dev/null +++ b/examples/memheap/README.md @@ -0,0 +1,44 @@ +# memheap + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/memheap/flash_prog_cfg.ini b/examples/memheap/flash_prog_cfg.ini new file mode 100644 index 00000000..f0300da5 --- /dev/null +++ b/examples/memheap/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/memheap_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/memheap/main.c b/examples/memheap/main.c new file mode 100644 index 00000000..cf4ae93b --- /dev/null +++ b/examples/memheap/main.c @@ -0,0 +1,271 @@ +#include "bflb_mtimer.h" +#include "board.h" +#include "string.h" +#include "stdlib.h" + +#include "mem.h" + +//随机生成堆的参数 +//堆区最大值 +#define MAX_HEAP_REGION 1024 +//堆区最小值 +#define MIN_HEAP_REGION 16 +//堆区倍乘数值 +#define HEAP_BLOCK_SIZE 16 +//堆区数量最大值 +#define MAX_HEAP_REGION_NUM 10 +//堆区数量最小值 +#define MIN_HEAP_REGION_NUM 2 + +//随机申请内存的参数 +//随机申请内存的最大对齐,2^MAX_ALIGN_MALLOC +#define MAX_ALIGN_MALLOC 10 +//随机申请内存的最小对齐,2^MIN_ALIGN_MALLOC +#define MIN_ALIGN_MALLOC 2 +//随机申请的最大内存 +#define MAX_WANT_MALLOC 1024 +//随机申请的最小内存 +#define MIN_WANT_MALLOC 1 +//随机申请内存最大次数 +#define MAX_MALLOC_CNT 1000 + +typedef struct heap_region { + void *addr; + size_t mem_size; +} Mem_Region; + +struct mem_heap_s g_userheap; + +//生成指定范围的随机数 +static inline unsigned int Get_Rand(unsigned int max, unsigned int min) +{ + return random() % (max - min + 1) + min; +} + + +//生成一个随机的堆 +Mem_Region *Mem_Manage_Generate_Rand_Heap(void) +{ + size_t region_num; + Mem_Region *pRegion; + + // region_num = Get_Rand(MAX_HEAP_REGION_NUM, MIN_HEAP_REGION_NUM); + region_num = 1; + pRegion = malloc(sizeof(Mem_Region) * (region_num + 1)); + + if (pRegion == NULL) + return NULL; + + // for (size_t i = 0; i < region_num; i++) { + // size_t region_size = Get_Rand(MAX_HEAP_REGION, MIN_HEAP_REGION) * HEAP_BLOCK_SIZE; + size_t region_size = 50 * 1024; + size_t i = 0; + + void *paddr = malloc(512); //确保内存不连续 + + pRegion[i].addr = malloc(region_size); + pRegion[i].mem_size = region_size; + free(paddr); + // } + + // for (size_t i = 0; i < region_num; i++) { //按地址进行排序，从低到高 + // for (size_t j = i + 1; j < region_num; j++) { + // if (pRegion[i].addr > pRegion[j].addr) { + // Mem_Region buf_region = pRegion[i]; + // pRegion[i] = pRegion[j]; + // pRegion[j] = buf_region; + // } + // } + // } + + pRegion[region_num].addr = NULL; + pRegion[region_num].mem_size = 0; + + return pRegion; +} + +void Mem_Manage_Free_Rand_Heap(Mem_Region *const pHeap) +{ + for (Mem_Region *buf_heap = pHeap; buf_heap->addr != NULL; buf_heap++) { + free(buf_heap->addr); + } + + free(pHeap); +} + +//打印堆的信息 +void Mem_Manage_Show_Heap_Info(Mem_Region *pHeap) +{ + printf("地址\t\t\t大小\r\n"); + for (; pHeap->addr != NULL; pHeap++) { + printf("0x%08x\t\t%d\r\n", (size_t)pHeap->addr, pHeap->mem_size); + } +} +//打印当前内存剩余 +size_t Mem_Manage_Show_Free_Heap(struct meminfo *info) +{ + bflb_mem_usage(&g_userheap, info); + printf("剩余内存：%d\r\n", info->free_size); + printf("内存利用率：%.2f%%\r\n", (info->used_size) * 100.0 / info->total_size); + printf("最大内存块：%d\r\n", info->max_free_size); + // printf("最小内存块：%d\r\n", use_state.min_node_size); + printf("剩余内存块数：%d\r\n", info->free_node); + return info->free_node; +} + +void memtest(void) +{ + Mem_Region *pRegion; + struct meminfo info; + uint64_t max_time = 0; + float avr_time = 0.0; + uint64_t time; + uint64_t time_tmp; + + // while (1) { + size_t heap_num; + printf("生成随机内存堆...\r\n"); + printf("<---------内存堆信息------------>\r\n"); + + pRegion = Mem_Manage_Generate_Rand_Heap(); + + Mem_Manage_Show_Heap_Info(pRegion); + + printf("<-------初始化内存堆--------->\r\n"); + umem_init(&g_userheap, pRegion[0].addr, pRegion[0].mem_size); + + // printf("start块:0x%08x,%d\r\n", (size_t)Mem_Handle.pStart, Mem_Handle.pStart->mem_size); + // printf("end 块:0x%08x,%d\r\n", (size_t)Mem_Handle.pEnd, Mem_Handle.pEnd->mem_size); + printf("总内存:%d\r\n", pRegion[0].mem_size); + printf("<---------初始空闲列表------------>\r\n"); + + heap_num = Mem_Manage_Show_Free_Heap(&info); + + printf("<-------malloc测试------------>\r\n"); + { + void **addr_buf = malloc(MAX_MALLOC_CNT * sizeof(void *)); + size_t *want_size = malloc(MAX_MALLOC_CNT * sizeof(size_t)); + void *buf_addr; + size_t malloc_cnt = 0; + size_t align_size; + size_t buf_size; + + while (malloc_cnt < MAX_MALLOC_CNT) { + align_size = 1 << Get_Rand(MAX_ALIGN_MALLOC, MIN_ALIGN_MALLOC); //确保为2的指数次幂 + want_size[malloc_cnt] = Get_Rand(MAX_WANT_MALLOC, MIN_WANT_MALLOC); + + time_tmp = bflb_mtimer_get_time_us(); + addr_buf[malloc_cnt] = bflb_malloc_align(&g_userheap, align_size, want_size[malloc_cnt]); + time = bflb_mtimer_get_time_us() - time_tmp; + + if (max_time < time) { + max_time = time; + } + avr_time += (float)time; + printf("malloc time %lld us %p\r\n", time, addr_buf[malloc_cnt]); + + if (addr_buf[malloc_cnt] == NULL) { + printf("malloc分配失败!\r\n"); + printf("期望对齐：%d,期望大小：%d\r\n", align_size, want_size[malloc_cnt]); + break; + } + if ((size_t)addr_buf[malloc_cnt] % align_size) { + printf("malloc 对齐出错！\r\n"); + } + + memset(addr_buf[malloc_cnt], malloc_cnt, want_size[malloc_cnt]); + + buf_size = Get_Rand(MAX_WANT_MALLOC, want_size[malloc_cnt]); + buf_addr = bflb_realloc(&g_userheap, addr_buf[malloc_cnt], buf_size); + + if (buf_addr == NULL) { + printf("realloc分配失败!\r\n"); + printf("期望大小：%d\r\n", buf_size); + break; + } + if ((size_t)buf_addr % align_size) { + printf("realloc 对齐出错！%p\r\n", buf_addr); + } + + memset((uint8_t *)buf_addr + want_size[malloc_cnt], malloc_cnt, buf_size - want_size[malloc_cnt]); + addr_buf[malloc_cnt] = buf_addr; + want_size[malloc_cnt] = buf_size; + malloc_cnt++; + } + + avr_time = avr_time / (float)malloc_cnt; + + printf("共分配%d次, 平均malloc耗时%.02fus, 最大耗时%ldus\r\n", malloc_cnt, avr_time, max_time); + printf("<---------测试后空闲列表------------>\r\n"); + Mem_Manage_Show_Free_Heap(&info); + + printf("内存区检查...\r\n"); + for (size_t i = 0; i < malloc_cnt; i++) { + for (size_t j = 0; j < want_size[i]; j++) { + if (((uint8_t *)addr_buf[i])[j] != (uint8_t)i) { + printf("校验出错！\r\n"); + } + } + } + + printf("<---------free测试----------->\r\n"); + for (size_t i = 0; i < malloc_cnt; i++) { + bflb_free(&g_userheap, addr_buf[i]); + } + + free(addr_buf); + free(want_size); + } + + // printf("start块:0x%08x,%d\r\n", (size_t)Mem_Handle.pStart, Mem_Handle.pStart->mem_size); + // printf("end 块:0x%08x,%d\r\n", (size_t)Mem_Handle.pEnd, Mem_Handle.pEnd->mem_size); + printf("总内存:%d\r\n", pRegion[0].mem_size); + printf("<---------内存释放后空闲列表------------>\r\n"); + if (Mem_Manage_Show_Free_Heap(&info) != heap_num) { + printf("算法异常！\r\n"); + } + + Mem_Manage_Free_Rand_Heap(pRegion); + // } +} + +int memheap_test(void) +{ + char *ptr = NULL; + + for (int i = 1;; i++) { + ptr = malloc(i * 128); + + if (ptr != NULL) { + memcpy(ptr, "hello123456789123456789123456789", 33); + printf("ptr :%s\r\n", ptr); + printf("get memory :%d byte\r\n", i * 128); + free(ptr); + printf("free memory :%d byte\r\n", i * 128); + ptr = NULL; + bflb_mtimer_delay_ms(100); + } else { + printf("try to get %d byte memory failed!\r\n", i * 128); + + return -1; + } + } + return 0; +} + +int main(void) +{ + board_init(); + + memtest(); + + if (memheap_test() == -1) { + printf("memheap test fail\r\n"); + while (1) { + } + } + printf("memheap test success\r\n"); + while (1) { + bflb_mtimer_delay_ms(1000); + } +} diff --git a/examples/memheap/proj.conf b/examples/memheap/proj.conf new file mode 100644 index 00000000..6c292125 --- /dev/null +++ b/examples/memheap/proj.conf @@ -0,0 +1 @@ +# set(CONFIG_TLSF 1) \ No newline at end of file diff --git a/examples/peripherals/adc/adc_dma/README.md b/examples/peripherals/adc/adc_dma/README.md new file mode 100644 index 00000000..649dcb1e --- /dev/null +++ b/examples/peripherals/adc/adc_dma/README.md @@ -0,0 +1,44 @@ +# adc_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/adc/adc_dma/flash_prog_cfg.ini b/examples/peripherals/adc/adc_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..9f1bdf53 --- /dev/null +++ b/examples/peripherals/adc/adc_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/adc*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/adc/adc_int/README.md b/examples/peripherals/adc/adc_int/README.md new file mode 100644 index 00000000..e11fb741 --- /dev/null +++ b/examples/peripherals/adc/adc_int/README.md @@ -0,0 +1,43 @@ +# adc_int + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/adc/adc_int/flash_prog_cfg.ini b/examples/peripherals/adc/adc_int/flash_prog_cfg.ini new file mode 100644 index 00000000..9f1bdf53 --- /dev/null +++ b/examples/peripherals/adc/adc_int/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/adc*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/adc/adc_poll/README.md b/examples/peripherals/adc/adc_poll/README.md new file mode 100644 index 00000000..9dba1d10 --- /dev/null +++ b/examples/peripherals/adc/adc_poll/README.md @@ -0,0 +1,44 @@ +# adc_poll + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/adc/adc_poll/flash_prog_cfg.ini b/examples/peripherals/adc/adc_poll/flash_prog_cfg.ini new file mode 100644 index 00000000..9f1bdf53 --- /dev/null +++ b/examples/peripherals/adc/adc_poll/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/adc*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/adc/adc_poll_diff_mode/README.md b/examples/peripherals/adc/adc_poll_diff_mode/README.md new file mode 100644 index 00000000..631f0eb0 --- /dev/null +++ b/examples/peripherals/adc/adc_poll_diff_mode/README.md @@ -0,0 +1,44 @@ +# adc_poll_diff_mode + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/adc/adc_poll_diff_mode/flash_prog_cfg.ini b/examples/peripherals/adc/adc_poll_diff_mode/flash_prog_cfg.ini new file mode 100644 index 00000000..9f1bdf53 --- /dev/null +++ b/examples/peripherals/adc/adc_poll_diff_mode/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/adc*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/adc/adc_tsen/README.md b/examples/peripherals/adc/adc_tsen/README.md new file mode 100644 index 00000000..7c2e207e --- /dev/null +++ b/examples/peripherals/adc/adc_tsen/README.md @@ -0,0 +1,44 @@ +# adc_tsen + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/adc/adc_tsen/flash_prog_cfg.ini b/examples/peripherals/adc/adc_tsen/flash_prog_cfg.ini new file mode 100644 index 00000000..9f1bdf53 --- /dev/null +++ b/examples/peripherals/adc/adc_tsen/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/adc*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/adc/adc_vbat/README.md b/examples/peripherals/adc/adc_vbat/README.md new file mode 100644 index 00000000..4903616d --- /dev/null +++ b/examples/peripherals/adc/adc_vbat/README.md @@ -0,0 +1,44 @@ +# adc_vbat + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/adc/adc_vbat/flash_prog_cfg.ini b/examples/peripherals/adc/adc_vbat/flash_prog_cfg.ini new file mode 100644 index 00000000..9f1bdf53 --- /dev/null +++ b/examples/peripherals/adc/adc_vbat/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/adc*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/cam/cam_crop/README.md b/examples/peripherals/cam/cam_crop/README.md new file mode 100644 index 00000000..953ff2a9 --- /dev/null +++ b/examples/peripherals/cam/cam_crop/README.md @@ -0,0 +1,43 @@ +# cam_crop + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/cam/cam_crop/flash_prog_cfg.ini b/examples/peripherals/cam/cam_crop/flash_prog_cfg.ini new file mode 100644 index 00000000..547f22e3 --- /dev/null +++ b/examples/peripherals/cam/cam_crop/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/cam*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/cam/cam_crop/main.c b/examples/peripherals/cam/cam_crop/main.c index 3ed5e82c..39be4811 100644 --- a/examples/peripherals/cam/cam_crop/main.c +++ b/examples/peripherals/cam/cam_crop/main.c @@ -39,6 +39,7 @@ int main(void) memcpy(&cam_config, sensor_config, IMAGE_SENSOR_INFO_COPY_SIZE); cam_config.with_mjpeg = false; + cam_config.input_source = CAM_INPUT_SOURCE_DVP; cam_config.output_format = CAM_OUTPUT_FORMAT_AUTO; cam_config.output_bufaddr = BFLB_PSRAM_BASE; cam_config.output_bufsize = CROP_WQVGA_X * CROP_WQVGA_Y * 8; diff --git a/examples/peripherals/cam/cam_int/README.md b/examples/peripherals/cam/cam_int/README.md new file mode 100644 index 00000000..d427d739 --- /dev/null +++ b/examples/peripherals/cam/cam_int/README.md @@ -0,0 +1,43 @@ +# cam_int + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/cam/cam_int/flash_prog_cfg.ini b/examples/peripherals/cam/cam_int/flash_prog_cfg.ini new file mode 100644 index 00000000..547f22e3 --- /dev/null +++ b/examples/peripherals/cam/cam_int/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/cam*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/cam/cam_int/main.c b/examples/peripherals/cam/cam_int/main.c index 7c0421f3..5fd32882 100644 --- a/examples/peripherals/cam/cam_int/main.c +++ b/examples/peripherals/cam/cam_int/main.c @@ -47,6 +47,7 @@ int main(void) memcpy(&cam_config, sensor_config, IMAGE_SENSOR_INFO_COPY_SIZE); cam_config.with_mjpeg = false; + cam_config.input_source = CAM_INPUT_SOURCE_DVP; cam_config.output_format = CAM_OUTPUT_FORMAT_AUTO; cam_config.output_bufaddr = BFLB_PSRAM_BASE; cam_config.output_bufsize = cam_config.resolution_x * cam_config.resolution_y * 12; diff --git a/examples/peripherals/cam/cam_normal/README.md b/examples/peripherals/cam/cam_normal/README.md new file mode 100644 index 00000000..5eec3cd3 --- /dev/null +++ b/examples/peripherals/cam/cam_normal/README.md @@ -0,0 +1,43 @@ +# cam_normal + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/cam/cam_normal/flash_prog_cfg.ini b/examples/peripherals/cam/cam_normal/flash_prog_cfg.ini new file mode 100644 index 00000000..547f22e3 --- /dev/null +++ b/examples/peripherals/cam/cam_normal/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/cam*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/cam/cam_normal/main.c b/examples/peripherals/cam/cam_normal/main.c index 1ead8415..64255bc6 100644 --- a/examples/peripherals/cam/cam_normal/main.c +++ b/examples/peripherals/cam/cam_normal/main.c @@ -32,6 +32,7 @@ int main(void) memcpy(&cam_config, sensor_config, IMAGE_SENSOR_INFO_COPY_SIZE); cam_config.with_mjpeg = false; + cam_config.input_source = CAM_INPUT_SOURCE_DVP; cam_config.output_format = CAM_OUTPUT_FORMAT_AUTO; cam_config.output_bufaddr = BFLB_PSRAM_BASE; cam_config.output_bufsize = cam_config.resolution_x * cam_config.resolution_y * 8; diff --git a/examples/peripherals/cam/cam_yuv420/README.md b/examples/peripherals/cam/cam_yuv420/README.md new file mode 100644 index 00000000..b1ed18d1 --- /dev/null +++ b/examples/peripherals/cam/cam_yuv420/README.md @@ -0,0 +1,43 @@ +# cam_yuv420 + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/cam/cam_yuv420/flash_prog_cfg.ini b/examples/peripherals/cam/cam_yuv420/flash_prog_cfg.ini new file mode 100644 index 00000000..547f22e3 --- /dev/null +++ b/examples/peripherals/cam/cam_yuv420/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/cam*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/cam/cam_yuv420/main.c b/examples/peripherals/cam/cam_yuv420/main.c index 25aa0362..4025f8e3 100644 --- a/examples/peripherals/cam/cam_yuv420/main.c +++ b/examples/peripherals/cam/cam_yuv420/main.c @@ -35,6 +35,7 @@ int main(void) /* Init cam0 for Y */ memcpy(&cam_config, sensor_config, IMAGE_SENSOR_INFO_COPY_SIZE); cam_config.with_mjpeg = false; + cam_config.input_source = CAM_INPUT_SOURCE_DVP; cam_config.output_format = CAM_OUTPUT_FORMAT_GRAY; cam_config.output_bufaddr = BFLB_PSRAM_BASE; cam_config.output_bufsize = cam_config.resolution_x * cam_config.resolution_y * 6; diff --git a/examples/peripherals/cks/cks_dma/README.md b/examples/peripherals/cks/cks_dma/README.md new file mode 100644 index 00000000..e9ab3a1c --- /dev/null +++ b/examples/peripherals/cks/cks_dma/README.md @@ -0,0 +1,44 @@ +# cks_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/cks/cks_dma/flash_prog_cfg.ini b/examples/peripherals/cks/cks_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..b586112b --- /dev/null +++ b/examples/peripherals/cks/cks_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/cks*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/cks/cks_normal/README.md b/examples/peripherals/cks/cks_normal/README.md new file mode 100644 index 00000000..356fb43b --- /dev/null +++ b/examples/peripherals/cks/cks_normal/README.md @@ -0,0 +1,44 @@ +# cks_normal + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/cks/cks_normal/flash_prog_cfg.ini b/examples/peripherals/cks/cks_normal/flash_prog_cfg.ini new file mode 100644 index 00000000..b586112b --- /dev/null +++ b/examples/peripherals/cks/cks_normal/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/cks*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/csi/csi_normal/CMakeLists.txt b/examples/peripherals/csi/csi_normal/CMakeLists.txt new file mode 100644 index 00000000..aba55b3c --- /dev/null +++ b/examples/peripherals/csi/csi_normal/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(csi_normal) diff --git a/examples/peripherals/csi/csi_normal/Makefile b/examples/peripherals/csi/csi_normal/Makefile new file mode 100644 index 00000000..43fe42c7 --- /dev/null +++ b/examples/peripherals/csi/csi_normal/Makefile @@ -0,0 +1,14 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl808 +BOARD ?= bl808dk +CPU_ID ?= m0 +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/csi/csi_normal/README.md b/examples/peripherals/csi/csi_normal/README.md new file mode 100644 index 00000000..f5d544e8 --- /dev/null +++ b/examples/peripherals/csi/csi_normal/README.md @@ -0,0 +1,23 @@ +# csi_normal + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL808 | | + +## Compile + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/csi/csi_normal/flash_prog_cfg.ini b/examples/peripherals/csi/csi_normal/flash_prog_cfg.ini new file mode 100644 index 00000000..6e240b77 --- /dev/null +++ b/examples/peripherals/csi/csi_normal/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/csi_normal*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/csi/csi_normal/main.c b/examples/peripherals/csi/csi_normal/main.c new file mode 100644 index 00000000..1f2f3ca7 --- /dev/null +++ b/examples/peripherals/csi/csi_normal/main.c @@ -0,0 +1,73 @@ +#include "bflb_mtimer.h" +#include "bflb_i2c.h" +#include "bflb_cam.h" +#include "bflb_csi.h" +#include "image_sensor.h" +#include "board.h" + +#define CAM_FRAME_COUNT_USE 50 + +static struct bflb_device_s *i2c0; +static struct bflb_device_s *cam0; +static struct bflb_device_s *csi; + +static struct bflb_cam_config_s cam_config; +static struct bflb_csi_config_s csi_config; + +int main(void) +{ + uint32_t i, pic_size; + uint8_t *pic; + struct image_sensor_config_s *sensor_config; + + board_init(); + board_csi_gpio_init(); + + i2c0 = bflb_device_get_by_name("i2c0"); + cam0 = bflb_device_get_by_name("cam0"); + csi = bflb_device_get_by_name("csi"); + + csi_config.lane_number = CSI_LANE_NUMBER_2; + csi_config.tx_clk_escape = 24000000; + csi_config.data_rate = 520000000; + bflb_csi_init(csi, &csi_config); + bflb_csi_start(csi); + + if(image_sensor_scan(i2c0, &sensor_config)){ + printf("\r\nSensor name: %s\r\n", sensor_config->name); + }else{ + printf("\r\nError! Can't identify sensor!\r\n"); + while(1){} + } + + bflb_csi_set_line_threshold(csi, sensor_config->resolution_x, sensor_config->pixel_clock, 80000000); + + memcpy(&cam_config, sensor_config, IMAGE_SENSOR_INFO_COPY_SIZE); + cam_config.with_mjpeg = false; + cam_config.input_source = CAM_INPUT_SOURCE_CSI; + cam_config.output_format = CAM_OUTPUT_FORMAT_AUTO; + cam_config.output_bufaddr = BFLB_PSRAM_BASE; + cam_config.output_bufsize = cam_config.resolution_x * cam_config.resolution_y * 8; + bflb_cam_init(cam0, &cam_config); + bflb_cam_start(cam0); + + for (i = 0; i < CAM_FRAME_COUNT_USE; i++) { + while(bflb_cam_get_frame_count(cam0) == 0){} + pic_size = bflb_cam_get_frame_info(cam0, &pic); + bflb_cam_pop_one_frame(cam0); + printf("pop picture %d: 0x%08x, len: %d\r\n", i, (uint32_t)pic, pic_size); + } + + bflb_cam_stop(cam0); + + //for (i = 0; i < pic_size; i++) { + // printf("%02x", pic[i]); + //} + //printf("\r\n"); + + printf("end\r\n"); + + while (1) { + bflb_mtimer_delay_ms(1000); + } +} diff --git a/examples/peripherals/csi/csi_normal/proj.conf b/examples/peripherals/csi/csi_normal/proj.conf new file mode 100644 index 00000000..f2defa6f --- /dev/null +++ b/examples/peripherals/csi/csi_normal/proj.conf @@ -0,0 +1,3 @@ +set(CONFIG_BSP_IMAGE_SENSOR 1) +set(CONFIG_PSRAM 1) +set(CONFIG_BSP_CSI 1) \ No newline at end of file diff --git a/examples/peripherals/dac/dac_dma/README.md b/examples/peripherals/dac/dac_dma/README.md new file mode 100644 index 00000000..9faf8ca9 --- /dev/null +++ b/examples/peripherals/dac/dac_dma/README.md @@ -0,0 +1,44 @@ +# dac_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/dac/dac_dma/flash_prog_cfg.ini b/examples/peripherals/dac/dac_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..ddc0ef45 --- /dev/null +++ b/examples/peripherals/dac/dac_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/dac*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/dac/dac_polling/README.md b/examples/peripherals/dac/dac_polling/README.md new file mode 100644 index 00000000..7f4812ad --- /dev/null +++ b/examples/peripherals/dac/dac_polling/README.md @@ -0,0 +1,44 @@ +# dac_polling + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/dac/dac_polling/flash_prog_cfg.ini b/examples/peripherals/dac/dac_polling/flash_prog_cfg.ini new file mode 100644 index 00000000..ddc0ef45 --- /dev/null +++ b/examples/peripherals/dac/dac_polling/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/dac*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/dma/dma_normal/README.md b/examples/peripherals/dma/dma_normal/README.md new file mode 100644 index 00000000..58c542e8 --- /dev/null +++ b/examples/peripherals/dma/dma_normal/README.md @@ -0,0 +1,44 @@ +# dma_normal + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in dma0~dma1, should use dma2 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/dma/dma_normal/flash_prog_cfg.ini b/examples/peripherals/dma/dma_normal/flash_prog_cfg.ini new file mode 100644 index 00000000..98d67842 --- /dev/null +++ b/examples/peripherals/dma/dma_normal/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/dma*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/dma/dma_normal_cycle/README.md b/examples/peripherals/dma/dma_normal_cycle/README.md new file mode 100644 index 00000000..304b9356 --- /dev/null +++ b/examples/peripherals/dma/dma_normal_cycle/README.md @@ -0,0 +1,44 @@ +# dma_normal_cycle + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in dma0~dma1, should use dma2 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/dma/dma_normal_cycle/flash_prog_cfg.ini b/examples/peripherals/dma/dma_normal_cycle/flash_prog_cfg.ini new file mode 100644 index 00000000..98d67842 --- /dev/null +++ b/examples/peripherals/dma/dma_normal_cycle/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/dma*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/dma/dma_reduce_or_add/README.md b/examples/peripherals/dma/dma_reduce_or_add/README.md new file mode 100644 index 00000000..89bc48b4 --- /dev/null +++ b/examples/peripherals/dma/dma_reduce_or_add/README.md @@ -0,0 +1,44 @@ +# dma_reduce_or_add + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in dma0~dma1, should use dma2 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/dma/dma_reduce_or_add/flash_prog_cfg.ini b/examples/peripherals/dma/dma_reduce_or_add/flash_prog_cfg.ini new file mode 100644 index 00000000..98d67842 --- /dev/null +++ b/examples/peripherals/dma/dma_reduce_or_add/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/dma*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/efuse/efuse_rw/README.md b/examples/peripherals/efuse/efuse_rw/README.md new file mode 100644 index 00000000..fb96a820 --- /dev/null +++ b/examples/peripherals/efuse/efuse_rw/README.md @@ -0,0 +1,44 @@ +# efuse_rw + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/efuse/efuse_rw/flash_prog_cfg.ini b/examples/peripherals/efuse/efuse_rw/flash_prog_cfg.ini new file mode 100644 index 00000000..e5a0dd47 --- /dev/null +++ b/examples/peripherals/efuse/efuse_rw/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/efuse*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/efuse/efuse_trim/README.md b/examples/peripherals/efuse/efuse_trim/README.md new file mode 100644 index 00000000..027e3349 --- /dev/null +++ b/examples/peripherals/efuse/efuse_trim/README.md @@ -0,0 +1,44 @@ +# efuse_trim + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/efuse/efuse_trim/flash_prog_cfg.ini b/examples/peripherals/efuse/efuse_trim/flash_prog_cfg.ini new file mode 100644 index 00000000..e5a0dd47 --- /dev/null +++ b/examples/peripherals/efuse/efuse_trim/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/efuse*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/emac/emac_basic/README.md b/examples/peripherals/emac/emac_basic/README.md new file mode 100644 index 00000000..70af695a --- /dev/null +++ b/examples/peripherals/emac/emac_basic/README.md @@ -0,0 +1,36 @@ +# emac_basic + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/emac/emac_basic/flash_prog_cfg.ini b/examples/peripherals/emac/emac_basic/flash_prog_cfg.ini new file mode 100644 index 00000000..d38d3fff --- /dev/null +++ b/examples/peripherals/emac/emac_basic/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/lwip_http_server_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/emac/lwip_http_server/FreeRTOSConfig.h b/examples/peripherals/emac/lwip_http_server/FreeRTOSConfig.h index 409ade00..c8973483 100644 --- a/examples/peripherals/emac/lwip_http_server/FreeRTOSConfig.h +++ b/examples/peripherals/emac/lwip_http_server/FreeRTOSConfig.h @@ -39,25 +39,29 @@ * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -#include "stdio.h" -#ifdef BL702 +#if defined(BL602) || defined(BL702) || defined(BL702L) #define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) #define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) #else -#define configMTIME_BASE_ADDRESS (0xE0000000UL + 0xBFF8UL) -#define configMTIMECMP_BASE_ADDRESS (0xE0000000UL + 0x4000UL) +#if __riscv_xlen == 64 +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) +#endif #endif #define configSUPPORT_STATIC_ALLOCATION 1 #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 +#define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ ((uint32_t)(1 * 1000 * 1000)) #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ -#define configTOTAL_HEAP_SIZE ((size_t)15 * 1024) +#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024) #define configMAX_TASK_NAME_LEN (16) #define configUSE_TRACE_FACILITY 1 #define configUSE_STATS_FORMATTING_FUNCTIONS 1 @@ -68,21 +72,22 @@ #define configCHECK_FOR_STACK_OVERFLOW 2 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_APPLICATION_TASK_TAG 1 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_TICKLESS_IDLE 0 +#define configUSE_POSIX_ERRNO 1 /* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) /* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) -#define configTIMER_QUEUE_LENGTH 8 -#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) /* Task priorities. Allow these to be overridden. */ #ifndef uartPRIMARY_PRIORITY @@ -108,6 +113,9 @@ to exclude the API function. */ header file. */ void vApplicationMallocFailedHook(void); void vAssertCalled(void); + +#include + #define configASSERT(x) \ if ((x) == 0) { \ printf("file [%s]\r\n", __FILE__); \ diff --git a/examples/peripherals/emac/lwip_http_server/README.md b/examples/peripherals/emac/lwip_http_server/README.md new file mode 100644 index 00000000..3e9f543e --- /dev/null +++ b/examples/peripherals/emac/lwip_http_server/README.md @@ -0,0 +1,36 @@ +# lwip_http_server + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/emac/lwip_http_server/flash_prog_cfg.ini b/examples/peripherals/emac/lwip_http_server/flash_prog_cfg.ini new file mode 100644 index 00000000..85d26932 --- /dev/null +++ b/examples/peripherals/emac/lwip_http_server/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/emac_basic_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/emac/lwip_http_server/lwipopts.h b/examples/peripherals/emac/lwip_http_server/lwipopts.h new file mode 100644 index 00000000..7bb966f6 --- /dev/null +++ b/examples/peripherals/emac/lwip_http_server/lwipopts.h @@ -0,0 +1,253 @@ +/** + * Copyright (c) 2022 Bouffalolab team + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + ****************************************************************************** + */ + +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#define NO_SYS 0 + +/* ---------- Memory options ---------- */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +#define MEM_ALIGNMENT 4 + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#define MEM_SIZE (15 * 1024) + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#define MEMP_NUM_PBUF 10 +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#define MEMP_NUM_UDP_PCB 6 +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#define MEMP_NUM_TCP_PCB 10 +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#define MEMP_NUM_TCP_PCB_LISTEN 5 +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#define MEMP_NUM_SYS_TIMEOUT 10 + +/* ---------- IPv4 options ---------- */ +#define LWIP_IPV4 1 + +/* ---------- TCP options ---------- */ +#define LWIP_TCP 1 +#define TCP_TTL 255 + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#define TCP_QUEUE_OOSEQ 0 + +/* TCP Maximum segment size. */ +#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */ + +/* TCP sender buffer space (bytes). */ +#define TCP_SND_BUF (4 * TCP_MSS) + +/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */ + +#define TCP_SND_QUEUELEN (2 * TCP_SND_BUF / TCP_MSS) + +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#define MEMP_NUM_TCP_SEG TCP_SND_QUEUELEN + +/* TCP receive window. */ +#define TCP_WND (2 * TCP_MSS) + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + @ note: used to allocate Tx pbufs only + mix pbuf size is (TCP_WND / TCP_MSS) */ +#define PBUF_POOL_SIZE (TCP_WND / TCP_MSS) + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +#define PBUF_POOL_BUFSIZE 1524 + +/* LWIP_SUPPORT_CUSTOM_PBUF == 1: to pass directly MAC Rx buffers to the stack + no copy is needed */ +#define LWIP_SUPPORT_CUSTOM_PBUF 1 + +/* ---------- ICMP options ---------- */ +#define LWIP_ICMP 1 + +/* ---------- DHCP options ---------- */ +#define LWIP_DHCP 0 + +/* ---------- UDP options ---------- */ +#define LWIP_UDP 1 +#define UDP_TTL 255 + +/* ---------- Statistics options ---------- */ +#define LWIP_STATS 0 + +/* ---------- link callback options ---------- */ +/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#define LWIP_NETIF_LINK_CALLBACK 1 + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/* LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from application buffers to pbufs. */ +#define LWIP_CHECKSUM_ON_COPY 0 + +#ifdef CHECKSUM_BY_HARDWARE +/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 0 +/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 0 +/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 0 +/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 0 +/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 0 +/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 0 +/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/ +#define CHECKSUM_GEN_ICMP 0 +#else +/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 1 +/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 1 +/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 1 +/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 1 +/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 1 +/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 1 +/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/ +#define CHECKSUM_GEN_ICMP 1 +#define CHECKSUM_CHECK_ICMP 1 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 1 + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 1 + +/* ---------------- httpd options --------------- */ +#define HTTPD_USE_CUSTOM_FSDATA 1 + +// /** Set this to 1 to support CGI (old style).*/ +// #define LWIP_HTTPD_CGI 1 + +// /** Set this to 1 to support SSI (Server-Side-Includes)*/ +// #define LWIP_HTTPD_SSI 0 + +// /** Set this to 1 to support HTTP POST */ +// #define LWIP_HTTPD_SUPPORT_POST 0 + +// /** Set this to 0 to not send the SSI tag (default is on, so the tag will +// * be sent in the HTML page */ +// #define LWIP_HTTPD_SSI_INCLUDE_TAG 0 + +// /** This is the size of a static buffer used when URIs end with '/'. +// * In this buffer, the directory requested is concatenated with all the +// * configured default file names. +// * Set to 0 to disable checking default filenames on non-root directories. +// */ +// #define LWIP_HTTPD_MAX_REQUEST_URI_LEN 256 + +// /** The server port for HTTPD to use */ +// #define HTTPD_SERVER_PORT LWIP_IANA_PORT_HTTP + +/* + ---------------------------------------- + ---------- Lwip Debug options ---------- + ---------------------------------------- +*/ +#define LWIP_DEBUG LWIP_DBG_OFF +#define ETHARP_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define SOCKET_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define HTTPD_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define IP_DEBUG LWIP_DBG_OFF + +/* + --------------------------------- + ---------- OS options ---------- + --------------------------------- +*/ + +#define TCPIP_THREAD_NAME "TCP/IP" +#define TCPIP_THREAD_STACKSIZE 1024 +#define TCPIP_MBOX_SIZE 50 +#define DEFAULT_UDP_RECVMBOX_SIZE 100 +#define DEFAULT_TCP_RECVMBOX_SIZE 100 +#define DEFAULT_ACCEPTMBOX_SIZE 100 +#define DEFAULT_THREAD_STACKSIZE 512 +#define TCPIP_THREAD_PRIO osPriorityHigh + +#endif /* __LWIPOPTS_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/peripherals/emac/lwip_http_server/main.c b/examples/peripherals/emac/lwip_http_server/main.c index 4b654c26..d70718e3 100644 --- a/examples/peripherals/emac/lwip_http_server/main.c +++ b/examples/peripherals/emac/lwip_http_server/main.c @@ -44,14 +44,6 @@ /* global network interface struct define */ struct netif gnetif; -/* free rtos heap define */ -static uint8_t freertos_heap[configTOTAL_HEAP_SIZE]; -static HeapRegion_t xHeapRegions[] = { - { (uint8_t *)freertos_heap, 0 }, - { NULL, 0 }, /* Terminates the array. */ - { NULL, 0 } /* Terminates the array. */ -}; - static StackType_t start_task_stack[512]; static StaticTask_t start_task_handle; @@ -132,9 +124,6 @@ int main(void) board_emac_gpio_init(); printf("EMAC lwip http test case !\r\n"); - /* freertos heap define */ - xHeapRegions[0].xSizeInBytes = configTOTAL_HEAP_SIZE; - vPortDefineHeapRegions(xHeapRegions); // ethernet_lwip_init(); vSemaphoreCreateBinary(console_lock); diff --git a/examples/peripherals/emac/lwip_http_server/proj.conf b/examples/peripherals/emac/lwip_http_server/proj.conf index dac65ad2..600d19c6 100644 --- a/examples/peripherals/emac/lwip_http_server/proj.conf +++ b/examples/peripherals/emac/lwip_http_server/proj.conf @@ -3,4 +3,4 @@ set(CONFIG_BFLOG 0) set(CONFIG_FREERTOS 1) set(CONFIG_LWIP 1) -set(CONFIG_ETHERNET 1) \ No newline at end of file +set(CONFIG_ETHERNET 1) diff --git a/examples/peripherals/emac/lwip_tcp/FreeRTOSConfig.h b/examples/peripherals/emac/lwip_tcp/FreeRTOSConfig.h index 409ade00..c8973483 100644 --- a/examples/peripherals/emac/lwip_tcp/FreeRTOSConfig.h +++ b/examples/peripherals/emac/lwip_tcp/FreeRTOSConfig.h @@ -39,25 +39,29 @@ * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -#include "stdio.h" -#ifdef BL702 +#if defined(BL602) || defined(BL702) || defined(BL702L) #define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) #define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) #else -#define configMTIME_BASE_ADDRESS (0xE0000000UL + 0xBFF8UL) -#define configMTIMECMP_BASE_ADDRESS (0xE0000000UL + 0x4000UL) +#if __riscv_xlen == 64 +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) +#endif #endif #define configSUPPORT_STATIC_ALLOCATION 1 #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 +#define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ ((uint32_t)(1 * 1000 * 1000)) #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ -#define configTOTAL_HEAP_SIZE ((size_t)15 * 1024) +#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024) #define configMAX_TASK_NAME_LEN (16) #define configUSE_TRACE_FACILITY 1 #define configUSE_STATS_FORMATTING_FUNCTIONS 1 @@ -68,21 +72,22 @@ #define configCHECK_FOR_STACK_OVERFLOW 2 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_APPLICATION_TASK_TAG 1 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_TICKLESS_IDLE 0 +#define configUSE_POSIX_ERRNO 1 /* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) /* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) -#define configTIMER_QUEUE_LENGTH 8 -#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) /* Task priorities. Allow these to be overridden. */ #ifndef uartPRIMARY_PRIORITY @@ -108,6 +113,9 @@ to exclude the API function. */ header file. */ void vApplicationMallocFailedHook(void); void vAssertCalled(void); + +#include + #define configASSERT(x) \ if ((x) == 0) { \ printf("file [%s]\r\n", __FILE__); \ diff --git a/examples/peripherals/emac/lwip_tcp/README.md b/examples/peripherals/emac/lwip_tcp/README.md new file mode 100644 index 00000000..652e3f2a --- /dev/null +++ b/examples/peripherals/emac/lwip_tcp/README.md @@ -0,0 +1,36 @@ +# lwip_tcp + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/emac/lwip_tcp/flash_prog_cfg.ini b/examples/peripherals/emac/lwip_tcp/flash_prog_cfg.ini new file mode 100644 index 00000000..1e71f9e8 --- /dev/null +++ b/examples/peripherals/emac/lwip_tcp/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/lwip_tcp_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/emac/lwip_tcp/lwipopts.h b/examples/peripherals/emac/lwip_tcp/lwipopts.h new file mode 100644 index 00000000..7bb966f6 --- /dev/null +++ b/examples/peripherals/emac/lwip_tcp/lwipopts.h @@ -0,0 +1,253 @@ +/** + * Copyright (c) 2022 Bouffalolab team + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + ****************************************************************************** + */ + +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#define NO_SYS 0 + +/* ---------- Memory options ---------- */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +#define MEM_ALIGNMENT 4 + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#define MEM_SIZE (15 * 1024) + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#define MEMP_NUM_PBUF 10 +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#define MEMP_NUM_UDP_PCB 6 +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#define MEMP_NUM_TCP_PCB 10 +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#define MEMP_NUM_TCP_PCB_LISTEN 5 +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#define MEMP_NUM_SYS_TIMEOUT 10 + +/* ---------- IPv4 options ---------- */ +#define LWIP_IPV4 1 + +/* ---------- TCP options ---------- */ +#define LWIP_TCP 1 +#define TCP_TTL 255 + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#define TCP_QUEUE_OOSEQ 0 + +/* TCP Maximum segment size. */ +#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */ + +/* TCP sender buffer space (bytes). */ +#define TCP_SND_BUF (4 * TCP_MSS) + +/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */ + +#define TCP_SND_QUEUELEN (2 * TCP_SND_BUF / TCP_MSS) + +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#define MEMP_NUM_TCP_SEG TCP_SND_QUEUELEN + +/* TCP receive window. */ +#define TCP_WND (2 * TCP_MSS) + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + @ note: used to allocate Tx pbufs only + mix pbuf size is (TCP_WND / TCP_MSS) */ +#define PBUF_POOL_SIZE (TCP_WND / TCP_MSS) + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +#define PBUF_POOL_BUFSIZE 1524 + +/* LWIP_SUPPORT_CUSTOM_PBUF == 1: to pass directly MAC Rx buffers to the stack + no copy is needed */ +#define LWIP_SUPPORT_CUSTOM_PBUF 1 + +/* ---------- ICMP options ---------- */ +#define LWIP_ICMP 1 + +/* ---------- DHCP options ---------- */ +#define LWIP_DHCP 0 + +/* ---------- UDP options ---------- */ +#define LWIP_UDP 1 +#define UDP_TTL 255 + +/* ---------- Statistics options ---------- */ +#define LWIP_STATS 0 + +/* ---------- link callback options ---------- */ +/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#define LWIP_NETIF_LINK_CALLBACK 1 + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/* LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from application buffers to pbufs. */ +#define LWIP_CHECKSUM_ON_COPY 0 + +#ifdef CHECKSUM_BY_HARDWARE +/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 0 +/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 0 +/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 0 +/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 0 +/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 0 +/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 0 +/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/ +#define CHECKSUM_GEN_ICMP 0 +#else +/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 1 +/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 1 +/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 1 +/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 1 +/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 1 +/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 1 +/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/ +#define CHECKSUM_GEN_ICMP 1 +#define CHECKSUM_CHECK_ICMP 1 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 1 + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 1 + +/* ---------------- httpd options --------------- */ +#define HTTPD_USE_CUSTOM_FSDATA 1 + +// /** Set this to 1 to support CGI (old style).*/ +// #define LWIP_HTTPD_CGI 1 + +// /** Set this to 1 to support SSI (Server-Side-Includes)*/ +// #define LWIP_HTTPD_SSI 0 + +// /** Set this to 1 to support HTTP POST */ +// #define LWIP_HTTPD_SUPPORT_POST 0 + +// /** Set this to 0 to not send the SSI tag (default is on, so the tag will +// * be sent in the HTML page */ +// #define LWIP_HTTPD_SSI_INCLUDE_TAG 0 + +// /** This is the size of a static buffer used when URIs end with '/'. +// * In this buffer, the directory requested is concatenated with all the +// * configured default file names. +// * Set to 0 to disable checking default filenames on non-root directories. +// */ +// #define LWIP_HTTPD_MAX_REQUEST_URI_LEN 256 + +// /** The server port for HTTPD to use */ +// #define HTTPD_SERVER_PORT LWIP_IANA_PORT_HTTP + +/* + ---------------------------------------- + ---------- Lwip Debug options ---------- + ---------------------------------------- +*/ +#define LWIP_DEBUG LWIP_DBG_OFF +#define ETHARP_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define SOCKET_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define HTTPD_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define IP_DEBUG LWIP_DBG_OFF + +/* + --------------------------------- + ---------- OS options ---------- + --------------------------------- +*/ + +#define TCPIP_THREAD_NAME "TCP/IP" +#define TCPIP_THREAD_STACKSIZE 1024 +#define TCPIP_MBOX_SIZE 50 +#define DEFAULT_UDP_RECVMBOX_SIZE 100 +#define DEFAULT_TCP_RECVMBOX_SIZE 100 +#define DEFAULT_ACCEPTMBOX_SIZE 100 +#define DEFAULT_THREAD_STACKSIZE 512 +#define TCPIP_THREAD_PRIO osPriorityHigh + +#endif /* __LWIPOPTS_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/peripherals/emac/lwip_tcp/main.c b/examples/peripherals/emac/lwip_tcp/main.c index 09c26f0b..0c2dd478 100644 --- a/examples/peripherals/emac/lwip_tcp/main.c +++ b/examples/peripherals/emac/lwip_tcp/main.c @@ -43,14 +43,6 @@ /* global network interface struct define */ struct netif gnetif; -/* free rtos heap define */ -static uint8_t freertos_heap[configTOTAL_HEAP_SIZE]; -static HeapRegion_t xHeapRegions[] = { - { (uint8_t *)freertos_heap, 0 }, - { NULL, 0 }, /* Terminates the array. */ - { NULL, 0 } /* Terminates the array. */ -}; - /* For emac tx and rx buffer,we put here to make controlling it's size easy */ #define ETH_RXBUFNB 5 #define ETH_TXBUFNB 5 @@ -118,9 +110,6 @@ int main(void) board_emac_gpio_init(); printf("EMAC lwip test case !\r\n"); - /* freertos heap define */ - xHeapRegions[0].xSizeInBytes = configTOTAL_HEAP_SIZE; - vPortDefineHeapRegions(xHeapRegions); ethernet_lwip_init(); diff --git a/examples/peripherals/emac/lwip_tcp/proj.conf b/examples/peripherals/emac/lwip_tcp/proj.conf index dac65ad2..600d19c6 100644 --- a/examples/peripherals/emac/lwip_tcp/proj.conf +++ b/examples/peripherals/emac/lwip_tcp/proj.conf @@ -3,4 +3,4 @@ set(CONFIG_BFLOG 0) set(CONFIG_FREERTOS 1) set(CONFIG_LWIP 1) -set(CONFIG_ETHERNET 1) \ No newline at end of file +set(CONFIG_ETHERNET 1) diff --git a/examples/peripherals/emac/lwip_udp/FreeRTOSConfig.h b/examples/peripherals/emac/lwip_udp/FreeRTOSConfig.h index 409ade00..c8973483 100644 --- a/examples/peripherals/emac/lwip_udp/FreeRTOSConfig.h +++ b/examples/peripherals/emac/lwip_udp/FreeRTOSConfig.h @@ -39,25 +39,29 @@ * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -#include "stdio.h" -#ifdef BL702 +#if defined(BL602) || defined(BL702) || defined(BL702L) #define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) #define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) #else -#define configMTIME_BASE_ADDRESS (0xE0000000UL + 0xBFF8UL) -#define configMTIMECMP_BASE_ADDRESS (0xE0000000UL + 0x4000UL) +#if __riscv_xlen == 64 +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) +#endif #endif #define configSUPPORT_STATIC_ALLOCATION 1 #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 -#define configUSE_TICK_HOOK 1 +#define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ ((uint32_t)(1 * 1000 * 1000)) #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ -#define configTOTAL_HEAP_SIZE ((size_t)15 * 1024) +#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024) #define configMAX_TASK_NAME_LEN (16) #define configUSE_TRACE_FACILITY 1 #define configUSE_STATS_FORMATTING_FUNCTIONS 1 @@ -68,21 +72,22 @@ #define configCHECK_FOR_STACK_OVERFLOW 2 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_APPLICATION_TASK_TAG 1 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_TICKLESS_IDLE 0 +#define configUSE_POSIX_ERRNO 1 /* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) /* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) -#define configTIMER_QUEUE_LENGTH 8 -#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) /* Task priorities. Allow these to be overridden. */ #ifndef uartPRIMARY_PRIORITY @@ -108,6 +113,9 @@ to exclude the API function. */ header file. */ void vApplicationMallocFailedHook(void); void vAssertCalled(void); + +#include + #define configASSERT(x) \ if ((x) == 0) { \ printf("file [%s]\r\n", __FILE__); \ diff --git a/examples/peripherals/emac/lwip_udp/README.md b/examples/peripherals/emac/lwip_udp/README.md new file mode 100644 index 00000000..dc2c3c17 --- /dev/null +++ b/examples/peripherals/emac/lwip_udp/README.md @@ -0,0 +1,36 @@ +# lwip_udp + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/emac/lwip_udp/flash_prog_cfg.ini b/examples/peripherals/emac/lwip_udp/flash_prog_cfg.ini new file mode 100644 index 00000000..b7b3fa74 --- /dev/null +++ b/examples/peripherals/emac/lwip_udp/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/lwip_udp_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/emac/lwip_udp/lwipopts.h b/examples/peripherals/emac/lwip_udp/lwipopts.h new file mode 100644 index 00000000..7bb966f6 --- /dev/null +++ b/examples/peripherals/emac/lwip_udp/lwipopts.h @@ -0,0 +1,253 @@ +/** + * Copyright (c) 2022 Bouffalolab team + * Copyright (c) 2001-2004 Swedish Institute of Computer Science. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT + * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + * This file is part of the lwIP TCP/IP stack. + * + * Author: Adam Dunkels + ****************************************************************************** + */ + +#ifndef __LWIPOPTS_H__ +#define __LWIPOPTS_H__ + +/** + * NO_SYS==1: Provides VERY minimal functionality. Otherwise, + * use lwIP facilities. + */ +#define NO_SYS 0 + +/* ---------- Memory options ---------- */ +/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which + lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2 + byte alignment -> define MEM_ALIGNMENT to 2. */ +#define MEM_ALIGNMENT 4 + +/* MEM_SIZE: the size of the heap memory. If the application will send +a lot of data that needs to be copied, this should be set high. */ +#define MEM_SIZE (15 * 1024) + +/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application + sends a lot of data out of ROM (or other static memory), this + should be set high. */ +#define MEMP_NUM_PBUF 10 +/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One + per active UDP "connection". */ +#define MEMP_NUM_UDP_PCB 6 +/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP + connections. */ +#define MEMP_NUM_TCP_PCB 10 +/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP + connections. */ +#define MEMP_NUM_TCP_PCB_LISTEN 5 +/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active + timeouts. */ +#define MEMP_NUM_SYS_TIMEOUT 10 + +/* ---------- IPv4 options ---------- */ +#define LWIP_IPV4 1 + +/* ---------- TCP options ---------- */ +#define LWIP_TCP 1 +#define TCP_TTL 255 + +/* Controls if TCP should queue segments that arrive out of + order. Define to 0 if your device is low on memory. */ +#define TCP_QUEUE_OOSEQ 0 + +/* TCP Maximum segment size. */ +#define TCP_MSS (1500 - 40) /* TCP_MSS = (Ethernet MTU - IP header size - TCP header size) */ + +/* TCP sender buffer space (bytes). */ +#define TCP_SND_BUF (4 * TCP_MSS) + +/* TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least + as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work. */ + +#define TCP_SND_QUEUELEN (2 * TCP_SND_BUF / TCP_MSS) + +/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP + segments. */ +#define MEMP_NUM_TCP_SEG TCP_SND_QUEUELEN + +/* TCP receive window. */ +#define TCP_WND (2 * TCP_MSS) + +/* ---------- Pbuf options ---------- */ +/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. + @ note: used to allocate Tx pbufs only + mix pbuf size is (TCP_WND / TCP_MSS) */ +#define PBUF_POOL_SIZE (TCP_WND / TCP_MSS) + +/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */ +#define PBUF_POOL_BUFSIZE 1524 + +/* LWIP_SUPPORT_CUSTOM_PBUF == 1: to pass directly MAC Rx buffers to the stack + no copy is needed */ +#define LWIP_SUPPORT_CUSTOM_PBUF 1 + +/* ---------- ICMP options ---------- */ +#define LWIP_ICMP 1 + +/* ---------- DHCP options ---------- */ +#define LWIP_DHCP 0 + +/* ---------- UDP options ---------- */ +#define LWIP_UDP 1 +#define UDP_TTL 255 + +/* ---------- Statistics options ---------- */ +#define LWIP_STATS 0 + +/* ---------- link callback options ---------- */ +/* LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface + * whenever the link changes (i.e., link down) + */ +#define LWIP_NETIF_LINK_CALLBACK 1 + +/* + -------------------------------------- + ---------- Checksum options ---------- + -------------------------------------- +*/ +/* LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from application buffers to pbufs. */ +#define LWIP_CHECKSUM_ON_COPY 0 + +#ifdef CHECKSUM_BY_HARDWARE +/* CHECKSUM_GEN_IP==0: Generate checksums by hardware for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 0 +/* CHECKSUM_GEN_UDP==0: Generate checksums by hardware for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 0 +/* CHECKSUM_GEN_TCP==0: Generate checksums by hardware for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 0 +/* CHECKSUM_CHECK_IP==0: Check checksums by hardware for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 0 +/* CHECKSUM_CHECK_UDP==0: Check checksums by hardware for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 0 +/* CHECKSUM_CHECK_TCP==0: Check checksums by hardware for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 0 +/* CHECKSUM_CHECK_ICMP==0: Check checksums by hardware for incoming ICMP packets.*/ +#define CHECKSUM_GEN_ICMP 0 +#else +/* CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.*/ +#define CHECKSUM_GEN_IP 1 +/* CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.*/ +#define CHECKSUM_GEN_UDP 1 +/* CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.*/ +#define CHECKSUM_GEN_TCP 1 +/* CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.*/ +#define CHECKSUM_CHECK_IP 1 +/* CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.*/ +#define CHECKSUM_CHECK_UDP 1 +/* CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.*/ +#define CHECKSUM_CHECK_TCP 1 +/* CHECKSUM_CHECK_ICMP==1: Check checksums by hardware for incoming ICMP packets.*/ +#define CHECKSUM_GEN_ICMP 1 +#define CHECKSUM_CHECK_ICMP 1 +#endif + +/* + ---------------------------------------------- + ---------- Sequential layer options ---------- + ---------------------------------------------- +*/ +/** + * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c) + */ +#define LWIP_NETCONN 1 + +/* + ------------------------------------ + ---------- Socket options ---------- + ------------------------------------ +*/ +/** + * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c) + */ +#define LWIP_SOCKET 1 + +/* ---------------- httpd options --------------- */ +#define HTTPD_USE_CUSTOM_FSDATA 1 + +// /** Set this to 1 to support CGI (old style).*/ +// #define LWIP_HTTPD_CGI 1 + +// /** Set this to 1 to support SSI (Server-Side-Includes)*/ +// #define LWIP_HTTPD_SSI 0 + +// /** Set this to 1 to support HTTP POST */ +// #define LWIP_HTTPD_SUPPORT_POST 0 + +// /** Set this to 0 to not send the SSI tag (default is on, so the tag will +// * be sent in the HTML page */ +// #define LWIP_HTTPD_SSI_INCLUDE_TAG 0 + +// /** This is the size of a static buffer used when URIs end with '/'. +// * In this buffer, the directory requested is concatenated with all the +// * configured default file names. +// * Set to 0 to disable checking default filenames on non-root directories. +// */ +// #define LWIP_HTTPD_MAX_REQUEST_URI_LEN 256 + +// /** The server port for HTTPD to use */ +// #define HTTPD_SERVER_PORT LWIP_IANA_PORT_HTTP + +/* + ---------------------------------------- + ---------- Lwip Debug options ---------- + ---------------------------------------- +*/ +#define LWIP_DEBUG LWIP_DBG_OFF +#define ETHARP_DEBUG LWIP_DBG_OFF +#define ICMP_DEBUG LWIP_DBG_OFF +#define TCPIP_DEBUG LWIP_DBG_OFF +#define TCP_DEBUG LWIP_DBG_OFF +#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF +#define UDP_DEBUG LWIP_DBG_OFF +#define SOCKET_DEBUG LWIP_DBG_OFF +#define API_LIB_DEBUG LWIP_DBG_OFF +#define HTTPD_DEBUG LWIP_DBG_OFF +#define PBUF_DEBUG LWIP_DBG_OFF +#define IP_DEBUG LWIP_DBG_OFF + +/* + --------------------------------- + ---------- OS options ---------- + --------------------------------- +*/ + +#define TCPIP_THREAD_NAME "TCP/IP" +#define TCPIP_THREAD_STACKSIZE 1024 +#define TCPIP_MBOX_SIZE 50 +#define DEFAULT_UDP_RECVMBOX_SIZE 100 +#define DEFAULT_TCP_RECVMBOX_SIZE 100 +#define DEFAULT_ACCEPTMBOX_SIZE 100 +#define DEFAULT_THREAD_STACKSIZE 512 +#define TCPIP_THREAD_PRIO osPriorityHigh + +#endif /* __LWIPOPTS_H__ */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/examples/peripherals/emac/lwip_udp/main.c b/examples/peripherals/emac/lwip_udp/main.c index 15df26cc..15cc25cd 100644 --- a/examples/peripherals/emac/lwip_udp/main.c +++ b/examples/peripherals/emac/lwip_udp/main.c @@ -42,14 +42,6 @@ /* global network interface struct define */ struct netif gnetif; -/* free rtos heap define */ -static uint8_t freertos_heap[configTOTAL_HEAP_SIZE]; -static HeapRegion_t xHeapRegions[] = { - { (uint8_t *)freertos_heap, 0 }, - { NULL, 0 }, /* Terminates the array. */ - { NULL, 0 } /* Terminates the array. */ -}; - /* For emac tx and rx buffer,we put here to make controlling it's size easy */ #define ETH_RXBUFNB 5 #define ETH_TXBUFNB 5 @@ -117,9 +109,6 @@ int main(void) board_emac_gpio_init(); printf("EMAC lwip test case !\r\n"); - /* freertos heap define */ - xHeapRegions[0].xSizeInBytes = configTOTAL_HEAP_SIZE; - vPortDefineHeapRegions(xHeapRegions); ethernet_lwip_init(); // bflb_emac_stop_tx(); diff --git a/examples/peripherals/emac/lwip_udp/proj.conf b/examples/peripherals/emac/lwip_udp/proj.conf index dac65ad2..600d19c6 100644 --- a/examples/peripherals/emac/lwip_udp/proj.conf +++ b/examples/peripherals/emac/lwip_udp/proj.conf @@ -3,4 +3,4 @@ set(CONFIG_BFLOG 0) set(CONFIG_FREERTOS 1) set(CONFIG_LWIP 1) -set(CONFIG_ETHERNET 1) \ No newline at end of file +set(CONFIG_ETHERNET 1) diff --git a/examples/peripherals/flash/flash_dma/README.md b/examples/peripherals/flash/flash_dma/README.md new file mode 100644 index 00000000..5fb79d33 --- /dev/null +++ b/examples/peripherals/flash/flash_dma/README.md @@ -0,0 +1,44 @@ +# flash_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/flash/flash_dma/flash_prog_cfg.ini b/examples/peripherals/flash/flash_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..0771813d --- /dev/null +++ b/examples/peripherals/flash/flash_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/flash*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/flash/flash_dma/main.c b/examples/peripherals/flash/flash_dma/main.c index aed1418c..37f22670 100644 --- a/examples/peripherals/flash/flash_dma/main.c +++ b/examples/peripherals/flash/flash_dma/main.c @@ -2,10 +2,16 @@ #include "bflb_dma.h" #include "board.h" + +#define FLASH_RW_START_ADDR 0x10000 +#define DMA_FLASH_ADDR_OFFSET 28 /* 0 or 28 for unaligned case */ #define DMA_BUFFER_LENGTH 260 -#define DMA_FLASH_ADDR_OFFSET 0 /* 0 or 28 */ static ATTR_NOCACHE_NOINIT_RAM_SECTION uint8_t dst_buffer[DMA_BUFFER_LENGTH]; +static uint8_t write_buf[DMA_BUFFER_LENGTH]; +static uint8_t dma_tc_flag0 = 0; +struct bflb_device_s *dma0_ch0; +static uint64_t start_time; static uint8_t src_burst[] = { DMA_BURST_INCR1, @@ -67,12 +73,6 @@ static uint8_t dst_width[] = { DMA_DATA_WIDTH_32BIT, }; -static uint8_t dma_tc_flag0 = 0; - -struct bflb_device_s *dma0_ch0; - -volatile uint64_t start_time; - void dma0_ch0_isr(void *arg) { printf("cost time:%d us\r\n", (uint32_t)(bflb_mtimer_get_time_us() - start_time)); @@ -83,18 +83,15 @@ void dma0_ch0_isr(void *arg) int main(void) { board_init(); - - uint8_t write_buf[DMA_BUFFER_LENGTH]; - for (uint16_t i = 0; i < DMA_BUFFER_LENGTH; i++) { write_buf[i] = (i & 0xff) + i / 256; } - /* erase 0x00010000 4k flash */ - bflb_flash_erase(0x00010000, 4096); + /* erase flash */ + bflb_flash_erase(FLASH_RW_START_ADDR, 4096); - /* write 0x00010000 flash data */ - bflb_flash_write(0x00010000, write_buf, sizeof(write_buf)); /* FLASH_XIP_BASE - 0x2000 + 0x00010000 */ + /* write flash data */ + bflb_flash_write(FLASH_RW_START_ADDR, write_buf, sizeof(write_buf)); /* FLASH_XIP_BASE - 0x2000 + 0x00010000 */ dma0_ch0 = bflb_device_get_by_name("dma0_ch0"); @@ -120,7 +117,7 @@ int main(void) struct bflb_dma_channel_lli_pool_s lli[1]; /* max trasnfer size 4064 * 1 */ struct bflb_dma_channel_lli_transfer_s transfers[1]; - transfers[0].src_addr = (uint32_t)(FLASH_XIP_BASE - bflb_flash_get_image_offset() + 0x00010000 + DMA_FLASH_ADDR_OFFSET); + transfers[0].src_addr = (uint32_t)(FLASH_XIP_BASE - bflb_flash_get_image_offset() + FLASH_RW_START_ADDR + DMA_FLASH_ADDR_OFFSET); transfers[0].dst_addr = (uint32_t)dst_buffer; transfers[0].nbytes = DMA_BUFFER_LENGTH - DMA_FLASH_ADDR_OFFSET; @@ -141,7 +138,7 @@ int main(void) } } - printf("flash test success\r\n"); + printf("flash dam case success\r\n"); while (1) { } } \ No newline at end of file diff --git a/examples/peripherals/flash/flash_iomode/README.md b/examples/peripherals/flash/flash_iomode/README.md new file mode 100644 index 00000000..b002c912 --- /dev/null +++ b/examples/peripherals/flash/flash_iomode/README.md @@ -0,0 +1,44 @@ +# flash_iomode + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/flash/flash_iomode/flash_prog_cfg.ini b/examples/peripherals/flash/flash_iomode/flash_prog_cfg.ini new file mode 100644 index 00000000..0771813d --- /dev/null +++ b/examples/peripherals/flash/flash_iomode/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/flash*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/flash/flash_iomode/main.c b/examples/peripherals/flash/flash_iomode/main.c index ee75c2db..ff397293 100644 --- a/examples/peripherals/flash/flash_iomode/main.c +++ b/examples/peripherals/flash/flash_iomode/main.c @@ -1,52 +1,67 @@ #include "bflb_flash.h" #include "board.h" -const char *iomode_string[] = { "NIO", "DO", "QO", "DIO", "QIO" }; #define FLASH_DATA_LEN 4096 +#define FLASH_RW_START_ADDR 0x10000 -uint8_t write_buf[FLASH_DATA_LEN]; -uint8_t read_buf[FLASH_DATA_LEN]; - -uint64_t start_time; +const char *iomode_string[] = { "NIO", "DO", "QO", "DIO", "QIO" }; +static uint8_t write_buf[FLASH_DATA_LEN]; +static uint8_t read_buf[FLASH_DATA_LEN]; +static uint64_t start_time; int main(void) { + uint32_t i; + board_init(); - for (uint16_t i = 0; i < FLASH_DATA_LEN; i++) { + for (i = 0; i < sizeof(write_buf); i++) { write_buf[i] = i & 0xff; } for (uint8_t iomode = FLASH_IOMODE_NIO; iomode <= FLASH_IOMODE_QIO; iomode++) { + printf("select flash iomode:%s\r\n", iomode_string[iomode]); bflb_flash_set_iomode(iomode); start_time = bflb_mtimer_get_time_ms(); - /* erase 0x00010000 4k flash */ - bflb_flash_erase(0x00010000, 4096); + /* erase flash */ + bflb_flash_erase(FLASH_RW_START_ADDR, sizeof(write_buf)); - /* write 0x00010000 flash data */ - bflb_flash_write(0x00010000, write_buf, sizeof(write_buf)); + memset(read_buf, 0, sizeof(read_buf)); + /* read flash data */ + bflb_flash_read(FLASH_RW_START_ADDR, read_buf, sizeof(read_buf)); - memset(read_buf, 0, FLASH_DATA_LEN); - - /* read 0x00010000 flash data */ - bflb_flash_read(0x00010000, read_buf, sizeof(read_buf)); - - printf("cost time:%lld ms\r\n", (bflb_mtimer_get_time_ms() - start_time)); - - for (uint16_t j = 0; j < FLASH_DATA_LEN; j++) { - if (read_buf[j] != write_buf[j]) { - printf("flash test fail at %d, expect:%d but with %d\r\n", j, write_buf[j], read_buf[j]); + for (i = 0; i < sizeof(read_buf); i++) { + if (read_buf[i] != 0xff) { + printf("flash erase fail at %d, expect:%d but get %d\r\n", i, 0xff, read_buf[i]); while (1) { } } } + + /* write flash data */ + bflb_flash_write(FLASH_RW_START_ADDR, write_buf, sizeof(write_buf)); + + memset(read_buf, 0, sizeof(read_buf)); + /* read flash data */ + bflb_flash_read(FLASH_RW_START_ADDR, read_buf, sizeof(read_buf)); + + printf("cost time:%lld ms\r\n", (bflb_mtimer_get_time_ms() - start_time)); + + for (i = 0; i < sizeof(write_buf); i++) { + if (read_buf[i] != write_buf[i]) { + printf("flash write fail at %d, expect:%d but get %d\r\n", i, write_buf[i], read_buf[i]); + while (1) { + } + } + } + printf("flash data check success\r\n"); } - printf("flash test success\r\n"); + printf("flash io case success\r\n"); while (1) { } } \ No newline at end of file diff --git a/examples/peripherals/flash/flash_read_write/README.md b/examples/peripherals/flash/flash_read_write/README.md new file mode 100644 index 00000000..8472af64 --- /dev/null +++ b/examples/peripherals/flash/flash_read_write/README.md @@ -0,0 +1,44 @@ +# flash_read_write + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/flash/flash_read_write/flash_prog_cfg.ini b/examples/peripherals/flash/flash_read_write/flash_prog_cfg.ini new file mode 100644 index 00000000..0771813d --- /dev/null +++ b/examples/peripherals/flash/flash_read_write/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/flash*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/flash/flash_read_write/main.c b/examples/peripherals/flash/flash_read_write/main.c index 71dfd8b5..0e82a8e5 100644 --- a/examples/peripherals/flash/flash_read_write/main.c +++ b/examples/peripherals/flash/flash_read_write/main.c @@ -1,53 +1,62 @@ #include "bflb_flash.h" #include "board.h" -#define FLASH_TEST_SIZE 1 * 1024 * 1024 +#define FLASH_RW_TOTAL_SIZE 512 * 1024 +#define FLASH_RW_START_ADDR 0x10000 + +static uint8_t write_buf[256]; +static uint8_t read_buf[256]; int main(void) { + uint32_t i,j; + uint32_t flash_addr; + board_init(); - uint8_t write_buf[256]; - uint8_t read_buf[256]; - - for (uint16_t i = 0; i < 256; i++) { + for (i = 0; i < sizeof(write_buf); i++) { write_buf[i] = i; } - for (uint32_t i = 1; i < (FLASH_TEST_SIZE / 1024); i++) { - printf("test addr:%08x\r\n", (0x00010000 + (i - 1) * 1024)); - /* erase 0x00010000 4k flash */ - bflb_flash_erase(0x00010000 + (i - 1) * 1024, i * 1024); + for (uint32_t offset = 0; offset < FLASH_RW_TOTAL_SIZE; offset+=sizeof(write_buf)){ - memset(read_buf, 0, 256); + flash_addr=FLASH_RW_START_ADDR+offset; + printf("erase addr:%08x\r\n", flash_addr); - /* read 0x00010000 flash data */ - bflb_flash_read(0x00010000 + (i - 1) * 1024, read_buf, sizeof(read_buf)); - for (uint16_t j = 0; j < 256; j++) { + /* erase flash */ + bflb_flash_erase(flash_addr,sizeof(write_buf)); + + memset(read_buf, 0, sizeof(read_buf)); + /* read flash data */ + bflb_flash_read(flash_addr, read_buf, sizeof(read_buf)); + + for (j = 0; j < sizeof(read_buf); j++) { if (read_buf[j] != 0xff) { - printf("flash test fail at %d, expect:%d but with %d\r\n", j, 0xff, read_buf[j]); + printf("flash erase fail at %d, expect:%d but get %d\r\n", j, 0xff, read_buf[j]); while (1) { } } } - /* write 0x00010000 flash data */ - bflb_flash_write(0x00010000 + (i - 1) * 1024, write_buf, sizeof(write_buf)); - memset(read_buf, 0, 256); + /* write flash data */ + bflb_flash_write(flash_addr, write_buf, sizeof(write_buf)); - /* read 0x00010000 flash data */ - bflb_flash_read(0x00010000 + (i - 1) * 1024, read_buf, sizeof(read_buf)); + memset(read_buf, 0, sizeof(read_buf)); + /* read flash data */ + bflb_flash_read(flash_addr, read_buf, sizeof(read_buf)); - for (uint16_t j = 0; j < 256; j++) { + for (j = 0; j < sizeof(read_buf); j++) { if (read_buf[j] != write_buf[j]) { - printf("flash test fail at %d, expect:%d but with %d\r\n", j, write_buf[j], read_buf[j]); + printf("flash read fail at %d, expect:%d but get %d\r\n", j, write_buf[j], read_buf[j]); while (1) { } } } + printf("check success\r\n"); } - printf("flash test success\r\n"); + printf("flash read write success\r\n"); + while (1) { } } \ No newline at end of file diff --git a/examples/peripherals/flash/flash_secure_read_write/README.md b/examples/peripherals/flash/flash_secure_read_write/README.md new file mode 100644 index 00000000..485705c1 --- /dev/null +++ b/examples/peripherals/flash/flash_secure_read_write/README.md @@ -0,0 +1,44 @@ +# flash_secure_read_write + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/flash/flash_secure_read_write/flash_prog_cfg.ini b/examples/peripherals/flash/flash_secure_read_write/flash_prog_cfg.ini new file mode 100644 index 00000000..0771813d --- /dev/null +++ b/examples/peripherals/flash/flash_secure_read_write/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/flash*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/flash/flash_xip_read/CMakeLists.txt b/examples/peripherals/flash/flash_xip_read/CMakeLists.txt new file mode 100644 index 00000000..57f4e134 --- /dev/null +++ b/examples/peripherals/flash/flash_xip_read/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(flash_xip_read) diff --git a/examples/peripherals/flash/flash_xip_read_write/Makefile b/examples/peripherals/flash/flash_xip_read/Makefile similarity index 100% rename from examples/peripherals/flash/flash_xip_read_write/Makefile rename to examples/peripherals/flash/flash_xip_read/Makefile diff --git a/examples/peripherals/flash/flash_xip_read/README.md b/examples/peripherals/flash/flash_xip_read/README.md new file mode 100644 index 00000000..b0ad3126 --- /dev/null +++ b/examples/peripherals/flash/flash_xip_read/README.md @@ -0,0 +1,44 @@ +# flash_xip_read + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/flash/flash_xip_read/flash_prog_cfg.ini b/examples/peripherals/flash/flash_xip_read/flash_prog_cfg.ini new file mode 100644 index 00000000..0771813d --- /dev/null +++ b/examples/peripherals/flash/flash_xip_read/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/flash*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/flash/flash_xip_read/main.c b/examples/peripherals/flash/flash_xip_read/main.c new file mode 100644 index 00000000..3fee57da --- /dev/null +++ b/examples/peripherals/flash/flash_xip_read/main.c @@ -0,0 +1,58 @@ +#include "bflb_flash.h" +#include "bflb_l1c.h" +#include "board.h" + +#define FLASH_RW_TOTAL_SIZE 512 * 1024 +#define FLASH_RW_START_ADDR 0x10000 + +static uint8_t write_buf[1024]; + +int main(void) +{ + uint8_t *read_buf; + uint32_t flash_addr; + + board_init(); + + for (uint16_t i = 0; i < sizeof(write_buf); i++) { + write_buf[i] = i; + } + + for (uint32_t offset = 0; offset < FLASH_RW_TOTAL_SIZE; offset+=sizeof(write_buf)) { + + flash_addr=FLASH_RW_START_ADDR + offset; + printf("erase addr:%08x\r\n", flash_addr); + + /* erase flash */ + bflb_flash_erase(flash_addr , sizeof(write_buf)); + + /* read flash data */ + read_buf = (uint8_t *)(FLASH_XIP_BASE + flash_addr - bflb_flash_get_image_offset()); + bflb_l1c_dcache_invalidate_range(read_buf, sizeof(write_buf)); + for (uint16_t j = 0; j < sizeof(write_buf); j++) { + if (read_buf[j] != 0xff) { + printf("flash erase fail at %d, expect:%d but get %d\r\n", j, 0xff, read_buf[j]); + while (1) { + } + } + } + /* write flash data */ + bflb_flash_write(flash_addr, write_buf, sizeof(write_buf)); + + /* read flash data */ + bflb_l1c_dcache_invalidate_range(read_buf, sizeof(write_buf)); + for (uint16_t j = 0; j < sizeof(write_buf); j++) { + if (read_buf[j] != write_buf[j]) { + printf("flash check fail at %d, expect:%d but get %d\r\n", j, write_buf[j], read_buf[j]); + while (1) { + } + } + } + printf("check success\r\n"); + } + + printf("flash xip read success\r\n"); + + while (1) { + } +} \ No newline at end of file diff --git a/examples/peripherals/flash/flash_xip_read_write/proj.conf b/examples/peripherals/flash/flash_xip_read/proj.conf similarity index 100% rename from examples/peripherals/flash/flash_xip_read_write/proj.conf rename to examples/peripherals/flash/flash_xip_read/proj.conf diff --git a/examples/peripherals/flash/flash_xip_read_write/main.c b/examples/peripherals/flash/flash_xip_read_write/main.c deleted file mode 100644 index f2e84ec4..00000000 --- a/examples/peripherals/flash/flash_xip_read_write/main.c +++ /dev/null @@ -1,51 +0,0 @@ -#include "bflb_flash.h" -#include "bflb_l1c.h" -#include "board.h" - -#define FLASH_TEST_SIZE 1 * 1024 * 1024 - -int main(void) -{ - board_init(); - - uint8_t write_buf[256]; - uint8_t *read_buf; - - for (uint16_t i = 0; i < 256; i++) { - write_buf[i] = i; - } - - for (uint32_t i = 1; i < (FLASH_TEST_SIZE / 1024); i++) { - printf("test addr:%08x\r\n", (0x00010000 + (i - 1) * 1024)); - /* erase 0x00010000 4k flash */ - bflb_flash_erase(0x00010000 + (i - 1) * 1024, i * 1024); - - /* read 0x00010000 flash data */ - read_buf = (uint8_t *)(FLASH_XIP_BASE - bflb_flash_get_image_offset() + 0x00010000 + (i - 1) * 1024); - bflb_l1c_dcache_invalidate_range(read_buf, 256); - for (uint16_t j = 0; j < 256; j++) { - if (read_buf[j] != 0xff) { - printf("flash test1 fail at %d, expect:%d but with %d\r\n", j, 0xff, read_buf[j]); - while (1) { - } - } - } - /* write 0x00010000 flash data */ - bflb_flash_write(0x00010000 + (i - 1) * 1024, write_buf, sizeof(write_buf)); - - /* read 0x00010000 flash data */ - read_buf = (uint8_t *)(FLASH_XIP_BASE - bflb_flash_get_image_offset() + 0x00010000 + (i - 1) * 1024); - bflb_l1c_dcache_invalidate_range(read_buf, 256); - for (uint16_t j = 0; j < 256; j++) { - if (read_buf[j] != write_buf[j]) { - printf("flash test2 fail at %d, expect:%d but with %d\r\n", j, write_buf[j], read_buf[j]); - while (1) { - } - } - } - } - - printf("flash test success\r\n"); - while (1) { - } -} \ No newline at end of file diff --git a/examples/peripherals/gpio/gpio_input_output/README.md b/examples/peripherals/gpio/gpio_input_output/README.md new file mode 100644 index 00000000..3e45d991 --- /dev/null +++ b/examples/peripherals/gpio/gpio_input_output/README.md @@ -0,0 +1,44 @@ +# gpio_input_output + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/gpio/gpio_input_output/flash_prog_cfg.ini b/examples/peripherals/gpio/gpio_input_output/flash_prog_cfg.ini new file mode 100644 index 00000000..43ed1aec --- /dev/null +++ b/examples/peripherals/gpio/gpio_input_output/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/gpio*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/gpio/gpio_interrupt/README.md b/examples/peripherals/gpio/gpio_interrupt/README.md new file mode 100644 index 00000000..5045a571 --- /dev/null +++ b/examples/peripherals/gpio/gpio_interrupt/README.md @@ -0,0 +1,43 @@ +# gpio_interrupt + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/gpio/gpio_interrupt/flash_prog_cfg.ini b/examples/peripherals/gpio/gpio_interrupt/flash_prog_cfg.ini new file mode 100644 index 00000000..43ed1aec --- /dev/null +++ b/examples/peripherals/gpio/gpio_interrupt/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/gpio*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_10_bit/README.md b/examples/peripherals/i2c/i2c_10_bit/README.md new file mode 100644 index 00000000..d336987d --- /dev/null +++ b/examples/peripherals/i2c/i2c_10_bit/README.md @@ -0,0 +1,30 @@ +# i2c_10_bit + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_10_bit/flash_prog_cfg.ini b/examples/peripherals/i2c/i2c_10_bit/flash_prog_cfg.ini new file mode 100644 index 00000000..79fea23c --- /dev/null +++ b/examples/peripherals/i2c/i2c_10_bit/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2c*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom/README.md b/examples/peripherals/i2c/i2c_eeprom/README.md new file mode 100644 index 00000000..afd679f8 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom/README.md @@ -0,0 +1,44 @@ +# i2c_eeprom + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom/flash_prog_cfg.ini b/examples/peripherals/i2c/i2c_eeprom/flash_prog_cfg.ini new file mode 100644 index 00000000..42578bc2 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/ir*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom_dma/README.md b/examples/peripherals/i2c/i2c_eeprom_dma/README.md new file mode 100644 index 00000000..d9ca3912 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_dma/README.md @@ -0,0 +1,44 @@ +# i2c_eeprom_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom_dma/flash_prog_cfg.ini b/examples/peripherals/i2c/i2c_eeprom_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..79fea23c --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2c*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom_interrupt/README.md b/examples/peripherals/i2c/i2c_eeprom_interrupt/README.md new file mode 100644 index 00000000..ee85be84 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_interrupt/README.md @@ -0,0 +1,43 @@ +# i2c_eeprom_interrupt + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom_interrupt/flash_prog_cfg.ini b/examples/peripherals/i2c/i2c_eeprom_interrupt/flash_prog_cfg.ini new file mode 100644 index 00000000..79fea23c --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_interrupt/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2c*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_dma/CMakeLists.txt b/examples/peripherals/i2s/i2s_dma/CMakeLists.txt new file mode 100755 index 00000000..f733bd98 --- /dev/null +++ b/examples/peripherals/i2s/i2s_dma/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(spi_dma) diff --git a/examples/peripherals/i2s/i2s_dma/Makefile b/examples/peripherals/i2s/i2s_dma/Makefile new file mode 100755 index 00000000..506b984f --- /dev/null +++ b/examples/peripherals/i2s/i2s_dma/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_dma/README.md b/examples/peripherals/i2s/i2s_dma/README.md new file mode 100644 index 00000000..4a1adbb1 --- /dev/null +++ b/examples/peripherals/i2s/i2s_dma/README.md @@ -0,0 +1,22 @@ +# i2s_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_dma/flash_prog_cfg.ini b/examples/peripherals/i2s/i2s_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..caf58b16 --- /dev/null +++ b/examples/peripherals/i2s/i2s_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2s*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_dma/main.c b/examples/peripherals/i2s/i2s_dma/main.c new file mode 100755 index 00000000..58ea0658 --- /dev/null +++ b/examples/peripherals/i2s/i2s_dma/main.c @@ -0,0 +1,128 @@ +#include "bflb_mtimer.h" +#include "bflb_i2s.h" +#include "bflb_dma.h" +#include "bflb_gpio.h" +#include "board.h" + +#include "bflb_clock.h" + +struct bflb_device_s *i2s0; +struct bflb_device_s *dma0_ch0; +struct bflb_device_s *dma0_ch1; + +static ATTR_NOCACHE_NOINIT_RAM_SECTION uint16_t tx_buffer[256]; +static ATTR_NOCACHE_NOINIT_RAM_SECTION uint16_t rx_buffer[256]; + +static volatile uint8_t dma_tc_flag0 = 0; +static volatile uint8_t dma_tc_flag1 = 0; + +void dma0_ch0_isr(void *arg) +{ + dma_tc_flag0++; + printf("tc done\r\n"); +} + +void dma0_ch1_isr(void *arg) +{ + dma_tc_flag1++; + printf("rx done\r\n"); +} + +void sram_init() +{ + uint32_t i; + + for (i = 0; i < 256; i++) { + tx_buffer[i] = i; + rx_buffer[i] = 0; + } +} + +int main(void) +{ + struct bflb_dma_channel_lli_pool_s tx_llipool[1]; + struct bflb_dma_channel_lli_transfer_s tx_transfers[1]; + struct bflb_dma_channel_lli_pool_s rx_llipool[1]; + struct bflb_dma_channel_lli_transfer_s rx_transfers[1]; + + struct bflb_i2s_config_s i2s_cfg = { + .bclk_freq_hz = 32000 * 32 * 2, /* bclk = Sampling_rate * frame_width * channel_num */ + .role = I2S_ROLE_MASTER, + .format_mode = I2S_MODE_LEFT_JUSTIFIED, + .channel_mode = I2S_CHANNEL_MODE_NUM_2, + .frame_width = I2S_SLOT_WIDTH_32, + .data_width = I2S_SLOT_WIDTH_16, + .fs_offset_cycle = 0, + + .tx_fifo_threshold = 0, + .rx_fifo_threshold = 0, + }; + + struct bflb_dma_channel_config_s tx_config = { + .direction = DMA_MEMORY_TO_PERIPH, + .src_req = DMA_REQUEST_NONE, + .dst_req = DMA_REQUEST_I2S_TX, + .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, + .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, + .src_burst_count = DMA_BURST_INCR1, + .dst_burst_count = DMA_BURST_INCR1, + .src_width = DMA_DATA_WIDTH_16BIT, + .dst_width = DMA_DATA_WIDTH_16BIT, + }; + + struct bflb_dma_channel_config_s rx_config = { + .direction = DMA_PERIPH_TO_MEMORY, + .src_req = DMA_REQUEST_I2S_RX, + .dst_req = DMA_REQUEST_NONE, + .src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, + .dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, + .src_burst_count = DMA_BURST_INCR1, + .dst_burst_count = DMA_BURST_INCR1, + .src_width = DMA_DATA_WIDTH_16BIT, + .dst_width = DMA_DATA_WIDTH_16BIT, + }; + + board_init(); + sram_init(); + /* gpio init */ + board_i2s_gpio_init(); + + i2s0 = bflb_device_get_by_name("i2s0"); + /* i2s init */ + bflb_i2s_init(i2s0, &i2s_cfg); + /* enable dma */ + bflb_i2s_link_txdma(i2s0, true); + bflb_i2s_link_rxdma(i2s0, true); + + printf("\n\ri2s dma test\n\r"); + + dma0_ch0 = bflb_device_get_by_name("dma0_ch0"); + dma0_ch1 = bflb_device_get_by_name("dma0_ch1"); + + bflb_dma_channel_init(dma0_ch0, &tx_config); + bflb_dma_channel_init(dma0_ch1, &rx_config); + + bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL); + bflb_dma_channel_irq_attach(dma0_ch1, dma0_ch1_isr, NULL); + + tx_transfers[0].src_addr = (uint32_t)tx_buffer; + tx_transfers[0].dst_addr = (uint32_t)DMA_ADDR_I2S_TDR; + tx_transfers[0].nbytes = 256 * 4; + + rx_transfers[0].src_addr = (uint32_t)DMA_ADDR_I2S_RDR; + rx_transfers[0].dst_addr = (uint32_t)rx_buffer; + rx_transfers[0].nbytes = 256 * 4; + + bflb_dma_channel_lli_reload(dma0_ch0, tx_llipool, 1, tx_transfers, 1); + bflb_dma_channel_lli_reload(dma0_ch1, rx_llipool, 1, rx_transfers, 1); + bflb_dma_channel_start(dma0_ch0); + bflb_dma_channel_start(dma0_ch1); + + /* enable i2s tx and rx */ + bflb_i2s_feature_control(i2s0, I2S_CMD_DATA_ENABLE, I2S_CMD_DATA_ENABLE_TX | I2S_CMD_DATA_ENABLE_RX); + + printf("\n\rtest end\n\r"); + + while (1) { + } +} diff --git a/examples/peripherals/i2s/i2s_dma/proj.conf b/examples/peripherals/i2s/i2s_dma/proj.conf new file mode 100755 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/i2s/i2s_dma/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_es8388/CMakeLists.txt b/examples/peripherals/i2s/i2s_es8388/CMakeLists.txt new file mode 100755 index 00000000..6a1e618b --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/CMakeLists.txt @@ -0,0 +1,11 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +target_sources(app PRIVATE bsp_es8388.c) + +sdk_set_main_file(main.c) + +project(i2s_es8388) diff --git a/examples/peripherals/i2s/i2s_es8388/Makefile b/examples/peripherals/i2s/i2s_es8388/Makefile new file mode 100755 index 00000000..506b984f --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_es8388/README.md b/examples/peripherals/i2s/i2s_es8388/README.md new file mode 100644 index 00000000..33573fa1 --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/README.md @@ -0,0 +1,22 @@ +# i2s_es8388 + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_es8388/bsp_es8388.c b/examples/peripherals/i2s/i2s_es8388/bsp_es8388.c new file mode 100755 index 00000000..708a3bd5 --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/bsp_es8388.c @@ -0,0 +1,496 @@ +/** + * @file bsp_es8388.c + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#include "bflb_i2c.h" +#include "bsp_es8388.h" + +/** @addtogroup BL702_STD_PERIPH_DRIVER + * @{ + */ + +/** @addtogroup ES8388 + * @{ + */ + +/** @defgroup ES8388_Private_Macros + * @{ + */ + +#define ES8388_I2C_SLAVE_ADDR 0x10 + +/*@} end of group ES8388_Private_Macros */ + +/** @defgroup ES8388_Private_Types + * @{ + */ + +/*@} end of group ES8388_Private_Types */ + +/** @defgroup ES8388_Private_Variables + * @{ + */ + +/*@} end of group ES8388_Private_Variables */ + +/** @defgroup ES8388_Global_Variables + * @{ + */ + +/*@} end of group ES8388_Global_Variables */ + +/** @defgroup ES8388_Private_Fun_Declaration + * @{ + */ + +/*@} end of group ES8388_Private_Fun_Declaration */ + +/** @defgroup ES8388_Private_Functions_User_Define + * @{ + */ + +/*@} end of group ES8388_Private_Functions_User_Define */ + +/** @defgroup ES8388_Private_Functions + * @{ + */ + +static struct bflb_device_s *i2c0; +static struct bflb_i2c_msg_s msgs[2]; + +/****************************************************************************/ /** + * @brief ES8388_I2C_Init + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ES8388_I2C_Init(void) +{ + // i2c_register(I2C0_INDEX, "i2c"); + // es8388_i2c = device_find("i2c"); + + // if (es8388_i2c) { + // device_open(es8388_i2c, 0); + // } + + i2c0 = bflb_device_get_by_name("i2c0"); + bflb_i2c_init(i2c0, 200000); +} + +/****************************************************************************/ /** + * @brief ES8388 write register + * + * @param addr: Register address + * @param data: data + * + * @return None + * +*******************************************************************************/ +int ES8388_Write_Reg(uint8_t addr, uint8_t data) +{ + msgs[0].addr = ES8388_I2C_SLAVE_ADDR; + msgs[0].flags = I2C_M_NOSTOP; + msgs[0].buffer = &addr; + msgs[0].length = 1; + + msgs[1].flags = 0; + msgs[1].buffer = &data; + msgs[1].length = 1; + + return bflb_i2c_transfer(i2c0, msgs, 2); +} + +/****************************************************************************/ /** + * @brief ES8388_Read_Reg + * + * @param addr: Register address + * @param rdata: data + * + * @return None + * +*******************************************************************************/ +int ES8388_Read_Reg(uint8_t addr, uint8_t *rdata) +{ + msgs[0].addr = ES8388_I2C_SLAVE_ADDR; + msgs[0].flags = I2C_M_NOSTOP; + msgs[0].buffer = &addr; + msgs[0].length = 1; + + msgs[1].flags = I2C_M_READ; + msgs[1].buffer = rdata; + msgs[1].length = 1; + + return bflb_i2c_transfer(i2c0, msgs, 2); +} + +/****************************************************************************/ /** + * @brief ES8388 codec mode + * + * @param cfg: None + * + * @return None + * +*******************************************************************************/ +void ES8388_Codec_Mode(ES8388_Cfg_Type *cfg) +{ + uint8_t tempVal = 0; + + ES8388_Write_Reg(0x01, 0x58); //power down whole chip analog + ES8388_Write_Reg(0x01, 0x50); //power up whole chip analog + + ES8388_Write_Reg(0x02, 0xf3); //power down ADC/DAC and reset ADC/DAC state machine + ES8388_Write_Reg(0x02, 0xf0); //power on ADC/DAC + + ES8388_Write_Reg(0x2B, 0x80); //set internal ADC and DAC use sanme LRCK clock + + ES8388_Write_Reg(0x00, 0x36); //ADC clock is same as DAC . DACMCLK is the chip master clock source + + if (cfg->role == ES8388_MASTER) { + ES8388_Write_Reg(0x08, 0x8D); + } else { + ES8388_Write_Reg(0x08, 0x00); + } + + ES8388_Write_Reg(0x04, 0x00); //power up dac + + ES8388_Write_Reg(0x05, 0x00); //stop lowpower mode + ES8388_Write_Reg(0x06, 0xc3); //stop lowpower mode + + if (cfg->mic_input_mode == ES8388_SINGLE_ENDED_MIC) { + /* + * default set LINPUT1 and RINPUT1 as single ended mic input + * if user want to use LINPUT2 and RINPUT2 as input + * please set 0x0a register as 0x50 + */ + ES8388_Write_Reg(0x0A, 0xf8); + ES8388_Write_Reg(0x0B, 0x88); //analog mono mix to left ADC + } else { + /* + * defualt select LIN1 and RIN1 as Mic diff input + * if user want to use LIN2 and RIN2 as input + * please set 0x0b register as 0x82 + */ + ES8388_Write_Reg(0x0A, 0xf8); // Fixed stereo problems + ES8388_Write_Reg(0x0B, 0x82); // stereo + } + + tempVal = cfg->data_width; + tempVal <<= 2; + tempVal |= cfg->i2s_frame; + + ES8388_Write_Reg(0x0C, tempVal); //ADC I2S Format sel as i2s_frame , data len as data_width + + tempVal = cfg->data_width; + tempVal <<= 2; + tempVal |= cfg->i2s_frame; + tempVal <<= 1; + + ES8388_Write_Reg(0x17, tempVal); //DAC I2S Format sel as i2s_frame , data len as data_width + + /* when work in master mode , BCLK is devided form MCLK + * default divider is 256 , see datasheet reigster 13 + */ + if (cfg->role == ES8388_MASTER) { + ES8388_Write_Reg(0x0d, 0x06); //ADCLRCK = MCLK/256 + ES8388_Write_Reg(0x18, 0x06); //DACLRCK = MCLK/256 + } + + /*set ADC/DAC default volume as 0 db */ + ES8388_Write_Reg(0x10, 0x00); //LADC volume as 0db + ES8388_Write_Reg(0x11, 0x00); //RADC volume as 0db + ES8388_Write_Reg(0x1A, 0x00); //LDAC volume as 0db + ES8388_Write_Reg(0x1B, 0x00); //RDAC volume as 0db + + tempVal = cfg->mic_pga; + tempVal <<= 4; + tempVal |= cfg->mic_pga; + + ES8388_Write_Reg(0x09, tempVal); //set ADC PGA as mic pga + + /*ADC ALC default Setting */ + ES8388_Write_Reg(0x12, 0xE2); + ES8388_Write_Reg(0x13, 0xC0); + ES8388_Write_Reg(0x14, 0x12); + ES8388_Write_Reg(0x15, 0x06); + ES8388_Write_Reg(0x16, 0xC3); + + /*Mixer setting for LDAC to LOUT and RDAC TO ROUT + * default close mixer + */ + ES8388_Write_Reg(0x27, 0xB8); + ES8388_Write_Reg(0x2A, 0xB8); + + ES8388_Write_Reg(0x02, 0x00); //startup FSM and DLL + bflb_mtimer_delay_ms(500); + + /* set LOUT1 ROUT1 LOUT2 ROUT2 volume */ + ES8388_Write_Reg(0x2e, 0x1E); + ES8388_Write_Reg(0x2f, 0x1E); + ES8388_Write_Reg(0x30, 0x1E); + ES8388_Write_Reg(0x31, 0x1E); + + //ES8388_Write_Reg(0x04,0x3C);//enable LOUT & ROUT + ES8388_Write_Reg(0x04, 0x24); + ES8388_Write_Reg(0x26, 0x01); + ES8388_Write_Reg(0x03, 0x09); //power up ADC Enable LIN &RIN. +} + +/****************************************************************************/ /** + * @brief ES8388 recording mode + * + * @param cfg: None + * + * @return None + * +*******************************************************************************/ +void ES8388_Recording_Mode(ES8388_Cfg_Type *cfg) +{ + uint8_t tempVal = 0; + ES8388_Write_Reg(0x01, 0x58); //power down whole chip analog + ES8388_Write_Reg(0x01, 0x50); //power up whole chip analog + + ES8388_Write_Reg(0x02, 0xf3); //power down ADC/DAC and reset ADC/DAC state machine + ES8388_Write_Reg(0x02, 0xf0); //power on ADC/DAC + ES8388_Write_Reg(0x2B, 0x80); //set internal ADC and DAC use the same LRCK clock + ES8388_Write_Reg(0x00, 0x16); //ADC clock is same as DAC. use ADC MCLK as internal MCLK + + if (cfg->role == ES8388_MASTER) { + ES8388_Write_Reg(0x08, 0x80); + } else { + ES8388_Write_Reg(0x08, 0x00); + } + + ES8388_Write_Reg(0x04, 0xc0); + ES8388_Write_Reg(0x05, 0x00); + ES8388_Write_Reg(0x06, 0xc3); + + if (cfg->mic_input_mode == ES8388_SINGLE_ENDED_MIC) { + /* + * default set LINPUT1 and RINPUT1 as single ended mic input + * if user want to use LINPUT2 and RINPUT2 as input + * please set 0x0a register as 0x50 + */ + //ES8388_Write_Reg(0x0A,0x00);//select lin1 and rin1 as micphone input + ES8388_Write_Reg(0x0A, 0xf8); + ES8388_Write_Reg(0x0B, 0x88); //analog mono mix to left ADC + //ES8388_Write_Reg(0x0B,0x90); //analog mono mix to right ADC + } else { + /* + * defualt select LIN1 and RIN1 as Mic diff input + * if user want to use LIN2 and RIN2 as input + * please set 0x0b register as 0x82 + */ + //ES8388_Write_Reg(0x0A,0xf0);//set micphone input as difference mode + //ES8388_Write_Reg(0x0B,0x02);//set LIN1 and RIN1 as micphone different input + ES8388_Write_Reg(0x0A, 0xf8); // Fixed stereo problems + ES8388_Write_Reg(0x0B, 0x82); // stereo + } + + tempVal = cfg->data_width; + tempVal <<= 2; + tempVal |= cfg->i2s_frame; + + ES8388_Write_Reg(0x0C, tempVal); //ADC I2S Format sel as i2s_frame , data len as data_width + + ES8388_Write_Reg(0x0d, 0x02); //ADC LRCK = MCLK/256 + + ES8388_Write_Reg(0x10, 0x00); //ADC VOLUME = 0 DB + ES8388_Write_Reg(0x11, 0x00); //set ADC VOLUME as 0 DB + + tempVal = cfg->mic_pga; + tempVal <<= 4; + tempVal |= cfg->mic_pga; + + ES8388_Write_Reg(0x09, tempVal); //MIC PGA SEL + + ES8388_Write_Reg(0x12, 0xe2); //MIC ALC SETTING + + ES8388_Write_Reg(0x13, 0xc0); + ES8388_Write_Reg(0x14, 0x12); + ES8388_Write_Reg(0x15, 0x06); + ES8388_Write_Reg(0x16, 0xc3); + + ES8388_Write_Reg(0x02, 0x55); //startup FSM and DLL + ES8388_Write_Reg(0x03, 0x09); //power up adc , enable LIN and RIN +} + +/****************************************************************************/ /** + * @brief ES8388 Playback mode + * + * @param cfg: None + * + * @return None + * +*******************************************************************************/ +void ES8388_Playback_Mode(ES8388_Cfg_Type *cfg) +{ + uint8_t tempVal = 0; + + ES8388_Write_Reg(0x00, 0x80); //Reset control port register to default + ES8388_Write_Reg(0x00, 0x06); //Close reset + bflb_mtimer_delay_ms(10); + ES8388_Write_Reg(0x02, 0xF3); //Stop STM, DLL and digital block + + if (cfg->role == ES8388_MASTER) { + ES8388_Write_Reg(0x08, 0x80); + } else { + ES8388_Write_Reg(0x08, 0x00); + } + + ES8388_Write_Reg(0x2B, 0x80); //Set ADC and DAC have the same LRCK + ES8388_Write_Reg(0x00, 0x05); //Start up reference + ES8388_Write_Reg(0x01, 0x40); //Start up reference + bflb_mtimer_delay_ms(30); + ES8388_Write_Reg(0x03, 0x00); //Power on ADC and LIN/RIN input + ES8388_Write_Reg(0x04, 0x3F); //Power on DAC and LOUT/ROUT input + + /* Set ADC */ + ES8388_Write_Reg(0x09, 0x77); //MicBoost PGA = +21dB + ES8388_Write_Reg(0x0A, 0xF0); //Differential input + ES8388_Write_Reg(0x0B, 0x02); //Select LIN1 and RIN1 as differential input pairs + + tempVal = cfg->data_width; + tempVal <<= 2; + tempVal |= cfg->i2s_frame; + + ES8388_Write_Reg(0x0C, tempVal); //ADC I2S Format sel as i2s_frame , data len as data_width + + ES8388_Write_Reg(0x0D, 0x04); //MCLK / LRCK = 512 + ES8388_Write_Reg(0x10, 0x00); //LADC volume = 0dB + ES8388_Write_Reg(0x11, 0x00); //RADC volume = 0dB + ES8388_Write_Reg(0x12, 0xE2); //ALC enable, PGA Max.Gain = 23.5dB, Min.Gain = 0dB + ES8388_Write_Reg(0x13, 0xC0); //ALC target = -4.5dB, ALC hold time = 0 ms + ES8388_Write_Reg(0x14, 0x12); //Decay time = 820us, attack time = 416us + ES8388_Write_Reg(0x15, 0x06); //ALC mode + ES8388_Write_Reg(0x16, 0xC3); //Nose gate =-40.5dB, NGG = 0x01(mute ADC) + + tempVal = cfg->data_width; + tempVal <<= 2; + tempVal |= cfg->i2s_frame; + tempVal <<= 1; + + ES8388_Write_Reg(0x18, 0x04); //MCLK / LRCK = 512 + ES8388_Write_Reg(0x1A, 0x00); //LDAC volume = 0dB + ES8388_Write_Reg(0x1B, 0x00); //RDAC volume = 0dB + ES8388_Write_Reg(0x26, 0x00); //Setup mixer + ES8388_Write_Reg(0x27, 0xB8); //Setup mixer + ES8388_Write_Reg(0x28, 0x38); //Setup mixer + ES8388_Write_Reg(0x29, 0x38); //Setup mixer + ES8388_Write_Reg(0x2A, 0xB8); //Setup mixer + ES8388_Write_Reg(0x2E, 0x1E); //Set Lout/Rout volume:0dB + ES8388_Write_Reg(0x2F, 0x1E); //Set Lout/Rout volume:0dB + ES8388_Write_Reg(0x30, 0x1E); //Set Lout/Rout volume:0dB + ES8388_Write_Reg(0x31, 0x1E); //Set Lout/Rout volume:0dB + ES8388_Write_Reg(0x02, 0x00); //Power up DEM and STM +} + +/****************************************************************************/ /** + * @brief ES8388_I2C_Init + * + * @param None + * + * @return None + * +*******************************************************************************/ +int ES8388_Set_Voice_Volume(int volume) +{ + int res; + + if (volume < 0) { + volume = 0; + } else if (volume > 100) { + volume = 100; + } + + volume /= 3; + res = ES8388_Write_Reg(0x2e, volume); + res |= ES8388_Write_Reg(0x2f, volume); + res |= ES8388_Write_Reg(0x30, volume); + res |= ES8388_Write_Reg(0x31, volume); + return res; +} + +/****************************************************************************/ /** + * @brief ES8388_Reg_Dump + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ES8388_Reg_Dump(void) +{ + int i; + uint8_t tmp; + + for (i = 0; i < 0X3F; i++) { + if (ES8388_Read_Reg(i, &tmp) != 0) { + printf("iic read err\r\n"); + } + + printf("Reg[%02d]=0x%02x \n", i, tmp); + } +} + +/*@} end of group ES8388_Private_Functions */ + +/** @defgroup ES8388_Public_Functions + * @{ + */ + +/****************************************************************************/ /** + * @brief ES8388 Init function + * + * @param cfg: None + * + * @return None + * +*******************************************************************************/ +void ES8388_Init(ES8388_Cfg_Type *cfg) +{ + ES8388_I2C_Init(); + + switch (cfg->work_mode) { + case ES8388_CODEC_MDOE: + ES8388_Codec_Mode(cfg); + break; + + case ES8388_RECORDING_MODE: + ES8388_Recording_Mode(cfg); + break; + + case ES8388_PLAY_BACK_MODE: + ES8388_Playback_Mode(cfg); + break; + + default: + break; + } +} + +/*@} end of group ES8388_Public_Functions */ + +/*@} end of group ES8388 */ + +/*@} end of group BL702_STD_PERIPH_DRIVER */ diff --git a/examples/peripherals/i2s/i2s_es8388/bsp_es8388.h b/examples/peripherals/i2s/i2s_es8388/bsp_es8388.h new file mode 100755 index 00000000..86efdaed --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/bsp_es8388.h @@ -0,0 +1,191 @@ +/** + * @file bsp_es8388.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ + +#ifndef __ES8388_H__ +#define __ES8388_H__ + +/** @addtogroup BL702_STD_PERIPH_DRIVER + * @{ + */ + +/** @addtogroup ES8388 + * @{ + */ + +/** @defgroup ES8388_Public_Types + * @{ + */ + +/** + * @brief ES8388 Role Matser Or Slave + */ +typedef enum { + ES8388_MASTER, /*!< Master Mode */ + ES8388_SLAVE, /*!< Slave Mode */ +} ES8388_Role_Type; + +/** + * @brief ES8388 Work Mode + */ +typedef enum { + ES8388_CODEC_MDOE, /*!< ES8388 work at codec mode */ + ES8388_RECORDING_MODE, /*!< ES8388 work at recording mode */ + ES8388_PLAY_BACK_MODE, /*!< ES8388 work at paly back mode */ + ES8388_BY_PASS_MODE, /*!< ES8388 work at by pass mode */ +} ES8388_Work_Mode; + +/** + * @brief ES8388 Microphone input type + */ +typedef enum { + ES8388_SINGLE_ENDED_MIC, /*!< Mic Single Input Mode */ + ES8388_DIFF_ENDED_MIC, /*!< Mic Different Input Mode */ +} ES8388_MIC_Input_Type; + +/** + * @brief ES8388 Microphone pga sel type + */ +typedef enum { + ES8388_MIC_PGA_0DB, /*!< Mic PGA as 0db */ + ES8388_MIC_PGA_3DB, /*!< Mic PGA as 3db */ + ES8388_MIC_PGA_6DB, /*!< Mic PGA as 6db */ + ES8388_MIC_PGA_9DB, /*!< Mic PGA as 9db */ + ES8388_MIC_PGA_12DB, /*!< Mic PGA as 12db */ + ES8388_MIC_PGA_15DB, /*!< Mic PGA as 15db */ + ES8388_MIC_PGA_18DB, /*!< Mic PGA as 18db */ + ES8388_MIC_PGA_21DB, /*!< Mic PGA as 21db */ + ES8388_MIC_PGA_24DB, /*!< Mic PGA as 24db */ +} ES8388_MIC_Input_PGA_Type; + +/** + * @brief ES8388 I2S Frame Type + */ +typedef enum { + ES8388_STD_I2S_FRAME, /*!< Standard I2S Frame */ + ES8388_LEFT_JUSTIFY_FRAME, /*!< Left Justify Frame */ + ES8388_RIGHT_JUSTIFY_FRAME, /*!< Right Justify Frame */ + ES8388_DSP_FRAME, /*!< DSP Frame */ +} ES8388_I2S_Frame_Type; + +/** + * @brief ES8388 I2S Data Len Type + */ +typedef enum { + ES8388_DATA_LEN_24, /*!< I2S Auido Data Len 24 */ + ES8388_DATA_LEN_20, /*!< I2S Auido Data Len 20 */ + ES8388_DATA_LEN_18, /*!< I2S Auido Data Len 18 */ + ES8388_DATA_LEN_16, /*!< I2S Auido Data Len 16 */ + ES8388_DATA_LEN_32, /*!< I2S Auido Data Len 32 */ +} ES8388_I2S_Data_Width; + +/** + * @brief ES8388_Cfg_Type + */ +typedef struct +{ + ES8388_Work_Mode work_mode; /*!< ES8388 work mode */ + ES8388_Role_Type role; /*!< ES8388 role */ + ES8388_MIC_Input_Type mic_input_mode; /*!< ES8388 mic input mode */ + ES8388_MIC_Input_PGA_Type mic_pga; /*!< ES8388 mic PGA */ + ES8388_I2S_Frame_Type i2s_frame; /*!< ES8388 I2S frame */ + ES8388_I2S_Data_Width data_width; /*!< ES8388 I2S dataWitdh */ +} ES8388_Cfg_Type; + +/*@} end of group ES8388_Public_Types */ + +/** @defgroup ES8388_Public_Constants + * @{ + */ + +/** @defgroup ES8388_ROLE_TYPE + * @{ + */ +#define IS_ES8388_ROLE_TYPE(type) (((type) == ES8388_MASTER) || \ + ((type) == ES8388_SLAVE)) + +/** @defgroup ES8388_WORK_MODE + * @{ + */ +#define IS_ES8388_WORK_MODE(type) (((type) == ES8388_CODEC_MDOE) || \ + ((type) == ES8388_RECORDING_MODE) || \ + ((type) == ES8388_PLAY_BACK_MODE) || \ + ((type) == ES8388_BY_PASS_MODE)) + +/** @defgroup ES8388_MIC_INPUT_TYPE + * @{ + */ +#define IS_ES8388_MIC_INPUT_TYPE(type) (((type) == ES8388_SINGLE_ENDED_MIC) || \ + ((type) == ES8388_DIFF_ENDED_MIC)) + +/** @defgroup ES8388_MIC_INPUT_PGA_TYPE + * @{ + */ +#define IS_ES8388_MIC_INPUT_PGA_TYPE(type) (((type) == ES8388_MIC_PGA_0DB) || \ + ((type) == ES8388_MIC_PGA_3DB) || \ + ((type) == ES8388_MIC_PGA_6DB) || \ + ((type) == ES8388_MIC_PGA_9DB) || \ + ((type) == ES8388_MIC_PGA_12DB) || \ + ((type) == ES8388_MIC_PGA_15DB) || \ + ((type) == ES8388_MIC_PGA_18DB) || \ + ((type) == ES8388_MIC_PGA_21DB) || \ + ((type) == ES8388_MIC_PGA_24DB)) + +/** @defgroup ES8388_I2S_FRAME_TYPE + * @{ + */ +#define IS_ES8388_I2S_FRAME_TYPE(type) (((type) == ES8388_STD_I2S_FRAME) || \ + ((type) == ES8388_LEFT_JUSTIFY_FRAME) || \ + ((type) == ES8388_RIGHT_JUSTIFY_FRAME) || \ + ((type) == ES8388_DSP_FRAME)) + +/** @defgroup ES8388_I2S_DATA_WIDTH + * @{ + */ +#define IS_ES8388_I2S_DATA_WIDTH(type) (((type) == ES8388_DATA_LEN_24) || \ + ((type) == ES8388_DATA_LEN_20) || \ + ((type) == ES8388_DATA_LEN_18) || \ + ((type) == ES8388_DATA_LEN_16) || \ + ((type) == ES8388_DATA_LEN_32)) + +/*@} end of group ES8388_Public_Constants */ + +/** @defgroup ES8388_Public_Macros + * @{ + */ + +/*@} end of group ES8388_Public_Macros */ + +/** @defgroup ES8388_Public_Functions + * @{ + */ +void ES8388_Init(ES8388_Cfg_Type *cfg); +void ES8388_Reg_Dump(void); +int ES8388_Set_Voice_Volume(int volume); + +/*@} end of group ES8388_Public_Functions */ + +/*@} end of group ES8388 */ + +/*@} end of group BL702_STD_PERIPH_DRIVER */ + +#endif /* __ES8388_H__ */ diff --git a/examples/peripherals/i2s/i2s_es8388/fhm_onechannel_16k_20.h b/examples/peripherals/i2s/i2s_es8388/fhm_onechannel_16k_20.h new file mode 100755 index 00000000..7883e38e --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/fhm_onechannel_16k_20.h @@ -0,0 +1,40031 @@ +/** + * @file fhm_onechannel_16k_20.h + * @brief + * + * Copyright (c) 2021 Bouffalolab team + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + */ +// clang-format off +//total len:640044 bytes +const unsigned char fhm_onechannel_16k_20[] = +{ + 0x52, 0x49, 0x46, 0x46, 0x24, 0xc4, 0x09, 0x00, 0x57, 0x41, 0x56, 0x45, 0x66, 0x6d, 0x74, 0x20, + 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01, 0x00, 0x80, 0x3e, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x00, + 0x02, 0x00, 0x10, 0x00, 0x64, 0x61, 0x74, 0x61, 0x00, 0xc4, 0x09, 0x00, 0x24, 0x00, 0x1a, 0x00, + 0x1e, 0x00, 0x1c, 0x00, 0x22, 0x00, 0x23, 0x00, 0x1e, 0x00, 0x27, 0x00, 0x20, 0x00, 0x1e, 0x00, + 0x25, 0x00, 0x25, 0x00, 0x25, 0x00, 0x23, 0x00, 0x28, 0x00, 0x2e, 0x00, 0x2f, 0x00, 0x30, 0x00, + 0x3a, 0x00, 0x37, 0x00, 0x38, 0x00, 0x39, 0x00, 0x35, 0x00, 0x31, 0x00, 0x31, 0x00, 0x28, 0x00, + 0x29, 0x00, 0x21, 0x00, 0x27, 0x00, 0x1c, 0x00, 0x20, 0x00, 0x1d, 0x00, 0x1b, 0x00, 0x1b, 0x00, + 0x1a, 0x00, 0x11, 0x00, 0x0e, 0x00, 0x0f, 0x00, 0x13, 0x00, 0x0a, 0x00, 0x0a, 0x00, 0x05, 0x00, + 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0x6b, 0xf7, 0x6f, 0xf4, 0x90, 0xf2, 0x29, 0xf5, 0x62, 0xfb, + 0xd2, 0xff, 0x66, 0x02, 0x57, 0x02, 0x91, 0x00, 0x37, 0x00, 0xee, 0xfd, 0xa6, 0xf7, 0x1e, 0xf1, + 0x60, 0xec, 0x54, 0xea, 0x50, 0xea, 0xf3, 0xea, 0x5c, 0xed, 0xd2, 0xf2, 0xc7, 0xf9, 0xa8, 0xff, + 0xa9, 0x03, 0xb4, 0x05, 0x04, 0x05, 0xfc, 0x04, 0xdf, 0x03, 0xf6, 0x01, 0xf5, 0x00, 0x27, 0xff, + 0x28, 0x00, 0xb0, 0x02, 0xb8, 0x08, 0xaf, 0x12, 0x3f, 0x19, 0x7f, 0x20, 0xb1, 0x23, 0x34, 0x24, + 0x5b, 0x22, 0x56, 0x1a, 0x19, 0x0f, 0x4f, 0x04, 0xf8, 0xfb, 0xa1, 0xf4, 0x80, 0xee, 0x35, 0xeb, + 0x07, 0xee, 0x5d, 0xf5, 0xd4, 0xfd, 0xfb, 0x04, 0xa9, 0x0b, 0x1d, 0x12, 0x15, 0x14, 0x1c, 0x14, + 0xe3, 0x10, 0x10, 0x0b, 0xe8, 0x04, 0x4e, 0xfd, 0x02, 0xf7, 0x4f, 0xf2, 0x15, 0xef, 0xba, 0xed, + 0x92, 0xee, 0x9d, 0xf3, 0x20, 0xfa, 0xb4, 0xfe, 0xbf, 0x00, 0xf8, 0x00, 0x06, 0x00, 0x05, 0xfe, + 0x6a, 0xf7, 0xde, 0xee, 0xac, 0xe8, 0x98, 0xe4, 0xd6, 0xe2, 0x77, 0xe3, 0xc6, 0xe5, 0x10, 0xeb, + 0x30, 0xf3, 0x71, 0xfb, 0x3c, 0x02, 0xdd, 0x05, 0x58, 0x07, 0xb8, 0x06, 0xbb, 0x05, 0xdc, 0x03, + 0x26, 0x00, 0x58, 0xfd, 0xd6, 0xfb, 0x88, 0xfc, 0x0a, 0xfe, 0xfc, 0x06, 0x1d, 0x0e, 0x16, 0x15, + 0x45, 0x1b, 0xdd, 0x1b, 0xd5, 0x1b, 0xe4, 0x15, 0xb7, 0x0a, 0x51, 0xfd, 0x2a, 0xf4, 0xca, 0xeb, + 0x2c, 0xe3, 0xe8, 0xdd, 0xea, 0xdc, 0xfc, 0xe1, 0xaf, 0xea, 0x85, 0xf2, 0x88, 0xf9, 0x1d, 0x02, + 0x26, 0x07, 0x60, 0x09, 0xbc, 0x0a, 0xcf, 0x08, 0xc6, 0x04, 0x2c, 0xff, 0x65, 0xf9, 0xed, 0xf5, + 0x23, 0xf5, 0xf8, 0xf4, 0xce, 0xf4, 0x1e, 0xf9, 0x1c, 0x00, 0x55, 0x05, 0xa2, 0x08, 0x1b, 0x0b, + 0x80, 0x0b, 0xc0, 0x0b, 0x76, 0x08, 0xf0, 0x00, 0x48, 0xfa, 0xa3, 0xf5, 0x11, 0xf3, 0x73, 0xf2, + 0xec, 0xf2, 0x0c, 0xf5, 0x9f, 0xf9, 0x0e, 0xff, 0x25, 0x04, 0x5f, 0x08, 0x4f, 0x0a, 0xc4, 0x0a, + 0xed, 0x09, 0xdb, 0x08, 0x4b, 0x08, 0x57, 0x07, 0xbb, 0x06, 0x7a, 0x09, 0xa8, 0x0b, 0xe0, 0x13, + 0x37, 0x1e, 0xac, 0x26, 0x13, 0x30, 0xd6, 0x32, 0x06, 0x34, 0x85, 0x30, 0x38, 0x27, 0x18, 0x19, + 0x3a, 0x0c, 0xdc, 0x01, 0x0e, 0xf8, 0xda, 0xef, 0x7e, 0xeb, 0x13, 0xee, 0x5c, 0xf5, 0x48, 0xfe, + 0x94, 0x05, 0x27, 0x0c, 0xcf, 0x10, 0x5e, 0x11, 0x05, 0x10, 0xf4, 0x0b, 0x9b, 0x06, 0xc2, 0xff, + 0xa7, 0xf7, 0xc8, 0xf0, 0x85, 0xeb, 0x34, 0xe9, 0x73, 0xe8, 0x91, 0xe9, 0x95, 0xee, 0x61, 0xf3, + 0x7a, 0xf5, 0xc1, 0xf4, 0x79, 0xf1, 0xe8, 0xee, 0x70, 0xeb, 0x9f, 0xe5, 0x03, 0xdf, 0x56, 0xd9, + 0x99, 0xd6, 0xee, 0xd6, 0x26, 0xd9, 0x7f, 0xdc, 0x88, 0xe1, 0x2f, 0xe7, 0x84, 0xec, 0x79, 0xf0, + 0xdc, 0xf2, 0x46, 0xf4, 0x02, 0xf4, 0x81, 0xf3, 0x22, 0xf3, 0xce, 0xf3, 0x93, 0xf4, 0x10, 0xf7, + 0xda, 0xfa, 0x16, 0x01, 0xec, 0x0d, 0x3f, 0x18, 0x2d, 0x22, 0x99, 0x28, 0x6e, 0x2b, 0x89, 0x2c, + 0xf1, 0x25, 0x99, 0x1a, 0xdd, 0x0e, 0x50, 0x06, 0xa2, 0xfe, 0x91, 0xf7, 0xc4, 0xf2, 0x60, 0xf2, + 0x83, 0xf7, 0x31, 0xfe, 0x91, 0x04, 0xe5, 0x0b, 0xca, 0x12, 0x9f, 0x15, 0x20, 0x16, 0x85, 0x14, + 0x5b, 0x10, 0xb4, 0x0a, 0x1c, 0x03, 0x71, 0xfc, 0x64, 0xf9, 0x28, 0xf9, 0xde, 0xf9, 0x1e, 0xfc, + 0x1c, 0x03, 0x62, 0x0b, 0x8e, 0x11, 0x87, 0x14, 0xa1, 0x14, 0x22, 0x13, 0x94, 0x10, 0x70, 0x0a, + 0x2b, 0x03, 0xc3, 0xfc, 0x08, 0xf7, 0xe8, 0xf3, 0xac, 0xf2, 0x4b, 0xf3, 0x30, 0xf6, 0x9b, 0xf9, + 0xdf, 0xfc, 0xda, 0x00, 0x8c, 0x03, 0xed, 0x03, 0x0d, 0x03, 0x37, 0x01, 0xd6, 0xfe, 0x95, 0xfc, + 0x42, 0xf9, 0xfc, 0xf7, 0x6d, 0xf8, 0x17, 0xfb, 0x4d, 0x05, 0xff, 0x0c, 0x16, 0x15, 0xed, 0x19, + 0x53, 0x1b, 0xce, 0x1c, 0xe4, 0x17, 0x5f, 0x0d, 0xf9, 0x00, 0xa7, 0xf7, 0x79, 0xf0, 0xda, 0xe8, + 0x60, 0xe3, 0x69, 0xe3, 0x8b, 0xe7, 0x49, 0xee, 0x1e, 0xf4, 0xa2, 0xf9, 0xf0, 0xff, 0x4f, 0x03, + 0x44, 0x04, 0xbd, 0x02, 0x8b, 0xff, 0x6d, 0xfa, 0x8c, 0xf3, 0x80, 0xed, 0x87, 0xea, 0xed, 0xea, + 0x67, 0xec, 0x16, 0xee, 0xd2, 0xf2, 0xd1, 0xfa, 0x81, 0x01, 0xc4, 0x05, 0xf0, 0x06, 0xb5, 0x06, + 0x26, 0x06, 0x2d, 0x01, 0x8e, 0xfa, 0x71, 0xf4, 0x88, 0xf0, 0x26, 0xef, 0x41, 0xef, 0x21, 0xf1, + 0x28, 0xf4, 0x4b, 0xf8, 0xd1, 0xfc, 0xc5, 0x00, 0xcd, 0x03, 0xd9, 0x04, +}; +// clang-format on \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_es8388/flash_prog_cfg.ini b/examples/peripherals/i2s/i2s_es8388/flash_prog_cfg.ini new file mode 100644 index 00000000..caf58b16 --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2s*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/i2s/i2s_es8388/main.c b/examples/peripherals/i2s/i2s_es8388/main.c new file mode 100755 index 00000000..0f8096b6 --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/main.c @@ -0,0 +1,155 @@ +#include "board.h" + +#include "bflb_clock.h" +#include "bflb_mtimer.h" +#include "bflb_i2s.h" +#include "bflb_i2c.h" +#include "bflb_dma.h" +#include "bflb_gpio.h" + +#include "bl616_glb.h" + +#include "fhm_onechannel_16k_20.h" +#include "bsp_es8388.h" + +struct bflb_device_s *i2s0; +struct bflb_device_s *i2c0; +struct bflb_device_s *dma0_ch0; + +volatile uint8_t dma_tc_flag0 = 0; + +static ES8388_Cfg_Type ES8388Cfg = { + .work_mode = ES8388_CODEC_MDOE, /*!< ES8388 work mode */ + .role = ES8388_SLAVE, /*!< ES8388 role */ + .mic_input_mode = ES8388_DIFF_ENDED_MIC, /*!< ES8388 mic input mode */ + .mic_pga = ES8388_MIC_PGA_3DB, /*!< ES8388 mic PGA */ + .i2s_frame = ES8388_LEFT_JUSTIFY_FRAME, /*!< ES8388 I2S frame */ + .data_width = ES8388_DATA_LEN_16, /*!< ES8388 I2S dataWitdh */ +}; + +void dma0_ch0_isr(void *arg) +{ + dma_tc_flag0++; + printf("tc done\r\n"); +} + +void i2s_gpio_init() +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + + /* I2S_FS */ + bflb_gpio_init(gpio, GPIO_PIN_13, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* I2S_DI */ + bflb_gpio_init(gpio, GPIO_PIN_14, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* I2S_DO */ + bflb_gpio_init(gpio, GPIO_PIN_15, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + /* I2S_BCLK */ + bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUNC_I2S | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* MCLK CLKOUT */ + bflb_gpio_init(gpio, GPIO_PIN_23, GPIO_FUNC_CLKOUT | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); + + /* I2C0_SCL */ + bflb_gpio_init(gpio, GPIO_PIN_10, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); + /* I2C0_SDA */ + bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2); +} + +void i2s_dma_init() +{ + static struct bflb_dma_channel_lli_pool_s tx_llipool[100]; + static struct bflb_dma_channel_lli_transfer_s tx_transfers[1]; + + struct bflb_i2s_config_s i2s_cfg = { + .bclk_freq_hz = 16000 * 32 * 2, /* bclk = Sampling_rate * frame_width * channel_num */ + .role = I2S_ROLE_MASTER, + .format_mode = I2S_MODE_LEFT_JUSTIFIED, + .channel_mode = I2S_CHANNEL_MODE_NUM_1, + .frame_width = I2S_SLOT_WIDTH_32, + .data_width = I2S_SLOT_WIDTH_16, + .fs_offset_cycle = 0, + + .tx_fifo_threshold = 0, + .rx_fifo_threshold = 0, + }; + + struct bflb_dma_channel_config_s tx_config = { + .direction = DMA_MEMORY_TO_PERIPH, + .src_req = DMA_REQUEST_NONE, + .dst_req = DMA_REQUEST_I2S_TX, + .src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, + .dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, + .src_burst_count = DMA_BURST_INCR1, + .dst_burst_count = DMA_BURST_INCR1, + .src_width = DMA_DATA_WIDTH_16BIT, + .dst_width = DMA_DATA_WIDTH_16BIT, + }; + + printf("i2s init\r\n"); + i2s0 = bflb_device_get_by_name("i2s0"); + /* i2s init */ + bflb_i2s_init(i2s0, &i2s_cfg); + /* enable dma */ + bflb_i2s_link_txdma(i2s0, true); + bflb_i2s_link_rxdma(i2s0, true); + + printf("dma init\r\n"); + dma0_ch0 = bflb_device_get_by_name("dma0_ch0"); + bflb_dma_channel_init(dma0_ch0, &tx_config); + bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL); + + tx_transfers[0].src_addr = (uint32_t)fhm_onechannel_16k_20; + tx_transfers[0].dst_addr = (uint32_t)DMA_ADDR_I2S_TDR; + tx_transfers[0].nbytes = sizeof(fhm_onechannel_16k_20); + + printf("dma lli init\r\n"); + uint32_t num = bflb_dma_channel_lli_reload(dma0_ch0, tx_llipool, 100, tx_transfers, 1); + bflb_dma_channel_lli_link_head(dma0_ch0, tx_llipool, num); + printf("dma lli num: %d \r\n", num); + bflb_dma_channel_start(dma0_ch0); +} + +void mclk_out_init() +{ +#ifdef BL616 + /* output MCLK, + Will change the clock source of i2s, + It needs to be called before i2s is initialized + clock source 25M + */ + GLB_Set_I2S_CLK(ENABLE, 2, GLB_I2S_DI_SEL_I2S_DI_INPUT, GLB_I2S_DO_SEL_I2S_DO_OUTPT); + GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_I2S_REF_CLK); +#endif +} + +int main(void) +{ + board_init(); + + printf("\n\ri2s dma test\n\r"); + + /* gpio init */ + i2s_gpio_init(); + + /* init ES8388 Codec */ + printf("es8388 init\n\r"); + ES8388_Init(&ES8388Cfg); + ES8388_Set_Voice_Volume(90); + + /* mclk clkout init */ + mclk_out_init(); + + /* i2s init */ + i2s_dma_init(); + + /* enable i2s tx and rx */ + bflb_i2s_feature_control(i2s0, I2S_CMD_DATA_ENABLE, I2S_CMD_DATA_ENABLE_TX | I2S_CMD_DATA_ENABLE_RX); + + printf("test end\n\r"); + + while (1) { + bflb_mtimer_delay_ms(10); + } +} diff --git a/examples/peripherals/i2s/i2s_es8388/proj.conf b/examples/peripherals/i2s/i2s_es8388/proj.conf new file mode 100755 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/i2s/i2s_es8388/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/ir/ir_nec/README.md b/examples/peripherals/ir/ir_nec/README.md new file mode 100644 index 00000000..809abbb1 --- /dev/null +++ b/examples/peripherals/ir/ir_nec/README.md @@ -0,0 +1,44 @@ +# ir_nec + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | Only support rx | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/ir/ir_nec/flash_prog_cfg.ini b/examples/peripherals/ir/ir_nec/flash_prog_cfg.ini new file mode 100644 index 00000000..79fea23c --- /dev/null +++ b/examples/peripherals/ir/ir_nec/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2c*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/ir/ir_rc5/README.md b/examples/peripherals/ir/ir_rc5/README.md new file mode 100644 index 00000000..4f9a1a2e --- /dev/null +++ b/examples/peripherals/ir/ir_rc5/README.md @@ -0,0 +1,44 @@ +# ir_rc5 + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | Only support rx | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/ir/ir_rc5/flash_prog_cfg.ini b/examples/peripherals/ir/ir_rc5/flash_prog_cfg.ini new file mode 100644 index 00000000..79fea23c --- /dev/null +++ b/examples/peripherals/ir/ir_rc5/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2c*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/ir/ir_swm/README.md b/examples/peripherals/ir/ir_swm/README.md new file mode 100644 index 00000000..19ada9ab --- /dev/null +++ b/examples/peripherals/ir/ir_swm/README.md @@ -0,0 +1,44 @@ +# ir_swm + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | Only support rx | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/ir/ir_swm/flash_prog_cfg.ini b/examples/peripherals/ir/ir_swm/flash_prog_cfg.ini new file mode 100644 index 00000000..79fea23c --- /dev/null +++ b/examples/peripherals/ir/ir_swm/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2c*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/ir/ir_tx_dma/README.md b/examples/peripherals/ir/ir_tx_dma/README.md new file mode 100644 index 00000000..75e8d99e --- /dev/null +++ b/examples/peripherals/ir/ir_tx_dma/README.md @@ -0,0 +1,44 @@ +# ir_tx_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | Only support rx | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/ir/ir_tx_dma/flash_prog_cfg.ini b/examples/peripherals/ir/ir_tx_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..79fea23c --- /dev/null +++ b/examples/peripherals/ir/ir_tx_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/i2c*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_filter/CMakeLists.txt b/examples/peripherals/iso11898/iso11898_filter/CMakeLists.txt new file mode 100644 index 00000000..c345faa4 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_filter/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(iso11898_filter) diff --git a/examples/peripherals/iso11898/iso11898_filter/Makefile b/examples/peripherals/iso11898/iso11898_filter/Makefile new file mode 100644 index 00000000..0b519efe --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_filter/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl628 +BOARD ?= bl628dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_filter/README.md b/examples/peripherals/iso11898/iso11898_filter/README.md new file mode 100644 index 00000000..ff1219bb --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_filter/README.md @@ -0,0 +1,29 @@ +# iso11898_filter + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_filter/flash_prog_cfg.ini b/examples/peripherals/iso11898/iso11898_filter/flash_prog_cfg.ini new file mode 100644 index 00000000..1bffa277 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_filter/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/iso11898*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_filter/main.c b/examples/peripherals/iso11898/iso11898_filter/main.c new file mode 100644 index 00000000..34661aad --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_filter/main.c @@ -0,0 +1,83 @@ +#include "bflb_mtimer.h" +#include "bflb_iso11898.h" +#include "board.h" + +struct bflb_device_s *iso11898; + +struct bflb_iso11898_config_s cfg = { + .prescaler = 0, /*!< specifies the length of a time quantum, ranges from 1 to 63, tq=tclk*2*(prescaler+1) */ + .mode = ISO11898_MODE_NORMAL, /*!< specifies the CAN operating mode. @ref ISO11898_MODE_XXX */ + .sample = ISO11898_SAMPLE_TRIPLE, /*!< specifies the number of sample times. @ref ISO11898_SAMPLE_XXX */ + .sjw = ISO11898_SJW_2TQ, /*!< specifies the maximum number of time quanta the ISO11898 hardware is allowed to lengthen or shorten a bit to perform resynchronization. @ref ISO11898_SJW_XXX */ + .bs1 = ISO11898_BS1_9TQ, /*!< specifies the number of time quanta in Bit Segment 1. @ref ISO11898_BS1_XXX */ + .bs2 = ISO11898_BS2_6TQ, /*!< specifies the number of time quanta in Bit Segment 2. @ref ISO11898_BS2_XXX */ +}; + +struct bflb_iso11898_filter_s filter = { + .filter_type = ISO11898_FILTER_TYPE_SINGLE, + .code0 = 0, + .code1 = 0, + .code2 = 0, + .code3 = 0x30, + .mask0 = 0xFF, + .mask1 = 0xFF, + .mask2 = 0xFF, + .mask3 = 0x80, +}; + +struct bflb_iso11898_msg_s msg_tx = { + .std_id = 0x59, /*!< specifies the standard identifier, this parameter can be a value between 0 to 0x7FF */ + .ext_id = 0x154863, /*!< specifies the extended identifier, this parameter can be a value between 0 to 0x1FFFFFFF */ + .id_type = ISO11898_ID_EXTENDED, /*!< specifies the type of identifier for the message that will be send or received. @ref ISO11898_ID_XXX */ + .rtr = ISO11898_RTR_DATA, /*!< specifies the type of frame for the message that will be send or received, @ref ISO11898_RTR_XXX */ + .dlc = 8, /*!< specifies the length of the frame that will be send or received, this parameter can be a value between 0 to 8 */ + .data = { 0x2E, 0x53, 0xF6, 0x81, 0xD4, 0xC0, 0x7A, 0xB9 }, /*!< contains the data to be send or received, it ranges from 0 to 0xFF */ +}; + +void iso11898_isr(int irq, void *arg) +{ + uint32_t int_status = bflb_iso11898_get_int_status(iso11898); + + if (int_status & ISO11898_INTSTS_RX) { + struct bflb_iso11898_msg_s msg; + bflb_iso11898_recv(iso11898, &msg, 100); + printf("Receive \r\n"); + if (msg.id_type == ISO11898_ID_STANDARD) { + printf("standard frame, ID = 0x%03x \r\n", msg.std_id); + } else { + printf("extend frame, ID = 0x%08x \r\n", msg.ext_id); + } + if (msg.rtr == ISO11898_RTR_DATA) { + printf("data frame[%d]\r\n", msg.dlc); + for (uint32_t i = 0; i < msg.dlc; i++) { + printf("%02X ", msg.data[i]); + } + printf("\r\n"); + } else { + printf("remote frame\r\n"); + } + } + if (int_status & ISO11898_INTSTS_TX) { + printf("tx succeed!\r\n"); + } +} + +int main(void) +{ + board_init(); + board_iso11898_gpio_init(); + + iso11898 = bflb_device_get_by_name("iso11898"); + + bflb_iso11898_init(iso11898, &cfg); + bflb_iso11898_set_filter(iso11898, &filter); + bflb_irq_attach(iso11898->irq_num, iso11898_isr, NULL); + bflb_iso11898_txint_mask(iso11898, false); + bflb_iso11898_rxint_mask(iso11898, false); + bflb_irq_enable(iso11898->irq_num); + bflb_iso11898_send(iso11898, &msg_tx, 1000); + + while (1) { + bflb_mtimer_delay_ms(2000); + } +} diff --git a/examples/peripherals/iso11898/iso11898_filter/proj.conf b/examples/peripherals/iso11898/iso11898_filter/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_filter/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_interrupt/CMakeLists.txt b/examples/peripherals/iso11898/iso11898_interrupt/CMakeLists.txt new file mode 100644 index 00000000..dbec9c80 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_interrupt/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(iso11898_interrupt) diff --git a/examples/peripherals/iso11898/iso11898_interrupt/Makefile b/examples/peripherals/iso11898/iso11898_interrupt/Makefile new file mode 100644 index 00000000..0b519efe --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_interrupt/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl628 +BOARD ?= bl628dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_interrupt/README.md b/examples/peripherals/iso11898/iso11898_interrupt/README.md new file mode 100644 index 00000000..3d36efd6 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_interrupt/README.md @@ -0,0 +1,29 @@ +# iso11898_interrupt + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_interrupt/flash_prog_cfg.ini b/examples/peripherals/iso11898/iso11898_interrupt/flash_prog_cfg.ini new file mode 100644 index 00000000..1bffa277 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_interrupt/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/iso11898*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_interrupt/main.c b/examples/peripherals/iso11898/iso11898_interrupt/main.c new file mode 100644 index 00000000..87acc3d0 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_interrupt/main.c @@ -0,0 +1,70 @@ +#include "bflb_mtimer.h" +#include "bflb_iso11898.h" +#include "board.h" + +struct bflb_device_s *iso11898; + +struct bflb_iso11898_config_s cfg = { + .prescaler = 0, /*!< specifies the length of a time quantum, ranges from 1 to 63, tq=tclk*2*(prescaler+1) */ + .mode = ISO11898_MODE_NORMAL, /*!< specifies the CAN operating mode. @ref ISO11898_MODE_XXX */ + .sample = ISO11898_SAMPLE_TRIPLE, /*!< specifies the number of sample times. @ref ISO11898_SAMPLE_XXX */ + .sjw = ISO11898_SJW_2TQ, /*!< specifies the maximum number of time quanta the ISO11898 hardware is allowed to lengthen or shorten a bit to perform resynchronization. @ref ISO11898_SJW_XXX */ + .bs1 = ISO11898_BS1_9TQ, /*!< specifies the number of time quanta in Bit Segment 1. @ref ISO11898_BS1_XXX */ + .bs2 = ISO11898_BS2_6TQ, /*!< specifies the number of time quanta in Bit Segment 2. @ref ISO11898_BS2_XXX */ +}; + +struct bflb_iso11898_msg_s msg_tx = { + .std_id = 0x59, /*!< specifies the standard identifier, this parameter can be a value between 0 to 0x7FF */ + .ext_id = 0x154863, /*!< specifies the extended identifier, this parameter can be a value between 0 to 0x1FFFFFFF */ + .id_type = ISO11898_ID_EXTENDED, /*!< specifies the type of identifier for the message that will be send or received. @ref ISO11898_ID_XXX */ + .rtr = ISO11898_RTR_DATA, /*!< specifies the type of frame for the message that will be send or received, @ref ISO11898_RTR_XXX */ + .dlc = 8, /*!< specifies the length of the frame that will be send or received, this parameter can be a value between 0 to 8 */ + .data = { 0x2E, 0x53, 0xF6, 0x81, 0xD4, 0xC0, 0x7A, 0xB9 }, /*!< contains the data to be send or received, it ranges from 0 to 0xFF */ +}; + +void iso11898_isr(int irq, void *arg) +{ + uint32_t int_status = bflb_iso11898_get_int_status(iso11898); + + if (int_status & ISO11898_INTSTS_RX) { + struct bflb_iso11898_msg_s msg; + bflb_iso11898_recv(iso11898, &msg, 100); + printf("Receive "); + if (msg.id_type == ISO11898_ID_STANDARD) { + printf("standard frame, ID = 0x%03lX, ", msg.std_id); + } else { + printf("extend frame, ID = 0x%08lX, ", msg.ext_id); + } + if (msg.rtr == ISO11898_RTR_DATA) { + printf("data frame[%d]\r\n", msg.dlc); + for (uint32_t i = 0; i < msg.dlc; i++) { + printf("%02X ", msg.data[i]); + } + printf("\r\n\r\n"); + } else { + printf("remote frame\r\n\r\n"); + } + } + if (int_status & ISO11898_INTSTS_TX) { + printf("tx succeed!\r\n\r\n"); + } +} + +int main(void) +{ + board_init(); + board_iso11898_gpio_init(); + + iso11898 = bflb_device_get_by_name("iso11898"); + + bflb_iso11898_init(iso11898, &cfg); + bflb_irq_attach(iso11898->irq_num, iso11898_isr, NULL); + bflb_iso11898_txint_mask(iso11898, false); + bflb_iso11898_rxint_mask(iso11898, false); + bflb_irq_enable(iso11898->irq_num); + bflb_iso11898_send(iso11898, &msg_tx, 1000); + + while (1) { + bflb_mtimer_delay_ms(2000); + } +} diff --git a/examples/peripherals/iso11898/iso11898_interrupt/proj.conf b/examples/peripherals/iso11898/iso11898_interrupt/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_interrupt/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_selftest/CMakeLists.txt b/examples/peripherals/iso11898/iso11898_selftest/CMakeLists.txt new file mode 100644 index 00000000..d33abb79 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_selftest/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(iso11898_selftest) diff --git a/examples/peripherals/iso11898/iso11898_selftest/Makefile b/examples/peripherals/iso11898/iso11898_selftest/Makefile new file mode 100644 index 00000000..0b519efe --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_selftest/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl628 +BOARD ?= bl628dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_selftest/README.md b/examples/peripherals/iso11898/iso11898_selftest/README.md new file mode 100644 index 00000000..6de40e1d --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_selftest/README.md @@ -0,0 +1,30 @@ +# iso11898_selftest + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_selftest/flash_prog_cfg.ini b/examples/peripherals/iso11898/iso11898_selftest/flash_prog_cfg.ini new file mode 100644 index 00000000..1bffa277 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_selftest/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/iso11898*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/iso11898/iso11898_selftest/main.c b/examples/peripherals/iso11898/iso11898_selftest/main.c new file mode 100644 index 00000000..7298d861 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_selftest/main.c @@ -0,0 +1,81 @@ +#include "bflb_mtimer.h" +#include "bflb_iso11898.h" +#include "board.h" + +struct bflb_device_s *iso11898; + +struct bflb_iso11898_config_s cfg = { + .prescaler = 0, /*!< specifies the length of a time quantum, ranges from 1 to 63, tq=tclk*2*(prescaler+1) */ + .mode = ISO11898_MODE_LOOPBACK, /*!< specifies the CAN operating mode. @ref ISO11898_MODE_XXX */ + .sample = ISO11898_SAMPLE_TRIPLE, /*!< specifies the number of sample times. @ref ISO11898_SAMPLE_XXX */ + .sjw = ISO11898_SJW_2TQ, /*!< specifies the maximum number of time quanta the ISO11898 hardware is allowed to lengthen or shorten a bit to perform resynchronization. @ref ISO11898_SJW_XXX */ + .bs1 = ISO11898_BS1_9TQ, /*!< specifies the number of time quanta in Bit Segment 1. @ref ISO11898_BS1_XXX */ + .bs2 = ISO11898_BS2_6TQ, /*!< specifies the number of time quanta in Bit Segment 2. @ref ISO11898_BS2_XXX */ +}; + +struct bflb_iso11898_filter_s filter = { + .filter_type = ISO11898_FILTER_TYPE_SINGLE, + .code0 = 0, + .code1 = 0, + .code2 = 0, + .code3 = 0, + .mask0 = 0xFF, + .mask1 = 0xFF, + .mask2 = 0xFF, + .mask3 = 0xFF, +}; + +struct bflb_iso11898_msg_s msg_tx = { + .std_id = 0x59, /*!< specifies the standard identifier, this parameter can be a value between 0 to 0x7FF */ + .ext_id = 0x154863, /*!< specifies the extended identifier, this parameter can be a value between 0 to 0x1FFFFFFF */ + .id_type = ISO11898_ID_EXTENDED, /*!< specifies the type of identifier for the message that will be send or received. @ref ISO11898_ID_XXX */ + .rtr = ISO11898_RTR_DATA, /*!< specifies the type of frame for the message that will be send or received, @ref ISO11898_RTR_XXX */ + .dlc = 8, /*!< specifies the length of the frame that will be send or received, this parameter can be a value between 0 to 8 */ + .data = { 0x2E, 0x53, 0xF6, 0x81, 0xD4, 0xC0, 0x7A, 0xB9 }, /*!< contains the data to be send or received, it ranges from 0 to 0xFF */ +}; + +struct bflb_iso11898_msg_s msg_rx; + +int main(void) +{ + int ret = 0; + board_init(); + board_iso11898_gpio_init(); + + iso11898 = bflb_device_get_by_name("iso11898"); + + bflb_iso11898_init(iso11898, &cfg); + bflb_iso11898_set_filter(iso11898, &filter); + ret = bflb_iso11898_send(iso11898, &msg_tx, 1000); + if (ret != 0) { + printf("send failed!\r\n"); + while (1) { + } + } + + ret = bflb_iso11898_recv(iso11898, &msg_rx, 10000); + if (ret != 0) { + printf("recv failed!\r\n"); + while (1) { + } + } + printf("Receive \r\n"); + if (msg_rx.id_type == ISO11898_ID_STANDARD) { + printf("standard frame, ID = 0x%03lX, ", msg_rx.std_id); + } else { + printf("extend frame, ID = 0x%08lX, ", msg_rx.ext_id); + } + if (msg_rx.rtr == ISO11898_RTR_DATA) { + printf("data frame[%d]\r\n", msg_rx.dlc); + for (uint32_t i = 0; i < msg_rx.dlc; i++) { + printf("%02X ", msg_rx.data[i]); + } + printf("\r\n\r\n"); + } else { + printf("remote frame\r\n\r\n"); + } + + while (1) { + bflb_mtimer_delay_ms(2000); + } +} diff --git a/examples/peripherals/iso11898/iso11898_selftest/proj.conf b/examples/peripherals/iso11898/iso11898_selftest/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/iso11898/iso11898_selftest/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/mjpeg/mjpeg_no_camera/README.md b/examples/peripherals/mjpeg/mjpeg_no_camera/README.md new file mode 100644 index 00000000..62fe1003 --- /dev/null +++ b/examples/peripherals/mjpeg/mjpeg_no_camera/README.md @@ -0,0 +1,37 @@ +# mjpeg_no_camera + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/mjpeg/mjpeg_no_camera/flash_prog_cfg.ini b/examples/peripherals/mjpeg/mjpeg_no_camera/flash_prog_cfg.ini new file mode 100644 index 00000000..17fcdebe --- /dev/null +++ b/examples/peripherals/mjpeg/mjpeg_no_camera/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/mjpeg*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/mtimer/README.md b/examples/peripherals/mtimer/README.md new file mode 100644 index 00000000..73557a7b --- /dev/null +++ b/examples/peripherals/mtimer/README.md @@ -0,0 +1,44 @@ +# mtimer + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/mtimer/flash_prog_cfg.ini b/examples/peripherals/mtimer/flash_prog_cfg.ini new file mode 100644 index 00000000..9c7dda92 --- /dev/null +++ b/examples/peripherals/mtimer/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/mtimer*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/psram/README.md b/examples/peripherals/psram/README.md new file mode 100644 index 00000000..fa6ab0c3 --- /dev/null +++ b/examples/peripherals/psram/README.md @@ -0,0 +1,37 @@ +# psram + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/psram/flash_prog_cfg.ini b/examples/peripherals/psram/flash_prog_cfg.ini new file mode 100644 index 00000000..9c7dda92 --- /dev/null +++ b/examples/peripherals/psram/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/mtimer*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v1/pwm_all_channels/README.md b/examples/peripherals/pwm_v1/pwm_all_channels/README.md new file mode 100644 index 00000000..73ca0fba --- /dev/null +++ b/examples/peripherals/pwm_v1/pwm_all_channels/README.md @@ -0,0 +1,23 @@ +# pwm_all_channels + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v1/pwm_all_channels/flash_prog_cfg.ini b/examples/peripherals/pwm_v1/pwm_all_channels/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v1/pwm_all_channels/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v1/pwm_basic/README.md b/examples/peripherals/pwm_v1/pwm_basic/README.md new file mode 100644 index 00000000..1925e5d1 --- /dev/null +++ b/examples/peripherals/pwm_v1/pwm_basic/README.md @@ -0,0 +1,23 @@ +# pwm_basic + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v1/pwm_basic/flash_prog_cfg.ini b/examples/peripherals/pwm_v1/pwm_basic/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v1/pwm_basic/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v1/pwm_int/README.md b/examples/peripherals/pwm_v1/pwm_int/README.md new file mode 100644 index 00000000..dfa5084f --- /dev/null +++ b/examples/peripherals/pwm_v1/pwm_int/README.md @@ -0,0 +1,23 @@ +# pwm_int + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v1/pwm_int/flash_prog_cfg.ini b/examples/peripherals/pwm_v1/pwm_int/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v1/pwm_int/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_all_channels/README.md b/examples/peripherals/pwm_v2/pwm_all_channels/README.md new file mode 100644 index 00000000..cebdb00b --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_all_channels/README.md @@ -0,0 +1,30 @@ +# pwm_all_channels + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_all_channels/flash_prog_cfg.ini b/examples/peripherals/pwm_v2/pwm_all_channels/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_all_channels/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_basic/README.md b/examples/peripherals/pwm_v2/pwm_basic/README.md new file mode 100644 index 00000000..6ad759e1 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_basic/README.md @@ -0,0 +1,30 @@ +# pwm_basic + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_basic/flash_prog_cfg.ini b/examples/peripherals/pwm_v2/pwm_basic/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_basic/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_config_channel/README.md b/examples/peripherals/pwm_v2/pwm_config_channel/README.md new file mode 100644 index 00000000..e531f226 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_config_channel/README.md @@ -0,0 +1,30 @@ +# pwm_config_channel + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_config_channel/flash_prog_cfg.ini b/examples/peripherals/pwm_v2/pwm_config_channel/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_config_channel/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_deadtime/README.md b/examples/peripherals/pwm_v2/pwm_deadtime/README.md new file mode 100644 index 00000000..75a1a418 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_deadtime/README.md @@ -0,0 +1,30 @@ +# pwm_deadtime + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_deadtime/flash_prog_cfg.ini b/examples/peripherals/pwm_v2/pwm_deadtime/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_deadtime/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_int/README.md b/examples/peripherals/pwm_v2/pwm_int/README.md new file mode 100644 index 00000000..65fd9a40 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_int/README.md @@ -0,0 +1,29 @@ +# pwm_int + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/pwm_v2/pwm_int/flash_prog_cfg.ini b/examples/peripherals/pwm_v2/pwm_int/flash_prog_cfg.ini new file mode 100644 index 00000000..c42feef9 --- /dev/null +++ b/examples/peripherals/pwm_v2/pwm_int/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/pwm*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/rtc/README.md b/examples/peripherals/rtc/README.md new file mode 100644 index 00000000..75d0ef3d --- /dev/null +++ b/examples/peripherals/rtc/README.md @@ -0,0 +1,44 @@ +# rtc + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/rtc/flash_prog_cfg.ini b/examples/peripherals/rtc/flash_prog_cfg.ini new file mode 100644 index 00000000..a5164a46 --- /dev/null +++ b/examples/peripherals/rtc/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/rtc*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/README.md b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/README.md new file mode 100644 index 00000000..4a1d7136 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/README.md @@ -0,0 +1,44 @@ +# sec_eng_aes_link_sw_key + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | Only support ecb/cbc/ctr | +|BL702/BL704/BL706 | Only support ecb/cbc/ctr | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_sw_key/README.md b/examples/peripherals/sec_eng/sec_eng_aes_sw_key/README.md new file mode 100644 index 00000000..f08377fc --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_sw_key/README.md @@ -0,0 +1,44 @@ +# sec_eng_aes_sw_key + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | Only support ecb/cbc/ctr | +|BL702/BL704/BL706 | Only support ecb/cbc/ctr | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_sw_key/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_aes_sw_key/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_sw_key/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/README.md b/examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/README.md new file mode 100644 index 00000000..92862cb8 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/README.md @@ -0,0 +1,44 @@ +# sec_eng_aes_sw_key_costtime + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | Only support ecb/cbc/ctr | +|BL702/BL704/BL706 | Only support ecb/cbc/ctr | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_sw_key_costtime/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_dsa/README.md b/examples/peripherals/sec_eng/sec_eng_dsa/README.md new file mode 100644 index 00000000..5e7dab61 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_dsa/README.md @@ -0,0 +1,44 @@ +# sec_eng_dsa + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_dsa/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_dsa/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_dsa/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_ecdh/README.md b/examples/peripherals/sec_eng/sec_eng_ecdh/README.md new file mode 100644 index 00000000..9e9e4880 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdh/README.md @@ -0,0 +1,44 @@ +# sec_eng_ecdh + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_ecdh/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_ecdh/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdh/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_ecdsa/README.md b/examples/peripherals/sec_eng/sec_eng_ecdsa/README.md new file mode 100644 index 00000000..b129275c --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdsa/README.md @@ -0,0 +1,44 @@ +# sec_eng_ecdsa + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_ecdsa/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_ecdsa/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdsa/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha/README.md b/examples/peripherals/sec_eng/sec_eng_sha/README.md new file mode 100644 index 00000000..4f1095b1 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha/README.md @@ -0,0 +1,44 @@ +# sec_eng_sha + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | Only support sha1/sha224/sha256 | +|BL702/BL704/BL706 | Only support sha1/sha224/sha256 | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_sha/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha_costtime/README.md b/examples/peripherals/sec_eng/sec_eng_sha_costtime/README.md new file mode 100644 index 00000000..f7a17826 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_costtime/README.md @@ -0,0 +1,44 @@ +# sec_eng_sha_costtime + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | Only support sha1/sha224/sha256 | +|BL702/BL704/BL706 | Only support sha1/sha224/sha256 | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha_costtime/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_sha_costtime/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_costtime/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha_link/README.md b/examples/peripherals/sec_eng/sec_eng_sha_link/README.md new file mode 100644 index 00000000..5f9e1e74 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_link/README.md @@ -0,0 +1,44 @@ +# sec_eng_sha_link + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | Only support sha1/sha224/sha256 | +|BL702/BL704/BL706 | Only support sha1/sha224/sha256 | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha_link/flash_prog_cfg.ini b/examples/peripherals/sec_eng/sec_eng_sha_link/flash_prog_cfg.ini new file mode 100644 index 00000000..496ccb39 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_link/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sec_eng*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/sec_eng/trng_random/README.md b/examples/peripherals/sec_eng/trng_random/README.md new file mode 100644 index 00000000..18f10af6 --- /dev/null +++ b/examples/peripherals/sec_eng/trng_random/README.md @@ -0,0 +1,44 @@ +# trng_random + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/sec_eng/trng_random/flash_prog_cfg.ini b/examples/peripherals/sec_eng/trng_random/flash_prog_cfg.ini new file mode 100644 index 00000000..b629af3a --- /dev/null +++ b/examples/peripherals/sec_eng/trng_random/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/trng_random*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/spi/spi_dma/README.md b/examples/peripherals/spi/spi_dma/README.md new file mode 100644 index 00000000..c38966c0 --- /dev/null +++ b/examples/peripherals/spi/spi_dma/README.md @@ -0,0 +1,44 @@ +# spi_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/spi/spi_dma/flash_prog_cfg.ini b/examples/peripherals/spi/spi_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..b68fbb6d --- /dev/null +++ b/examples/peripherals/spi/spi_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/spi*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/spi/spi_int/README.md b/examples/peripherals/spi/spi_int/README.md new file mode 100644 index 00000000..68b3dd3a --- /dev/null +++ b/examples/peripherals/spi/spi_int/README.md @@ -0,0 +1,44 @@ +# spi_int + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in spi0, should use spi1 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/spi/spi_int/flash_prog_cfg.ini b/examples/peripherals/spi/spi_int/flash_prog_cfg.ini new file mode 100644 index 00000000..b68fbb6d --- /dev/null +++ b/examples/peripherals/spi/spi_int/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/spi*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/spi/spi_poll/README.md b/examples/peripherals/spi/spi_poll/README.md new file mode 100644 index 00000000..a0944968 --- /dev/null +++ b/examples/peripherals/spi/spi_poll/README.md @@ -0,0 +1,44 @@ +# spi_poll + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/spi/spi_poll/flash_prog_cfg.ini b/examples/peripherals/spi/spi_poll/flash_prog_cfg.ini new file mode 100644 index 00000000..b68fbb6d --- /dev/null +++ b/examples/peripherals/spi/spi_poll/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/spi*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/timer/timer_clksource_check/README.md b/examples/peripherals/timer/timer_clksource_check/README.md new file mode 100644 index 00000000..2dcec54a --- /dev/null +++ b/examples/peripherals/timer/timer_clksource_check/README.md @@ -0,0 +1,44 @@ +# timer_clksource_check + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/timer/timer_clksource_check/flash_prog_cfg.ini b/examples/peripherals/timer/timer_clksource_check/flash_prog_cfg.ini new file mode 100644 index 00000000..682a97ff --- /dev/null +++ b/examples/peripherals/timer/timer_clksource_check/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/timer*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/timer/timer_int/README.md b/examples/peripherals/timer/timer_int/README.md new file mode 100644 index 00000000..e9f98ad3 --- /dev/null +++ b/examples/peripherals/timer/timer_int/README.md @@ -0,0 +1,44 @@ +# timer_int + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/timer/timer_int/flash_prog_cfg.ini b/examples/peripherals/timer/timer_int/flash_prog_cfg.ini new file mode 100644 index 00000000..682a97ff --- /dev/null +++ b/examples/peripherals/timer/timer_int/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/timer*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_auto_baudrate/README.md b/examples/peripherals/uart/uart_auto_baudrate/README.md new file mode 100644 index 00000000..3f297176 --- /dev/null +++ b/examples/peripherals/uart/uart_auto_baudrate/README.md @@ -0,0 +1,44 @@ +# uart_auto_baudrate + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in uart0 ~uart2, should use uart3 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_auto_baudrate/flash_prog_cfg.ini b/examples/peripherals/uart/uart_auto_baudrate/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_auto_baudrate/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_dma/README.md b/examples/peripherals/uart/uart_dma/README.md new file mode 100644 index 00000000..3509777e --- /dev/null +++ b/examples/peripherals/uart/uart_dma/README.md @@ -0,0 +1,44 @@ +# uart_dma + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_dma/flash_prog_cfg.ini b/examples/peripherals/uart/uart_dma/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_dma/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_error_interrupt/README.md b/examples/peripherals/uart/uart_error_interrupt/README.md new file mode 100644 index 00000000..3f297176 --- /dev/null +++ b/examples/peripherals/uart/uart_error_interrupt/README.md @@ -0,0 +1,44 @@ +# uart_auto_baudrate + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in uart0 ~uart2, should use uart3 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_error_interrupt/flash_prog_cfg.ini b/examples/peripherals/uart/uart_error_interrupt/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_error_interrupt/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_feature_control/README.md b/examples/peripherals/uart/uart_feature_control/README.md new file mode 100644 index 00000000..ba0f8565 --- /dev/null +++ b/examples/peripherals/uart/uart_feature_control/README.md @@ -0,0 +1,44 @@ +# uart_feature_control + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_feature_control/flash_prog_cfg.ini b/examples/peripherals/uart/uart_feature_control/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_feature_control/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_fifo_interrupt/README.md b/examples/peripherals/uart/uart_fifo_interrupt/README.md new file mode 100644 index 00000000..f6728780 --- /dev/null +++ b/examples/peripherals/uart/uart_fifo_interrupt/README.md @@ -0,0 +1,44 @@ +# uart_fifo_interrupt + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in uart0 ~uart2, should use uart3 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_fifo_interrupt/flash_prog_cfg.ini b/examples/peripherals/uart/uart_fifo_interrupt/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_fifo_interrupt/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_ir/README.md b/examples/peripherals/uart/uart_ir/README.md new file mode 100644 index 00000000..d94c082c --- /dev/null +++ b/examples/peripherals/uart/uart_ir/README.md @@ -0,0 +1,44 @@ +# uart_ir + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_ir/flash_prog_cfg.ini b/examples/peripherals/uart/uart_ir/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_ir/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_lin/README.md b/examples/peripherals/uart/uart_lin/README.md new file mode 100644 index 00000000..6a20c590 --- /dev/null +++ b/examples/peripherals/uart/uart_lin/README.md @@ -0,0 +1,44 @@ +# uart_lin + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in uart0 ~uart2, should use uart3 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_lin/flash_prog_cfg.ini b/examples/peripherals/uart/uart_lin/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_lin/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_poll/README.md b/examples/peripherals/uart/uart_poll/README.md new file mode 100644 index 00000000..9079f188 --- /dev/null +++ b/examples/peripherals/uart/uart_poll/README.md @@ -0,0 +1,44 @@ +# uart_poll + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_poll/flash_prog_cfg.ini b/examples/peripherals/uart/uart_poll/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_poll/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_rs485/README.md b/examples/peripherals/uart/uart_rs485/README.md new file mode 100644 index 00000000..bc66575e --- /dev/null +++ b/examples/peripherals/uart/uart_rs485/README.md @@ -0,0 +1,44 @@ +# uart_rs485 + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in uart0 ~uart2, should use uart3 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_rs485/flash_prog_cfg.ini b/examples/peripherals/uart/uart_rs485/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_rs485/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/uart/uart_sw_rts/README.md b/examples/peripherals/uart/uart_sw_rts/README.md new file mode 100644 index 00000000..bad78b93 --- /dev/null +++ b/examples/peripherals/uart/uart_sw_rts/README.md @@ -0,0 +1,44 @@ +# uart_sw_rts + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq in uart0 ~uart2, should use uart3 | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/uart/uart_sw_rts/flash_prog_cfg.ini b/examples/peripherals/uart/uart_sw_rts/flash_prog_cfg.ini new file mode 100644 index 00000000..53bd7cd6 --- /dev/null +++ b/examples/peripherals/uart/uart_sw_rts/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/uart*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/README.md b/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/README.md new file mode 100644 index 00000000..d3cbfb23 --- /dev/null +++ b/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/README.md @@ -0,0 +1,37 @@ +# usbd_audio_v1_mic_speaker_multichan + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/flash_prog_cfg.ini b/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/flash_prog_cfg.ini new file mode 100644 index 00000000..5bde55b9 --- /dev/null +++ b/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/usbd*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/pic_data.h b/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/pic_data.h deleted file mode 100644 index 1adca60e..00000000 --- a/examples/peripherals/usbdev/usbd_audio_v1_mic_speaker_multichan/pic_data.h +++ /dev/null @@ -1,1163 +0,0 @@ -/** - * @file pic_data.h - * @brief - * - * Copyright (c) 2022 sakumisu - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __PIC_DATA_H_ -#define __PIC_DATA_H_ - -const unsigned char jpeg_data[8493] = { - 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x48, - 0x00, 0x48, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x0D, 0x09, 0x0A, 0x0B, 0x0A, 0x08, 0x0D, - 0x0B, 0x0A, 0x0B, 0x0E, 0x0E, 0x0D, 0x0F, 0x13, 0x20, 0x15, 0x13, 0x12, 0x12, 0x13, 0x27, 0x1C, - 0x1E, 0x17, 0x20, 0x2E, 0x29, 0x31, 0x30, 0x2E, 0x29, 0x2D, 0x2C, 0x33, 0x3A, 0x4A, 0x3E, 0x33, - 0x36, 0x46, 0x37, 0x2C, 0x2D, 0x40, 0x57, 0x41, 0x46, 0x4C, 0x4E, 0x52, 0x53, 0x52, 0x32, 0x3E, - 0x5A, 0x61, 0x5A, 0x50, 0x60, 0x4A, 0x51, 0x52, 0x4F, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x0E, 0x0E, - 0x0E, 0x13, 0x11, 0x13, 0x26, 0x15, 0x15, 0x26, 0x4F, 0x35, 0x2D, 0x35, 0x4F, 0x4F, 0x4F, 0x4F, - 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, - 0x4F, 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0xFA, 0xD2, 0xDE, 0xF0, 0xD9, 0xAD, - 0x9E, 0xA8, 0x1B, 0xA3, 0xD7, 0xAA, 0x73, 0x27, 0x2D, 0xC4, 0x3D, 0x95, 0xC5, 0x6D, 0x46, 0x0C, - 0xDC, 0x22, 0xBD, 0xAC, 0x62, 0x19, 0x31, 0x5A, 0xDB, 0xF4, 0xEF, 0x17, 0xA8, 0xF7, 0x9F, 0x2F, - 0x03, 0x1F, 0xF3, 0xF3, 0x06, 0xFC, 0xBD, 0xB5, 0xE5, 0xF3, 0x57, 0xFF, 0xD9 -}; - -const unsigned char jpeg_data1[6603] = { - 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x48, - 0x00, 0x48, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x09, 0x06, 0x06, 0x08, 0x06, 0x05, 0x09, - 0x08, 0x07, 0x08, 0x0A, 0x09, 0x09, 0x0A, 0x0D, 0x16, 0x0E, 0x0D, 0x0C, 0x0C, 0x0D, 0x1A, 0x13, - 0x14, 0x10, 0x16, 0x1F, 0x1C, 0x21, 0x20, 0x1F, 0x1C, 0x1E, 0x1E, 0x23, 0x27, 0x32, 0x2A, 0x23, - 0x25, 0x2F, 0x25, 0x1E, 0x1E, 0x2B, 0x3B, 0x2C, 0x2F, 0x33, 0x35, 0x38, 0x38, 0x38, 0x21, 0x2A, - 0x3D, 0x41, 0x3C, 0x36, 0x41, 0x32, 0x37, 0x38, 0x35, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x09, 0x0A, - 0x0A, 0x0D, 0x0B, 0x0D, 0x19, 0x0E, 0x0E, 0x19, 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0x5D, 0xA0, 0xE7, 0x93, 0x2A, 0x81, 0xFE, 0x7D, 0xAB, 0xF2, 0xF3, 0x5F, 0x8F, 0xEC, 0x3F, 0x12, 0x3C, 0x59, 0x0F, 0x3F, 0xBB, 0xD5, 0x6E, 0x57, 0x07, 0xB6, 0x25, 0x7A, 0x32, 0x7A, 0x74, 0xEB, 0xC2, 0x2E, 0xB5, 0x28, 0xA6, 0xD5, 0xF4, 0x8A, 0x5D, 0x5A, 0x33, 0xE2, 0x48, 0x54, 0xC1, 0xD6, 0x94, 0x30, 0xD8, 0x8A, 0x92, 0x8A, 0x93, 0x8E, 0xB3, 0x6F, 0xEC, 0xA7, 0xE5, 0xDC, 0xE9, 0xAE, 0x3F, 0x6A, 0x9F, 0x8B, 0xF7, 0x27, 0xF7, 0x9E, 0x34, 0xD6, 0x1F, 0xD4, 0xB4, 0xC0, 0xFF, 0x00, 0x4A, 0x8C, 0x7E, 0xD4, 0x1F, 0x17, 0x19, 0x7E, 0x5F, 0x1A, 0x6A, 0xCA, 0x3D, 0xA6, 0x03, 0xFA, 0x57, 0x27, 0x3C, 0xF8, 0xFC, 0x7D, 0x6A, 0x9C, 0x92, 0x90, 0x31, 0x9E, 0x2B, 0xDB, 0x96, 0x5F, 0x86, 0xFE, 0x45, 0xF7, 0x1F, 0x37, 0x1C, 0xC3, 0x17, 0xBF, 0xB5, 0x97, 0xFE, 0x04, 0xCF, 0x52, 0xB5, 0xF8, 0x8B, 0xF1, 0xBF, 0x57, 0xD2, 0x56, 0xFA, 0x1F, 0x16, 0x6A, 0x52, 0xC0, 0xDD, 0x1B, 0xED, 0x23, 0x3F, 0xCA, 0xB3, 0xE6, 0xF8, 0x9D, 0xF1, 0x9B, 0x3C, 0xF8, 0xAB, 0x55, 0xEB, 0xFF, 0x00, 0x3F, 0x03, 0xFC, 0x2B, 0x2B, 0xE1, 0xBF, 0xC5, 0x19, 0x7C, 0x34, 0x92, 0x59, 0x4C, 0xCC, 0xD6, 0xB3, 0xF0, 0xA0, 0xFF, 0x00, 0x01, 0xF6, 0xAE, 0xCD, 0xAF, 0xC5, 0xCA, 0xEF, 0x56, 0xCA, 0xB7, 0x35, 0x8C, 0x70, 0x74, 0x96, 0xF0, 0x5F, 0x71, 0xA4, 0xB1, 0x95, 0xDD, 0xB9, 0x6A, 0xCB, 0xFF, 0x00, 0x02, 0x67, 0xFF, 0xD9 -}; -#endif diff --git a/examples/peripherals/usbdev/usbd_cdc_acm/README.md b/examples/peripherals/usbdev/usbd_cdc_acm/README.md new file mode 100644 index 00000000..3bf5dd89 --- /dev/null +++ b/examples/peripherals/usbdev/usbd_cdc_acm/README.md @@ -0,0 +1,37 @@ +# usbd_cdc_acm + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_cdc_acm/flash_prog_cfg.ini b/examples/peripherals/usbdev/usbd_cdc_acm/flash_prog_cfg.ini new file mode 100644 index 00000000..5bde55b9 --- /dev/null +++ b/examples/peripherals/usbdev/usbd_cdc_acm/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/usbd*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_msc_ram/README.md b/examples/peripherals/usbdev/usbd_msc_ram/README.md new file mode 100644 index 00000000..1c18f1e2 --- /dev/null +++ b/examples/peripherals/usbdev/usbd_msc_ram/README.md @@ -0,0 +1,37 @@ +# usbd_msc_ram + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_msc_ram/flash_prog_cfg.ini b/examples/peripherals/usbdev/usbd_msc_ram/flash_prog_cfg.ini new file mode 100644 index 00000000..5bde55b9 --- /dev/null +++ b/examples/peripherals/usbdev/usbd_msc_ram/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/usbd*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_msc_ram/pic_data.h b/examples/peripherals/usbdev/usbd_msc_ram/pic_data.h deleted file mode 100644 index 1adca60e..00000000 --- a/examples/peripherals/usbdev/usbd_msc_ram/pic_data.h +++ /dev/null @@ -1,1163 +0,0 @@ -/** - * @file pic_data.h - * @brief - * - * Copyright (c) 2022 sakumisu - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __PIC_DATA_H_ -#define __PIC_DATA_H_ - -const unsigned char jpeg_data[8493] = { - 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x48, - 0x00, 0x48, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x0D, 0x09, 0x0A, 0x0B, 0x0A, 0x08, 0x0D, - 0x0B, 0x0A, 0x0B, 0x0E, 0x0E, 0x0D, 0x0F, 0x13, 0x20, 0x15, 0x13, 0x12, 0x12, 0x13, 0x27, 0x1C, - 0x1E, 0x17, 0x20, 0x2E, 0x29, 0x31, 0x30, 0x2E, 0x29, 0x2D, 0x2C, 0x33, 0x3A, 0x4A, 0x3E, 0x33, - 0x36, 0x46, 0x37, 0x2C, 0x2D, 0x40, 0x57, 0x41, 0x46, 0x4C, 0x4E, 0x52, 0x53, 0x52, 0x32, 0x3E, - 0x5A, 0x61, 0x5A, 0x50, 0x60, 0x4A, 0x51, 0x52, 0x4F, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x0E, 0x0E, - 0x0E, 0x13, 0x11, 0x13, 0x26, 0x15, 0x15, 0x26, 0x4F, 0x35, 0x2D, 0x35, 0x4F, 0x4F, 0x4F, 0x4F, - 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, - 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, - 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0xFF, 0xC0, - 0x00, 0x11, 0x08, 0x00, 0xF0, 0x01, 0x40, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, - 0x01, 0xFF, 0xC4, 0x00, 0x1B, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0xFF, 0xC4, - 0x00, 0x3B, 0x10, 0x01, 0x00, 0x02, 0x01, 0x02, 0x03, 0x05, 0x06, 0x04, 0x05, 0x04, 0x02, 0x02, - 0x03, 0x00, 0x00, 0x01, 0x00, 0x02, 0x03, 0x04, 0x11, 0x05, 0x21, 0x31, 0x12, 0x41, 0x51, 0x61, - 0x71, 0x06, 0x13, 0x81, 0x91, 0xA1, 0xC1, 0x14, 0x22, 0xB1, 0xD1, 0x07, 0x23, 0x32, 0x52, 0xF0, - 0x33, 0x42, 0x72, 0xE1, 0x15, 0x62, 0x24, 0xF1, 0x43, 0x53, 0xB2, 0xFF, 0xC4, 0x00, 0x1A, 0x01, - 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0xFF, 0xC4, 0x00, 0x23, 0x11, 0x01, 0x01, 0x00, 0x02, - 0x02, 0x03, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x11, - 0x03, 0x21, 0x12, 0x31, 0x41, 0x13, 0x22, 0x51, 0x04, 0x33, 0x14, 0x61, 0xFF, 0xDA, 0x00, 0x0C, - 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xE4, 0x12, 0x0A, 0x49, 0x12, 0x0A, - 0x4F, 0x66, 0xF2, 0xC6, 0x04, 0x82, 0x90, 0xD2, 0x32, 0x49, 0xAC, 0x68, 0xD2, 0x32, 0x43, 0x48, - 0x29, 0x15, 0x43, 0x02, 0x46, 0x48, 0x69, 0x05, 0x21, 0x31, 0x81, 0x20, 0xA4, 0x91, 0x20, 0xA4, - 0x55, 0x0D, 0x1A, 0x41, 0x49, 0x22, 0x41, 0x48, 0xAB, 0x18, 0x12, 0x0A, 0x43, 0x48, 0xC9, 0x15, - 0x43, 0x46, 0x90, 0x52, 0x48, 0x90, 0x52, 0x2A, 0x86, 0x04, 0x8A, 0x3A, 0x46, 0x48, 0xAA, 0x19, - 0x45, 0x14, 0x50, 0x9C, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, - 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, - 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x45, 0xBC, 0x91, 0x92, 0x48, - 0x90, 0x12, 0x74, 0x5E, 0x58, 0xC0, 0x90, 0x52, 0x48, 0x90, 0x52, 0x15, 0x0C, 0x09, 0x05, 0x21, - 0xA4, 0x64, 0x93, 0x58, 0xD1, 0xA4, 0x64, 0x86, 0x90, 0x52, 0x2A, 0x86, 0x04, 0x8C, 0x90, 0xD2, - 0x0A, 0x42, 0x63, 0x02, 0x41, 0x49, 0x22, 0x41, 0x48, 0xAA, 0x1A, 0x34, 0x82, 0x92, 0x44, 0x82, - 0x91, 0x56, 0x30, 0x24, 0x14, 0x86, 0x91, 0x92, 0x2A, 0x86, 0x8D, 0x20, 0xA4, 0x91, 0x20, 0xA4, - 0x55, 0x0C, 0x09, 0x14, 0x74, 0x8C, 0x91, 0x54, 0x32, 0x8A, 0x28, 0x55, 0xAB, 0x62, 0xDB, 0x1F, - 0xD2, 0x6E, 0xF9, 0x1B, 0xED, 0xF7, 0x22, 0x9C, 0x31, 0xC7, 0x64, 0x50, 0x4F, 0x08, 0xD1, 0x47, - 0x15, 0xBC, 0xDA, 0x44, 0xC3, 0x5C, 0xF8, 0xB7, 0xB6, 0x2B, 0x1C, 0xFC, 0x6A, 0xF7, 0x8F, 0xEF, - 0x2A, 0x4D, 0x8D, 0x05, 0xF6, 0xD1, 0xD4, 0x7A, 0x2B, 0xC9, 0xF5, 0x94, 0x75, 0xB8, 0x0C, 0x79, - 0x56, 0x86, 0xD4, 0xB7, 0x30, 0xF0, 0xF2, 0x92, 0x36, 0x99, 0x61, 0xD7, 0x91, 0x55, 0x88, 0xE7, - 0x3A, 0x0E, 0x03, 0xC3, 0x31, 0xE4, 0xDF, 0x53, 0xAA, 0xA1, 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0xFA, 0xD2, 0xDE, 0xF0, 0xD9, 0xAD, - 0x9E, 0xA8, 0x1B, 0xA3, 0xD7, 0xAA, 0x73, 0x27, 0x2D, 0xC4, 0x3D, 0x95, 0xC5, 0x6D, 0x46, 0x0C, - 0xDC, 0x22, 0xBD, 0xAC, 0x62, 0x19, 0x31, 0x5A, 0xDB, 0xF4, 0xEF, 0x17, 0xA8, 0xF7, 0x9F, 0x2F, - 0x03, 0x1F, 0xF3, 0xF3, 0x06, 0xFC, 0xBD, 0xB5, 0xE5, 0xF3, 0x57, 0xFF, 0xD9 -}; - -const unsigned char jpeg_data1[6603] = { - 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x48, - 0x00, 0x48, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x09, 0x06, 0x06, 0x08, 0x06, 0x05, 0x09, - 0x08, 0x07, 0x08, 0x0A, 0x09, 0x09, 0x0A, 0x0D, 0x16, 0x0E, 0x0D, 0x0C, 0x0C, 0x0D, 0x1A, 0x13, - 0x14, 0x10, 0x16, 0x1F, 0x1C, 0x21, 0x20, 0x1F, 0x1C, 0x1E, 0x1E, 0x23, 0x27, 0x32, 0x2A, 0x23, - 0x25, 0x2F, 0x25, 0x1E, 0x1E, 0x2B, 0x3B, 0x2C, 0x2F, 0x33, 0x35, 0x38, 0x38, 0x38, 0x21, 0x2A, - 0x3D, 0x41, 0x3C, 0x36, 0x41, 0x32, 0x37, 0x38, 0x35, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x09, 0x0A, - 0x0A, 0x0D, 0x0B, 0x0D, 0x19, 0x0E, 0x0E, 0x19, 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com name +``` \ No newline at end of file diff --git a/examples/peripherals/usbdev/usbd_static_video/flash_prog_cfg.ini b/examples/peripherals/usbdev/usbd_static_video/flash_prog_cfg.ini new file mode 100644 index 00000000..5bde55b9 --- /dev/null +++ b/examples/peripherals/usbdev/usbd_static_video/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/usbd*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/usbhost/FreeRTOSConfig.h b/examples/peripherals/usbhost/FreeRTOSConfig.h index 6b521a6a..c8973483 100644 --- a/examples/peripherals/usbhost/FreeRTOSConfig.h +++ b/examples/peripherals/usbhost/FreeRTOSConfig.h @@ -39,17 +39,21 @@ * * See http://www.freertos.org/a00110.html. *----------------------------------------------------------*/ -#include "stdio.h" -#ifdef BL702 +#if defined(BL602) || defined(BL702) || defined(BL702L) #define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) #define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) #else -#define configMTIME_BASE_ADDRESS (0xE0000000UL + 0xBFF8UL) -#define configMTIMECMP_BASE_ADDRESS (0xE0000000UL + 0x4000UL) +#if __riscv_xlen == 64 +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) +#endif #endif -// #define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 #define configUSE_TICK_HOOK 0 @@ -57,7 +61,7 @@ #define configTICK_RATE_HZ ((TickType_t)1000) #define configMAX_PRIORITIES (7) #define configMINIMAL_STACK_SIZE ((unsigned short)128) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ -#define configTOTAL_HEAP_SIZE ((size_t)12 * 1024) +#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024) #define configMAX_TASK_NAME_LEN (16) #define configUSE_TRACE_FACILITY 1 #define configUSE_STATS_FORMATTING_FUNCTIONS 1 @@ -68,21 +72,22 @@ #define configCHECK_FOR_STACK_OVERFLOW 2 #define configUSE_RECURSIVE_MUTEXES 1 #define configUSE_MALLOC_FAILED_HOOK 1 -#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_APPLICATION_TASK_TAG 1 #define configUSE_COUNTING_SEMAPHORES 1 #define configGENERATE_RUN_TIME_STATS 0 #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 #define configUSE_TICKLESS_IDLE 0 +#define configUSE_POSIX_ERRNO 1 /* Co-routine definitions. */ -#define configUSE_CO_ROUTINES 0 -#define configMAX_CO_ROUTINE_PRIORITIES (2) +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) /* Software timer definitions. */ -#define configUSE_TIMERS 1 -#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) -#define configTIMER_QUEUE_LENGTH 4 -#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) /* Task priorities. Allow these to be overridden. */ #ifndef uartPRIMARY_PRIORITY @@ -108,6 +113,9 @@ to exclude the API function. */ header file. */ void vApplicationMallocFailedHook(void); void vAssertCalled(void); + +#include + #define configASSERT(x) \ if ((x) == 0) { \ printf("file [%s]\r\n", __FILE__); \ diff --git a/examples/peripherals/usbhost/README.md b/examples/peripherals/usbhost/README.md new file mode 100644 index 00000000..460738b7 --- /dev/null +++ b/examples/peripherals/usbhost/README.md @@ -0,0 +1,29 @@ +# usbhost + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL616/BL618 | | +|BL808 | D0 has no irq | + +## Compile + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/usbhost/flash_prog_cfg.ini b/examples/peripherals/usbhost/flash_prog_cfg.ini new file mode 100644 index 00000000..85581a43 --- /dev/null +++ b/examples/peripherals/usbhost/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/usbhost*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/usbhost/main.c b/examples/peripherals/usbhost/main.c index 178f2c00..f5347bd6 100644 --- a/examples/peripherals/usbhost/main.c +++ b/examples/peripherals/usbhost/main.c @@ -3,23 +3,12 @@ #include "usbh_core.h" #include "board.h" -static uint8_t freertos_heap[configTOTAL_HEAP_SIZE]; - -static HeapRegion_t xHeapRegions[] = { - { (uint8_t *)freertos_heap, 0 }, - { NULL, 0 }, /* Terminates the array. */ - { NULL, 0 } /* Terminates the array. */ -}; - extern void usbh_class_test(void); int main(void) { board_init(); - xHeapRegions[0].xSizeInBytes = configTOTAL_HEAP_SIZE; - vPortDefineHeapRegions(xHeapRegions); - printf("Starting usb host task...\r\n"); usbh_initialize(); usbh_class_test(); @@ -27,4 +16,4 @@ int main(void) while (1) { } -} \ No newline at end of file +} diff --git a/examples/peripherals/usbhost/proj.conf b/examples/peripherals/usbhost/proj.conf index c5b281c2..034ee7ed 100644 --- a/examples/peripherals/usbhost/proj.conf +++ b/examples/peripherals/usbhost/proj.conf @@ -2,4 +2,4 @@ set(CONFIG_FREERTOS 1) set(CONFIG_CHERRYUSB 1) set(CONFIG_CHERRYUSB_HOST 1) set(CONFIG_CHERRYUSB_HOST_DEMO 1) -set(CONFIG_PSRAM 1) \ No newline at end of file +set(CONFIG_PSRAM 1) diff --git a/examples/peripherals/usbhost/usb_host.c b/examples/peripherals/usbhost/usb_host.c index d7c57050..f13859fb 100644 --- a/examples/peripherals/usbhost/usb_host.c +++ b/examples/peripherals/usbhost/usb_host.c @@ -194,7 +194,178 @@ int hid_test(void) ret = usbh_submit_urb(&hid_intin_urb); return ret; } +#if 0 +#define TEST_MJPEG 1 +#define USE_VIDEO_IRQ 1 +#define VIDEO_ISO_PACKETS 8 + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t video_buffer[VIDEO_ISO_PACKETS * 3072]; /* just for reference , use ram larger than 4M */ +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t video_buffer2[VIDEO_ISO_PACKETS * 3072]; /* just for reference , use ram larger than 4M */ + +struct usbh_videostreaming g_uvcsteam; +volatile uint32_t number = 0; + +//uint8_t data_buffer[200*1024]; +void usbh_videostreaming_output(uint8_t *input, uint32_t input_len) +{ + //memcpy(&data_buffer[g_uvcsteam.bufoffset], input, input_len); +} + +void usbh_video_one_frame_callback(struct usbh_videostreaming *stream) +{ + number++; + //printf("l:%d\r\n", stream->bufoffset); +} + +struct usbh_urb *video_urb; +struct usbh_urb *video_urb2; + +volatile bool video_urb_select = 0; +volatile bool usb_transfer_abort = false; + +void usbh_iso_complete_callback(void *arg, int nbytes) +{ + if (nbytes == 0) { + video_urb2->start_frame = video_urb->start_frame; + usbh_submit_urb(video_urb2); +#if TEST_MJPEG + usbh_videostreaming_parse_mjpeg(video_urb, &g_uvcsteam); +#else + usbh_videostreaming_parse_yuyv2(video_urb, &g_uvcsteam); +#endif + } else { + printf("break1\r\n"); + usb_transfer_abort = true; + } +} + +void usbh_iso_complete_callback2(void *arg, int nbytes) +{ + if (nbytes == 0) { + video_urb->start_frame = video_urb2->start_frame; + usbh_submit_urb(video_urb); +#if TEST_MJPEG + usbh_videostreaming_parse_mjpeg(video_urb2, &g_uvcsteam); +#else + usbh_videostreaming_parse_yuyv2(video_urb2, &g_uvcsteam); +#endif + } else { + printf("break2\r\n"); + usb_transfer_abort = true; + } +} + +int video_test(void) +{ + int ret; + struct usbh_video *video_class = (struct usbh_video *)usbh_find_class_instance("/dev/video0"); + if (video_class == NULL) { + USB_LOG_RAW("do not find /dev/video0\r\n"); + return -1; + } + + uint8_t hz = 0x01; + usbh_video_set_cur(video_class, video_class->ctrl_intf, 0x02, VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE, &hz, 1); +#if TEST_MJPEG + ret = usbh_video_open(video_class, USBH_VIDEO_FORMAT_MJPEG, 1280, 720, 7); +#else + ret = usbh_video_open(video_class, USBH_VIDEO_FORMAT_UNCOMPRESSED, 640, 480, 7); +#endif + if (ret < 0) { + USB_LOG_RAW("no such setting, ret:%d\r\n", ret); + return -1; + } + + usb_osal_msleep(100); + + video_urb = usb_malloc(sizeof(struct usbh_urb) + sizeof(struct usbh_iso_frame_packet) * VIDEO_ISO_PACKETS); + if (video_urb == NULL) { + USB_LOG_ERR("No memory to alloc urb\r\n"); + while (1) { + } + } + + uint8_t *tmp_buf = video_buffer; + memset(video_urb, 0, sizeof(struct usbh_urb) + sizeof(struct usbh_iso_frame_packet) * VIDEO_ISO_PACKETS); + video_urb->pipe = video_class->isoin; + video_urb->num_of_iso_packets = VIDEO_ISO_PACKETS; + video_urb->timeout = 0xffffffff; +#if USE_VIDEO_IRQ + video_urb->complete = usbh_iso_complete_callback; + video_urb->timeout = 0; +#endif + video_urb->start_frame = (usbh_get_frame_number() + 2) & 0x3ff; + for (uint32_t i = 0; i < VIDEO_ISO_PACKETS; i++) { + video_urb->iso_packet[i].transfer_buffer = tmp_buf; + video_urb->iso_packet[i].transfer_buffer_length = video_class->isoin_mps; + tmp_buf += video_class->isoin_mps; /* enable this when use ram larger than 4M */ + } + + video_urb2 = usb_malloc(sizeof(struct usbh_urb) + sizeof(struct usbh_iso_frame_packet) * VIDEO_ISO_PACKETS); + if (video_urb2 == NULL) { + USB_LOG_ERR("No memory to alloc urb\r\n"); + while (1) { + } + } + + tmp_buf = video_buffer2; + memset(video_urb2, 0, sizeof(struct usbh_urb) + sizeof(struct usbh_iso_frame_packet) * VIDEO_ISO_PACKETS); + video_urb2->pipe = video_class->isoin; + video_urb2->num_of_iso_packets = VIDEO_ISO_PACKETS; + video_urb2->timeout = 0xffffffff; +#if USE_VIDEO_IRQ + video_urb2->complete = usbh_iso_complete_callback2; + video_urb2->timeout = 0; +#endif + video_urb2->start_frame = video_urb->start_frame; + for (uint32_t i = 0; i < VIDEO_ISO_PACKETS; i++) { + video_urb2->iso_packet[i].transfer_buffer = tmp_buf; + video_urb2->iso_packet[i].transfer_buffer_length = video_class->isoin_mps; + tmp_buf += video_class->isoin_mps; /* enable this when use ram larger than 4M */ + } + + g_uvcsteam.bufoffset = 0; + g_uvcsteam.video_one_frame_callback = usbh_video_one_frame_callback; +#if USE_VIDEO_IRQ + ret = usbh_submit_urb(video_urb); +#endif + static uint32_t start_time = 0; + start_time = bflb_mtimer_get_time_ms(); + while (1) { +#if USE_VIDEO_IRQ == 0 + ret = usbh_submit_urb(video_urb); + if (ret < 0) { + break; + } + video_urb2->start_frame = video_urb->start_frame; + ret = usbh_submit_urb(video_urb2); +#if TEST_MJPEG + usbh_videostreaming_parse_mjpeg(video_urb, &g_uvcsteam); +#else + usbh_videostreaming_parse_yuyv2(video_urb, &g_uvcsteam); +#endif + if (ret < 0) { + break; + } +#if TEST_MJPEG + usbh_videostreaming_parse_mjpeg(video_urb2, &g_uvcsteam); +#else + usbh_videostreaming_parse_yuyv2(video_urb2, &g_uvcsteam); +#endif + video_urb->start_frame = video_urb2->start_frame; +#else + printf("fps:%d\r\n",(number * 1000 / ((uint32_t)bflb_mtimer_get_time_ms() - start_time))); + usb_osal_msleep(1000); +#endif + } + printf("transfer failed\r\n"); + video_class->is_opened = false; + usb_free(video_urb); + usb_free(video_urb2); + return ret; +} +#endif static void usbh_class_test_thread(void *argument) { while (1) { @@ -203,7 +374,7 @@ static void usbh_class_test_thread(void *argument) cdc_acm_test(); msc_test(); hid_test(); - //video_test(); + // video_test(); } } diff --git a/examples/peripherals/wdg/wdg_clksource_check/README.md b/examples/peripherals/wdg/wdg_clksource_check/README.md new file mode 100644 index 00000000..2685ca88 --- /dev/null +++ b/examples/peripherals/wdg/wdg_clksource_check/README.md @@ -0,0 +1,44 @@ +# wdg_clksource_check + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/wdg/wdg_clksource_check/flash_prog_cfg.ini b/examples/peripherals/wdg/wdg_clksource_check/flash_prog_cfg.ini new file mode 100644 index 00000000..07abf323 --- /dev/null +++ b/examples/peripherals/wdg/wdg_clksource_check/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/wdg*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/wdg/wdg_int/README.md b/examples/peripherals/wdg/wdg_int/README.md new file mode 100644 index 00000000..0e03b5af --- /dev/null +++ b/examples/peripherals/wdg/wdg_int/README.md @@ -0,0 +1,44 @@ +# wdg_int + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/wdg/wdg_int/flash_prog_cfg.ini b/examples/peripherals/wdg/wdg_int/flash_prog_cfg.ini new file mode 100644 index 00000000..07abf323 --- /dev/null +++ b/examples/peripherals/wdg/wdg_int/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/wdg*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/peripherals/wdg/wdg_reset/README.md b/examples/peripherals/wdg/wdg_reset/README.md new file mode 100644 index 00000000..6b630b97 --- /dev/null +++ b/examples/peripherals/wdg/wdg_reset/README.md @@ -0,0 +1,44 @@ +# wdg_reset + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/peripherals/wdg/wdg_reset/flash_prog_cfg.ini b/examples/peripherals/wdg/wdg_reset/flash_prog_cfg.ini new file mode 100644 index 00000000..07abf323 --- /dev/null +++ b/examples/peripherals/wdg/wdg_reset/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/wdg*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/posix/freertos/CMakeLists.txt b/examples/posix/freertos/CMakeLists.txt new file mode 100644 index 00000000..dc1f167c --- /dev/null +++ b/examples/posix/freertos/CMakeLists.txt @@ -0,0 +1,12 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +target_sources(app PRIVATE mqueues_test.c semaphores_test.c) +sdk_add_include_directories(.) + +project(posix) diff --git a/examples/posix/freertos/FreeRTOSConfig.h b/examples/posix/freertos/FreeRTOSConfig.h new file mode 100644 index 00000000..94ad1f18 --- /dev/null +++ b/examples/posix/freertos/FreeRTOSConfig.h @@ -0,0 +1,135 @@ +/* + * FreeRTOS Kernel V10.2.1 + * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +#if defined(BL602) || defined(BL702) || defined(BL702L) +#define configMTIME_BASE_ADDRESS (0x02000000UL + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS (0x02000000UL + 0x4000UL) +#else +#if __riscv_xlen == 64 +#define configMTIME_BASE_ADDRESS (0) +#define configMTIMECMP_BASE_ADDRESS ((0xE4000000UL) + 0x4000UL) +#else +#define configMTIME_BASE_ADDRESS ((0xE0000000UL) + 0xBFF8UL) +#define configMTIMECMP_BASE_ADDRESS ((0xE0000000UL) + 0x4000UL) +#endif +#endif + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ((uint32_t)(1 * 1000 * 1000)) +#define configTICK_RATE_HZ ((TickType_t)1000) +#define configMAX_PRIORITIES (7) +#define configMINIMAL_STACK_SIZE ((unsigned short)2048) /* Only needs to be this high as some demo tasks also use this constant. In production only the idle task would use this. */ +#define configTOTAL_HEAP_SIZE ((size_t)24 * 1024) +#define configMAX_TASK_NAME_LEN (16) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 0 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configUSE_POSIX_ERRNO 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES (2) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES - 1) +#define configTIMER_QUEUE_LENGTH 4 +#define configTIMER_TASK_STACK_DEPTH (configMINIMAL_STACK_SIZE) + +/* Task priorities. Allow these to be overridden. */ +#ifndef uartPRIMARY_PRIORITY +#define uartPRIMARY_PRIORITY (configMAX_PRIORITIES - 3) +#endif + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 +#define INCLUDE_xSemaphoreGetMutexHolder 1 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vApplicationMallocFailedHook(void); +void vAssertCalled(void); + +#include + +#define configASSERT(x) \ + if ((x) == 0) { \ + printf("file [%s]\r\n", __FILE__); \ + printf("func [%s]\r\n", __FUNCTION__); \ + printf("line [%d]\r\n", __LINE__); \ + printf("%s\r\n", (const char *)(#x)); \ + vAssertCalled(); \ + } + +#if (configUSE_TICKLESS_IDLE != 0) +void vApplicationSleep(uint32_t xExpectedIdleTime); +#define portSUPPRESS_TICKS_AND_SLEEP(xExpectedIdleTime) vApplicationSleep(xExpectedIdleTime) +#endif + +// #define portUSING_MPU_WRAPPERS + +#endif /* FREERTOS_CONFIG_H */ diff --git a/examples/posix/freertos/Makefile b/examples/posix/freertos/Makefile new file mode 100644 index 00000000..9b01b7fe --- /dev/null +++ b/examples/posix/freertos/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/posix/freertos/README.md b/examples/posix/freertos/README.md new file mode 100644 index 00000000..4d991507 --- /dev/null +++ b/examples/posix/freertos/README.md @@ -0,0 +1,44 @@ +# shell_no_os + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/posix/freertos/flash_prog_cfg.ini b/examples/posix/freertos/flash_prog_cfg.ini new file mode 100644 index 00000000..32ab2f58 --- /dev/null +++ b/examples/posix/freertos/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/posix*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/posix/freertos/main.c b/examples/posix/freertos/main.c new file mode 100644 index 00000000..edb2264c --- /dev/null +++ b/examples/posix/freertos/main.c @@ -0,0 +1,27 @@ +#include +#include "semphr.h" +#include "board.h" + +static void proc_hellow_entry(void *pvParameters) +{ + extern int mqueues_test(void); + mqueues_test(); + extern int semaphores_test(void); + semaphores_test(); + + vTaskDelete(NULL); +} + +int main(void) +{ + board_init(); + + + puts("[OS] Starting proc_hellow_entry task...\r\n"); + xTaskCreate(proc_hellow_entry, (char*)"hellow", 2048, NULL, 6, NULL); + + vTaskStartScheduler(); + + while (1) { + } +} diff --git a/examples/posix/freertos/mqueues_test.c b/examples/posix/freertos/mqueues_test.c new file mode 100644 index 00000000..ecbc9647 --- /dev/null +++ b/examples/posix/freertos/mqueues_test.c @@ -0,0 +1,146 @@ + +/* + * Copyright (c) 2002, Intel Corporation. All rights reserved. + * Created by: crystal.xiong REMOVE-THIS AT intel DOT com + * This file is licensed under the GPL license. For the full content + * of this license, see the COPYING file at the top level of this + * source tree. + * + * 1. Two threads sending/receiving on different message queue. + * 2. Set different Priority to the messages in the message queue, to + * see whether the highest priority is received first. + */ + +// #include +#include +#include +#include "FreeRTOS_POSIX.h" +#include "FreeRTOS_POSIX/fcntl.h" +#include "FreeRTOS_POSIX/pthread.h" +#include "FreeRTOS_POSIX/mqueue.h" + +#define MQ_NAME_1 "/testmsg1" +#define MQ_NAME_2 "/testmsg2" +#define MSG_SIZE 128 +#define MAX_MSG 3 + +extern int FreeRTOS_errno; +static const char *s_msg_ptr[] = { "msg test 1", "msg test 2", "msg test 3" }; + +static char r_msg_ptr_1[MAX_MSG][MSG_SIZE]; +static char r_msg_ptr_2[MAX_MSG][MSG_SIZE]; +static pthread_t send1, send2, rev1, rev2; + +static void send_1(void *mq) +{ + int i; + mqd_t mq1 = *(mqd_t *) mq; + + printf("Enter into send_1 \r\n"); + for (i = 0; i < MAX_MSG; i++) { + if (-1 == mq_send(mq1, s_msg_ptr[i], MSG_SIZE, i)) { + printf("mq_send doesn't return success \r\n"); + pthread_exit((void *)1); + } + printf("[%d] send '%s' in thread send_1. \r\n", i + 1, + s_msg_ptr[i]); + } + pthread_exit(NULL); + +} + +static void send_2(void *mq) +{ + int i; + mqd_t mq2 = *(mqd_t *) mq; + + printf("Enter into send_2 \r\n"); + for (i = 0; i < MAX_MSG; i++) { + if (-1 == mq_send(mq2, s_msg_ptr[i], MSG_SIZE, i)) { + printf("mq_send doesn't return success \r\n"); + pthread_exit((void *)1); + } + printf("[%d] send '%s' in thread send_2. \r\n", i + 1, + s_msg_ptr[i]); + } + pthread_exit(NULL); +} + +static void receive_1(void *mq) +{ + int i; + mqd_t mq1 = *(mqd_t *) mq; + + printf("Enter into receive_1 \r\n"); + for (i = 0; i < MAX_MSG; i++) { +retry: + if (-1 == mq_receive(mq1, r_msg_ptr_1[i], MSG_SIZE, NULL)) { + printf("errno: %d \r\n", FreeRTOS_errno); + if (FreeRTOS_errno == 11) + goto retry; + printf("mq_receive doesn't return success \r\n"); + pthread_exit((void *)1); + } + printf("[%d] receive '%s' in thread receive_1. \r\n", i + 1, + r_msg_ptr_1[i]); + } + pthread_exit(NULL); +} + +static void receive_2(void *mq) +{ + int i; + mqd_t mq2 = *(mqd_t *) mq; + + printf("Enter into receive_2 \r\n"); + for (i = 0; i < MAX_MSG; i++) { +retry: + if (-1 == mq_receive(mq2, r_msg_ptr_2[i], MSG_SIZE, NULL)) { + printf("errno: %d \r\n", FreeRTOS_errno); + if (FreeRTOS_errno == 11) + goto retry; + printf("mq_receive doesn't return success \r\n"); + pthread_exit((void *)1); + } + printf("[%d] receive '%s' in thread receive_2. \r\n", i + 1, + r_msg_ptr_2[i]); + } + pthread_exit(NULL); +} + +int mqueues_test(void) +{ + + mqd_t mq1 = 0, mq2 = 0; + struct mq_attr mqstat; + int oflag = O_CREAT | O_NONBLOCK | O_RDWR; + + memset(&mqstat, 0, sizeof(mqstat)); + mqstat.mq_maxmsg = MAX_MSG; + mqstat.mq_msgsize = MSG_SIZE; + mqstat.mq_flags = 0; + + if ((mq1 = mq_open(MQ_NAME_1, oflag, 0777, &mqstat)) == (mqd_t)-1) { + printf("mq_open doesn't return success \r\n"); + return -1; + } + if ((mq2 = mq_open(MQ_NAME_2, oflag, 0777, &mqstat)) == (mqd_t)-1) { + printf("mq_open doesn't return success \r\n"); + return -1; + } + pthread_create(&send1, NULL, (void *)send_1, (void *)&mq1); + pthread_create(&send2, NULL, (void *)send_2, (void *)&mq2); + pthread_create(&rev1, NULL, (void *)receive_1, (void *)&mq1); + pthread_create(&rev2, NULL, (void *)receive_2, (void *)&mq2); + pthread_join(send1, NULL); + pthread_join(send2, NULL); + pthread_join(rev1, NULL); + pthread_join(rev2, NULL); + + mq_close(mq1); + mq_close(mq2); + mq_unlink(MQ_NAME_1); + mq_unlink(MQ_NAME_2); + printf("mq PASS \r\n"); + return 0; +} diff --git a/examples/posix/freertos/proj.conf b/examples/posix/freertos/proj.conf new file mode 100644 index 00000000..987e3878 --- /dev/null +++ b/examples/posix/freertos/proj.conf @@ -0,0 +1,2 @@ +set(CONFIG_FREERTOS 1) +set(CONFIG_POSIX 1) \ No newline at end of file diff --git a/examples/posix/freertos/semaphores_test.c b/examples/posix/freertos/semaphores_test.c new file mode 100644 index 00000000..d55a85e8 --- /dev/null +++ b/examples/posix/freertos/semaphores_test.c @@ -0,0 +1,124 @@ + +/* + * Copyright (c) 2002, Intel Corporation. All rights reserved. + * Created by: crystal.xiong REMOVE-THIS AT intel DOT com + * This file is licensed under the GPL license. For the full content + * of this license, see the COPYING file at the top level of this + * source tree. + * + * This is a test about producer and consumer. Producer sends data + * to a buffer. Consumer keeps reading data from the buffer. + */ + +#include +#include +#include +#include "FreeRTOS_POSIX.h" +#include "FreeRTOS_POSIX/fcntl.h" +#include "FreeRTOS_POSIX/pthread.h" +#include "FreeRTOS_POSIX/semaphore.h" + +#define BUF_SIZE 5 +#define Max_Num 10 + +typedef struct { + int buffer[BUF_SIZE]; + sem_t occupied; + sem_t empty; + sem_t lock; +} buf_t; + +static int in, out; + +static void producer(buf_t * buf) +{ + int data; + int i; + + for (i = 0; i < Max_Num; i++) { + if (-1 == sem_wait(&buf->occupied)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + if (-1 == sem_wait(&buf->lock)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + data = 100 * i; + buf->buffer[in] = data; + printf("producer has added %d to the buffer[%d] \r\n", data, in); + in = (in + 1) % BUF_SIZE; + if (-1 == sem_post(&buf->lock)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + if (-1 == sem_post(&buf->empty)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + } + pthread_exit(NULL); +} + +static void consumer(buf_t * buf) +{ + int data; + int i; + + for (i = 0; i < Max_Num; i++) { + if (-1 == sem_wait(&buf->empty)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + if (-1 == sem_wait(&buf->lock)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + data = buf->buffer[out]; + printf("consumer has taken %d from buffer[%d] \r\n", data, out); + out = (out + 1) % BUF_SIZE; + if (-1 == sem_post(&buf->lock)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + if (-1 == sem_post(&buf->occupied)) { + printf("sem_wait didn't return success \r\n"); + pthread_exit((void *)1); + } + } + pthread_exit(0); +} + +int semaphores_test(void) +{ + int shared = 1; + int occupied_value = BUF_SIZE; + int empty_value = 0; + int lock_value = 1; + buf_t buf; + pthread_t con, pro; + + if (-1 == sem_init(&buf.occupied, shared, occupied_value)) { + printf("sem_init didn't return success \r\n"); + return -1; + } + if (-1 == sem_init(&buf.empty, shared, empty_value)) { + printf("sem_init didn't return success \r\n"); + return -1; + } + if (-1 == sem_init(&buf.lock, shared, lock_value)) { + printf("sem_init didn't return success \r\n"); + return -1; + } + in = out = 0; + + pthread_create(&con, NULL, (void *)consumer, &buf); + pthread_create(&pro, NULL, (void *)producer, &buf); + pthread_join(con, NULL); + pthread_join(pro, NULL); + sem_destroy(&buf.occupied); + sem_destroy(&buf.empty); + + printf("sema PASS\r\r\n"); + return 0; +} diff --git a/examples/printf/README.md b/examples/printf/README.md new file mode 100644 index 00000000..e2f44307 --- /dev/null +++ b/examples/printf/README.md @@ -0,0 +1,44 @@ +# printf + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/printf/flash_prog_cfg.ini b/examples/printf/flash_prog_cfg.ini new file mode 100644 index 00000000..3f9b1453 --- /dev/null +++ b/examples/printf/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/printf_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/shell/shell_no_os/README.md b/examples/shell/shell_no_os/README.md new file mode 100644 index 00000000..4d991507 --- /dev/null +++ b/examples/shell/shell_no_os/README.md @@ -0,0 +1,44 @@ +# shell_no_os + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/shell/shell_no_os/flash_prog_cfg.ini b/examples/shell/shell_no_os/flash_prog_cfg.ini new file mode 100644 index 00000000..9b323088 --- /dev/null +++ b/examples/shell/shell_no_os/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/shell*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/shell/shell_os/FreeRTOSConfig.h b/examples/shell/shell_os/FreeRTOSConfig.h index 6b521a6a..e0de2e33 100644 --- a/examples/shell/shell_os/FreeRTOSConfig.h +++ b/examples/shell/shell_os/FreeRTOSConfig.h @@ -49,7 +49,7 @@ #define configMTIMECMP_BASE_ADDRESS (0xE0000000UL + 0x4000UL) #endif -// #define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_STATIC_ALLOCATION 1 #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 #define configUSE_TICK_HOOK 0 diff --git a/examples/shell/shell_os/README.md b/examples/shell/shell_os/README.md new file mode 100644 index 00000000..66e78e85 --- /dev/null +++ b/examples/shell/shell_os/README.md @@ -0,0 +1,44 @@ +# shell_os + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/shell/shell_os/flash_prog_cfg.ini b/examples/shell/shell_os/flash_prog_cfg.ini new file mode 100644 index 00000000..9b323088 --- /dev/null +++ b/examples/shell/shell_os/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/shell*_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/shell/shell_os/main.c b/examples/shell/shell_os/main.c index 87584bc8..92526973 100644 --- a/examples/shell/shell_os/main.c +++ b/examples/shell/shell_os/main.c @@ -5,14 +5,6 @@ #include "semphr.h" #include "board.h" -static uint8_t freertos_heap[configTOTAL_HEAP_SIZE]; - -static HeapRegion_t xHeapRegions[] = { - { (uint8_t *)freertos_heap, 0 }, - { NULL, 0 }, /* Terminates the array. */ - { NULL, 0 } /* Terminates the array. */ -}; - static struct bflb_device_s *uart0; extern void shell_init_with_task(struct bflb_device_s *shell); @@ -20,8 +12,6 @@ extern void shell_init_with_task(struct bflb_device_s *shell); int main(void) { board_init(); - xHeapRegions[0].xSizeInBytes = configTOTAL_HEAP_SIZE; - vPortDefineHeapRegions(xHeapRegions); configASSERT((configMAX_PRIORITIES > 4)); diff --git a/examples/shell/shell_os/proj.conf b/examples/shell/shell_os/proj.conf index 9aa717c8..4a9ec117 100644 --- a/examples/shell/shell_os/proj.conf +++ b/examples/shell/shell_os/proj.conf @@ -1,4 +1,4 @@ set(CONFIG_VLIBC 0) set(CONFIG_BFLOG 0) set(CONFIG_FREERTOS 1) -set(CONFIG_SHELL 1) \ No newline at end of file +set(CONFIG_SHELL 1) diff --git a/examples/tensorflowlite/sinx/README.md b/examples/tensorflowlite/sinx/README.md new file mode 100644 index 00000000..3aa0b8ad --- /dev/null +++ b/examples/tensorflowlite/sinx/README.md @@ -0,0 +1,44 @@ +# tlite_sinx + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/tensorflowlite/sinx/flash_prog_cfg.ini b/examples/tensorflowlite/sinx/flash_prog_cfg.ini new file mode 100644 index 00000000..8e3cf3b8 --- /dev/null +++ b/examples/tensorflowlite/sinx/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/sinx_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/examples/tinymaix/README.md b/examples/tinymaix/README.md new file mode 100644 index 00000000..8bdf3040 --- /dev/null +++ b/examples/tinymaix/README.md @@ -0,0 +1,44 @@ +# tinymaix + + +## Support CHIP + +| CHIP | Remark | +|:----------------:|:------:| +|BL602/BL604 | | +|BL702/BL704/BL706 | | +|BL616/BL618 | | +|BL808 | | + +## Compile + +- BL602/BL604 + +``` +make CHIP=bl602 BOARD=bl602dk +``` + +- BL702/BL704/BL706 + +``` +make CHIP=bl702 BOARD=bl702dk +``` + +- BL616/BL618 + +``` +make CHIP=bl616 BOARD=bl616dk +``` + +- BL808 + +``` +make CHIP=bl808 BOARD=bl808dk CPU_ID=m0 +make CHIP=bl808 BOARD=bl808dk CPU_ID=d0 +``` + +## Flash + +``` +make flash CHIP=chip_name COMX=xxx # xxx is your com name +``` \ No newline at end of file diff --git a/examples/tinymaix/flash_prog_cfg.ini b/examples/tinymaix/flash_prog_cfg.ini new file mode 100644 index 00000000..68c9e454 --- /dev/null +++ b/examples/tinymaix/flash_prog_cfg.ini @@ -0,0 +1,11 @@ +[cfg] +# 0: no erase, 1:programmed section erase, 2: chip erase +erase = 1 +# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated +skip_mode = 0x0, 0x0 +# 0: not use isp mode, #1: isp mode +boot2_isp_mode = 0 + +[FW] +filedir = ./build/build_out/tinymaix_$(CHIPNAME).bin +address = 0x000000 \ No newline at end of file diff --git a/project.build b/project.build index 3d08266f..72128d92 100644 --- a/project.build +++ b/project.build @@ -6,8 +6,12 @@ endif ifeq ($(OS),Windows_NT) CMAKE = $(BL_SDK_BASE)/tools/cmake/bin/cmake.exe +BL_FLASH_PROGRAM = ${BL_SDK_BASE}/tools/bflb_tools/bouffalo_flash_cube/BLFlashCommand.exe +cmake_generator = "MinGW Makefiles" else CMAKE = $(BL_SDK_BASE)/tools/cmake/bin/cmake +BL_FLASH_PROGRAM = ${BL_SDK_BASE}/tools/bflb_tools/bouffalo_flash_cube/BLFlashCommand +cmake_generator = "Unix Makefiles" endif # The command to remove a file. @@ -17,6 +21,9 @@ CPU_ID ?= CONFIG_USB_HS ?=y CONFIG_ROMAPI ?=y CONFIG_DEBUG ?=y +CONFIG_TLSF ?=y +COMX ?=COM5 +BAUDRATE ?=2000000 BOARD_DIR ?= #cmake definition config @@ -28,11 +35,13 @@ cmake_definition+= -DBOARD_DIR=$(BOARD_DIR) cmake_definition+= -DCONFIG_DEBUG=$(CONFIG_DEBUG) cmake_definition+= -DCONFIG_ROMAPI=$(CONFIG_ROMAPI) cmake_definition+= -DCONFIG_USB_HS=$(CONFIG_USB_HS) +cmake_definition+= -DCONFIG_COMX=$(COMX) cmake_definition+= -DCMAKE_EXPORT_COMPILE_COMMANDS=OFF +cmake_definition+= -DCONFIG_TLSF=$(CONFIG_TLSF) build:Makefile - $(CMAKE) -S . -B build -G "Unix Makefiles" $(cmake_definition) - cd build && make -j4 + $(CMAKE) -S . -B build -G $(cmake_generator) $(cmake_definition) + cd build && make -j8 ninja:Makefile $(CMAKE) -S . -B build -G Ninja $(cmake_definition) @@ -42,7 +51,18 @@ clean: $(RM) build menuconfig: - python ../../tools/kconfig/menuconfig.py + python $(BL_SDK_BASE)/tools/kconfig/menuconfig.py + +flash: + @echo "Support in next version, please use devcube now" + +efuse: + $(BL_FLASH_PROGRAM) \ + --interface=uart \ + --baudrate=$(BAUDRATE) \ + --port=$(COMX) \ + --chipname=$(CHIP) \ + --efuse=build/build_out/efusedata.bin .PHONY:build clean menuconfig ninja