2022-10-21 10:17:49 +08:00
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#ifndef _BFLB_UART_H
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#define _BFLB_UART_H
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#include "bflb_core.h"
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/** @defgroup UART_DIRECTION uart direction enable definition
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* @{
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*/
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#define UART_DIRECTION_TX (1 << 0)
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#define UART_DIRECTION_RX (1 << 1)
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#define UART_DIRECTION_TXRX (UART_DIRECTION_TX | UART_DIRECTION_RX)
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#define UART_DIRECTION_MASK UART_DIRECTION_TXRX
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/**
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* @}
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*/
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/** @defgroup UART_DATABITS uart data bits definition
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* @{
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*/
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#define UART_DATA_BITS_5 0
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#define UART_DATA_BITS_6 1
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#define UART_DATA_BITS_7 2
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#define UART_DATA_BITS_8 3
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/**
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* @}
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*/
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/** @defgroup UART_STOPBITS uart stop bits definition
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* @{
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*/
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#define UART_STOP_BITS_0_5 0
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#define UART_STOP_BITS_1 1
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#define UART_STOP_BITS_1_5 2
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#define UART_STOP_BITS_2 3
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/**
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* @}
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*/
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/** @defgroup UART_PARITY uart parity definition
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* @{
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*/
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#define UART_PARITY_NONE 0
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#define UART_PARITY_ODD 1
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#define UART_PARITY_EVEN 2
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#define UART_PARITY_MARK 3
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#define UART_PARITY_SPACE 4
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/**
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* @}
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*/
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/** @defgroup UART_BITORDER uart bitorder definition
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* @{
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*/
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#define UART_LSB_FIRST 0
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#define UART_MSB_FIRST 1
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/**
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* @}
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*/
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/** @defgroup UART_FLOWCTRL uart flow ctrl definition
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* @{
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*/
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#define UART_FLOWCTRL_NONE 0
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#define UART_FLOWCTRL_RTS (1 << 0)
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#define UART_FLOWCTRL_CTS (1 << 1)
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#define UART_FLOWCTRL_RTS_CTS (UART_FLOWCTRL_RTS | UART_FLOWCTRL_CTS)
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/**
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* @}
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*/
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/** @defgroup UART_INTSTS uart interrupt status definition
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* @{
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*/
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#define UART_INTSTS_TX_END (1 << 0)
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#define UART_INTSTS_RX_END (1 << 1)
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#define UART_INTSTS_TX_FIFO (1 << 2)
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#define UART_INTSTS_RX_FIFO (1 << 3)
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#define UART_INTSTS_RTO (1 << 4)
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#define UART_INTSTS_PCE (1 << 5)
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#define UART_INTSTS_TX_FER (1 << 6)
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#define UART_INTSTS_RX_FER (1 << 7)
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#if !defined(BL602)
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#define UART_INTSTS_RX_LSE (1 << 8)
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#endif
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#if !defined(BL602) && !defined(BL702)
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#define UART_INTSTS_RX_BCR (1 << 9)
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#define UART_INTSTS_RX_ADS (1 << 10)
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#define UART_INTSTS_RX_AD5 (1 << 11)
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#endif
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2022-10-29 13:33:23 +08:00
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/**
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* @}
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*/
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2022-10-21 10:17:49 +08:00
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/** @defgroup UART_INTCLR uart interrupt clear definition
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* @{
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*/
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#define UART_INTCLR_TX_END (1 << 0)
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#define UART_INTCLR_RX_END (1 << 1)
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#define UART_INTCLR_RTO (1 << 4)
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#define UART_INTCLR_PCE (1 << 5)
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#if !defined(BL602)
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#define UART_INTCLR_RX_LSE (1 << 8)
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#endif
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#if !defined(BL602) && !defined(BL702)
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#define UART_INTCLR_RX_BCR (1 << 9)
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#define UART_INTCLR_RX_ADS (1 << 10)
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#define UART_INTCLR_RX_AD5 (1 << 11)
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#endif
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/**
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* @}
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*/
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/** @defgroup UART_CMD uart feature control cmd definition
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* @{
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*/
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2022-10-29 13:33:23 +08:00
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#define UART_CMD_SET_BAUD_RATE (0x01)
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#define UART_CMD_SET_DATA_BITS (0x02)
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#define UART_CMD_SET_STOP_BITS (0x03)
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#define UART_CMD_SET_PARITY_BITS (0x04)
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#define UART_CMD_CLR_TX_FIFO (0x05)
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#define UART_CMD_CLR_RX_FIFO (0x06)
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#define UART_CMD_SET_RTO_VALUE (0x07)
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#define UART_CMD_SET_RTS_VALUE (0x08)
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#define UART_CMD_GET_TX_FIFO_CNT (0x09)
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#define UART_CMD_GET_RX_FIFO_CNT (0x0a)
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#define UART_CMD_SET_AUTO_BAUD (0x0b)
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#define UART_CMD_GET_AUTO_BAUD (0x0c)
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#define UART_CMD_SET_BREAK_VALUE (0x0d)
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#define UART_CMD_SET_TX_LIN_VALUE (0x0e)
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#define UART_CMD_SET_RX_LIN_VALUE (0x0f)
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#define UART_CMD_SET_TX_RX_EN (0x10)
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#define UART_CMD_SET_TX_RS485_EN (0x11)
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#define UART_CMD_SET_TX_RS485_POLARITY (0x12)
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#define UART_CMD_SET_ABR_ALLOWABLE_ERROR (0x13)
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#define UART_CMD_SET_SW_RTS_CONTROL (0x14)
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2022-11-05 10:44:08 +08:00
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#define UART_CMD_IR_CONFIG (0x15)
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2022-10-21 10:17:49 +08:00
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/**
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* @}
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*/
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#define UART_AUTO_BAUD_START 0
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#define UART_AUTO_BAUD_0X55 1
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2022-11-05 10:44:08 +08:00
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struct bflb_uart_ir_config_s {
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bool tx_en;
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bool rx_en;
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bool tx_inverse;
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bool rx_inverse;
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uint16_t tx_pluse_start;
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uint16_t tx_pluse_stop;
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uint16_t rx_pluse_start;
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};
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2022-10-21 10:17:49 +08:00
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/**
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* @brief UART configuration structure
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*
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* @param baudrate UART baudrate setting in bps,should be less than uart_clk/2
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* @param direction UART direction, use @ref UART_DIRECTION
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* @param data_bits UART data bits, use @ref UART_DATABITS
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* @param stop_bits UART stop bits, use @ref UART_STOPBITS
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* @param parity UART parity bit, use @ref UART_PARITY
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* @param bit_order UART bit first, use @ref UART_BITORDER
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* @param flow_ctrl UART flow control setting, use @ref UART_FLOWCTRL
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* @param tx_fifo_threshold UART tx fifo threshold, should be less than 32.
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* @param rx_fifo_threshold UART rx fifo threshold, should be less than 32.
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*/
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struct bflb_uart_config_s {
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uint32_t baudrate;
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uint8_t direction;
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uint8_t data_bits;
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uint8_t stop_bits;
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uint8_t parity;
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uint8_t bit_order;
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uint8_t flow_ctrl;
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uint8_t tx_fifo_threshold;
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uint8_t rx_fifo_threshold;
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};
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#ifdef __cplusplus
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extern "C" {
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#endif
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void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *config);
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void bflb_uart_deinit(struct bflb_device_s *dev);
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2022-10-29 13:33:23 +08:00
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void bflb_uart_enable(struct bflb_device_s *dev);
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void bflb_uart_disable(struct bflb_device_s *dev);
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2022-10-21 10:17:49 +08:00
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void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable);
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void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable);
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void bflb_uart_putchar(struct bflb_device_s *dev, int ch);
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int bflb_uart_getchar(struct bflb_device_s *dev);
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2022-10-29 13:33:23 +08:00
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void bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
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int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
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2022-10-21 10:17:49 +08:00
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bool bflb_uart_txready(struct bflb_device_s *dev);
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bool bflb_uart_txempty(struct bflb_device_s *dev);
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bool bflb_uart_rxavailable(struct bflb_device_s *dev);
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void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask);
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void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask);
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void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask);
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uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev);
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void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
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2022-10-29 13:33:23 +08:00
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int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
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2022-10-21 10:17:49 +08:00
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#ifdef __cplusplus
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}
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#endif
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#endif
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