9646 lines
907 KiB
XML
9646 lines
907 KiB
XML
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<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Wed Jul 13 12:14:55 2011">
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<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45t" PACKAGE="fgg484" PART="xc6slx45tfgg484-3" SOURCE="/proj/emb_apps/keshava/sysace/SP605_System/HW/MicroBlaze_ProcessorSubSystem/system.xmp" SPEEDGRADE="-3"/>
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<EXTERNALPORTS>
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<PORT DIR="I" MHS_INDEX="0" NAME="fpga_0_RS232_Uart_1_sin_pin" SIGNAME="fpga_0_RS232_Uart_1_sin"/>
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<PORT DIR="O" MHS_INDEX="1" NAME="fpga_0_RS232_Uart_1_sout_pin" SIGNAME="fpga_0_RS232_Uart_1_sout"/>
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<PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="2" MSB="0" NAME="fpga_0_LEDs_4Bit_GPIO_d_out_pin" RIGHT="3" SIGNAME="fpga_0_LEDs_4Bit_GPIO_d_out"/>
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<PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="3" MSB="0" NAME="fpga_0_Push_Buttons_4Bit_GPIO_IO_pin" RIGHT="3" SIGNAME="fpga_0_Push_Buttons_4Bit_GPIO_IO"/>
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<PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MHS_INDEX="4" MSB="0" NAME="fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin" RIGHT="3" SIGNAME="fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin"/>
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<PORT DIR="IO" MHS_INDEX="5" NAME="fpga_0_IIC_EEPROM_Scl_pin" SIGNAME="fpga_0_IIC_EEPROM_Scl"/>
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<PORT DIR="IO" MHS_INDEX="6" NAME="fpga_0_IIC_EEPROM_Sda_pin" SIGNAME="fpga_0_IIC_EEPROM_Sda"/>
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<PORT DIR="O" ENDIAN="BIG" LEFT="7" LSB="30" MHS_INDEX="7" MSB="7" NAME="fpga_0_FLASH_Mem_A_pin" RIGHT="30" SIGNAME="fpga_0_FLASH_Mem_A"/>
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<PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="15" MHS_INDEX="8" MSB="0" NAME="fpga_0_FLASH_Mem_DQ_Shared_pin" RIGHT="15" SIGNAME="fpga_0_FLASH_Mem_DQ_Shared"/>
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<PORT DIR="O" MHS_INDEX="9" NAME="fpga_0_FLASH_Mem_WEN_pin" SIGNAME="fpga_0_FLASH_Mem_WEN"/>
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<PORT DIR="O" MHS_INDEX="10" NAME="fpga_0_FLASH_Mem_OEN_pin" SIGNAME="fpga_0_FLASH_Mem_OEN"/>
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<PORT DIR="O" MHS_INDEX="11" NAME="fpga_0_FLASH_Mem_CEN_pin" SIGNAME="fpga_0_FLASH_Mem_CEN"/>
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<PORT DIR="O" MHS_INDEX="12" NAME="fpga_0_FLASH_Mem_ADV_LDN_pin" SIGNAME="fpga_0_FLASH_Mem_ADV_LDN"/>
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<PORT DIR="O" MHS_INDEX="13" NAME="fpga_0_FLASH_Mem_RPN_pin" SIGNAME="fpga_0_FLASH_Mem_RPN"/>
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<PORT DIR="IO" MHS_INDEX="14" NAME="fpga_0_SPI_FLASH_MOSI_pin" SIGNAME="fpga_0_SPI_FLASH_MOSI"/>
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<PORT DIR="IO" MHS_INDEX="15" NAME="fpga_0_SPI_FLASH_SCK_pin" SIGNAME="fpga_0_SPI_FLASH_SCK"/>
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<PORT DIR="IO" ENDIAN="BIG" LEFT="0" LSB="0" MHS_INDEX="16" MSB="0" NAME="fpga_0_SPI_FLASH_SS_pin" RIGHT="0" SIGNAME="fpga_0_SPI_FLASH_SS"/>
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<PORT DIR="O" ENDIAN="LITTLE" LEFT="12" LSB="0" MHS_INDEX="17" MSB="12" NAME="mcbx_dram_addr_pin" RIGHT="0" SIGNAME="mcbx_dram_addr"/>
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<PORT DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MHS_INDEX="18" MSB="2" NAME="mcbx_dram_ba_pin" RIGHT="0" SIGNAME="mcbx_dram_ba"/>
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<PORT DIR="O" MHS_INDEX="19" NAME="mcbx_dram_ras_n_pin" SIGNAME="mcbx_dram_ras_n"/>
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<PORT DIR="O" MHS_INDEX="20" NAME="mcbx_dram_cas_n_pin" SIGNAME="mcbx_dram_cas_n"/>
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<PORT DIR="O" MHS_INDEX="21" NAME="mcbx_dram_we_n_pin" SIGNAME="mcbx_dram_we_n"/>
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<PORT DIR="O" MHS_INDEX="22" NAME="mcbx_dram_cke_pin" SIGNAME="mcbx_dram_cke"/>
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<PORT DIR="O" MHS_INDEX="23" NAME="mcbx_dram_clk_pin" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
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<PORT DIR="O" MHS_INDEX="24" NAME="mcbx_dram_clk_n_pin" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
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<PORT DIR="IO" ENDIAN="LITTLE" LEFT="15" LSB="0" MHS_INDEX="25" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq"/>
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<PORT DIR="IO" MHS_INDEX="26" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
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<PORT DIR="IO" MHS_INDEX="27" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
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<PORT DIR="O" MHS_INDEX="28" NAME="mcbx_dram_odt_pin" SIGNAME="mcbx_dram_odt"/>
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<PORT DIR="O" MHS_INDEX="29" NAME="mcbx_dram_ldm_pin" SIGNAME="mcbx_dram_ldm"/>
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<PORT DIR="O" MHS_INDEX="30" NAME="mcbx_dram_udm_pin" SIGNAME="mcbx_dram_udm"/>
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<PORT DIR="IO" MHS_INDEX="31" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
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<PORT DIR="IO" MHS_INDEX="32" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
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<PORT DIR="O" MHS_INDEX="33" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
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<PORT DIR="IO" MHS_INDEX="34" NAME="mcbx_dram_rzq" SIGNAME="mcbx_dram_rzq"/>
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<PORT DIR="IO" MHS_INDEX="35" NAME="mcbx_dram_zio" SIGNAME="mcbx_dram_zio"/>
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<PORT DIR="O" MHS_INDEX="36" NAME="Soft_Ethernet_MAC_RST_n_pin" SIGNAME="Soft_Ethernet_MAC_RST_N"/>
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<PORT DIR="I" MHS_INDEX="37" NAME="Soft_Ethernet_MAC_MII_TX_CLK_pin" SIGNAME="Soft_Ethernet_MAC_MII_TX_CLK"/>
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<PORT DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="38" MSB="7" NAME="Soft_Ethernet_MAC_GMII_TXD_pin" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_GMII_TXD"/>
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<PORT DIR="O" MHS_INDEX="39" NAME="Soft_Ethernet_MAC_GMII_TX_EN_pin" SIGNAME="Soft_Ethernet_MAC_GMII_TX_EN"/>
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<PORT DIR="O" MHS_INDEX="40" NAME="Soft_Ethernet_MAC_GMII_TX_ER_pin" SIGNAME="Soft_Ethernet_MAC_GMII_TX_ER"/>
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<PORT DIR="O" MHS_INDEX="41" NAME="Soft_Ethernet_MAC_GMII_TX_CLK_pin" SIGNAME="Soft_Ethernet_MAC_GMII_TX_CLK"/>
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<PORT DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="42" MSB="7" NAME="Soft_Ethernet_MAC_GMII_RXD_pin" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_GMII_RXD"/>
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<PORT DIR="I" MHS_INDEX="43" NAME="Soft_Ethernet_MAC_GMII_RX_DV_pin" SIGNAME="Soft_Ethernet_MAC_GMII_RX_DV"/>
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<PORT DIR="I" MHS_INDEX="44" NAME="Soft_Ethernet_MAC_GMII_RX_ER_pin" SIGNAME="Soft_Ethernet_MAC_GMII_RX_ER"/>
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<PORT DIR="I" MHS_INDEX="45" NAME="Soft_Ethernet_MAC_GMII_RX_CLK_pin" SIGNAME="Soft_Ethernet_MAC_GMII_RX_CLK"/>
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<PORT DIR="I" MHS_INDEX="46" NAME="Soft_Ethernet_MAC_GMII_COL_pin" SIGNAME="Soft_Ethernet_MAC_GMII_COL"/>
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<PORT DIR="I" MHS_INDEX="47" NAME="Soft_Ethernet_MAC_GMII_CRS_pin" SIGNAME="Soft_Ethernet_MAC_GMII_CRS"/>
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<PORT DIR="O" MHS_INDEX="48" NAME="Soft_Ethernet_MAC_MDC_pin" SIGNAME="Soft_Ethernet_MAC_MDC"/>
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<PORT DIR="IO" MHS_INDEX="49" NAME="Soft_Ethernet_MAC_MDIO_pin" SIGNAME="Soft_Ethernet_MAC_MDIO"/>
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<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="P" DIR="I" MHS_INDEX="50" NAME="sys_clk_in_p" SIGIS="CLK" SIGNAME="dcm_clk_s"/>
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<PORT CLKFREQUENCY="200000000" DIFFPOLARITY="N" DIR="I" MHS_INDEX="51" NAME="sys_clk_in_n" SIGIS="CLK" SIGNAME="dcm_clk_s"/>
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<PORT DIR="I" MHS_INDEX="52" NAME="sys_rst_pin" RSTPOLARITY="1" SIGIS="RST" SIGNAME="sys_rst_s"/>
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<PORT DIR="I" MHS_INDEX="53" NAME="fpga_0_SysACE_CompactFlash_SysACE_CLK" SIGNAME="SysACE_CLK"/>
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<PORT DIR="I" MHS_INDEX="54" NAME="fpga_0_SysACE_CompactFlash_SysACE_MPIRQ" SIGNAME="SysACE_MPIRQ"/>
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<PORT DIR="O" ENDIAN="LITTLE" LEFT="6" LSB="0" MHS_INDEX="55" MSB="6" NAME="fpga_0_SysACE_CompactFlash_SysACE_MPA" RIGHT="0" SIGNAME="SysACE_MPA"/>
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<PORT DIR="O" MHS_INDEX="56" NAME="fpga_0_SysACE_CompactFlash_SysACE_CEN" SIGNAME="SysACE_CEN"/>
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<PORT DIR="O" MHS_INDEX="57" NAME="fpga_0_SysACE_CompactFlash_SysACE_OEN" SIGNAME="SysACE_OEN"/>
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<PORT DIR="O" MHS_INDEX="58" NAME="fpga_0_SysACE_CompactFlash_SysACE_WEN" SIGNAME="SysACE_WEN"/>
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<PORT DIR="IO" ENDIAN="LITTLE" LEFT="7" LSB="0" MHS_INDEX="59" MSB="7" NAME="fpga_0_SysACE_CompactFlash_SysACE_MPD" RIGHT="0" SIGNAME="SysACE_MPD"/>
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</EXTERNALPORTS>
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<MODULES>
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<MODULE HWVERSION="2.00.b" INSTANCE="Debug_Module" IPTYPE="PERIPHERAL" MHS_INDEX="0" MODCLASS="DEBUG" MODTYPE="mdm">
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<DESCRIPTION TYPE="SHORT">MicroBlaze Debug Module (MDM)</DESCRIPTION>
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<DESCRIPTION TYPE="LONG">Debug module for MicroBlaze Soft Processor.</DESCRIPTION>
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<DOCUMENTATION>
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<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/mdm_v2_00_b/doc/mdm.pdf" TYPE="IP"/>
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</DOCUMENTATION>
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<LICENSEINFO ICON_NAME="ps_core_preferred"/>
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<PARAMETERS>
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<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
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<DESCRIPTION>Device Family</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="1" NAME="C_JTAG_CHAIN" TYPE="INTEGER" VALUE="2">
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<DESCRIPTION>Specifies the JTAG user-defined register used </DESCRIPTION>
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</PARAMETER>
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<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_INTERCONNECT" TYPE="INTEGER" VALUE="2">
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<DESCRIPTION>Specifies the Bus Interface for the JTAG UART </DESCRIPTION>
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</PARAMETER>
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<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="3" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x84400000">
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<DESCRIPTION>Base Address</DESCRIPTION>
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</PARAMETER>
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<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="4" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8440ffff">
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<DESCRIPTION>High Address</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="5" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32">
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<DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="6" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32">
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<DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0">
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<DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="8" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="3">
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<DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="9" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="8">
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<DESCRIPTION>Number of PLB Masters</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="10" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
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<DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="11" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
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<DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="12" NAME="C_MB_DBG_PORTS" TYPE="INTEGER" VALUE="1">
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<DESCRIPTION>Number of MicroBlaze debug ports </DESCRIPTION>
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</PARAMETER>
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<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="13" NAME="C_USE_UART" TYPE="INTEGER" VALUE="1">
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<DESCRIPTION>Enable JTAG UART </DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="14" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
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<DESCRIPTION>AXI Address Width</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
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<DESCRIPTION>AXI Data Width</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="16" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
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<DESCRIPTION>AXI4LITE protocal</DESCRIPTION>
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</PARAMETER>
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</PARAMETERS>
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<PORTS>
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<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="1" NAME="Debug_SYS_Rst" SIGNAME="Debug_SYS_Rst"/>
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<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
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<PORT DIR="O" MPD_INDEX="0" NAME="Interrupt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
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<PORT DEF_SIGNAME="Ext_BRK" DIR="O" MPD_INDEX="2" NAME="Ext_BRK" SIGNAME="Ext_BRK"/>
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<PORT DEF_SIGNAME="Ext_NM_BRK" DIR="O" MPD_INDEX="3" NAME="Ext_NM_BRK" SIGNAME="Ext_NM_BRK"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="5" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[(C_S_AXI_DATA_WIDTH/8-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="11" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="12" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="13" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="14" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="15" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="25" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="26" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="27" NAME="PLB_PAValid" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="28" NAME="PLB_SAValid" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="29" NAME="PLB_rdPrim" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="30" NAME="PLB_wrPrim" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="31" MSB="0" NAME="PLB_masterID" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="32" NAME="PLB_abort" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="33" NAME="PLB_busLock" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="34" NAME="PLB_RNW" SIGNAME="__NOC__"/>
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<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="35" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="36" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="37" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="PLB_lockErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="40" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="PLB_wrBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="PLB_rdBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="PLB_wrPendReq" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="PLB_rdPendReq" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="45" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="46" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="48" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="49" NAME="Sl_addrAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="50" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="51" NAME="Sl_wait" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="52" NAME="Sl_rearbitrate" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="53" NAME="Sl_wrDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="54" NAME="Sl_wrComp" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="55" NAME="Sl_wrBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="57" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="58" NAME="Sl_rdDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="Sl_rdComp" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="Sl_rdBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="61" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="62" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="63" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="64" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Dbg_Clk" DIR="O" MPD_INDEX="65" NAME="Dbg_Clk_0" SIGNAME="microblaze_0_dbg_Dbg_Clk"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Dbg_TDI" DIR="O" MPD_INDEX="66" NAME="Dbg_TDI_0" SIGNAME="microblaze_0_dbg_Dbg_TDI"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Dbg_TDO" DIR="I" MPD_INDEX="67" NAME="Dbg_TDO_0" SIGNAME="microblaze_0_dbg_Dbg_TDO"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Dbg_Reg_En" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="68" MSB="0" NAME="Dbg_Reg_En_0" RIGHT="7" SIGNAME="microblaze_0_dbg_Dbg_Reg_En" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Dbg_Capture" DIR="O" MPD_INDEX="69" NAME="Dbg_Capture_0" SIGNAME="microblaze_0_dbg_Dbg_Capture"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Dbg_Shift" DIR="O" MPD_INDEX="70" NAME="Dbg_Shift_0" SIGNAME="microblaze_0_dbg_Dbg_Shift"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Dbg_Update" DIR="O" MPD_INDEX="71" NAME="Dbg_Update_0" SIGNAME="microblaze_0_dbg_Dbg_Update"/>
|
|
<PORT BUS="MBDEBUG_0" DEF_SIGNAME="microblaze_0_dbg_Debug_Rst" DIR="O" MPD_INDEX="72" NAME="Dbg_Rst_0" SIGNAME="microblaze_0_dbg_Debug_Rst"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="73" NAME="Dbg_Clk_1" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="74" NAME="Dbg_TDI_1" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="75" NAME="Dbg_TDO_1" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="76" MSB="0" NAME="Dbg_Reg_En_1" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="77" NAME="Dbg_Capture_1" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="Dbg_Shift_1" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="79" NAME="Dbg_Update_1" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="80" NAME="Dbg_Rst_1" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="81" NAME="Dbg_Clk_2" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="82" NAME="Dbg_TDI_2" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="Dbg_TDO_2" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="84" MSB="0" NAME="Dbg_Reg_En_2" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="85" NAME="Dbg_Capture_2" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="86" NAME="Dbg_Shift_2" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="Dbg_Update_2" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="88" NAME="Dbg_Rst_2" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="89" NAME="Dbg_Clk_3" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="Dbg_TDI_3" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="Dbg_TDO_3" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="92" MSB="0" NAME="Dbg_Reg_En_3" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="93" NAME="Dbg_Capture_3" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="Dbg_Shift_3" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="95" NAME="Dbg_Update_3" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="Dbg_Rst_3" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="Dbg_Clk_4" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="98" NAME="Dbg_TDI_4" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="99" NAME="Dbg_TDO_4" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="100" MSB="0" NAME="Dbg_Reg_En_4" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="Dbg_Capture_4" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="102" NAME="Dbg_Shift_4" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="103" NAME="Dbg_Update_4" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="Dbg_Rst_4" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="Dbg_Clk_5" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="106" NAME="Dbg_TDI_5" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="Dbg_TDO_5" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="108" MSB="0" NAME="Dbg_Reg_En_5" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="109" NAME="Dbg_Capture_5" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="Dbg_Shift_5" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="Dbg_Update_5" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="112" NAME="Dbg_Rst_5" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="113" NAME="Dbg_Clk_6" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="114" NAME="Dbg_TDI_6" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="115" NAME="Dbg_TDO_6" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="116" MSB="0" NAME="Dbg_Reg_En_6" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="117" NAME="Dbg_Capture_6" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="118" NAME="Dbg_Shift_6" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="119" NAME="Dbg_Update_6" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="Dbg_Rst_6" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="121" NAME="Dbg_Clk_7" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="122" NAME="Dbg_TDI_7" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="123" NAME="Dbg_TDO_7" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="124" MSB="0" NAME="Dbg_Reg_En_7" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="125" NAME="Dbg_Capture_7" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="126" NAME="Dbg_Shift_7" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="Dbg_Update_7" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MBDEBUG_7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="128" NAME="Dbg_Rst_7" SIGNAME="__NOC__"/>
|
|
<PORT DEF_SIGNAME="bscan_tdi" DIR="O" MPD_INDEX="129" NAME="bscan_tdi" SIGNAME="bscan_tdi"/>
|
|
<PORT DEF_SIGNAME="bscan_reset" DIR="O" MPD_INDEX="130" NAME="bscan_reset" SIGNAME="bscan_reset"/>
|
|
<PORT DEF_SIGNAME="bscan_shift" DIR="O" MPD_INDEX="131" NAME="bscan_shift" SIGNAME="bscan_shift"/>
|
|
<PORT DEF_SIGNAME="bscan_update" DIR="O" MPD_INDEX="132" NAME="bscan_update" SIGNAME="bscan_update"/>
|
|
<PORT DEF_SIGNAME="bscan_capture" DIR="O" MPD_INDEX="133" NAME="bscan_capture" SIGNAME="bscan_capture"/>
|
|
<PORT DEF_SIGNAME="bscan_sel1" DIR="O" MPD_INDEX="134" NAME="bscan_sel1" SIGNAME="bscan_sel1"/>
|
|
<PORT DEF_SIGNAME="bscan_drck1" DIR="O" MPD_INDEX="135" NAME="bscan_drck1" SIGNAME="bscan_drck1"/>
|
|
<PORT DEF_SIGNAME="bscan_tdo1" DIR="I" MPD_INDEX="136" NAME="bscan_tdo1" SIGNAME="bscan_tdo1"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="137" NAME="Ext_JTAG_DRCK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="138" NAME="Ext_JTAG_RESET" SIGNAME="__NOC__"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="139" NAME="Ext_JTAG_SEL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="140" NAME="Ext_JTAG_CAPTURE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="141" NAME="Ext_JTAG_SHIFT" SIGNAME="__NOC__"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="142" NAME="Ext_JTAG_UPDATE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="143" NAME="Ext_JTAG_TDI" SIGNAME="__NOC__"/>
|
|
<PORT BUS="XMTC" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="144" NAME="Ext_JTAG_TDO" SIGNAME="__NOC__"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="1" NAME="SPLB" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_size"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_type"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="microblaze_0_dbg" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MBDEBUG_0" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_0"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_0"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="3" NAME="MBDEBUG_1" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_1"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_1"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="4" NAME="MBDEBUG_2" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_2"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_2"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_2"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_2"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_2"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_2"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_2"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_2"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="5" NAME="MBDEBUG_3" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_3"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_3"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_3"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_3"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_3"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_3"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_3"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_3"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="6" NAME="MBDEBUG_4" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_4"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_4"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_4"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_4"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_4"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_4"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_4"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_4"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="7" NAME="MBDEBUG_5" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_5"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_5"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_5"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_5"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_5"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_5"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_5"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_5"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="8" NAME="MBDEBUG_6" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_6"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_6"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_6"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_6"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_6"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_6"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_6"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_6"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_VALID="FALSE" MPD_INDEX="9" NAME="MBDEBUG_7" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Clk_7"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_TDI_7"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Dbg_TDO_7"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Reg_En_7"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Capture_7"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Shift_7"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Update_7"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Dbg_Rst_7"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_BSCAN" MPD_INDEX="10" NAME="XMTC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Ext_JTAG_DRCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Ext_JTAG_RESET"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SEL"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Ext_JTAG_CAPTURE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Ext_JTAG_SHIFT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Ext_JTAG_UPDATE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Ext_JTAG_TDI"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Ext_JTAG_TDO"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2218786816" BASENAME="C_BASEADDR" BASEVALUE="0x84400000" HIGHDECIMAL="2218852351" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8440ffff" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="SPLB"/>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="8.20.a" INSTANCE="microblaze_0" IPTYPE="PROCESSOR" MHS_INDEX="1" MODCLASS="PROCESSOR" MODTYPE="microblaze" PROCTYPE="MICROBLAZE">
|
|
<DESCRIPTION TYPE="SHORT">MicroBlaze</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">The MicroBlaze 32 bit soft processor</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/microblaze_v8_20_a/doc/microblaze.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER MPD_INDEX="0" NAME="C_SCO" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FREQ" TYPE="integer" VALUE="100000000"/>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_DATA_SIZE" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_DYNAMIC_BUS_SIZING" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_INSTANCE" TYPE="string" VALUE="microblaze_0"/>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_AVOID_PRIMITIVES" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_FAULT_TOLERANT" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Fault Tolerance Support</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_ECC_USE_CE_EXCEPTION" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_LOCKSTEP_SLAVE" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="33" MPD_INDEX="10" NAME="C_ENDIANNESS" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_AREA_OPTIMIZED" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Select implementation to optimize area (with lower instruction throughput)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_OPTIMIZATION" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_INTERCONNECT" TYPE="integer" VALUE="2">
|
|
<DESCRIPTION>Select Bus Interfaces</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_STREAM_INTERCONNECT" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Select Stream Interfaces</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_DPLB_DWIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_DPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="17" NAME="C_DPLB_BURST_EN" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_DPLB_P2P" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="19" NAME="C_IPLB_DWIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_IPLB_NATIVE_DWIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="21" NAME="C_IPLB_BURST_EN" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_IPLB_P2P" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_M_AXI_DP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_M_AXI_DP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_M_AXI_DP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="26" NAME="C_M_AXI_DP_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="27" NAME="C_M_AXI_DP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="28" NAME="C_M_AXI_DP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_M_AXI_DP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_M_AXI_DP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_M_AXI_DP_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="32" NAME="C_INTERCONNECT_M_AXI_DP_READ_ISSUING" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_INTERCONNECT_M_AXI_DP_WRITE_ISSUING" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_M_AXI_IP_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="35" NAME="C_M_AXI_IP_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="36" NAME="C_M_AXI_IP_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="37" NAME="C_M_AXI_IP_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="38" NAME="C_M_AXI_IP_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_M_AXI_IP_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="40" NAME="C_M_AXI_IP_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_M_AXI_IP_PROTOCOL" TYPE="string" VALUE="AXI4LITE"/>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_INTERCONNECT_M_AXI_IP_READ_ISSUING" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="43" NAME="C_D_AXI" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_D_PLB" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_D_LMB" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_I_AXI" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_I_PLB" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_I_LMB" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_USE_MSR_INSTR" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Additional Machine Status Register Instructions</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_USE_PCMP_INSTR" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Pattern Comparator</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="51" NAME="C_USE_BARREL" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Barrel Shifter</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_USE_DIV" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Integer Divider</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_USE_HW_MUL" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Integer Multiplier</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_USE_FPU" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Floating Point Unit</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="55" NAME="C_UNALIGNED_EXCEPTIONS" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Unaligned Data Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="56" NAME="C_ILL_OPCODE_EXCEPTION" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Illegal Instruction Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_M_AXI_I_BUS_EXCEPTION" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Instruction-side AXI Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="58" NAME="C_M_AXI_D_BUS_EXCEPTION" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Data-side AXI Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_IPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Instruction-side PLB Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_DPLB_BUS_EXCEPTION" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Data-side PLB Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="61" NAME="C_DIV_ZERO_EXCEPTION" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Integer Divide Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="62" NAME="C_FPU_EXCEPTION" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Floating Point Unit Exceptions</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_FSL_EXCEPTION" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Stream Exception</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_USE_STACK_PROTECTION" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION><qt>Enable stack protection</qt></DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="65" NAME="C_PVR" TYPE="integer" VALUE="2">
|
|
<DESCRIPTION>Specifies Processor Version Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ENDIAN="BIG" LSB="7" MPD_INDEX="66" MSB="0" NAME="C_PVR_USER1" TYPE="std_logic_vector" VALUE="0x00">
|
|
<DESCRIPTION>Specify USER1 Bits in Processor Version Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ENDIAN="BIG" LSB="31" MPD_INDEX="67" MSB="0" NAME="C_PVR_USER2" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Specify USER2 Bits in Processor Version Registers</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="68" NAME="C_DEBUG_ENABLED" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable MicroBlaze Debug Module Interface</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="69" NAME="C_NUMBER_OF_PC_BRK" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Number of PC Breakpoints </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="70" NAME="C_NUMBER_OF_RD_ADDR_BRK" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Number of Read Address Watchpoints </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="71" NAME="C_NUMBER_OF_WR_ADDR_BRK" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Number of Write Address Watchpoints </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="72" NAME="C_INTERRUPT_IS_EDGE" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Sense Interrupt on Edge vs. Level </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="73" NAME="C_EDGE_IS_POSITIVE" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Sense Interrupt on Rising vs. Falling Edge </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="74" NAME="C_RESET_MSR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Specify Reset Value for Select MSR Bits</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="25" MPD_INDEX="75" NAME="C_OPCODE_0x0_ILLEGAL" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION><qt>Generate Illegal Instruction Exception for NULL Instruction</qt></DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="76" NAME="C_FSL_LINKS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Number of Stream Links </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="77" NAME="C_FSL_DATA_SIZE" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="78" NAME="C_USE_EXTENDED_FSL_INSTR" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Additional Stream Instructions</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="79" NAME="C_M0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="80" NAME="C_S0_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="81" NAME="C_M1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="82" NAME="C_S1_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="83" NAME="C_M2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="84" NAME="C_S2_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="85" NAME="C_M3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="86" NAME="C_S3_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="87" NAME="C_M4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="88" NAME="C_S4_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="89" NAME="C_M5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="90" NAME="C_S5_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="91" NAME="C_M6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="92" NAME="C_S6_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="93" NAME="C_M7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="94" NAME="C_S7_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="95" NAME="C_M8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="96" NAME="C_S8_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="97" NAME="C_M9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="98" NAME="C_S9_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="99" NAME="C_M10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="100" NAME="C_S10_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="101" NAME="C_M11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="102" NAME="C_S11_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="103" NAME="C_M12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="104" NAME="C_S12_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="105" NAME="C_M13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="106" NAME="C_S13_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="107" NAME="C_M14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="108" NAME="C_S14_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="109" NAME="C_M15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="110" NAME="C_S15_AXIS_PROTOCOL" TYPE="string" VALUE="GENERIC"/>
|
|
<PARAMETER MPD_INDEX="111" NAME="C_M0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="112" NAME="C_S0_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="113" NAME="C_M1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="114" NAME="C_S1_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="115" NAME="C_M2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="116" NAME="C_S2_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="117" NAME="C_M3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="118" NAME="C_S3_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="119" NAME="C_M4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="120" NAME="C_S4_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="121" NAME="C_M5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="122" NAME="C_S5_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="123" NAME="C_M6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="124" NAME="C_S6_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="125" NAME="C_M7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="126" NAME="C_S7_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="127" NAME="C_M8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="128" NAME="C_S8_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="129" NAME="C_M9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="130" NAME="C_S9_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="131" NAME="C_M10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="132" NAME="C_S10_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="133" NAME="C_M11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="134" NAME="C_S11_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="135" NAME="C_M12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="136" NAME="C_S12_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="137" NAME="C_M13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="138" NAME="C_S13_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="139" NAME="C_M14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="140" NAME="C_S14_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="141" NAME="C_M15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="142" NAME="C_S15_AXIS_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="143" NAME="C_ICACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000">
|
|
<DESCRIPTION>Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="144" NAME="C_ICACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4fffffff">
|
|
<DESCRIPTION>High Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="145" NAME="C_USE_ICACHE" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Instruction Cache </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="146" NAME="C_ALLOW_ICACHE_WR" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Writes</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="147" NAME="C_ADDR_TAG_BITS" TYPE="integer" VALUE="15"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="148" NAME="C_CACHE_BYTE_SIZE" TYPE="integer" VALUE="8192">
|
|
<DESCRIPTION>Size in Bytes</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="149" NAME="C_ICACHE_USE_FSL" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="150" NAME="C_ICACHE_LINE_LEN" TYPE="integer" VALUE="8">
|
|
<DESCRIPTION>Line Length</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="151" NAME="C_ICACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Use Cache Links for All Memory Accesses </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="152" NAME="C_ICACHE_INTERFACE" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="153" NAME="C_ICACHE_VICTIMS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Number of Victims</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="154" NAME="C_ICACHE_STREAMS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Number of Streams</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="155" NAME="C_ICACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Use Distributed RAM for Tags</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="156" NAME="C_ICACHE_DATA_WIDTH" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="157" NAME="C_M_AXI_IC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="158" NAME="C_M_AXI_IC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="159" NAME="C_M_AXI_IC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="160" NAME="C_M_AXI_IC_SUPPORTS_WRITE" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="161" NAME="C_M_AXI_IC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="162" NAME="C_M_AXI_IC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="163" NAME="C_M_AXI_IC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="164" NAME="C_M_AXI_IC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
|
|
<PARAMETER MPD_INDEX="165" NAME="C_M_AXI_IC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
|
|
<PARAMETER MPD_INDEX="166" NAME="C_M_AXI_IC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="167" NAME="C_M_AXI_IC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
|
|
<PARAMETER MPD_INDEX="168" NAME="C_M_AXI_IC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
|
|
<PARAMETER MPD_INDEX="169" NAME="C_M_AXI_IC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="170" NAME="C_M_AXI_IC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="171" NAME="C_M_AXI_IC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="172" NAME="C_INTERCONNECT_M_AXI_IC_READ_ISSUING" TYPE="integer" VALUE="2"/>
|
|
<PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="173" NAME="C_DCACHE_BASEADDR" TYPE="std_logic_vector" VALUE="0x40000000">
|
|
<DESCRIPTION>Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="NONE" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="174" NAME="C_DCACHE_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4fffffff">
|
|
<DESCRIPTION>High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="175" NAME="C_USE_DCACHE" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Data Cache</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="176" NAME="C_ALLOW_DCACHE_WR" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Enable Writes</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="177" NAME="C_DCACHE_ADDR_TAG" TYPE="integer" VALUE="15"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="178" NAME="C_DCACHE_BYTE_SIZE" TYPE="integer" VALUE="8192">
|
|
<DESCRIPTION>Size in Bytes</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="179" NAME="C_DCACHE_USE_FSL" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="180" NAME="C_DCACHE_LINE_LEN" TYPE="integer" VALUE="8">
|
|
<DESCRIPTION>Line Length</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="181" NAME="C_DCACHE_ALWAYS_USED" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Use Cache Links for All Memory Accesses </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="182" NAME="C_DCACHE_INTERFACE" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="183" NAME="C_DCACHE_USE_WRITEBACK" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Write-back Storage Policy</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="184" NAME="C_DCACHE_VICTIMS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Number of Victims</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="185" NAME="C_DCACHE_FORCE_TAG_LUTRAM" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Use Distributed RAM for Tags</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="186" NAME="C_DCACHE_DATA_WIDTH" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="187" NAME="C_M_AXI_DC_SUPPORTS_THREADS" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="188" NAME="C_M_AXI_DC_THREAD_ID_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="189" NAME="C_M_AXI_DC_SUPPORTS_READ" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="190" NAME="C_M_AXI_DC_SUPPORTS_WRITE" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="191" NAME="C_M_AXI_DC_SUPPORTS_NARROW_BURST" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="192" NAME="C_M_AXI_DC_DATA_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="193" NAME="C_M_AXI_DC_ADDR_WIDTH" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="194" NAME="C_M_AXI_DC_PROTOCOL" TYPE="string" VALUE="AXI4"/>
|
|
<PARAMETER MPD_INDEX="195" NAME="C_M_AXI_DC_EXCLUSIVE_ACCESS" TYPE="integer" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="196" NAME="C_M_AXI_DC_USER_VALUE" TYPE="integer" VALUE="0b11111"/>
|
|
<PARAMETER MPD_INDEX="197" NAME="C_M_AXI_DC_SUPPORTS_USER_SIGNALS" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="198" NAME="C_M_AXI_DC_AWUSER_WIDTH" TYPE="integer" VALUE="5"/>
|
|
<PARAMETER MPD_INDEX="199" NAME="C_M_AXI_DC_ARUSER_WIDTH" TYPE="integer" VALUE="5"/>
|
|
<PARAMETER MPD_INDEX="200" NAME="C_M_AXI_DC_WUSER_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="201" NAME="C_M_AXI_DC_RUSER_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="202" NAME="C_M_AXI_DC_BUSER_WIDTH" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="203" NAME="C_INTERCONNECT_M_AXI_DC_READ_ISSUING" TYPE="integer" VALUE="2"/>
|
|
<PARAMETER MPD_INDEX="204" NAME="C_INTERCONNECT_M_AXI_DC_WRITE_ISSUING" TYPE="integer" VALUE="32"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="205" NAME="C_USE_MMU" TYPE="integer" VALUE="3">
|
|
<DESCRIPTION>Memory Management</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="206" NAME="C_MMU_DTLB_SIZE" TYPE="integer" VALUE="2">
|
|
<DESCRIPTION>Data Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="207" NAME="C_MMU_ITLB_SIZE" TYPE="integer" VALUE="2">
|
|
<DESCRIPTION>Instruction Shadow Translation Look-Aside Buffer Size</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="208" NAME="C_MMU_TLB_ACCESS" TYPE="integer" VALUE="3">
|
|
<DESCRIPTION>Enable Access to Memory Management Special Registers</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="209" NAME="C_MMU_ZONES" TYPE="integer" VALUE="2">
|
|
<DESCRIPTION>Number of Memory Protection Zones</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="210" NAME="C_MMU_PRIVILEGED_INSTR" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Privileged Instructions</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="211" NAME="C_USE_INTERRUPT" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="212" NAME="C_USE_EXT_BRK" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="213" NAME="C_USE_EXT_NM_BRK" TYPE="integer" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="214" NAME="C_USE_BRANCH_TARGET_CACHE" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Enable Branch Target Cache</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="215" NAME="C_BRANCH_TARGET_CACHE_SIZE" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Branch Target Cache Size</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_M_AXI_DC_AW_REGISTER" VALUE="8"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="29" NAME="C_INTERCONNECT_M_AXI_DC_AR_REGISTER" VALUE="8"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="30" NAME="C_INTERCONNECT_M_AXI_DC_W_REGISTER" VALUE="8"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="31" NAME="C_INTERCONNECT_M_AXI_DC_R_REGISTER" VALUE="8"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="32" NAME="C_INTERCONNECT_M_AXI_DC_B_REGISTER" VALUE="8"/>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="MB_RESET" SIGIS="RST" SIGNAME="mb_reset"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Interrupt"/>
|
|
<PORT BUS="DPLB:IPLB:DLMB:ILMB:M_AXI_DP:M_AXI_IP:M_AXI_DC:M_AXI_IC" CLKFREQUENCY="100000000" DEF_SIGNAME="sys_clk_s" DIR="I" MPD_INDEX="0" NAME="CLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="DLMB:ILMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="RESET" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/>
|
|
<PORT DEF_SIGNAME="Ext_BRK" DIR="I" MPD_INDEX="4" NAME="EXT_BRK" SIGNAME="Ext_BRK"/>
|
|
<PORT DEF_SIGNAME="Ext_NM_BRK" DIR="I" MPD_INDEX="5" NAME="EXT_NM_BRK" SIGNAME="Ext_NM_BRK"/>
|
|
<PORT DIR="I" MPD_INDEX="6" NAME="DBG_STOP" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="7" NAME="MB_Halted" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="8" NAME="MB_Error" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="4095" MPD_INDEX="9" MSB="0" NAME="LOCKSTEP_MASTER_OUT" RIGHT="4095" SIGNAME="__NOC__" VECFORMULA="[0:4095]"/>
|
|
<PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="4095" MPD_INDEX="10" MSB="0" NAME="LOCKSTEP_SLAVE_IN" RIGHT="4095" SIGNAME="__NOC__" VECFORMULA="[0:4095]"/>
|
|
<PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="4095" MPD_INDEX="11" MSB="0" NAME="LOCKSTEP_OUT" RIGHT="4095" SIGNAME="__NOC__" VECFORMULA="[0:4095]"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="INSTR" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Ready" DIR="I" MPD_INDEX="13" NAME="IREADY" SIGNAME="ilmb_LMB_Ready"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_Wait" DIR="I" MPD_INDEX="14" NAME="IWAIT" SIGNAME="ilmb_LMB_Wait"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_CE" DIR="I" MPD_INDEX="15" NAME="ICE" SIGNAME="ilmb_LMB_CE"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_LMB_UE" DIR="I" MPD_INDEX="16" NAME="IUE" SIGNAME="ilmb_LMB_UE"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="INSTR_ADDR" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="O" MPD_INDEX="18" NAME="IFETCH" SIGNAME="ilmb_M_ReadStrobe"/>
|
|
<PORT BUS="ILMB" DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="O" MPD_INDEX="19" NAME="I_AS" SIGNAME="ilmb_M_AddrStrobe"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="20" NAME="IPLB_M_ABort" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="IPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="22" MSB="0" NAME="IPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="23" MSB="0" NAME="IPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_IPLB_DWIDTH-1)/8]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="24" NAME="IPLB_M_busLock" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="25" NAME="IPLB_M_lockErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="IPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="IPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="28" NAME="IPLB_M_rdBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="IPLB_M_request" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="30" NAME="IPLB_M_RNW" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="31" MSB="0" NAME="IPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="32" MSB="0" NAME="IPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="33" MSB="0" NAME="IPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="IPLB_M_wrBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="IPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="36" NAME="IPLB_MBusy" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="37" NAME="IPLB_MRdErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="38" NAME="IPLB_MWrErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="39" NAME="IPLB_MIRQ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="40" NAME="IPLB_MWrBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="41" NAME="IPLB_MWrDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="IPLB_MAddrAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="IPLB_MRdBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="IPLB_MRdDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="45" MSB="0" NAME="IPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_IPLB_DWIDTH-1]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="46" MSB="0" NAME="IPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="47" NAME="IPLB_MRearbitrate" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="48" MSB="0" NAME="IPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="IPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="IPLB_MTimeout" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="50" MSB="0" NAME="DATA_READ" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Ready" DIR="I" MPD_INDEX="51" NAME="DREADY" SIGNAME="dlmb_LMB_Ready"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_Wait" DIR="I" MPD_INDEX="52" NAME="DWAIT" SIGNAME="dlmb_LMB_Wait"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_CE" DIR="I" MPD_INDEX="53" NAME="DCE" SIGNAME="dlmb_LMB_CE"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_LMB_UE" DIR="I" MPD_INDEX="54" NAME="DUE" SIGNAME="dlmb_LMB_UE"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="55" MSB="0" NAME="DATA_WRITE" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="56" MSB="0" NAME="DATA_ADDR" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="O" MPD_INDEX="57" NAME="D_AS" SIGNAME="dlmb_M_AddrStrobe"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="O" MPD_INDEX="58" NAME="READ_STROBE" SIGNAME="dlmb_M_ReadStrobe"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="O" MPD_INDEX="59" NAME="WRITE_STROBE" SIGNAME="dlmb_M_WriteStrobe"/>
|
|
<PORT BUS="DLMB" DEF_SIGNAME="dlmb_M_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="60" MSB="0" NAME="BYTE_ENABLE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="61" NAME="DPLB_M_ABort" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="62" MSB="0" NAME="DPLB_M_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="63" MSB="0" NAME="DPLB_M_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="64" MSB="0" NAME="DPLB_M_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:(C_DPLB_DWIDTH-1)/8]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="DPLB_M_busLock" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="66" NAME="DPLB_M_lockErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="67" MSB="0" NAME="DPLB_M_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="68" MSB="0" NAME="DPLB_M_priority" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="DPLB_M_rdBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="70" NAME="DPLB_M_request" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="DPLB_M_RNW" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="72" MSB="0" NAME="DPLB_M_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="73" MSB="0" NAME="DPLB_M_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="74" MSB="0" NAME="DPLB_M_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="DPLB_M_wrBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="76" MSB="0" NAME="DPLB_M_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="77" NAME="DPLB_MBusy" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="78" NAME="DPLB_MRdErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="DPLB_MWrErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="80" NAME="DPLB_MIRQ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="81" NAME="DPLB_MWrBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="82" NAME="DPLB_MWrDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="83" NAME="DPLB_MAddrAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="84" NAME="DPLB_MRdBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="85" NAME="DPLB_MRdDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="86" MSB="0" NAME="DPLB_MRdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DPLB_DWIDTH-1]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="87" MSB="0" NAME="DPLB_MRdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="88" NAME="DPLB_MRearbitrate" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="89" MSB="0" NAME="DPLB_MSSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="DPLB" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="90" NAME="DPLB_MTimeout" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="91" NAME="M_AXI_IP_AWID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="92" MSB="31" NAME="M_AXI_IP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="93" MSB="7" NAME="M_AXI_IP_AWLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="94" MSB="2" NAME="M_AXI_IP_AWSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="95" MSB="1" NAME="M_AXI_IP_AWBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="M_AXI_IP_AWLOCK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="97" MSB="3" NAME="M_AXI_IP_AWCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="98" MSB="2" NAME="M_AXI_IP_AWPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="M_AXI_IP_AWQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="100" NAME="M_AXI_IP_AWVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="101" NAME="M_AXI_IP_AWREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="102" MSB="31" NAME="M_AXI_IP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="103" MSB="3" NAME="M_AXI_IP_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_M_AXI_IP_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="104" NAME="M_AXI_IP_WLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="M_AXI_IP_WVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="106" NAME="M_AXI_IP_WREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="107" NAME="M_AXI_IP_BID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="108" MSB="1" NAME="M_AXI_IP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="M_AXI_IP_BVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="110" NAME="M_AXI_IP_BREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="111" NAME="M_AXI_IP_ARID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
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<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="112" MSB="31" NAME="M_AXI_IP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_ADDR_WIDTH-1):0]"/>
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|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="M_AXI_IP_ARLEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="114" MSB="2" NAME="M_AXI_IP_ARSIZE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="115" MSB="1" NAME="M_AXI_IP_ARBURST" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="116" NAME="M_AXI_IP_ARLOCK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="117" MSB="3" NAME="M_AXI_IP_ARCACHE" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="118" MSB="2" NAME="M_AXI_IP_ARPROT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="119" MSB="3" NAME="M_AXI_IP_ARQOS" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="120" NAME="M_AXI_IP_ARVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="121" NAME="M_AXI_IP_ARREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="122" NAME="M_AXI_IP_RID" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="M_AXI_IP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_M_AXI_IP_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="124" MSB="1" NAME="M_AXI_IP_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="125" NAME="M_AXI_IP_RLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="126" NAME="M_AXI_IP_RVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_IP" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="127" NAME="M_AXI_IP_RREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWID" DIR="O" MPD_INDEX="128" NAME="M_AXI_DP_AWID" SIGNAME="AXI_Lite_S_AWID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="129" MSB="31" NAME="M_AXI_DP_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_S_AWADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="M_AXI_DP_AWLEN" RIGHT="0" SIGNAME="AXI_Lite_S_AWLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="131" MSB="2" NAME="M_AXI_DP_AWSIZE" RIGHT="0" SIGNAME="AXI_Lite_S_AWSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="132" MSB="1" NAME="M_AXI_DP_AWBURST" RIGHT="0" SIGNAME="AXI_Lite_S_AWBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWLOCK" DIR="O" MPD_INDEX="133" NAME="M_AXI_DP_AWLOCK" SIGNAME="AXI_Lite_S_AWLOCK"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="134" MSB="3" NAME="M_AXI_DP_AWCACHE" RIGHT="0" SIGNAME="AXI_Lite_S_AWCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="M_AXI_DP_AWPROT" RIGHT="0" SIGNAME="AXI_Lite_S_AWPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="136" MSB="3" NAME="M_AXI_DP_AWQOS" RIGHT="0" SIGNAME="AXI_Lite_S_AWQOS" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWVALID" DIR="O" MPD_INDEX="137" NAME="M_AXI_DP_AWVALID" SIGNAME="AXI_Lite_S_AWVALID"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_AWREADY" DIR="I" MPD_INDEX="138" NAME="M_AXI_DP_AWREADY" SIGNAME="AXI_Lite_S_AWREADY"/>
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|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="139" MSB="31" NAME="M_AXI_DP_WDATA" RIGHT="0" SIGNAME="AXI_Lite_S_WDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="M_AXI_DP_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_S_WSTRB" VECFORMULA="[((C_M_AXI_DP_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_WLAST" DIR="O" MPD_INDEX="141" NAME="M_AXI_DP_WLAST" SIGNAME="AXI_Lite_S_WLAST"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_WVALID" DIR="O" MPD_INDEX="142" NAME="M_AXI_DP_WVALID" SIGNAME="AXI_Lite_S_WVALID"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_WREADY" DIR="I" MPD_INDEX="143" NAME="M_AXI_DP_WREADY" SIGNAME="AXI_Lite_S_WREADY"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_BID" DIR="I" MPD_INDEX="144" NAME="M_AXI_DP_BID" SIGNAME="AXI_Lite_S_BID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="M_AXI_DP_BRESP" RIGHT="0" SIGNAME="AXI_Lite_S_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_BVALID" DIR="I" MPD_INDEX="146" NAME="M_AXI_DP_BVALID" SIGNAME="AXI_Lite_S_BVALID"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_BREADY" DIR="O" MPD_INDEX="147" NAME="M_AXI_DP_BREADY" SIGNAME="AXI_Lite_S_BREADY"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARID" DIR="O" MPD_INDEX="148" NAME="M_AXI_DP_ARID" SIGNAME="AXI_Lite_S_ARID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="149" MSB="31" NAME="M_AXI_DP_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_S_ARADDR" VECFORMULA="[(C_M_AXI_DP_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="150" MSB="7" NAME="M_AXI_DP_ARLEN" RIGHT="0" SIGNAME="AXI_Lite_S_ARLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="151" MSB="2" NAME="M_AXI_DP_ARSIZE" RIGHT="0" SIGNAME="AXI_Lite_S_ARSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="152" MSB="1" NAME="M_AXI_DP_ARBURST" RIGHT="0" SIGNAME="AXI_Lite_S_ARBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARLOCK" DIR="O" MPD_INDEX="153" NAME="M_AXI_DP_ARLOCK" SIGNAME="AXI_Lite_S_ARLOCK"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="154" MSB="3" NAME="M_AXI_DP_ARCACHE" RIGHT="0" SIGNAME="AXI_Lite_S_ARCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="155" MSB="2" NAME="M_AXI_DP_ARPROT" RIGHT="0" SIGNAME="AXI_Lite_S_ARPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="156" MSB="3" NAME="M_AXI_DP_ARQOS" RIGHT="0" SIGNAME="AXI_Lite_S_ARQOS" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARVALID" DIR="O" MPD_INDEX="157" NAME="M_AXI_DP_ARVALID" SIGNAME="AXI_Lite_S_ARVALID"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_ARREADY" DIR="I" MPD_INDEX="158" NAME="M_AXI_DP_ARREADY" SIGNAME="AXI_Lite_S_ARREADY"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_RID" DIR="I" MPD_INDEX="159" NAME="M_AXI_DP_RID" SIGNAME="AXI_Lite_S_RID" VECFORMULA="[(C_M_AXI_DP_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="M_AXI_DP_RDATA" RIGHT="0" SIGNAME="AXI_Lite_S_RDATA" VECFORMULA="[(C_M_AXI_DP_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="161" MSB="1" NAME="M_AXI_DP_RRESP" RIGHT="0" SIGNAME="AXI_Lite_S_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_RLAST" DIR="I" MPD_INDEX="162" NAME="M_AXI_DP_RLAST" SIGNAME="AXI_Lite_S_RLAST"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_RVALID" DIR="I" MPD_INDEX="163" NAME="M_AXI_DP_RVALID" SIGNAME="AXI_Lite_S_RVALID"/>
|
|
<PORT BUS="M_AXI_DP" DEF_SIGNAME="AXI_Lite_S_RREADY" DIR="O" MPD_INDEX="164" NAME="M_AXI_DP_RREADY" SIGNAME="AXI_Lite_S_RREADY"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWID" DIR="O" MPD_INDEX="165" NAME="M_AXI_IC_AWID" SIGNAME="AXI_MM_S_AWID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="166" MSB="31" NAME="M_AXI_IC_AWADDR" RIGHT="0" SIGNAME="AXI_MM_S_AWADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="167" MSB="7" NAME="M_AXI_IC_AWLEN" RIGHT="0" SIGNAME="AXI_MM_S_AWLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="168" MSB="2" NAME="M_AXI_IC_AWSIZE" RIGHT="0" SIGNAME="AXI_MM_S_AWSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="169" MSB="1" NAME="M_AXI_IC_AWBURST" RIGHT="0" SIGNAME="AXI_MM_S_AWBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWLOCK" DIR="O" MPD_INDEX="170" NAME="M_AXI_IC_AWLOCK" SIGNAME="AXI_MM_S_AWLOCK"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="171" MSB="3" NAME="M_AXI_IC_AWCACHE" RIGHT="0" SIGNAME="AXI_MM_S_AWCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="172" MSB="2" NAME="M_AXI_IC_AWPROT" RIGHT="0" SIGNAME="AXI_MM_S_AWPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="173" MSB="3" NAME="M_AXI_IC_AWQOS" RIGHT="0" SIGNAME="AXI_MM_S_AWQOS" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWVALID" DIR="O" MPD_INDEX="174" NAME="M_AXI_IC_AWVALID" SIGNAME="AXI_MM_S_AWVALID"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWREADY" DIR="I" MPD_INDEX="175" NAME="M_AXI_IC_AWREADY" SIGNAME="AXI_MM_S_AWREADY"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="176" MSB="4" NAME="M_AXI_IC_AWUSER" RIGHT="0" SIGNAME="AXI_MM_S_AWUSER" VECFORMULA="[(C_M_AXI_IC_AWUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="177" MSB="31" NAME="M_AXI_IC_WDATA" RIGHT="0" SIGNAME="AXI_MM_S_WDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="178" MSB="3" NAME="M_AXI_IC_WSTRB" RIGHT="0" SIGNAME="AXI_MM_S_WSTRB" VECFORMULA="[((C_M_AXI_IC_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_WLAST" DIR="O" MPD_INDEX="179" NAME="M_AXI_IC_WLAST" SIGNAME="AXI_MM_S_WLAST"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_WVALID" DIR="O" MPD_INDEX="180" NAME="M_AXI_IC_WVALID" SIGNAME="AXI_MM_S_WVALID"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_WREADY" DIR="I" MPD_INDEX="181" NAME="M_AXI_IC_WREADY" SIGNAME="AXI_MM_S_WREADY"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_WUSER" DIR="O" MPD_INDEX="182" NAME="M_AXI_IC_WUSER" SIGNAME="AXI_MM_S_WUSER" VECFORMULA="[(C_M_AXI_IC_WUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_BID" DIR="I" MPD_INDEX="183" NAME="M_AXI_IC_BID" SIGNAME="AXI_MM_S_BID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="184" MSB="1" NAME="M_AXI_IC_BRESP" RIGHT="0" SIGNAME="AXI_MM_S_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_BVALID" DIR="I" MPD_INDEX="185" NAME="M_AXI_IC_BVALID" SIGNAME="AXI_MM_S_BVALID"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_BREADY" DIR="O" MPD_INDEX="186" NAME="M_AXI_IC_BREADY" SIGNAME="AXI_MM_S_BREADY"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_BUSER" DIR="I" MPD_INDEX="187" NAME="M_AXI_IC_BUSER" SIGNAME="AXI_MM_S_BUSER" VECFORMULA="[(C_M_AXI_IC_BUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARID" DIR="O" MPD_INDEX="188" NAME="M_AXI_IC_ARID" SIGNAME="AXI_MM_S_ARID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="189" MSB="31" NAME="M_AXI_IC_ARADDR" RIGHT="0" SIGNAME="AXI_MM_S_ARADDR" VECFORMULA="[(C_M_AXI_IC_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="190" MSB="7" NAME="M_AXI_IC_ARLEN" RIGHT="0" SIGNAME="AXI_MM_S_ARLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="191" MSB="2" NAME="M_AXI_IC_ARSIZE" RIGHT="0" SIGNAME="AXI_MM_S_ARSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="192" MSB="1" NAME="M_AXI_IC_ARBURST" RIGHT="0" SIGNAME="AXI_MM_S_ARBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARLOCK" DIR="O" MPD_INDEX="193" NAME="M_AXI_IC_ARLOCK" SIGNAME="AXI_MM_S_ARLOCK"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="194" MSB="3" NAME="M_AXI_IC_ARCACHE" RIGHT="0" SIGNAME="AXI_MM_S_ARCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="195" MSB="2" NAME="M_AXI_IC_ARPROT" RIGHT="0" SIGNAME="AXI_MM_S_ARPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="196" MSB="3" NAME="M_AXI_IC_ARQOS" RIGHT="0" SIGNAME="AXI_MM_S_ARQOS" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARVALID" DIR="O" MPD_INDEX="197" NAME="M_AXI_IC_ARVALID" SIGNAME="AXI_MM_S_ARVALID"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARREADY" DIR="I" MPD_INDEX="198" NAME="M_AXI_IC_ARREADY" SIGNAME="AXI_MM_S_ARREADY"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="199" MSB="4" NAME="M_AXI_IC_ARUSER" RIGHT="0" SIGNAME="AXI_MM_S_ARUSER" VECFORMULA="[(C_M_AXI_IC_ARUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_RID" DIR="I" MPD_INDEX="200" NAME="M_AXI_IC_RID" SIGNAME="AXI_MM_S_RID" VECFORMULA="[(C_M_AXI_IC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="M_AXI_IC_RDATA" RIGHT="0" SIGNAME="AXI_MM_S_RDATA" VECFORMULA="[(C_M_AXI_IC_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="202" MSB="1" NAME="M_AXI_IC_RRESP" RIGHT="0" SIGNAME="AXI_MM_S_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_RLAST" DIR="I" MPD_INDEX="203" NAME="M_AXI_IC_RLAST" SIGNAME="AXI_MM_S_RLAST"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_RVALID" DIR="I" MPD_INDEX="204" NAME="M_AXI_IC_RVALID" SIGNAME="AXI_MM_S_RVALID"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_RREADY" DIR="O" MPD_INDEX="205" NAME="M_AXI_IC_RREADY" SIGNAME="AXI_MM_S_RREADY"/>
|
|
<PORT BUS="M_AXI_IC" DEF_SIGNAME="AXI_MM_S_RUSER" DIR="I" MPD_INDEX="206" NAME="M_AXI_IC_RUSER" SIGNAME="AXI_MM_S_RUSER" VECFORMULA="[(C_M_AXI_IC_RUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWID" DIR="O" MPD_INDEX="207" NAME="M_AXI_DC_AWID" SIGNAME="AXI_MM_S_AWID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="208" MSB="31" NAME="M_AXI_DC_AWADDR" RIGHT="0" SIGNAME="AXI_MM_S_AWADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="209" MSB="7" NAME="M_AXI_DC_AWLEN" RIGHT="0" SIGNAME="AXI_MM_S_AWLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="210" MSB="2" NAME="M_AXI_DC_AWSIZE" RIGHT="0" SIGNAME="AXI_MM_S_AWSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="211" MSB="1" NAME="M_AXI_DC_AWBURST" RIGHT="0" SIGNAME="AXI_MM_S_AWBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWLOCK" DIR="O" MPD_INDEX="212" NAME="M_AXI_DC_AWLOCK" SIGNAME="AXI_MM_S_AWLOCK"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="213" MSB="3" NAME="M_AXI_DC_AWCACHE" RIGHT="0" SIGNAME="AXI_MM_S_AWCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="214" MSB="2" NAME="M_AXI_DC_AWPROT" RIGHT="0" SIGNAME="AXI_MM_S_AWPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="215" MSB="3" NAME="M_AXI_DC_AWQOS" RIGHT="0" SIGNAME="AXI_MM_S_AWQOS" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWVALID" DIR="O" MPD_INDEX="216" NAME="M_AXI_DC_AWVALID" SIGNAME="AXI_MM_S_AWVALID"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWREADY" DIR="I" MPD_INDEX="217" NAME="M_AXI_DC_AWREADY" SIGNAME="AXI_MM_S_AWREADY"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="218" MSB="4" NAME="M_AXI_DC_AWUSER" RIGHT="0" SIGNAME="AXI_MM_S_AWUSER" VECFORMULA="[(C_M_AXI_DC_AWUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="219" MSB="31" NAME="M_AXI_DC_WDATA" RIGHT="0" SIGNAME="AXI_MM_S_WDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="220" MSB="3" NAME="M_AXI_DC_WSTRB" RIGHT="0" SIGNAME="AXI_MM_S_WSTRB" VECFORMULA="[((C_M_AXI_DC_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_WLAST" DIR="O" MPD_INDEX="221" NAME="M_AXI_DC_WLAST" SIGNAME="AXI_MM_S_WLAST"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_WVALID" DIR="O" MPD_INDEX="222" NAME="M_AXI_DC_WVALID" SIGNAME="AXI_MM_S_WVALID"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_WREADY" DIR="I" MPD_INDEX="223" NAME="M_AXI_DC_WREADY" SIGNAME="AXI_MM_S_WREADY"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_WUSER" DIR="O" MPD_INDEX="224" NAME="M_AXI_DC_WUSER" SIGNAME="AXI_MM_S_WUSER" VECFORMULA="[(C_M_AXI_DC_WUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_BID" DIR="I" MPD_INDEX="225" NAME="M_AXI_DC_BID" SIGNAME="AXI_MM_S_BID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="226" MSB="1" NAME="M_AXI_DC_BRESP" RIGHT="0" SIGNAME="AXI_MM_S_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_BVALID" DIR="I" MPD_INDEX="227" NAME="M_AXI_DC_BVALID" SIGNAME="AXI_MM_S_BVALID"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_BREADY" DIR="O" MPD_INDEX="228" NAME="M_AXI_DC_BREADY" SIGNAME="AXI_MM_S_BREADY"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_BUSER" DIR="I" MPD_INDEX="229" NAME="M_AXI_DC_BUSER" SIGNAME="AXI_MM_S_BUSER" VECFORMULA="[(C_M_AXI_DC_BUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARID" DIR="O" MPD_INDEX="230" NAME="M_AXI_DC_ARID" SIGNAME="AXI_MM_S_ARID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="231" MSB="31" NAME="M_AXI_DC_ARADDR" RIGHT="0" SIGNAME="AXI_MM_S_ARADDR" VECFORMULA="[(C_M_AXI_DC_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="232" MSB="7" NAME="M_AXI_DC_ARLEN" RIGHT="0" SIGNAME="AXI_MM_S_ARLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="233" MSB="2" NAME="M_AXI_DC_ARSIZE" RIGHT="0" SIGNAME="AXI_MM_S_ARSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="234" MSB="1" NAME="M_AXI_DC_ARBURST" RIGHT="0" SIGNAME="AXI_MM_S_ARBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARLOCK" DIR="O" MPD_INDEX="235" NAME="M_AXI_DC_ARLOCK" SIGNAME="AXI_MM_S_ARLOCK"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="236" MSB="3" NAME="M_AXI_DC_ARCACHE" RIGHT="0" SIGNAME="AXI_MM_S_ARCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="237" MSB="2" NAME="M_AXI_DC_ARPROT" RIGHT="0" SIGNAME="AXI_MM_S_ARPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="238" MSB="3" NAME="M_AXI_DC_ARQOS" RIGHT="0" SIGNAME="AXI_MM_S_ARQOS" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARVALID" DIR="O" MPD_INDEX="239" NAME="M_AXI_DC_ARVALID" SIGNAME="AXI_MM_S_ARVALID"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARREADY" DIR="I" MPD_INDEX="240" NAME="M_AXI_DC_ARREADY" SIGNAME="AXI_MM_S_ARREADY"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="4" LSB="0" MPD_INDEX="241" MSB="4" NAME="M_AXI_DC_ARUSER" RIGHT="0" SIGNAME="AXI_MM_S_ARUSER" VECFORMULA="[(C_M_AXI_DC_ARUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_RID" DIR="I" MPD_INDEX="242" NAME="M_AXI_DC_RID" SIGNAME="AXI_MM_S_RID" VECFORMULA="[(C_M_AXI_DC_THREAD_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="243" MSB="31" NAME="M_AXI_DC_RDATA" RIGHT="0" SIGNAME="AXI_MM_S_RDATA" VECFORMULA="[(C_M_AXI_DC_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="244" MSB="1" NAME="M_AXI_DC_RRESP" RIGHT="0" SIGNAME="AXI_MM_S_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_RLAST" DIR="I" MPD_INDEX="245" NAME="M_AXI_DC_RLAST" SIGNAME="AXI_MM_S_RLAST"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_RVALID" DIR="I" MPD_INDEX="246" NAME="M_AXI_DC_RVALID" SIGNAME="AXI_MM_S_RVALID"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_RREADY" DIR="O" MPD_INDEX="247" NAME="M_AXI_DC_RREADY" SIGNAME="AXI_MM_S_RREADY"/>
|
|
<PORT BUS="M_AXI_DC" DEF_SIGNAME="AXI_MM_S_RUSER" DIR="I" MPD_INDEX="248" NAME="M_AXI_DC_RUSER" SIGNAME="AXI_MM_S_RUSER" VECFORMULA="[(C_M_AXI_DC_RUSER_WIDTH-1):0]"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Dbg_Clk" DIR="I" MPD_INDEX="249" NAME="DBG_CLK" SIGNAME="microblaze_0_dbg_Dbg_Clk"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Dbg_TDI" DIR="I" MPD_INDEX="250" NAME="DBG_TDI" SIGNAME="microblaze_0_dbg_Dbg_TDI"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Dbg_TDO" DIR="O" MPD_INDEX="251" NAME="DBG_TDO" SIGNAME="microblaze_0_dbg_Dbg_TDO"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Dbg_Reg_En" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="252" MSB="0" NAME="DBG_REG_EN" RIGHT="7" SIGNAME="microblaze_0_dbg_Dbg_Reg_En" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Dbg_Shift" DIR="I" MPD_INDEX="253" NAME="DBG_SHIFT" SIGNAME="microblaze_0_dbg_Dbg_Shift"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Dbg_Capture" DIR="I" MPD_INDEX="254" NAME="DBG_CAPTURE" SIGNAME="microblaze_0_dbg_Dbg_Capture"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Dbg_Update" DIR="I" MPD_INDEX="255" NAME="DBG_UPDATE" SIGNAME="microblaze_0_dbg_Dbg_Update"/>
|
|
<PORT BUS="DEBUG" DEF_SIGNAME="microblaze_0_dbg_Debug_Rst" DIR="I" MPD_INDEX="256" NAME="DEBUG_RST" SIGIS="RST" SIGNAME="microblaze_0_dbg_Debug_Rst"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="257" MSB="0" NAME="Trace_Instruction" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="258" NAME="Trace_Valid_Instr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="259" MSB="0" NAME="Trace_PC" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="260" NAME="Trace_Reg_Write" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="261" MSB="0" NAME="Trace_Reg_Addr" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="14" MPD_INDEX="262" MSB="0" NAME="Trace_MSR_Reg" RIGHT="14" SIGNAME="__NOC__" VECFORMULA="[0:14]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="263" MSB="0" NAME="Trace_PID_Reg" RIGHT="7" SIGNAME="__NOC__" VECFORMULA="[0:7]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="264" MSB="0" NAME="Trace_New_Reg_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="265" NAME="Trace_Exception_Taken" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="266" MSB="0" NAME="Trace_Exception_Kind" RIGHT="4" SIGNAME="__NOC__" VECFORMULA="[0:4]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="267" NAME="Trace_Jump_Taken" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="268" NAME="Trace_Delay_Slot" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="269" MSB="0" NAME="Trace_Data_Address" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="270" NAME="Trace_Data_Access" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="271" NAME="Trace_Data_Read" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="272" NAME="Trace_Data_Write" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="273" MSB="0" NAME="Trace_Data_Write_Value" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="274" MSB="0" NAME="Trace_Data_Byte_Enable" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="275" NAME="Trace_DCache_Req" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="276" NAME="Trace_DCache_Hit" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="277" NAME="Trace_DCache_Rdy" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="278" NAME="Trace_DCache_Read" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="279" NAME="Trace_ICache_Req" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="280" NAME="Trace_ICache_Hit" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="281" NAME="Trace_ICache_Rdy" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="282" NAME="Trace_OF_PipeRun" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="283" NAME="Trace_EX_PipeRun" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="284" NAME="Trace_MEM_PipeRun" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="285" NAME="Trace_MB_Halted" SIGNAME="__NOC__"/>
|
|
<PORT BUS="TRACE" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="286" NAME="Trace_Jump_Hit" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="287" NAME="FSL0_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="288" NAME="FSL0_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="289" MSB="0" NAME="FSL0_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="290" NAME="FSL0_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL0:DRFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="291" NAME="FSL0_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="292" NAME="FSL0_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="293" NAME="FSL0_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="294" MSB="0" NAME="FSL0_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="295" NAME="FSL0_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL0:DWFSL0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="296" NAME="FSL0_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="297" NAME="FSL1_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="298" NAME="FSL1_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="299" MSB="0" NAME="FSL1_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="300" NAME="FSL1_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL1:DRFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="301" NAME="FSL1_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="302" NAME="FSL1_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="303" NAME="FSL1_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="304" MSB="0" NAME="FSL1_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="305" NAME="FSL1_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL1:DWFSL1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="306" NAME="FSL1_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="307" NAME="FSL2_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="308" NAME="FSL2_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="309" MSB="0" NAME="FSL2_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="310" NAME="FSL2_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL2:DRFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="311" NAME="FSL2_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="312" NAME="FSL2_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="313" NAME="FSL2_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="314" MSB="0" NAME="FSL2_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="315" NAME="FSL2_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL2:DWFSL2" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="316" NAME="FSL2_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="317" NAME="FSL3_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="318" NAME="FSL3_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="319" MSB="0" NAME="FSL3_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="320" NAME="FSL3_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL3:DRFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="321" NAME="FSL3_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="322" NAME="FSL3_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="323" NAME="FSL3_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="324" MSB="0" NAME="FSL3_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="325" NAME="FSL3_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL3:DWFSL3" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="326" NAME="FSL3_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="327" NAME="FSL4_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="328" NAME="FSL4_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="329" MSB="0" NAME="FSL4_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="330" NAME="FSL4_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL4:DRFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="331" NAME="FSL4_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="332" NAME="FSL4_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="333" NAME="FSL4_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="334" MSB="0" NAME="FSL4_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="335" NAME="FSL4_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL4:DWFSL4" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="336" NAME="FSL4_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="337" NAME="FSL5_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="338" NAME="FSL5_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="339" MSB="0" NAME="FSL5_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="340" NAME="FSL5_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL5:DRFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="341" NAME="FSL5_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="342" NAME="FSL5_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="343" NAME="FSL5_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="344" MSB="0" NAME="FSL5_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="345" NAME="FSL5_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL5:DWFSL5" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="346" NAME="FSL5_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="347" NAME="FSL6_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="348" NAME="FSL6_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="349" MSB="0" NAME="FSL6_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="350" NAME="FSL6_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL6:DRFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="351" NAME="FSL6_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="352" NAME="FSL6_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="353" NAME="FSL6_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="354" MSB="0" NAME="FSL6_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="355" NAME="FSL6_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL6:DWFSL6" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="356" NAME="FSL6_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="357" NAME="FSL7_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="358" NAME="FSL7_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="359" MSB="0" NAME="FSL7_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="360" NAME="FSL7_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL7:DRFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="361" NAME="FSL7_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="362" NAME="FSL7_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="363" NAME="FSL7_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="364" MSB="0" NAME="FSL7_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="365" NAME="FSL7_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL7:DWFSL7" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="366" NAME="FSL7_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="367" NAME="FSL8_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="368" NAME="FSL8_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="369" MSB="0" NAME="FSL8_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="370" NAME="FSL8_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL8:DRFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="371" NAME="FSL8_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="372" NAME="FSL8_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="373" NAME="FSL8_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="374" MSB="0" NAME="FSL8_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="375" NAME="FSL8_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL8:DWFSL8" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="376" NAME="FSL8_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="377" NAME="FSL9_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="378" NAME="FSL9_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="379" MSB="0" NAME="FSL9_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="380" NAME="FSL9_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL9:DRFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="381" NAME="FSL9_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="382" NAME="FSL9_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="383" NAME="FSL9_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="384" MSB="0" NAME="FSL9_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="385" NAME="FSL9_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL9:DWFSL9" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="386" NAME="FSL9_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="387" NAME="FSL10_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="388" NAME="FSL10_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="389" MSB="0" NAME="FSL10_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="390" NAME="FSL10_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL10:DRFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="391" NAME="FSL10_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="392" NAME="FSL10_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="393" NAME="FSL10_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="394" MSB="0" NAME="FSL10_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="395" NAME="FSL10_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL10:DWFSL10" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="396" NAME="FSL10_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="397" NAME="FSL11_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="398" NAME="FSL11_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="399" MSB="0" NAME="FSL11_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="400" NAME="FSL11_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL11:DRFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="401" NAME="FSL11_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="402" NAME="FSL11_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="403" NAME="FSL11_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="404" MSB="0" NAME="FSL11_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="405" NAME="FSL11_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL11:DWFSL11" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="406" NAME="FSL11_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="407" NAME="FSL12_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="408" NAME="FSL12_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="409" MSB="0" NAME="FSL12_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="410" NAME="FSL12_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL12:DRFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="411" NAME="FSL12_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="412" NAME="FSL12_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="413" NAME="FSL12_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="414" MSB="0" NAME="FSL12_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="415" NAME="FSL12_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL12:DWFSL12" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="416" NAME="FSL12_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="417" NAME="FSL13_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="418" NAME="FSL13_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="419" MSB="0" NAME="FSL13_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="420" NAME="FSL13_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL13:DRFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="421" NAME="FSL13_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="422" NAME="FSL13_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="423" NAME="FSL13_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="424" MSB="0" NAME="FSL13_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="425" NAME="FSL13_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL13:DWFSL13" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="426" NAME="FSL13_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="427" NAME="FSL14_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="428" NAME="FSL14_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="429" MSB="0" NAME="FSL14_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="430" NAME="FSL14_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL14:DRFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="431" NAME="FSL14_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="432" NAME="FSL14_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="433" NAME="FSL14_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="434" MSB="0" NAME="FSL14_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="435" NAME="FSL14_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL14:DWFSL14" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="436" NAME="FSL14_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="437" NAME="FSL15_S_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="438" NAME="FSL15_S_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="439" MSB="0" NAME="FSL15_S_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="440" NAME="FSL15_S_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SFSL15:DRFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="441" NAME="FSL15_S_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="442" NAME="FSL15_M_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="443" NAME="FSL15_M_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="444" MSB="0" NAME="FSL15_M_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_FSL_DATA_SIZE-1]"/>
|
|
<PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="445" NAME="FSL15_M_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="MFSL15:DWFSL15" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="446" NAME="FSL15_M_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="447" NAME="M0_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="448" MSB="31" NAME="M0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M0_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="449" NAME="M0_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="450" NAME="M0_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="451" NAME="S0_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="452" MSB="31" NAME="S0_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S0_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="453" NAME="S0_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S0_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="454" NAME="S0_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="455" NAME="M1_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="456" MSB="31" NAME="M1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M1_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="457" NAME="M1_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="458" NAME="M1_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="459" NAME="S1_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="460" MSB="31" NAME="S1_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S1_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="461" NAME="S1_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S1_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="462" NAME="S1_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="463" NAME="M2_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="464" MSB="31" NAME="M2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M2_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="465" NAME="M2_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="466" NAME="M2_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="467" NAME="S2_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="468" MSB="31" NAME="S2_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S2_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="469" NAME="S2_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S2_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="470" NAME="S2_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="471" NAME="M3_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="472" MSB="31" NAME="M3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M3_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="473" NAME="M3_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="474" NAME="M3_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="475" NAME="S3_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="476" MSB="31" NAME="S3_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S3_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="477" NAME="S3_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="478" NAME="S3_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="479" NAME="M4_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="480" MSB="31" NAME="M4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M4_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="481" NAME="M4_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="482" NAME="M4_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="483" NAME="S4_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="484" MSB="31" NAME="S4_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S4_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="485" NAME="S4_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="486" NAME="S4_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="487" NAME="M5_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="488" MSB="31" NAME="M5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M5_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="489" NAME="M5_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="490" NAME="M5_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="491" NAME="S5_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="492" MSB="31" NAME="S5_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S5_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="493" NAME="S5_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="494" NAME="S5_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="495" NAME="M6_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="496" MSB="31" NAME="M6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M6_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="497" NAME="M6_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="498" NAME="M6_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="499" NAME="S6_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="500" MSB="31" NAME="S6_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S6_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="501" NAME="S6_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S6_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="502" NAME="S6_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="503" NAME="M7_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="504" MSB="31" NAME="M7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M7_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="505" NAME="M7_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="506" NAME="M7_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="507" NAME="S7_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="508" MSB="31" NAME="S7_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S7_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="509" NAME="S7_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S7_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="510" NAME="S7_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="511" NAME="M8_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="512" MSB="31" NAME="M8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M8_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="513" NAME="M8_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="514" NAME="M8_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="515" NAME="S8_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="516" MSB="31" NAME="S8_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S8_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="517" NAME="S8_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S8_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="518" NAME="S8_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="519" NAME="M9_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="520" MSB="31" NAME="M9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M9_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="521" NAME="M9_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="522" NAME="M9_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="523" NAME="S9_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="524" MSB="31" NAME="S9_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S9_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="525" NAME="S9_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S9_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="526" NAME="S9_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="527" NAME="M10_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="528" MSB="31" NAME="M10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M10_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="529" NAME="M10_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="530" NAME="M10_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="531" NAME="S10_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="532" MSB="31" NAME="S10_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S10_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="533" NAME="S10_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S10_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="534" NAME="S10_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="535" NAME="M11_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="536" MSB="31" NAME="M11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M11_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="537" NAME="M11_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="538" NAME="M11_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="539" NAME="S11_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="540" MSB="31" NAME="S11_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S11_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="541" NAME="S11_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S11_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="542" NAME="S11_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="543" NAME="M12_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="544" MSB="31" NAME="M12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M12_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="545" NAME="M12_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="546" NAME="M12_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="547" NAME="S12_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="548" MSB="31" NAME="S12_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S12_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="549" NAME="S12_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S12_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="550" NAME="S12_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="551" NAME="M13_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="552" MSB="31" NAME="M13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M13_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="553" NAME="M13_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="554" NAME="M13_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="555" NAME="S13_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="556" MSB="31" NAME="S13_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S13_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="557" NAME="S13_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S13_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="558" NAME="S13_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="559" NAME="M14_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="560" MSB="31" NAME="M14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M14_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="561" NAME="M14_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="562" NAME="M14_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="563" NAME="S14_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="564" MSB="31" NAME="S14_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S14_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="565" NAME="S14_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S14_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="566" NAME="S14_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="567" NAME="M15_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="568" MSB="31" NAME="M15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_M15_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="569" NAME="M15_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="M15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="570" NAME="M15_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="571" NAME="S15_AXIS_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="572" MSB="31" NAME="S15_AXIS_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S15_AXIS_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="573" NAME="S15_AXIS_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S15_AXIS" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="574" NAME="S15_AXIS_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="575" NAME="ICACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="576" NAME="ICACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="577" MSB="0" NAME="ICACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="578" NAME="ICACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="579" NAME="ICACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="580" NAME="ICACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="581" NAME="ICACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="582" MSB="0" NAME="ICACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="583" NAME="ICACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="IXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="584" NAME="ICACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="585" NAME="DCACHE_FSL_IN_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="586" NAME="DCACHE_FSL_IN_READ" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="587" MSB="0" NAME="DCACHE_FSL_IN_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="588" NAME="DCACHE_FSL_IN_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="589" NAME="DCACHE_FSL_IN_EXISTS" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="590" NAME="DCACHE_FSL_OUT_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="591" NAME="DCACHE_FSL_OUT_WRITE" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="592" MSB="0" NAME="DCACHE_FSL_OUT_DATA" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="593" NAME="DCACHE_FSL_OUT_CONTROL" SIGNAME="__NOC__"/>
|
|
<PORT BUS="DXCL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="594" NAME="DCACHE_FSL_OUT_FULL" SIGNAME="__NOC__"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="2" NAME="DPLB" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_ABort"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_ABus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_UABus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_BE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_busLock"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_lockErr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_MSize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_priority"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_rdBurst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_request"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_RNW"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_size"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_TAttribute"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_type"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_wrBurst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DPLB_M_wrDBus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MBusy"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MRdErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MWrErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MIRQ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MWrBTerm"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MWrDAck"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MAddrAck"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MRdBTerm"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MRdDAck"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MRdDBus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MRdWdAddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MRearbitrate"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MSSize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DPLB_MTimeout"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="3" NAME="IPLB" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_ABort"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_ABus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_UABus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_BE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_busLock"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_lockErr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_MSize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_priority"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_rdBurst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_request"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_RNW"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_size"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_TAttribute"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_type"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_wrBurst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IPLB_M_wrDBus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MBusy"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MRdErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MWrErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MIRQ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MWrBTerm"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MWrDAck"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MAddrAck"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MRdBTerm"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MRdDAck"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MRdDBus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MRdWdAddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MRearbitrate"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MSSize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IPLB_MTimeout"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="0" NAME="DLMB" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RESET"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DATA_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DWAIT"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DCE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DUE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DATA_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DATA_ADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="D_AS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="READ_STROBE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="WRITE_STROBE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BYTE_ENABLE"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="ILMB" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RESET"/>
|
|
<PORTMAP DIR="I" PHYSICAL="INSTR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IWAIT"/>
|
|
<PORTMAP DIR="I" PHYSICAL="ICE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="IUE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="INSTR_ADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="IFETCH"/>
|
|
<PORTMAP DIR="O" PHYSICAL="I_AS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="4" NAME="M_AXI_DP" PROTOCOL="AXI4LITE" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_AWVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_AWREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WSTRB"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_WVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_WREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_BVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_BREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_ARVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_ARREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DP_RVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DP_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTRUCTION="TRUE" MPD_INDEX="5" NAME="M_AXI_IP" PROTOCOL="AXI4LITE" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_AWVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_AWREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WSTRB"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_WVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_WREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_BVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_BREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_ARVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_ARREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IP_RVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IP_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_DATA="TRUE" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="104" NAME="M_AXI_DC" PROTOCOL="AXI4" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_AWREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_AWUSER"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WSTRB"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_WUSER"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_BUSER"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_ARUSER"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_DC_RREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_DC_RUSER"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" IS_INSTRUCTION="TRUE" MHS_INDEX="2" MPD_INDEX="105" NAME="M_AXI_IC" PROTOCOL="AXI4" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_AWREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_AWUSER"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WSTRB"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_WUSER"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_BUSER"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARSIZE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARBURST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARLOCK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARCACHE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARQOS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_ARUSER"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RRESP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M_AXI_IC_RREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M_AXI_IC_RUSER"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="microblaze_0_dbg" BUSSTD="XIL" BUSSTD_PSF="XIL_MBDEBUG3" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="106" NAME="DEBUG" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="DBG_CLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DBG_TDI"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DBG_TDO"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DBG_REG_EN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DBG_SHIFT"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DBG_CAPTURE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DBG_UPDATE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DEBUG_RST"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MBTRACE2" MPD_INDEX="107" NAME="TRACE" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Instruction"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Valid_Instr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_PC"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Reg_Write"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Reg_Addr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_MSR_Reg"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_PID_Reg"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_New_Reg_Value"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Exception_Taken"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Exception_Kind"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Jump_Taken"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Delay_Slot"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Data_Address"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Data_Access"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Data_Read"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Data_Write"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Data_Write_Value"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Data_Byte_Enable"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_DCache_Req"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_DCache_Hit"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_DCache_Rdy"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_DCache_Read"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_ICache_Req"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_ICache_Hit"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_ICache_Rdy"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_OF_PipeRun"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_EX_PipeRun"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_MEM_PipeRun"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_MB_Halted"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Trace_Jump_Hit"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="6" NAME="SFSL0" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="38" NAME="DRFSL0" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="7" NAME="MFSL0" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="39" NAME="DWFSL0" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL0_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL0_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="8" NAME="SFSL1" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="40" NAME="DRFSL1" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="9" NAME="MFSL1" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="41" NAME="DWFSL1" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL1_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL1_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="10" NAME="SFSL2" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="42" NAME="DRFSL2" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="11" NAME="MFSL2" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="43" NAME="DWFSL2" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL2_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL2_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="12" NAME="SFSL3" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="44" NAME="DRFSL3" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="13" NAME="MFSL3" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="45" NAME="DWFSL3" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL3_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL3_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="14" NAME="SFSL4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="46" NAME="DRFSL4" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="15" NAME="MFSL4" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="47" NAME="DWFSL4" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL4_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL4_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="16" NAME="SFSL5" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="48" NAME="DRFSL5" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="17" NAME="MFSL5" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="49" NAME="DWFSL5" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL5_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL5_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="18" NAME="SFSL6" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="50" NAME="DRFSL6" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="19" NAME="MFSL6" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="51" NAME="DWFSL6" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL6_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL6_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="20" NAME="SFSL7" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="52" NAME="DRFSL7" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="21" NAME="MFSL7" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="53" NAME="DWFSL7" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL7_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL7_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="22" NAME="SFSL8" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="54" NAME="DRFSL8" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="23" NAME="MFSL8" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="55" NAME="DWFSL8" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL8_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL8_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="24" NAME="SFSL9" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="56" NAME="DRFSL9" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="25" NAME="MFSL9" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="57" NAME="DWFSL9" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL9_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL9_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="26" NAME="SFSL10" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="58" NAME="DRFSL10" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="27" NAME="MFSL10" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="59" NAME="DWFSL10" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL10_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL10_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="28" NAME="SFSL11" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="60" NAME="DRFSL11" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="29" NAME="MFSL11" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="61" NAME="DWFSL11" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL11_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL11_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="30" NAME="SFSL12" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="62" NAME="DRFSL12" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="31" NAME="MFSL12" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="63" NAME="DWFSL12" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL12_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL12_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="32" NAME="SFSL13" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="64" NAME="DRFSL13" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="33" NAME="MFSL13" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="65" NAME="DWFSL13" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL13_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL13_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="34" NAME="SFSL14" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="66" NAME="DRFSL14" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="35" NAME="MFSL14" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="67" NAME="DWFSL14" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL14_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL14_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="36" NAME="SFSL15" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DRFSL" IS_VALID="FALSE" MPD_INDEX="68" NAME="DRFSL15" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_S_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_S_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_S_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_S_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_S_EXISTS"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="FSL" BUSSTD_PSF="FSL" IS_VALID="FALSE" MPD_INDEX="37" NAME="MFSL15" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_DWFSL" IS_VALID="FALSE" MPD_INDEX="69" NAME="DWFSL15" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="FSL15_M_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="FSL15_M_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="70" NAME="M0_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M0_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M0_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M0_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M0_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="71" NAME="S0_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S0_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S0_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S0_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S0_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="72" NAME="M1_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M1_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M1_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M1_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M1_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="73" NAME="S1_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S1_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S1_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S1_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S1_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="74" NAME="M2_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M2_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M2_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M2_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M2_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="75" NAME="S2_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S2_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S2_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S2_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S2_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="76" NAME="M3_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M3_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M3_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M3_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M3_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="77" NAME="S3_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S3_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S3_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S3_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S3_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="78" NAME="M4_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M4_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M4_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M4_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M4_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="79" NAME="S4_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S4_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S4_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S4_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S4_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="80" NAME="M5_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M5_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M5_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M5_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M5_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="81" NAME="S5_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S5_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S5_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S5_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S5_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="82" NAME="M6_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M6_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M6_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M6_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M6_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="83" NAME="S6_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S6_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S6_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S6_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S6_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="84" NAME="M7_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M7_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M7_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M7_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M7_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="85" NAME="S7_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S7_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S7_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S7_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S7_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="86" NAME="M8_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M8_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M8_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M8_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M8_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="87" NAME="S8_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S8_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S8_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S8_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S8_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="88" NAME="M9_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M9_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M9_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M9_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M9_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="89" NAME="S9_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S9_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S9_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S9_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S9_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="90" NAME="M10_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M10_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M10_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M10_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M10_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="91" NAME="S10_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S10_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S10_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S10_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S10_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="92" NAME="M11_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M11_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M11_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M11_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M11_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="93" NAME="S11_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S11_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S11_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S11_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S11_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="94" NAME="M12_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M12_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M12_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M12_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M12_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="95" NAME="S12_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S12_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S12_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S12_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S12_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="96" NAME="M13_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M13_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M13_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M13_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M13_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="97" NAME="S13_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S13_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S13_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S13_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S13_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="98" NAME="M14_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M14_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M14_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M14_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M14_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="99" NAME="S14_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S14_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S14_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S14_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S14_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="100" NAME="M15_AXIS" PROTOCOL="GENERIC" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="M15_AXIS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M15_AXIS_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="M15_AXIS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="M15_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="101" NAME="S15_AXIS" PROTOCOL="GENERIC" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S15_AXIS_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S15_AXIS_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S15_AXIS_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S15_AXIS_TREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_INSTRUCTION="TRUE" IS_VALID="FALSE" MPD_INDEX="103" NAME="IXCL" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_IN_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_IN_EXISTS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="ICACHE_FSL_OUT_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="ICACHE_FSL_OUT_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_MEMORY_CHANNEL" IS_DATA="TRUE" IS_VALID="FALSE" MPD_INDEX="102" NAME="DXCL" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_IN_READ"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_DATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_IN_EXISTS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_WRITE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_DATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DCACHE_FSL_OUT_CONTROL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DCACHE_FSL_OUT_FULL"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="65535" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0000FFFF" INSTANCE="LocalMemory_Cntlr_D" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="dlmb"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="65535" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0000FFFF" INSTANCE="LocalMemory_Cntlr_I" IS_DATA="FALSE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="ilmb"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2218786816" BASENAME="C_BASEADDR" BASEVALUE="0x84400000" HIGHDECIMAL="2218852351" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8440ffff" INSTANCE="Debug_Module" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" INSTANCE="RS232_Uart_1" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2210398208" BASENAME="C_BASEADDR" BASEVALUE="0x83c00000" HIGHDECIMAL="2210463743" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x83c0ffff" INSTANCE="Dual_Timer_Counter" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2172649472" BASENAME="C_BASEADDR" BASEVALUE="0x81800000" HIGHDECIMAL="2172715007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8180ffff" INSTANCE="Interrupt_Cntlr" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2202009600" BASENAME="C_BASEADDR" BASEVALUE="0x83400000" HIGHDECIMAL="2202075135" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8340ffff" INSTANCE="SPI_FLASH" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2170552320" BASENAME="C_BASEADDR" BASEVALUE="0x81600000" HIGHDECIMAL="2170617855" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8160ffff" INSTANCE="IIC_EEPROM" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2168586240" BASENAME="C_BASEADDR" BASEVALUE="0x81420000" HIGHDECIMAL="2168651775" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8142FFFF" INSTANCE="LEDs_4Bit" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2168455168" BASENAME="C_BASEADDR" BASEVALUE="0x81400000" HIGHDECIMAL="2168520703" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8140ffff" INSTANCE="Push_Buttons_4Bit" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2168717312" BASENAME="C_BASEADDR" BASEVALUE="0x81440000" HIGHDECIMAL="2168782847" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8144ffff" INSTANCE="DIP_Switches_4Bit" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2147483648" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHDECIMAL="2147549183" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8000FFFF" INSTANCE="AXI_DMA_Ethernet" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2248146944" BASENAME="C_BASEADDR" BASEVALUE="0x86000000" HIGHDECIMAL="2248671231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8607FFFF" INSTANCE="Soft_Ethernet_MAC" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="524288" SIZEABRV="512K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="2441084928" BASENAME="C_BASEADDR" BASEVALUE="0x91800000" HIGHDECIMAL="2441150463" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x9180ffff" INSTANCE="SysACE_CompactFlash" IS_DATA="TRUE" IS_INSTRUCTION="FALSE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_Lite"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1207959551" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0x47FFFFFF" INSTANCE="DDR3_SDRAM" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="134217728" SIZEABRV="128M">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_MM"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="1241513984" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x4A000000" HIGHDECIMAL="1241579519" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x4A00FFFF" INSTANCE="Internal_BRAM" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="65536" SIZEABRV="64K">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_MM"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="1207959552" BASENAME="C_S_AXI_MEM0_BASEADDR" BASEVALUE="0x48000000" HIGHDECIMAL="1241513983" HIGHNAME="C_S_AXI_MEM0_HIGHADDR" HIGHVALUE="0x49FFFFFF" INSTANCE="FLASH" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="33554432" SIZEABRV="32M">
|
|
<ACCESSROUTE>
|
|
<ROUTEPNT INDEX="0" INSTANCE="AXI_MM"/>
|
|
</ACCESSROUTE>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<PERIPHERALS>
|
|
<PERIPHERAL INSTANCE="LocalMemory_Cntlr_D"/>
|
|
<PERIPHERAL INSTANCE="LocalMemory_Cntlr_I"/>
|
|
<PERIPHERAL INSTANCE="Debug_Module"/>
|
|
<PERIPHERAL INSTANCE="RS232_Uart_1"/>
|
|
<PERIPHERAL INSTANCE="Dual_Timer_Counter"/>
|
|
<PERIPHERAL INSTANCE="Interrupt_Cntlr"/>
|
|
<PERIPHERAL INSTANCE="SPI_FLASH"/>
|
|
<PERIPHERAL INSTANCE="IIC_EEPROM"/>
|
|
<PERIPHERAL INSTANCE="LEDs_4Bit"/>
|
|
<PERIPHERAL INSTANCE="Push_Buttons_4Bit"/>
|
|
<PERIPHERAL INSTANCE="DIP_Switches_4Bit"/>
|
|
<PERIPHERAL INSTANCE="AXI_DMA_Ethernet"/>
|
|
<PERIPHERAL INSTANCE="Soft_Ethernet_MAC"/>
|
|
<PERIPHERAL INSTANCE="SysACE_CompactFlash"/>
|
|
<PERIPHERAL INSTANCE="DDR3_SDRAM"/>
|
|
<PERIPHERAL INSTANCE="Internal_BRAM"/>
|
|
<PERIPHERAL INSTANCE="FLASH"/>
|
|
</PERIPHERALS>
|
|
<INTERRUPTINFO TYPE="TARGET">
|
|
<SOURCE INSTANCE="Interrupt_Cntlr" INTC_INDEX="0"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.b" INSTANCE="ilmb" IPTYPE="BUS" MHS_INDEX="2" MODCLASS="BUS" MODTYPE="lmb_v10">
|
|
<DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_b/doc/lmb_v10.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Active High External Reset</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGNAME="sys_bus_reset"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="ilmb_LMB_Rst"/>
|
|
<PORT DEF_SIGNAME="ilmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="ilmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="ilmb_M_ReadStrobe"/>
|
|
<PORT DEF_SIGNAME="ilmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="ilmb_M_WriteStrobe"/>
|
|
<PORT DEF_SIGNAME="ilmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="ilmb_M_AddrStrobe"/>
|
|
<PORT DEF_SIGNAME="ilmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="ilmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="ilmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="ilmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="ilmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="ilmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="ilmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="ilmb_LMB_Ready"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="ilmb_LMB_Wait"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="ilmb_LMB_UE"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="ilmb_LMB_CE"/>
|
|
<PORT DEF_SIGNAME="ilmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES/>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
|
|
</IOINTERFACES>
|
|
</MODULE>
|
|
<MODULE BUSSTD="LMB" BUSSTD_PSF="LMB" HWVERSION="2.00.b" INSTANCE="dlmb" IPTYPE="BUS" MHS_INDEX="3" MODCLASS="BUS" MODTYPE="lmb_v10">
|
|
<DESCRIPTION TYPE="SHORT">Local Memory Bus (LMB) 1.0</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_v10_v2_00_b/doc/lmb_v10.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_LMB_NUM_SLAVES" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Number of Bus Slaves </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Active High External Reset</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGNAME="sys_bus_reset"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_Rst" DIR="O" MPD_INDEX="2" NAME="LMB_Rst" SIGNAME="dlmb_LMB_Rst"/>
|
|
<PORT DEF_SIGNAME="dlmb_M_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="M_ABus" RIGHT="31" SIGNAME="dlmb_M_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_M_ReadStrobe" DIR="I" MPD_INDEX="4" NAME="M_ReadStrobe" SIGNAME="dlmb_M_ReadStrobe"/>
|
|
<PORT DEF_SIGNAME="dlmb_M_WriteStrobe" DIR="I" MPD_INDEX="5" NAME="M_WriteStrobe" SIGNAME="dlmb_M_WriteStrobe"/>
|
|
<PORT DEF_SIGNAME="dlmb_M_AddrStrobe" DIR="I" MPD_INDEX="6" NAME="M_AddrStrobe" SIGNAME="dlmb_M_AddrStrobe"/>
|
|
<PORT DEF_SIGNAME="dlmb_M_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="M_DBus" RIGHT="31" SIGNAME="dlmb_M_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_M_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="8" MSB="0" NAME="M_BE" RIGHT="3" SIGNAME="dlmb_M_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_Sl_DBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="9" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:(C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_Sl_Ready" DIR="I" MPD_INDEX="10" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_Sl_Wait" DIR="I" MPD_INDEX="11" NAME="Sl_Wait" SIGNAME="dlmb_Sl_Wait" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_Sl_UE" DIR="I" MPD_INDEX="12" NAME="Sl_UE" SIGNAME="dlmb_Sl_UE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_Sl_CE" DIR="I" MPD_INDEX="13" NAME="Sl_CE" SIGNAME="dlmb_Sl_CE" VECFORMULA="[0:C_LMB_NUM_SLAVES-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="14" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="O" MPD_INDEX="15" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="O" MPD_INDEX="16" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="O" MPD_INDEX="17" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_ReadDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="LMB_ReadDBus" RIGHT="31" SIGNAME="dlmb_LMB_ReadDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_Ready" DIR="O" MPD_INDEX="20" NAME="LMB_Ready" SIGNAME="dlmb_LMB_Ready"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_Wait" DIR="O" MPD_INDEX="21" NAME="LMB_Wait" SIGNAME="dlmb_LMB_Wait"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_UE" DIR="O" MPD_INDEX="22" NAME="LMB_UE" SIGNAME="dlmb_LMB_UE"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_CE" DIR="O" MPD_INDEX="23" NAME="LMB_CE" SIGNAME="dlmb_LMB_CE"/>
|
|
<PORT DEF_SIGNAME="dlmb_LMB_BE" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="24" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:(C_LMB_DWIDTH+7)/8-1]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES/>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
|
|
</IOINTERFACES>
|
|
</MODULE>
|
|
<MODULE HWVERSION="3.00.b" INSTANCE="LocalMemory_Cntlr_D" IPTYPE="PERIPHERAL" MHS_INDEX="4" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
|
|
<DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x0000FFFF">
|
|
<DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0xc0000000">
|
|
<DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Error Correction Code </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Select Interconnect </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Fault Inject Registers </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>ECC On/Off Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
|
|
<DESCRIPTION>Write Access setting </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Number of PLB Masters</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="sys_clk_s" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="dlmb_LMB_Rst"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="dlmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="dlmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="dlmb_LMB_AddrStrobe"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="dlmb_LMB_ReadStrobe"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="dlmb_LMB_WriteStrobe"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="dlmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="dlmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="dlmb_Sl_Ready"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="dlmb_Sl_Wait"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="dlmb_Sl_UE"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="dlmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="dlmb_Sl_CE"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="dlmb_port_BRAM_Rst"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="dlmb_port_BRAM_Clk"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="dlmb_port_BRAM_EN"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
|
|
<PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="dlmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="65535" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0000FFFF" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="SLMB"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="SPLB_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="3.00.b" INSTANCE="LocalMemory_Cntlr_I" IPTYPE="PERIPHERAL" MHS_INDEX="5" MODCLASS="MEMORY_CNTLR" MODTYPE="lmb_bram_if_cntlr">
|
|
<DESCRIPTION TYPE="SHORT">LMB BRAM Controller</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/lmb_bram_if_cntlr_v3_00_b/doc/lmb_bram_if_cntlr.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="2" MPD_INDEX="0" MSB="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>LMB BRAM Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LSB="31" MHS_INDEX="3" MPD_INDEX="1" MSB="0" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x0000FFFF">
|
|
<DESCRIPTION>LMB BRAM High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_FAMILY" TYPE="string" VALUE="spartan6"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" ENDIAN="BIG" LSB="31" MPD_INDEX="3" MSB="0" NAME="C_MASK" TYPE="std_logic_vector" VALUE="0xc0000000">
|
|
<DESCRIPTION>LMB Address Decode Mask</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_LMB_AWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Address Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_LMB_DWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>LMB Data Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_ECC" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Error Correction Code </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_INTERCONNECT" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Select Interconnect </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_FAULT_INJECT" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Fault Inject Registers </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_CE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Correctable Error First Failing Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_UE_FAILING_REGISTERS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Uncorrectable Error First Failing Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_ECC_STATUS_REGISTERS" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>ECC Status and Control Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_ECC_ONOFF_REGISTER" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>ECC On/Off Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="13" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>ECC On/Off Reset Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_CE_COUNTER_WIDTH" TYPE="integer" VALUE="0">
|
|
<DESCRIPTION>Correctable Error Counter Register Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_WRITE_ACCESS" TYPE="integer" VALUE="2">
|
|
<DESCRIPTION>Write Access setting </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="16" NAME="C_SPLB_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>Base Address for PLB Interface</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="17" NAME="C_SPLB_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>High Address for PLB Interface</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_SPLB_CTRL_AWIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>PLB Address Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="19" NAME="C_SPLB_CTRL_DWIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>PLB Data Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_SPLB_CTRL_P2P" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>PLB Slave Uses P2P Topology</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="21" NAME="C_SPLB_CTRL_MID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Master ID Bus Width of PLB</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_SPLB_CTRL_NUM_MASTERS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Number of PLB Masters</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_SPLB_CTRL_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>PLB Slave is Capable of Bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_SPLB_CTRL_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Native Data Bus Width of PLB Slave</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_SPLB_CTRL_CLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>Frequency of PLB Slave</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="26" NAME="C_S_AXI_CTRL_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>S_AXI_CTRL Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="27" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>S_AXI_CTRL Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="28" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>S_AXI_CTRL High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>S_AXI_CTRL Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>S_AXI_CTRL Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>S_AXI_CTRL Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="SLMB" CLKFREQUENCY="100000000" DEF_SIGNAME="sys_clk_s" DIR="I" MPD_INDEX="0" NAME="LMB_Clk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_Rst" DIR="I" MPD_INDEX="1" NAME="LMB_Rst" SIGIS="RST" SIGNAME="ilmb_LMB_Rst"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="LMB_ABus" RIGHT="31" SIGNAME="ilmb_LMB_ABus" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="LMB_WriteDBus" RIGHT="31" SIGNAME="ilmb_LMB_WriteDBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_AddrStrobe" DIR="I" MPD_INDEX="4" NAME="LMB_AddrStrobe" SIGNAME="ilmb_LMB_AddrStrobe"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_ReadStrobe" DIR="I" MPD_INDEX="5" NAME="LMB_ReadStrobe" SIGNAME="ilmb_LMB_ReadStrobe"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_WriteStrobe" DIR="I" MPD_INDEX="6" NAME="LMB_WriteStrobe" SIGNAME="ilmb_LMB_WriteStrobe"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_LMB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="7" MSB="0" NAME="LMB_BE" RIGHT="3" SIGNAME="ilmb_LMB_BE" VECFORMULA="[0:C_LMB_DWIDTH/8-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_DBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="8" MSB="0" NAME="Sl_DBus" RIGHT="31" SIGNAME="ilmb_Sl_DBus" VECFORMULA="[0:C_LMB_DWIDTH-1]"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Ready" DIR="O" MPD_INDEX="9" NAME="Sl_Ready" SIGNAME="ilmb_Sl_Ready"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_Wait" DIR="O" MPD_INDEX="10" NAME="Sl_Wait" SIGNAME="ilmb_Sl_Wait"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_UE" DIR="O" MPD_INDEX="11" NAME="Sl_UE" SIGNAME="ilmb_Sl_UE"/>
|
|
<PORT BUS="SLMB" DEF_SIGNAME="ilmb_Sl_CE" DIR="O" MPD_INDEX="12" NAME="Sl_CE" SIGNAME="ilmb_Sl_CE"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="O" MPD_INDEX="13" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="O" MPD_INDEX="14" NAME="BRAM_Clk_A" SIGNAME="ilmb_port_BRAM_Clk"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="O" MPD_INDEX="15" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:((C_LMB_DWIDTH+8*C_ECC)/8)-1]"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_LMB_AWIDTH-1]"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="18" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
|
|
<PORT BUS="BRAM_PORT" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="19" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_LMB_DWIDTH-1+8*C_ECC]"/>
|
|
<PORT DIR="O" MPD_INDEX="20" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="SPLB_CTRL_PLB_ABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="22" NAME="SPLB_CTRL_PLB_PAValid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="23" NAME="SPLB_CTRL_PLB_masterID" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_MID_WIDTH-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="24" NAME="SPLB_CTRL_PLB_RNW" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="25" MSB="0" NAME="SPLB_CTRL_PLB_BE" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:((C_SPLB_CTRL_DWIDTH/8)-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="26" MSB="0" NAME="SPLB_CTRL_PLB_size" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="27" MSB="0" NAME="SPLB_CTRL_PLB_type" RIGHT="2" SIGNAME="__NOC__" VECFORMULA="[0:2]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="28" MSB="0" NAME="SPLB_CTRL_PLB_wrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="29" NAME="SPLB_CTRL_Sl_addrAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="30" MSB="0" NAME="SPLB_CTRL_Sl_SSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="31" NAME="SPLB_CTRL_Sl_wait" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="32" NAME="SPLB_CTRL_Sl_rearbitrate" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="33" NAME="SPLB_CTRL_Sl_wrDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="34" NAME="SPLB_CTRL_Sl_wrComp" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="35" MSB="0" NAME="SPLB_CTRL_Sl_rdDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_DWIDTH-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="36" NAME="SPLB_CTRL_Sl_rdDAck" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="37" NAME="SPLB_CTRL_Sl_rdComp" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="38" NAME="SPLB_CTRL_Sl_MBusy" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="39" NAME="SPLB_CTRL_Sl_MWrErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="40" NAME="SPLB_CTRL_Sl_MRdErr" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="41" MSB="0" NAME="SPLB_CTRL_PLB_UABus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:31]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="42" NAME="SPLB_CTRL_PLB_SAValid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="43" NAME="SPLB_CTRL_PLB_rdPrim" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="44" NAME="SPLB_CTRL_PLB_wrPrim" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="45" NAME="SPLB_CTRL_PLB_abort" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="46" NAME="SPLB_CTRL_PLB_busLock" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="47" MSB="0" NAME="SPLB_CTRL_PLB_MSize" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="48" NAME="SPLB_CTRL_PLB_lockErr" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="49" NAME="SPLB_CTRL_PLB_wrBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="50" NAME="SPLB_CTRL_PLB_rdBurst" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="51" NAME="SPLB_CTRL_PLB_wrPendReq" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="52" NAME="SPLB_CTRL_PLB_rdPendReq" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="53" MSB="0" NAME="SPLB_CTRL_PLB_wrPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="54" MSB="0" NAME="SPLB_CTRL_PLB_rdPendPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="55" MSB="0" NAME="SPLB_CTRL_PLB_reqPri" RIGHT="1" SIGNAME="__NOC__" VECFORMULA="[0:1]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="56" MSB="0" NAME="SPLB_CTRL_PLB_TAttribute" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:15]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="57" NAME="SPLB_CTRL_Sl_wrBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="58" MSB="0" NAME="SPLB_CTRL_Sl_rdWdAddr" RIGHT="3" SIGNAME="__NOC__" VECFORMULA="[0:3]"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="59" NAME="SPLB_CTRL_Sl_rdBTerm" SIGNAME="__NOC__"/>
|
|
<PORT BUS="SPLB_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="60" NAME="SPLB_CTRL_Sl_MIRQ" SIGNAME="__NOC__" VECFORMULA="[0:(C_SPLB_CTRL_NUM_MASTERS-1)]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="61" NAME="S_AXI_CTRL_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="62" NAME="S_AXI_CTRL_ARESETN" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="64" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="65" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="67" MSB="3" NAME="S_AXI_CTRL_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_CTRL_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="68" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="69" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="71" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="72" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="73" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="74" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="75" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="76" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="78" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="79" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="ilmb" BUSSTD="LMB" BUSSTD_PSF="LMB" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SLMB" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_Clk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_Rst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_ABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_WriteDBus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_AddrStrobe"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_ReadStrobe"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_WriteStrobe"/>
|
|
<PORTMAP DIR="I" PHYSICAL="LMB_BE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_DBus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_Ready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_Wait"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_UE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sl_CE"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="BRAM_PORT" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_EN_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_WEN_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Din_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Dout_A"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_VALID="FALSE" MPD_INDEX="2" NAME="SPLB_CTRL" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_ABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_PAValid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_masterID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_RNW"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_BE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_size"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_type"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrDBus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_addrAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_SSize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wait"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rearbitrate"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrDAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrComp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDBus"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdDAck"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdComp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MBusy"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MWrErr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MRdErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_UABus"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_SAValid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPrim"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPrim"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_abort"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_busLock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_MSize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_lockErr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrBurst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdBurst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendReq"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendReq"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_wrPendPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_rdPendPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_reqPri"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SPLB_CTRL_PLB_TAttribute"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_wrBTerm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdWdAddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_rdBTerm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SPLB_CTRL_Sl_MIRQ"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="0" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHDECIMAL="65535" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x0000FFFF" MEMTYPE="MEMORY" MINSIZE="0x800" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="SLMB"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_SPLB_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_SPLB_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="SPLB_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" MINSIZE="0x100" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.00.a" INSTANCE="lmb_bram" IPTYPE="PERIPHERAL" MHS_INDEX="6" MODCLASS="MEMORY" MODTYPE="bram_block">
|
|
<DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x10000">
|
|
<DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
|
|
<DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="ilmb_port_BRAM_Rst"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="ilmb_port_BRAM_Clk"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="ilmb_port_BRAM_EN"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="ilmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="ilmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="ilmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="dlmb_port_BRAM_Rst"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="dlmb_port_BRAM_Clk"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="dlmb_port_BRAM_EN"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="dlmb_port_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="dlmb_port_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="dlmb_port_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="ilmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="dlmb_port" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.03.a" INSTANCE="DDR3_SDRAM" IPTYPE="PERIPHERAL" MHS_INDEX="7" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_s6_ddrx">
|
|
<DESCRIPTION TYPE="SHORT">AXI S6 Memory Controller(DDR/DDR2/DDR3)</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Spartan-6 memory controller</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_s6_ddrx_v1_03_a/doc/axi_s6_ddrx.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER MPD_INDEX="0" NAME="C_MCB_LOC" VALUE="MEMC3"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="C_MCB_RZQ_LOC" TYPE="STRING" VALUE="K7"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_MCB_ZIO_LOC" TYPE="STRING" VALUE="M7"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_MCB_PERFORMANCE" TYPE="STRING" VALUE="STANDARD"/>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_BYPASS_CORE_UCF" VALUE="0"/>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="5" NAME="C_S0_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x40000000"/>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="6" NAME="C_S0_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x47FFFFFF"/>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="7" NAME="C_S1_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x40000000"/>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="8" NAME="C_S1_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x47FFFFFF"/>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="9" NAME="C_S2_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x40000000"/>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="10" NAME="C_S2_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x47FFFFFF"/>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="11" NAME="C_S3_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="12" NAME="C_S3_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="13" NAME="C_S4_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="14" NAME="C_S4_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="15" NAME="C_S5_AXI_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF"/>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="16" NAME="C_S5_AXI_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000"/>
|
|
<PARAMETER MPD_INDEX="17" NAME="C_MEM_TYPE" TYPE="STRING" VALUE="DDR3"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="18" NAME="C_MEM_PARTNO" TYPE="STRING" VALUE="MT41J64M16XX-187E"/>
|
|
<PARAMETER MPD_INDEX="19" NAME="C_MEM_BASEPARTNO" TYPE="STRING" VALUE="NOT_SET"/>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_NUM_DQ_PINS" TYPE="INTEGER" VALUE="16"/>
|
|
<PARAMETER MPD_INDEX="21" NAME="C_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="13"/>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_MEM_BANKADDR_WIDTH" TYPE="INTEGER" VALUE="3"/>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_MEM_NUM_COL_BITS" TYPE="INTEGER" VALUE="10"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="24" NAME="C_MEM_TRAS" TYPE="INTEGER" VALUE="37500"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="25" NAME="C_MEM_TRCD" TYPE="INTEGER" VALUE="13130"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="26" NAME="C_MEM_TREFI" TYPE="INTEGER" VALUE="7800000"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_MEM_TRFC" TYPE="INTEGER" VALUE="160000"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_MEM_TRP" TYPE="INTEGER" VALUE="13130"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="29" NAME="C_MEM_TWR" TYPE="INTEGER" VALUE="15000"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="30" NAME="C_MEM_TRTP" TYPE="INTEGER" VALUE="7500"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="31" NAME="C_MEM_TWTR" TYPE="INTEGER" VALUE="7500"/>
|
|
<PARAMETER MPD_INDEX="32" NAME="C_PORT_CONFIG" TYPE="STRING" VALUE="B32_B32_B32_B32"/>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_SKIP_IN_TERM_CAL" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_SKIP_IN_TERM_CAL_VALUE" TYPE="STRING" VALUE="NONE"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_MEMCLK_PERIOD" TYPE="INTEGER" VALUE="2999"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="36" NAME="C_MEM_ADDR_ORDER" TYPE="STRING" VALUE="BANK_ROW_COLUMN"/>
|
|
<PARAMETER MPD_INDEX="37" NAME="C_MEM_TZQINIT_MAXCNT" TYPE="INTEGER" VALUE="512"/>
|
|
<PARAMETER MPD_INDEX="38" NAME="C_MEM_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_SIMULATION" TYPE="STRING" VALUE="TRUE"/>
|
|
<PARAMETER MPD_INDEX="40" NAME="C_MEM_DDR1_2_ODS" TYPE="STRING" VALUE="FULL"/>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_MEM_DDR1_2_ADDR_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_MEM_DDR1_2_DATA_CONTROL_SSTL_ODS" TYPE="STRING" VALUE="CLASS_II"/>
|
|
<PARAMETER MPD_INDEX="43" NAME="C_MEM_DDR2_RTT" TYPE="STRING" VALUE="150OHMS"/>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_MEM_DDR2_DIFF_DQS_EN" TYPE="STRING" VALUE="YES"/>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_MEM_DDR2_3_PA_SR" TYPE="STRING" VALUE="FULL"/>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_MEM_DDR2_3_HIGH_TEMP_SR" TYPE="STRING" VALUE="NORMAL"/>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_MEM_DDR3_CAS_WR_LATENCY" TYPE="INTEGER" VALUE="5"/>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_MEM_DDR3_CAS_LATENCY" TYPE="INTEGER" VALUE="6"/>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_MEM_DDR3_ODS" TYPE="STRING" VALUE="DIV6"/>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_MEM_DDR3_RTT" TYPE="STRING" VALUE="DIV4"/>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_MEM_DDR3_AUTO_SR" TYPE="STRING" VALUE="ENABLED"/>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_MEM_MOBILE_PA_SR" TYPE="STRING" VALUE="FULL"/>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_MEM_MDDR_ODS" TYPE="STRING" VALUE="FULL"/>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_ARB_ALGORITHM" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="55" NAME="C_ARB_NUM_TIME_SLOTS" TYPE="INTEGER" VALUE="12"/>
|
|
<PARAMETER MPD_INDEX="56" NAME="C_ARB_TIME_SLOT_0" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_ARB_TIME_SLOT_1" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
|
|
<PARAMETER MPD_INDEX="58" NAME="C_ARB_TIME_SLOT_2" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_ARB_TIME_SLOT_3" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_ARB_TIME_SLOT_4" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
|
|
<PARAMETER MPD_INDEX="61" NAME="C_ARB_TIME_SLOT_5" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
|
|
<PARAMETER MPD_INDEX="62" NAME="C_ARB_TIME_SLOT_6" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_ARB_TIME_SLOT_7" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_ARB_TIME_SLOT_8" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000000001010011"/>
|
|
<PARAMETER MPD_INDEX="65" NAME="C_ARB_TIME_SLOT_9" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000001010011000"/>
|
|
<PARAMETER MPD_INDEX="66" NAME="C_ARB_TIME_SLOT_10" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000010011000001"/>
|
|
<PARAMETER MPD_INDEX="67" NAME="C_ARB_TIME_SLOT_11" TYPE="STD_LOGIC_VECTOR" VALUE="0b000000011000001010"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="68" NAME="C_S0_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="69" NAME="C_S0_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="70" NAME="C_S0_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="71" NAME="C_S0_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="72" NAME="C_S0_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="73" NAME="C_S0_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="74" NAME="C_S0_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="25" MPD_INDEX="75" NAME="C_S0_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="76" NAME="C_S0_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
|
|
<PARAMETER MPD_INDEX="77" NAME="C_S0_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
|
|
<PARAMETER MPD_INDEX="78" NAME="C_S0_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="79" NAME="C_S0_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="80" NAME="C_INTERCONNECT_S0_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="81" NAME="C_INTERCONNECT_S0_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="82" NAME="C_S1_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="83" NAME="C_S1_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="84" NAME="C_S1_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="85" NAME="C_S1_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="86" NAME="C_S1_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="87" NAME="C_S1_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="88" NAME="C_S1_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="89" NAME="C_S1_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="90" NAME="C_S1_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
|
|
<PARAMETER MPD_INDEX="91" NAME="C_S1_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
|
|
<PARAMETER MPD_INDEX="92" NAME="C_S1_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="93" NAME="C_S1_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="94" NAME="C_INTERCONNECT_S1_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="95" NAME="C_INTERCONNECT_S1_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="96" NAME="C_S2_AXI_ENABLE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="97" NAME="C_S2_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="98" NAME="C_S2_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="99" NAME="C_S2_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="100" NAME="C_S2_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="101" NAME="C_S2_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="102" NAME="C_S2_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="103" NAME="C_S2_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="104" NAME="C_S2_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000"/>
|
|
<PARAMETER MPD_INDEX="105" NAME="C_S2_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
|
|
<PARAMETER MPD_INDEX="106" NAME="C_S2_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="107" NAME="C_S2_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="108" NAME="C_INTERCONNECT_S2_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="109" NAME="C_INTERCONNECT_S2_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="110" NAME="C_S3_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="111" NAME="C_S3_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
|
|
<PARAMETER MPD_INDEX="112" NAME="C_S3_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="113" NAME="C_S3_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="114" NAME="C_S3_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="115" NAME="C_S3_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="116" NAME="C_S3_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="117" NAME="C_S3_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="118" NAME="C_S3_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
|
|
<PARAMETER MPD_INDEX="119" NAME="C_S3_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
|
|
<PARAMETER MPD_INDEX="120" NAME="C_S3_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="121" NAME="C_S3_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="122" NAME="C_INTERCONNECT_S3_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="123" NAME="C_INTERCONNECT_S3_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="124" NAME="C_S4_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="125" NAME="C_S4_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
|
|
<PARAMETER MPD_INDEX="126" NAME="C_S4_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="127" NAME="C_S4_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="128" NAME="C_S4_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="129" NAME="C_S4_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="130" NAME="C_S4_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="131" NAME="C_S4_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="132" NAME="C_S4_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
|
|
<PARAMETER MPD_INDEX="133" NAME="C_S4_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
|
|
<PARAMETER MPD_INDEX="134" NAME="C_S4_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="135" NAME="C_S4_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="136" NAME="C_INTERCONNECT_S4_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="137" NAME="C_INTERCONNECT_S4_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="138" NAME="C_S5_AXI_ENABLE" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="139" NAME="C_S5_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4"/>
|
|
<PARAMETER MPD_INDEX="140" NAME="C_S5_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="141" NAME="C_S5_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER MPD_INDEX="142" NAME="C_S5_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="143" NAME="C_S5_AXI_SUPPORTS_READ" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="144" NAME="C_S5_AXI_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="145" NAME="C_S5_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="146" NAME="C_S5_AXI_REG_EN0" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000F"/>
|
|
<PARAMETER MPD_INDEX="147" NAME="C_S5_AXI_REG_EN1" TYPE="STD_LOGIC_VECTOR" VALUE="0x01000"/>
|
|
<PARAMETER MPD_INDEX="148" NAME="C_S5_AXI_STRICT_COHERENCY" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="149" NAME="C_S5_AXI_ENABLE_AP" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER MPD_INDEX="150" NAME="C_INTERCONNECT_S5_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="151" NAME="C_INTERCONNECT_S5_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="4"/>
|
|
<PARAMETER MPD_INDEX="152" NAME="C_MCB_USE_EXTERNAL_BUFPLL" TYPE="INTEGER" VALUE="0"/>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="153" NAME="C_SYS_RST_PRESENT" TYPE="INTEGER" VALUE="1"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="28" NAME="C_INTERCONNECT_S0_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="29" NAME="C_INTERCONNECT_S1_AXI_MASTERS" VALUE="AXI_DMA_Ethernet.M_AXI_SG"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="30" NAME="C_INTERCONNECT_S2_AXI_MASTERS" VALUE="AXI_DMA_Ethernet.M_AXI_MM2S & AXI_DMA_Ethernet.M_AXI_S2MM"/>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="10" NAME="sys_rst" SIGIS="RST" SIGNAME="sys_bus_reset"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="4" NAME="pll_lock" SIGNAME="Dcm_all_locked"/>
|
|
<PORT BUS="S0_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="32" NAME="s0_axi_aclk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="S1_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="71" NAME="s1_axi_aclk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="S2_AXI" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="110" NAME="s2_axi_aclk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT CLKFREQUENCY="83333333" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="30" NAME="ui_clk" SIGIS="CLK" SIGNAME="pll_module_0_CLKOUT2"/>
|
|
<PORT CLKFREQUENCY="666666667" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="0" NAME="sysclk_2x" SIGIS="CLK" SIGNAME="pll_module_0_CLKOUT0"/>
|
|
<PORT CLKFREQUENCY="666666667" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="1" NAME="sysclk_2x_180" SIGIS="CLK" SIGNAME="pll_module_0_CLKOUT1"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="12" LSB="0" MHS_INDEX="8" MPD_INDEX="11" MSB="12" NAME="mcbx_dram_addr" RIGHT="0" SIGNAME="mcbx_dram_addr" VECFORMULA="[C_MEM_ADDR_WIDTH-1:0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" LEFT="2" LSB="0" MHS_INDEX="9" MPD_INDEX="12" MSB="2" NAME="mcbx_dram_ba" RIGHT="0" SIGNAME="mcbx_dram_ba" VECFORMULA="[C_MEM_BANKADDR_WIDTH-1:0]"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="mcbx_dram_ras_n" SIGNAME="mcbx_dram_ras_n"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="14" NAME="mcbx_dram_cas_n" SIGNAME="mcbx_dram_cas_n"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="15" NAME="mcbx_dram_we_n" SIGNAME="mcbx_dram_we_n"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="16" NAME="mcbx_dram_cke" SIGNAME="mcbx_dram_cke"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="17" NAME="mcbx_dram_clk" SIGIS="CLK" SIGNAME="mcbx_dram_clk"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="18" NAME="mcbx_dram_clk_n" SIGIS="CLK" SIGNAME="mcbx_dram_clk_n"/>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" LEFT="15" LSB="0" MHS_INDEX="16" MPD_INDEX="19" MSB="15" NAME="mcbx_dram_dq" RIGHT="0" SIGNAME="mcbx_dram_dq" VECFORMULA="[C_NUM_DQ_PINS-1:0]"/>
|
|
<PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="17" MPD_INDEX="20" NAME="mcbx_dram_dqs" SIGNAME="mcbx_dram_dqs"/>
|
|
<PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="18" MPD_INDEX="22" NAME="mcbx_dram_udqs" SIGNAME="mcbx_dram_udqs"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="26" NAME="mcbx_dram_odt" SIGNAME="mcbx_dram_odt"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="25" NAME="mcbx_dram_ldm" SIGNAME="mcbx_dram_ldm"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="24" NAME="mcbx_dram_udm" SIGNAME="mcbx_dram_udm"/>
|
|
<PORT DIR="O" IOS="memory_0" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="27" NAME="mcbx_dram_ddr3_rst" SIGNAME="mcbx_dram_ddr3_rst"/>
|
|
<PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="23" MPD_INDEX="23" NAME="mcbx_dram_udqs_n" SIGNAME="mcbx_dram_udqs_n"/>
|
|
<PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="24" MPD_INDEX="21" NAME="mcbx_dram_dqs_n" SIGNAME="mcbx_dram_dqs_n"/>
|
|
<PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="25" MPD_INDEX="28" NAME="rzq" SIGNAME="mcbx_dram_rzq"/>
|
|
<PORT DIR="IO" IOS="memory_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="FALSE" MHS_INDEX="26" MPD_INDEX="29" NAME="zio" SIGNAME="mcbx_dram_zio"/>
|
|
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="2" NAME="pll_ce_0" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="pll_ce_90" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="5" NAME="pll_lock_bufpll_o" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="6" NAME="sysclk_2x_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="7" NAME="sysclk_2x_180_bufpll_o" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="8" NAME="pll_ce_0_bufpll_o" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="9" NAME="pll_ce_90_bufpll_o" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="31" NAME="uo_done_cal" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_aresetn" DIR="I" MPD_INDEX="33" NAME="s0_axi_aresetn" SIGIS="RST" SIGNAME="AXI_MM_M_aresetn"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awid" DIR="I" MPD_INDEX="34" NAME="s0_axi_awid" SIGNAME="AXI_MM_M_awid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="35" MSB="31" NAME="s0_axi_awaddr" RIGHT="0" SIGNAME="AXI_MM_M_awaddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="36" MSB="7" NAME="s0_axi_awlen" RIGHT="0" SIGNAME="AXI_MM_M_awlen" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="37" MSB="2" NAME="s0_axi_awsize" RIGHT="0" SIGNAME="AXI_MM_M_awsize" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="s0_axi_awburst" RIGHT="0" SIGNAME="AXI_MM_M_awburst" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awlock" DIR="I" MPD_INDEX="39" NAME="s0_axi_awlock" SIGNAME="AXI_MM_M_awlock" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="40" MSB="3" NAME="s0_axi_awcache" RIGHT="0" SIGNAME="AXI_MM_M_awcache" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="s0_axi_awprot" RIGHT="0" SIGNAME="AXI_MM_M_awprot" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="s0_axi_awqos" RIGHT="0" SIGNAME="AXI_MM_M_awqos" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awvalid" DIR="I" MPD_INDEX="43" NAME="s0_axi_awvalid" SIGNAME="AXI_MM_M_awvalid"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_awready" DIR="O" MPD_INDEX="44" NAME="s0_axi_awready" SIGNAME="AXI_MM_M_awready"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="s0_axi_wdata" RIGHT="0" SIGNAME="AXI_MM_M_wdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="s0_axi_wstrb" RIGHT="0" SIGNAME="AXI_MM_M_wstrb" VECFORMULA="[((C_S0_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_wlast" DIR="I" MPD_INDEX="47" NAME="s0_axi_wlast" SIGNAME="AXI_MM_M_wlast"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_wvalid" DIR="I" MPD_INDEX="48" NAME="s0_axi_wvalid" SIGNAME="AXI_MM_M_wvalid"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_wready" DIR="O" MPD_INDEX="49" NAME="s0_axi_wready" SIGNAME="AXI_MM_M_wready"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_bid" DIR="O" MPD_INDEX="50" NAME="s0_axi_bid" SIGNAME="AXI_MM_M_bid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="s0_axi_bresp" RIGHT="0" SIGNAME="AXI_MM_M_bresp" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_bvalid" DIR="O" MPD_INDEX="52" NAME="s0_axi_bvalid" SIGNAME="AXI_MM_M_bvalid"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_bready" DIR="I" MPD_INDEX="53" NAME="s0_axi_bready" SIGNAME="AXI_MM_M_bready"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arid" DIR="I" MPD_INDEX="54" NAME="s0_axi_arid" SIGNAME="AXI_MM_M_arid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="55" MSB="31" NAME="s0_axi_araddr" RIGHT="0" SIGNAME="AXI_MM_M_araddr" VECFORMULA="[(C_S0_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="56" MSB="7" NAME="s0_axi_arlen" RIGHT="0" SIGNAME="AXI_MM_M_arlen" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="57" MSB="2" NAME="s0_axi_arsize" RIGHT="0" SIGNAME="AXI_MM_M_arsize" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="58" MSB="1" NAME="s0_axi_arburst" RIGHT="0" SIGNAME="AXI_MM_M_arburst" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arlock" DIR="I" MPD_INDEX="59" NAME="s0_axi_arlock" SIGNAME="AXI_MM_M_arlock" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="60" MSB="3" NAME="s0_axi_arcache" RIGHT="0" SIGNAME="AXI_MM_M_arcache" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="s0_axi_arprot" RIGHT="0" SIGNAME="AXI_MM_M_arprot" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="62" MSB="3" NAME="s0_axi_arqos" RIGHT="0" SIGNAME="AXI_MM_M_arqos" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arvalid" DIR="I" MPD_INDEX="63" NAME="s0_axi_arvalid" SIGNAME="AXI_MM_M_arvalid"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_arready" DIR="O" MPD_INDEX="64" NAME="s0_axi_arready" SIGNAME="AXI_MM_M_arready"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_rid" DIR="O" MPD_INDEX="65" NAME="s0_axi_rid" SIGNAME="AXI_MM_M_rid" VECFORMULA="[(C_S0_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="s0_axi_rdata" RIGHT="0" SIGNAME="AXI_MM_M_rdata" VECFORMULA="[(C_S0_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="67" MSB="1" NAME="s0_axi_rresp" RIGHT="0" SIGNAME="AXI_MM_M_rresp" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_rlast" DIR="O" MPD_INDEX="68" NAME="s0_axi_rlast" SIGNAME="AXI_MM_M_rlast"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_rvalid" DIR="O" MPD_INDEX="69" NAME="s0_axi_rvalid" SIGNAME="AXI_MM_M_rvalid"/>
|
|
<PORT BUS="S0_AXI" DEF_SIGNAME="AXI_MM_M_rready" DIR="I" MPD_INDEX="70" NAME="s0_axi_rready" SIGNAME="AXI_MM_M_rready"/>
|
|
<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_aresetn" DIR="I" MPD_INDEX="72" NAME="s1_axi_aresetn" SIGIS="RST" SIGNAME="AXI_DMA_SG_M_aresetn"/>
|
|
<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awid" DIR="I" MPD_INDEX="73" NAME="s1_axi_awid" SIGNAME="AXI_DMA_SG_M_awid" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="74" MSB="31" NAME="s1_axi_awaddr" RIGHT="0" SIGNAME="AXI_DMA_SG_M_awaddr" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="75" MSB="7" NAME="s1_axi_awlen" RIGHT="0" SIGNAME="AXI_DMA_SG_M_awlen" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="76" MSB="2" NAME="s1_axi_awsize" RIGHT="0" SIGNAME="AXI_DMA_SG_M_awsize" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="77" MSB="1" NAME="s1_axi_awburst" RIGHT="0" SIGNAME="AXI_DMA_SG_M_awburst" VECFORMULA="[1:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awlock" DIR="I" MPD_INDEX="78" NAME="s1_axi_awlock" SIGNAME="AXI_DMA_SG_M_awlock" VECFORMULA="[0:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="79" MSB="3" NAME="s1_axi_awcache" RIGHT="0" SIGNAME="AXI_DMA_SG_M_awcache" VECFORMULA="[3:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="80" MSB="2" NAME="s1_axi_awprot" RIGHT="0" SIGNAME="AXI_DMA_SG_M_awprot" VECFORMULA="[2:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="81" MSB="3" NAME="s1_axi_awqos" RIGHT="0" SIGNAME="AXI_DMA_SG_M_awqos" VECFORMULA="[3:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awvalid" DIR="I" MPD_INDEX="82" NAME="s1_axi_awvalid" SIGNAME="AXI_DMA_SG_M_awvalid"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_awready" DIR="O" MPD_INDEX="83" NAME="s1_axi_awready" SIGNAME="AXI_DMA_SG_M_awready"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="84" MSB="31" NAME="s1_axi_wdata" RIGHT="0" SIGNAME="AXI_DMA_SG_M_wdata" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="85" MSB="3" NAME="s1_axi_wstrb" RIGHT="0" SIGNAME="AXI_DMA_SG_M_wstrb" VECFORMULA="[((C_S1_AXI_DATA_WIDTH/8)-1):0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_wlast" DIR="I" MPD_INDEX="86" NAME="s1_axi_wlast" SIGNAME="AXI_DMA_SG_M_wlast"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_wvalid" DIR="I" MPD_INDEX="87" NAME="s1_axi_wvalid" SIGNAME="AXI_DMA_SG_M_wvalid"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_wready" DIR="O" MPD_INDEX="88" NAME="s1_axi_wready" SIGNAME="AXI_DMA_SG_M_wready"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_bid" DIR="O" MPD_INDEX="89" NAME="s1_axi_bid" SIGNAME="AXI_DMA_SG_M_bid" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="90" MSB="1" NAME="s1_axi_bresp" RIGHT="0" SIGNAME="AXI_DMA_SG_M_bresp" VECFORMULA="[1:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_bvalid" DIR="O" MPD_INDEX="91" NAME="s1_axi_bvalid" SIGNAME="AXI_DMA_SG_M_bvalid"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_bready" DIR="I" MPD_INDEX="92" NAME="s1_axi_bready" SIGNAME="AXI_DMA_SG_M_bready"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arid" DIR="I" MPD_INDEX="93" NAME="s1_axi_arid" SIGNAME="AXI_DMA_SG_M_arid" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="s1_axi_araddr" RIGHT="0" SIGNAME="AXI_DMA_SG_M_araddr" VECFORMULA="[(C_S1_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="95" MSB="7" NAME="s1_axi_arlen" RIGHT="0" SIGNAME="AXI_DMA_SG_M_arlen" VECFORMULA="[7:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="96" MSB="2" NAME="s1_axi_arsize" RIGHT="0" SIGNAME="AXI_DMA_SG_M_arsize" VECFORMULA="[2:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="97" MSB="1" NAME="s1_axi_arburst" RIGHT="0" SIGNAME="AXI_DMA_SG_M_arburst" VECFORMULA="[1:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arlock" DIR="I" MPD_INDEX="98" NAME="s1_axi_arlock" SIGNAME="AXI_DMA_SG_M_arlock" VECFORMULA="[0:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s1_axi_arcache" RIGHT="0" SIGNAME="AXI_DMA_SG_M_arcache" VECFORMULA="[3:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="100" MSB="2" NAME="s1_axi_arprot" RIGHT="0" SIGNAME="AXI_DMA_SG_M_arprot" VECFORMULA="[2:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="101" MSB="3" NAME="s1_axi_arqos" RIGHT="0" SIGNAME="AXI_DMA_SG_M_arqos" VECFORMULA="[3:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arvalid" DIR="I" MPD_INDEX="102" NAME="s1_axi_arvalid" SIGNAME="AXI_DMA_SG_M_arvalid"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_arready" DIR="O" MPD_INDEX="103" NAME="s1_axi_arready" SIGNAME="AXI_DMA_SG_M_arready"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_rid" DIR="O" MPD_INDEX="104" NAME="s1_axi_rid" SIGNAME="AXI_DMA_SG_M_rid" VECFORMULA="[(C_S1_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="105" MSB="31" NAME="s1_axi_rdata" RIGHT="0" SIGNAME="AXI_DMA_SG_M_rdata" VECFORMULA="[(C_S1_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="106" MSB="1" NAME="s1_axi_rresp" RIGHT="0" SIGNAME="AXI_DMA_SG_M_rresp" VECFORMULA="[1:0]"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_rlast" DIR="O" MPD_INDEX="107" NAME="s1_axi_rlast" SIGNAME="AXI_DMA_SG_M_rlast"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_rvalid" DIR="O" MPD_INDEX="108" NAME="s1_axi_rvalid" SIGNAME="AXI_DMA_SG_M_rvalid"/>
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<PORT BUS="S1_AXI" DEF_SIGNAME="AXI_DMA_SG_M_rready" DIR="I" MPD_INDEX="109" NAME="s1_axi_rready" SIGNAME="AXI_DMA_SG_M_rready"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_aresetn" DIR="I" MPD_INDEX="111" NAME="s2_axi_aresetn" SIGIS="RST" SIGNAME="AXI_DMA_MM_M_aresetn"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awid" DIR="I" MPD_INDEX="112" NAME="s2_axi_awid" SIGNAME="AXI_DMA_MM_M_awid" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awaddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="113" MSB="31" NAME="s2_axi_awaddr" RIGHT="0" SIGNAME="AXI_DMA_MM_M_awaddr" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="s2_axi_awlen" RIGHT="0" SIGNAME="AXI_DMA_MM_M_awlen" VECFORMULA="[7:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="115" MSB="2" NAME="s2_axi_awsize" RIGHT="0" SIGNAME="AXI_DMA_MM_M_awsize" VECFORMULA="[2:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="116" MSB="1" NAME="s2_axi_awburst" RIGHT="0" SIGNAME="AXI_DMA_MM_M_awburst" VECFORMULA="[1:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awlock" DIR="I" MPD_INDEX="117" NAME="s2_axi_awlock" SIGNAME="AXI_DMA_MM_M_awlock" VECFORMULA="[0:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="118" MSB="3" NAME="s2_axi_awcache" RIGHT="0" SIGNAME="AXI_DMA_MM_M_awcache" VECFORMULA="[3:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="119" MSB="2" NAME="s2_axi_awprot" RIGHT="0" SIGNAME="AXI_DMA_MM_M_awprot" VECFORMULA="[2:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="120" MSB="3" NAME="s2_axi_awqos" RIGHT="0" SIGNAME="AXI_DMA_MM_M_awqos" VECFORMULA="[3:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awvalid" DIR="I" MPD_INDEX="121" NAME="s2_axi_awvalid" SIGNAME="AXI_DMA_MM_M_awvalid"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_awready" DIR="O" MPD_INDEX="122" NAME="s2_axi_awready" SIGNAME="AXI_DMA_MM_M_awready"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_wdata" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="123" MSB="31" NAME="s2_axi_wdata" RIGHT="0" SIGNAME="AXI_DMA_MM_M_wdata" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_wstrb" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="124" MSB="3" NAME="s2_axi_wstrb" RIGHT="0" SIGNAME="AXI_DMA_MM_M_wstrb" VECFORMULA="[((C_S2_AXI_DATA_WIDTH/8)-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_wlast" DIR="I" MPD_INDEX="125" NAME="s2_axi_wlast" SIGNAME="AXI_DMA_MM_M_wlast"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_wvalid" DIR="I" MPD_INDEX="126" NAME="s2_axi_wvalid" SIGNAME="AXI_DMA_MM_M_wvalid"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_wready" DIR="O" MPD_INDEX="127" NAME="s2_axi_wready" SIGNAME="AXI_DMA_MM_M_wready"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_bid" DIR="O" MPD_INDEX="128" NAME="s2_axi_bid" SIGNAME="AXI_DMA_MM_M_bid" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_bresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="129" MSB="1" NAME="s2_axi_bresp" RIGHT="0" SIGNAME="AXI_DMA_MM_M_bresp" VECFORMULA="[1:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_bvalid" DIR="O" MPD_INDEX="130" NAME="s2_axi_bvalid" SIGNAME="AXI_DMA_MM_M_bvalid"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_bready" DIR="I" MPD_INDEX="131" NAME="s2_axi_bready" SIGNAME="AXI_DMA_MM_M_bready"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arid" DIR="I" MPD_INDEX="132" NAME="s2_axi_arid" SIGNAME="AXI_DMA_MM_M_arid" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_araddr" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="133" MSB="31" NAME="s2_axi_araddr" RIGHT="0" SIGNAME="AXI_DMA_MM_M_araddr" VECFORMULA="[(C_S2_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arlen" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="s2_axi_arlen" RIGHT="0" SIGNAME="AXI_DMA_MM_M_arlen" VECFORMULA="[7:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arsize" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="135" MSB="2" NAME="s2_axi_arsize" RIGHT="0" SIGNAME="AXI_DMA_MM_M_arsize" VECFORMULA="[2:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arburst" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="136" MSB="1" NAME="s2_axi_arburst" RIGHT="0" SIGNAME="AXI_DMA_MM_M_arburst" VECFORMULA="[1:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arlock" DIR="I" MPD_INDEX="137" NAME="s2_axi_arlock" SIGNAME="AXI_DMA_MM_M_arlock" VECFORMULA="[0:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arcache" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="138" MSB="3" NAME="s2_axi_arcache" RIGHT="0" SIGNAME="AXI_DMA_MM_M_arcache" VECFORMULA="[3:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arprot" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="139" MSB="2" NAME="s2_axi_arprot" RIGHT="0" SIGNAME="AXI_DMA_MM_M_arprot" VECFORMULA="[2:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arqos" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="140" MSB="3" NAME="s2_axi_arqos" RIGHT="0" SIGNAME="AXI_DMA_MM_M_arqos" VECFORMULA="[3:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arvalid" DIR="I" MPD_INDEX="141" NAME="s2_axi_arvalid" SIGNAME="AXI_DMA_MM_M_arvalid"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_arready" DIR="O" MPD_INDEX="142" NAME="s2_axi_arready" SIGNAME="AXI_DMA_MM_M_arready"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_rid" DIR="O" MPD_INDEX="143" NAME="s2_axi_rid" SIGNAME="AXI_DMA_MM_M_rid" VECFORMULA="[(C_S2_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_rdata" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="144" MSB="31" NAME="s2_axi_rdata" RIGHT="0" SIGNAME="AXI_DMA_MM_M_rdata" VECFORMULA="[(C_S2_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_rresp" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="145" MSB="1" NAME="s2_axi_rresp" RIGHT="0" SIGNAME="AXI_DMA_MM_M_rresp" VECFORMULA="[1:0]"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_rlast" DIR="O" MPD_INDEX="146" NAME="s2_axi_rlast" SIGNAME="AXI_DMA_MM_M_rlast"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_rvalid" DIR="O" MPD_INDEX="147" NAME="s2_axi_rvalid" SIGNAME="AXI_DMA_MM_M_rvalid"/>
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<PORT BUS="S2_AXI" DEF_SIGNAME="AXI_DMA_MM_M_rready" DIR="I" MPD_INDEX="148" NAME="s2_axi_rready" SIGNAME="AXI_DMA_MM_M_rready"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="149" NAME="s3_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="150" NAME="s3_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="151" MSB="3" NAME="s3_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="152" MSB="31" NAME="s3_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="153" MSB="7" NAME="s3_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
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|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="154" MSB="2" NAME="s3_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
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|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="155" MSB="1" NAME="s3_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="156" NAME="s3_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="157" MSB="3" NAME="s3_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="158" MSB="2" NAME="s3_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
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|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="159" MSB="3" NAME="s3_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
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|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="160" NAME="s3_axi_awvalid" SIGNAME="__NOC__"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="161" NAME="s3_axi_awready" SIGNAME="__NOC__"/>
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|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="162" MSB="31" NAME="s3_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="163" MSB="3" NAME="s3_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S3_AXI_DATA_WIDTH/8)-1):0]"/>
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|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="164" NAME="s3_axi_wlast" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="165" NAME="s3_axi_wvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="166" NAME="s3_axi_wready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="167" MSB="3" NAME="s3_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="168" MSB="1" NAME="s3_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="169" NAME="s3_axi_bvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="170" NAME="s3_axi_bready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="171" MSB="3" NAME="s3_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="s3_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="173" MSB="7" NAME="s3_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="174" MSB="2" NAME="s3_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="175" MSB="1" NAME="s3_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="176" NAME="s3_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="177" MSB="3" NAME="s3_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="178" MSB="2" NAME="s3_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="179" MSB="3" NAME="s3_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="180" NAME="s3_axi_arvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="181" NAME="s3_axi_arready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="182" MSB="3" NAME="s3_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="s3_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S3_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="184" MSB="1" NAME="s3_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="185" NAME="s3_axi_rlast" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="186" NAME="s3_axi_rvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S3_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="187" NAME="s3_axi_rready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="188" NAME="s4_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="189" NAME="s4_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="190" MSB="3" NAME="s4_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="191" MSB="31" NAME="s4_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="192" MSB="7" NAME="s4_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="193" MSB="2" NAME="s4_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="194" MSB="1" NAME="s4_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="195" NAME="s4_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="196" MSB="3" NAME="s4_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="197" MSB="2" NAME="s4_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="198" MSB="3" NAME="s4_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="199" NAME="s4_axi_awvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="200" NAME="s4_axi_awready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="s4_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="202" MSB="3" NAME="s4_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S4_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="203" NAME="s4_axi_wlast" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="204" NAME="s4_axi_wvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="205" NAME="s4_axi_wready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="206" MSB="3" NAME="s4_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="207" MSB="1" NAME="s4_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="208" NAME="s4_axi_bvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="209" NAME="s4_axi_bready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="210" MSB="3" NAME="s4_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="211" MSB="31" NAME="s4_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="212" MSB="7" NAME="s4_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="213" MSB="2" NAME="s4_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="214" MSB="1" NAME="s4_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="215" NAME="s4_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="216" MSB="3" NAME="s4_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="217" MSB="2" NAME="s4_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="218" MSB="3" NAME="s4_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="219" NAME="s4_axi_arvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="220" NAME="s4_axi_arready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="221" MSB="3" NAME="s4_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="222" MSB="31" NAME="s4_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S4_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="223" MSB="1" NAME="s4_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="224" NAME="s4_axi_rlast" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="225" NAME="s4_axi_rvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S4_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="226" NAME="s4_axi_rready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="227" NAME="s5_axi_aclk" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="228" NAME="s5_axi_aresetn" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="229" MSB="3" NAME="s5_axi_awid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="230" MSB="31" NAME="s5_axi_awaddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="231" MSB="7" NAME="s5_axi_awlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="232" MSB="2" NAME="s5_axi_awsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="233" MSB="1" NAME="s5_axi_awburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="234" NAME="s5_axi_awlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="235" MSB="3" NAME="s5_axi_awcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="236" MSB="2" NAME="s5_axi_awprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="237" MSB="3" NAME="s5_axi_awqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="238" NAME="s5_axi_awvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="239" NAME="s5_axi_awready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="240" MSB="31" NAME="s5_axi_wdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="241" MSB="3" NAME="s5_axi_wstrb" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S5_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="242" NAME="s5_axi_wlast" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="243" NAME="s5_axi_wvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="244" NAME="s5_axi_wready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="245" MSB="3" NAME="s5_axi_bid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="246" MSB="1" NAME="s5_axi_bresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="247" NAME="s5_axi_bvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="248" NAME="s5_axi_bready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="249" MSB="3" NAME="s5_axi_arid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="250" MSB="31" NAME="s5_axi_araddr" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="251" MSB="7" NAME="s5_axi_arlen" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="252" MSB="2" NAME="s5_axi_arsize" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="253" MSB="1" NAME="s5_axi_arburst" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="254" NAME="s5_axi_arlock" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="255" MSB="3" NAME="s5_axi_arcache" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="256" MSB="2" NAME="s5_axi_arprot" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="257" MSB="3" NAME="s5_axi_arqos" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="258" NAME="s5_axi_arvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="259" NAME="s5_axi_arready" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="260" MSB="3" NAME="s5_axi_rid" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="261" MSB="31" NAME="s5_axi_rdata" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S5_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="262" MSB="1" NAME="s5_axi_rresp" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="263" NAME="s5_axi_rlast" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="264" NAME="s5_axi_rvalid" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S5_AXI" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="265" NAME="s5_axi_rready" SIGNAME="__NOC__"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S0_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_aresetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awaddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_awvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_awready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_wdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_wstrb"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_wlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_wvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_wready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_bid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_bresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_bvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_bready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_araddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_arvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_arready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_rid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_rdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_rresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_rlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s0_axi_rvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s0_axi_rready"/>
|
|
</PORTMAPS>
|
|
<MASTERS>
|
|
<MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
|
|
<MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
|
|
</MASTERS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_SG" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="S1_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_aresetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awaddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_awvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_awready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_wdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_wstrb"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_wlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_wvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_wready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_bid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_bresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_bvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_bready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_araddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_arvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_arready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_rid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_rdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_rresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_rlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s1_axi_rvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s1_axi_rready"/>
|
|
</PORTMAPS>
|
|
<MASTERS>
|
|
<MASTER BUSINTERFACE="M_AXI_SG" INSTANCE="AXI_DMA_Ethernet"/>
|
|
</MASTERS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="S2_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_aresetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awaddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_awvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_awready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_wdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_wstrb"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_wlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_wvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_wready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_bid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_bresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_bvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_bready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_araddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_arvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_arready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_rid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_rdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_rresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_rlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2_axi_rvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s2_axi_rready"/>
|
|
</PORTMAPS>
|
|
<MASTERS>
|
|
<MASTER BUSINTERFACE="M_AXI_MM2S" INSTANCE="AXI_DMA_Ethernet"/>
|
|
<MASTER BUSINTERFACE="M_AXI_S2MM" INSTANCE="AXI_DMA_Ethernet"/>
|
|
</MASTERS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="3" NAME="S3_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_aresetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awaddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_awvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_awready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_wdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_wstrb"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_wlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_wvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_wready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_bid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_bresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_bvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_bready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_araddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_arvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_arready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_rid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_rdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_rresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_rlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s3_axi_rvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s3_axi_rready"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="4" NAME="S4_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_aresetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awaddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_awvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_awready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_wdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_wstrb"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_wlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_wvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_wready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_bid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_bresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_bvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_bready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_araddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_arvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_arready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_rid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_rdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_rresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_rlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s4_axi_rvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s4_axi_rready"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="5" NAME="S5_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_aresetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awaddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_awvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_awready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_wdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_wstrb"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_wlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_wvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_wready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_bid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_bresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_bvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_bready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_araddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arlen"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arsize"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arburst"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arlock"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arcache"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arprot"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arqos"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_arvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_arready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_rid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_rdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_rresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_rlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s5_axi_rvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s5_axi_rready"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="memory_0" TYPE="hide_122_XIL_MEMORY_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_addr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_ba"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_ras_n"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_cas_n"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_we_n"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_cke"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_clk_n"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dq"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_odt"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_ldm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_udm"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mcbx_dram_ddr3_rst"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="mcbx_dram_udqs_n"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="mcbx_dram_dqs_n"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="rzq"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="zio"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_S0_AXI_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1207959551" HIGHNAME="C_S0_AXI_HIGHADDR" HIGHVALUE="0x47FFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S0_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_S1_AXI_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1207959551" HIGHNAME="C_S1_AXI_HIGHADDR" HIGHVALUE="0x47FFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S1_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="1073741824" BASENAME="C_S2_AXI_BASEADDR" BASEVALUE="0x40000000" HIGHDECIMAL="1207959551" HIGHNAME="C_S2_AXI_HIGHADDR" HIGHVALUE="0x47FFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="134217728" SIZEABRV="128M">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S2_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S3_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S3_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S3_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S4_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S4_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S4_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S5_AXI_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_S5_AXI_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x1000" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S5_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="4.02.a" INSTANCE="clock_generator_0" IPTYPE="PERIPHERAL" MHS_INDEX="8" MODCLASS="IP" MODTYPE="clock_generator">
|
|
<DESCRIPTION TYPE="SHORT">Clock Generator</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Clock generator for processor system.</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/clock_generator_v4_02_a/doc/clock_generator.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_DEVICE" TYPE="STRING" VALUE="6slx45t">
|
|
<DESCRIPTION>Device</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PACKAGE" TYPE="STRING" VALUE="fgg484">
|
|
<DESCRIPTION>Package</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPEEDGRADE" TYPE="STRING" VALUE="-3">
|
|
<DESCRIPTION>Speed Grade</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="4" NAME="C_CLKIN_FREQ" TYPE="INTEGER" VALUE="200000000">
|
|
<DESCRIPTION>Input Clock Frequency (Hz) </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="5" NAME="C_CLKOUT0_FREQ" TYPE="INTEGER" VALUE="666666667">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="6" NAME="C_CLKOUT0_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="7" NAME="C_CLKOUT0_GROUP" TYPE="STRING" VALUE="PLL0">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="8" NAME="C_CLKOUT0_BUF" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Buffered </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_CLKOUT0_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="10" NAME="C_CLKOUT1_FREQ" TYPE="INTEGER" VALUE="666666667">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="11" NAME="C_CLKOUT1_PHASE" TYPE="INTEGER" VALUE="180">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="12" NAME="C_CLKOUT1_GROUP" TYPE="STRING" VALUE="PLL0">
|
|
<DESCRIPTION>Required Group </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="13" NAME="C_CLKOUT1_BUF" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_CLKOUT1_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="15" NAME="C_CLKOUT2_FREQ" TYPE="INTEGER" VALUE="83333333">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="16" NAME="C_CLKOUT2_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="17" NAME="C_CLKOUT2_GROUP" TYPE="STRING" VALUE="PLL0">
|
|
<DESCRIPTION>Required Group </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="18" NAME="C_CLKOUT2_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="19" NAME="C_CLKOUT2_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Varaible Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="20" NAME="C_CLKOUT3_FREQ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="21" NAME="C_CLKOUT3_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="22" NAME="C_CLKOUT3_GROUP" TYPE="STRING" VALUE="PLL1">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="23" NAME="C_CLKOUT3_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_CLKOUT3_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="25" NAME="C_CLKOUT4_FREQ" TYPE="INTEGER" VALUE="50000000">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="26" NAME="C_CLKOUT4_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="27" NAME="C_CLKOUT4_GROUP" TYPE="STRING" VALUE="PLL1">
|
|
<DESCRIPTION>Required Group </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="28" NAME="C_CLKOUT4_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_CLKOUT4_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="30" NAME="C_CLKOUT5_FREQ" TYPE="INTEGER" VALUE="125000000">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="25" MPD_INDEX="31" NAME="C_CLKOUT5_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="26" MPD_INDEX="32" NAME="C_CLKOUT5_GROUP" TYPE="STRING" VALUE="PLL1">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="27" MPD_INDEX="33" NAME="C_CLKOUT5_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_CLKOUT5_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="28" MPD_INDEX="35" NAME="C_CLKOUT6_FREQ" TYPE="INTEGER" VALUE="200000000">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="29" MPD_INDEX="36" NAME="C_CLKOUT6_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="30" MPD_INDEX="37" NAME="C_CLKOUT6_GROUP" TYPE="STRING" VALUE="PLL1">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="31" MPD_INDEX="38" NAME="C_CLKOUT6_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_CLKOUT6_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="40" NAME="C_CLKOUT7_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_CLKOUT7_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_CLKOUT7_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="43" NAME="C_CLKOUT7_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_CLKOUT7_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_CLKOUT8_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_CLKOUT8_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_CLKOUT8_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_CLKOUT8_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_CLKOUT8_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_CLKOUT9_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_CLKOUT9_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_CLKOUT9_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_CLKOUT9_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_CLKOUT9_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION> Varaible Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="55" NAME="C_CLKOUT10_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="56" NAME="C_CLKOUT10_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_CLKOUT10_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="58" NAME="C_CLKOUT10_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_CLKOUT10_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_CLKOUT11_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="61" NAME="C_CLKOUT11_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="62" NAME="C_CLKOUT11_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_CLKOUT11_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_CLKOUT11_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="65" NAME="C_CLKOUT12_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="66" NAME="C_CLKOUT12_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="67" NAME="C_CLKOUT12_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="68" NAME="C_CLKOUT12_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="69" NAME="C_CLKOUT12_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION> Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="70" NAME="C_CLKOUT13_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="71" NAME="C_CLKOUT13_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="72" NAME="C_CLKOUT13_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="73" NAME="C_CLKOUT13_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="74" NAME="C_CLKOUT13_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="75" NAME="C_CLKOUT14_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="76" NAME="C_CLKOUT14_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="77" NAME="C_CLKOUT14_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="78" NAME="C_CLKOUT14_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="79" NAME="C_CLKOUT14_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="80" NAME="C_CLKOUT15_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="81" NAME="C_CLKOUT15_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="82" NAME="C_CLKOUT15_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="83" NAME="C_CLKOUT15_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="84" NAME="C_CLKOUT15_VARIABLE_PHASE" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION> Variable Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="85" NAME="C_CLKFBIN_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="86" NAME="C_CLKFBIN_DESKEW" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Clock Deskew</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="87" NAME="C_CLKFBOUT_FREQ" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Frequency (Hz)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="88" NAME="C_CLKFBOUT_PHASE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Required Phase</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="89" NAME="C_CLKFBOUT_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Required Group</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="90" NAME="C_CLKFBOUT_BUF" TYPE="BOOLEAN" VALUE="TRUE">
|
|
<DESCRIPTION>Buffered</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="91" NAME="C_PSDONE_GROUP" TYPE="STRING" VALUE="NONE">
|
|
<DESCRIPTION>Variable Phase Shift</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="92" NAME="C_EXT_RESET_HIGH" VALUE="1"/>
|
|
<PARAMETER MPD_INDEX="93" NAME="C_CLK_PRIMITIVE_FEEDBACK_BUF" TYPE="BOOLEAN" VALUE="FALSE">
|
|
<DESCRIPTION>Clock Primitive Feedback Buffer</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="94" NAME="C_CLKOUT0_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="95" NAME="C_CLKOUT1_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="96" NAME="C_CLKOUT2_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="97" NAME="C_CLKOUT3_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="98" NAME="C_CLKOUT4_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="99" NAME="C_CLKOUT5_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="100" NAME="C_CLKOUT6_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="101" NAME="C_CLKOUT7_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="102" NAME="C_CLKOUT8_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="103" NAME="C_CLKOUT9_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="104" NAME="C_CLKOUT10_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="105" NAME="C_CLKOUT11_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="106" NAME="C_CLKOUT12_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="107" NAME="C_CLKOUT13_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="108" NAME="C_CLKOUT14_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="109" NAME="C_CLKOUT15_DUTY_CYCLE" TYPE="REAL" VALUE="0.500000"/>
|
|
<PARAMETER MPD_INDEX="110" NAME="C_CLK_GEN" VALUE="UPDATE"/>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="CLKIN" SIGIS="CLK" SIGNAME="dcm_clk_s"/>
|
|
<PORT CLKFREQUENCY="666666667" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="CLKOUT0" SIGIS="CLK" SIGNAME="pll_module_0_CLKOUT0"/>
|
|
<PORT CLKFREQUENCY="666666667" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="CLKOUT1" SIGIS="CLK" SIGNAME="pll_module_0_CLKOUT1"/>
|
|
<PORT CLKFREQUENCY="83333333" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="CLKOUT2" SIGIS="CLK" SIGNAME="pll_module_0_CLKOUT2"/>
|
|
<PORT CLKFREQUENCY="100000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="CLKOUT3" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT CLKFREQUENCY="50000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="CLKOUT4" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT CLKFREQUENCY="125000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="6" NAME="CLKOUT5" SIGIS="CLK" SIGNAME="ethernet_clk_s"/>
|
|
<PORT CLKFREQUENCY="200000000" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="7" NAME="CLKOUT6" SIGIS="CLK" SIGNAME="clk_ref"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="24" NAME="LOCKED" SIGNAME="Dcm_all_locked"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="23" NAME="RST" SIGIS="RST" SIGNAME="sys_rst_s"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="CLKOUT7" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="9" NAME="CLKOUT8" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="CLKOUT9" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="11" NAME="CLKOUT10" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="12" NAME="CLKOUT11" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="13" NAME="CLKOUT12" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="CLKOUT13" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="15" NAME="CLKOUT14" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="16" NAME="CLKOUT15" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="17" NAME="CLKFBIN" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="18" NAME="CLKFBOUT" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" MPD_INDEX="19" NAME="PSCLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" MPD_INDEX="20" NAME="PSEN" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" MPD_INDEX="21" NAME="PSINCDEC" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="22" NAME="PSDONE" SIGNAME="__NOC__"/>
|
|
</PORTS>
|
|
<BUSINTERFACES/>
|
|
</MODULE>
|
|
<MODULE HWVERSION="3.00.a" INSTANCE="proc_sys_reset_0" IPTYPE="PERIPHERAL" MHS_INDEX="9" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset">
|
|
<DESCRIPTION TYPE="SHORT">Processor System Reset Module</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Reset management module</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_sys_reset_v3_00_a/doc/proc_sys_reset.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_SUBFAMILY" TYPE="string" VALUE="t">
|
|
<DESCRIPTION>Device Subfamily</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_EXT_RST_WIDTH" TYPE="integer" VALUE="4">
|
|
<DESCRIPTION>Number of Clocks Before Input Change is Recognized On The External Reset Input </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_AUX_RST_WIDTH" TYPE="integer" VALUE="4">
|
|
<DESCRIPTION>Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="3" NAME="C_EXT_RESET_HIGH" TYPE="std_logic" VALUE="1">
|
|
<DESCRIPTION>External Reset Active High </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_AUX_RESET_HIGH" TYPE="std_logic" VALUE="1">
|
|
<DESCRIPTION>Auxiliary Reset Active High </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_NUM_BUS_RST" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Number of Bus Structure Reset Registered Outputs </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_NUM_PERP_RST" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Number of Peripheral Reset Registered Outputs </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_NUM_INTERCONNECT_ARESETN" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Number of Active Low Interconnect Reset Registered Outputs </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_NUM_PERP_ARESETN" TYPE="integer" VALUE="1">
|
|
<DESCRIPTION>Number of Active Low Peripheral Reset Registered Outputs </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="9" NAME="C_FAMILY" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT CLKFREQUENCY="50000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="Slowest_sync_clk" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="Ext_Reset_In" SIGIS="RST" SIGNAME="sys_rst_s"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="10" NAME="Dcm_locked" SIGNAME="Dcm_all_locked"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="17" NAME="MB_Reset" SIGIS="RST" SIGNAME="mb_reset"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="18" NAME="Bus_Struct_Reset" SIGIS="RST" SIGNAME="sys_bus_reset" VECFORMULA="[0:C_NUM_BUS_RST-1]"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="MB_Debug_Sys_Rst" SIGIS="RST" SIGNAME="Debug_SYS_Rst"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="19" NAME="Peripheral_Reset" SIGIS="RST" SIGNAME="sys_periph_reset" VECFORMULA="[0:C_NUM_PERP_RST-1]"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="20" NAME="Interconnect_aresetn" SIGIS="RST" SIGNAME="sys_bus_reset_n" VECFORMULA="[0:C_NUM_INTERCONNECT_ARESETN-1]"/>
|
|
<PORT DIR="I" MPD_INDEX="2" NAME="Aux_Reset_In" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="4" NAME="Core_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="5" NAME="Chip_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="6" NAME="System_Reset_Req_0" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="7" NAME="Core_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="8" NAME="Chip_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="9" NAME="System_Reset_Req_1" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="11" NAME="RstcPPCresetcore_0" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="12" NAME="RstcPPCresetchip_0" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC0" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="13" NAME="RstcPPCresetsys_0" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="14" NAME="RstcPPCresetcore_1" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="15" NAME="RstcPPCresetchip_1" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="RESETPPC1" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="16" NAME="RstcPPCresetsys_1" SIGIS="RST" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="21" NAME="Peripheral_aresetn" SIGIS="RST" SIGNAME="__NOC__" VECFORMULA="[0:C_NUM_PERP_ARESETN-1]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="0" NAME="RESETPPC0" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_0"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_0"/>
|
|
<PORTMAP DIR="I" PHYSICAL="System_Reset_Req_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_0"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_0"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="XIL" BUSSTD_PSF="XIL_RESETPPC" IS_VALID="FALSE" MPD_INDEX="1" NAME="RESETPPC1" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="Core_Reset_Req_1"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Chip_Reset_Req_1"/>
|
|
<PORTMAP DIR="I" PHYSICAL="System_Reset_Req_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetcore_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetchip_1"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RstcPPCresetsys_1"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
|
|
</IOINTERFACES>
|
|
</MODULE>
|
|
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.03.a" INSTANCE="AXI_MM" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="10" MODCLASS="BUS" MODTYPE="axi_interconnect">
|
|
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_03_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Base Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Number of Slave Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="3">
|
|
<DESCRIPTION>Number of Master Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI ID Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Master AXI Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000048000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff000000004a000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000">
|
|
<DESCRIPTION>Master AXI Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000049ffffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004a00ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047ffffff">
|
|
<DESCRIPTION>Master AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000">
|
|
<DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100">
|
|
<DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e100">
|
|
<DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101">
|
|
<DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Propagate USER Signals</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="5">
|
|
<DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="5">
|
|
<DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>WUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>RUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>BUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000030000000300000003">
|
|
<DESCRIPTION>AXI Connectivity</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100">
|
|
<DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100">
|
|
<DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000020">
|
|
<DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000002">
|
|
<DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000004">
|
|
<DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000200000004">
|
|
<DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Secure</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008">
|
|
<DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008">
|
|
<DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008">
|
|
<DESCRIPTION>Slave AXI W Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008">
|
|
<DESCRIPTION>Slave AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008">
|
|
<DESCRIPTION>Slave AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000800000000">
|
|
<DESCRIPTION>Master AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000800000000">
|
|
<DESCRIPTION>Master AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000800000000">
|
|
<DESCRIPTION>Master AXI W Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Interconnect Architecture</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Generate Interrupts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
|
|
<DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Simulation debug</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Select SI slot for DEBUG outputs</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Select MI slot for DEBUG outputs</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Thread depth of DEBUG signal</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="sys_bus_reset_n"/>
|
|
<PORT DEF_SIGNAME="axi_mm_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_mm_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="3" MSB="2" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_mm_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DEF_SIGNAME="sys_clk_s&sys_clk_s" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="sys_clk_s&sys_clk_s" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
|
|
<SIGNALS>
|
|
<SIGNAL NAME="sys_clk_s"/>
|
|
<SIGNAL NAME="sys_clk_s"/>
|
|
</SIGNALS>
|
|
</PORT>
|
|
<PORT DEF_SIGNAME="axi_mm_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi_mm_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_mm_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_mm_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_mm_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_mm_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_mm_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_mm_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_mm_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_mm_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="15" MSB="9" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi_mm_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi_mm_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi_mm_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_mm_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_mm_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi_mm_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi_mm_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi_mm_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi_mm_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi_mm_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_mm_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi_mm_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi_mm_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi_mm_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi_mm_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_mm_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_mm_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_mm_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_mm_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_mm_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_mm_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_mm_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_mm_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="9" LSB="0" MPD_INDEX="38" MSB="9" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi_mm_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi_mm_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi_mm_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi_mm_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_mm_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_mm_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi_mm_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi_mm_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi_mm_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi_mm_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="sys_clk_s&sys_clk_s&sys_clk_s" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="48" MSB="2" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="sys_clk_s&sys_clk_s&sys_clk_s" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
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<SIGNALS>
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<SIGNAL NAME="sys_clk_s"/>
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<SIGNAL NAME="sys_clk_s"/>
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<SIGNAL NAME="sys_clk_s"/>
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</SIGNALS>
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</PORT>
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<PORT DEF_SIGNAME="axi_mm_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="49" MSB="2" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi_mm_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="50" MSB="95" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_mm_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="51" MSB="23" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_mm_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="52" MSB="8" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_mm_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="53" MSB="5" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_mm_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="54" MSB="5" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_mm_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="55" MSB="11" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_mm_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="56" MSB="8" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_mm_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="57" MSB="11" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_mm_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="58" MSB="11" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_mm_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="59" MSB="14" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi_mm_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="60" MSB="2" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi_mm_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="61" MSB="2" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi_mm_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="62" MSB="2" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi_mm_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="63" MSB="95" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_mm_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="64" MSB="11" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_mm_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="65" MSB="2" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi_mm_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="66" MSB="2" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi_mm_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="67" MSB="2" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi_mm_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="68" MSB="2" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi_mm_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="69" MSB="2" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi_mm_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="70" MSB="5" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_mm_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="71" MSB="2" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi_mm_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="72" MSB="2" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi_mm_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="73" MSB="2" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi_mm_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="74" MSB="2" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi_mm_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="75" MSB="95" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_mm_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="76" MSB="23" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_mm_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="77" MSB="8" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_mm_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="78" MSB="5" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_mm_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="79" MSB="5" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_mm_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="80" MSB="11" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_mm_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="8" LSB="0" MPD_INDEX="81" MSB="8" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_mm_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_mm_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="82" MSB="11" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_mm_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="83" MSB="11" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_mm_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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|
<PORT DEF_SIGNAME="axi_mm_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="14" LSB="0" MPD_INDEX="84" MSB="14" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi_mm_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="85" MSB="2" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi_mm_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="86" MSB="2" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi_mm_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="87" MSB="2" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi_mm_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="88" MSB="95" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_mm_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="89" MSB="5" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_mm_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="90" MSB="2" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi_mm_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="91" MSB="2" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi_mm_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="92" MSB="2" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi_mm_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_mm_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="93" MSB="2" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi_mm_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="110" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="111" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="115" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="116" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="117" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="118" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="122" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="123" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="124" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="125" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="137" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="138" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="139" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="140" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="141" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="142" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="143" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="144" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="145" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="146" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="147" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="148" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="149" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="150" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="151" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="152" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="153" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="154" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="155" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="156" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="157" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="158" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="159" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="161" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="162" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="164" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="165" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="166" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="167" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="168" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="169" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="170" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="171" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="173" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="175" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="176" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="177" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="178" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="179" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="180" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="181" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="182" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="184" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="185" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="186" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="187" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="188" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="189" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="190" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="191" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="192" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="193" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="194" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="195" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="196" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="197" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="198" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="199" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="200" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="202" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.03.a" INSTANCE="AXI_DMA_SG" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="11" MODCLASS="BUS" MODTYPE="axi_interconnect">
|
|
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_03_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Base Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Number of Slave Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Number of Master Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI ID Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Master AXI Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000">
|
|
<DESCRIPTION>Master AXI Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047ffffff">
|
|
<DESCRIPTION>Master AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
|
|
<DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
|
|
<DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Propagate USER Signals</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>WUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>RUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>BUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001">
|
|
<DESCRIPTION>AXI Connectivity</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
|
|
<DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
|
|
<DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Secure</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI W Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI W Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Interconnect Architecture</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Generate Interrupts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
|
|
<DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Simulation debug</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Select SI slot for DEBUG outputs</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Select MI slot for DEBUG outputs</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Thread depth of DEBUG signal</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="sys_bus_reset_n"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_dma_sg_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_dma_sg_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DEF_SIGNAME="sys_clk_s" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi_dma_sg_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_dma_sg_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_dma_sg_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_dma_sg_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_dma_sg_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_dma_sg_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_dma_sg_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_dma_sg_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_dma_sg_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi_dma_sg_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi_dma_sg_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi_dma_sg_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_dma_sg_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_dma_sg_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi_dma_sg_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi_dma_sg_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi_dma_sg_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi_dma_sg_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi_dma_sg_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_dma_sg_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi_dma_sg_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi_dma_sg_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi_dma_sg_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi_dma_sg_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_dma_sg_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_dma_sg_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_dma_sg_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_dma_sg_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_dma_sg_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_dma_sg_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_dma_sg_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_dma_sg_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi_dma_sg_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi_dma_sg_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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|
<PORT DEF_SIGNAME="axi_dma_sg_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi_dma_sg_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi_dma_sg_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_dma_sg_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_dma_sg_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi_dma_sg_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi_dma_sg_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi_dma_sg_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi_dma_sg_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="sys_clk_s" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi_dma_sg_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_dma_sg_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_dma_sg_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_dma_sg_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_dma_sg_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_dma_sg_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_dma_sg_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_dma_sg_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_dma_sg_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_dma_sg_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWUSER" DIR="O" MPD_INDEX="59" NAME="M_AXI_AWUSER" SIGNAME="axi_dma_sg_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi_dma_sg_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi_dma_sg_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi_dma_sg_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_dma_sg_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_dma_sg_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi_dma_sg_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi_dma_sg_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi_dma_sg_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi_dma_sg_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi_dma_sg_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_dma_sg_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi_dma_sg_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi_dma_sg_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi_dma_sg_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi_dma_sg_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_dma_sg_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_dma_sg_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_dma_sg_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_dma_sg_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_dma_sg_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_dma_sg_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_dma_sg_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_dma_sg_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_dma_sg_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARUSER" DIR="O" MPD_INDEX="84" NAME="M_AXI_ARUSER" SIGNAME="axi_dma_sg_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi_dma_sg_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi_dma_sg_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi_dma_sg_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_dma_sg_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_dma_sg_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi_dma_sg_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi_dma_sg_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi_dma_sg_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_sg_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi_dma_sg_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
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<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="110" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="111" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="115" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="116" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="117" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="118" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="122" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="123" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="124" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="125" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="137" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="138" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="139" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="140" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="141" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="142" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="143" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="144" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="145" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="146" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="147" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="148" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="149" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="150" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="151" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="152" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="153" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="154" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="155" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="156" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="157" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="158" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="159" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="161" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="162" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="164" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="165" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="166" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="167" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="168" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="169" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="170" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="171" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="173" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="175" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="176" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="177" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="178" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="179" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="180" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="181" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="182" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="184" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="185" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="186" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="187" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="188" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="189" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="190" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="191" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="192" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="193" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="194" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="195" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="196" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="197" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="198" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="199" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="200" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="202" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.03.a" INSTANCE="AXI_DMA_MM" IPTYPE="BUS" IS_CROSSBAR="TRUE" MHS_INDEX="12" MODCLASS="BUS" MODTYPE="axi_interconnect">
|
|
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_03_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Base Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Number of Slave Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Number of Master Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI ID Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Master AXI Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000040000000">
|
|
<DESCRIPTION>Master AXI Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000047ffffff">
|
|
<DESCRIPTION>Master AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000">
|
|
<DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e100">
|
|
<DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
|
|
<DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
|
|
<DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111101">
|
|
<DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Propagate USER Signals</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>WUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>RUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>BUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003">
|
|
<DESCRIPTION>AXI Connectivity</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111100">
|
|
<DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
|
|
<DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000400000001">
|
|
<DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
|
|
<DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
|
|
<DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004">
|
|
<DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Secure</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000200">
|
|
<DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI W Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI W Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Interconnect Architecture</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Generate Interrupts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
|
|
<DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Simulation debug</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Select SI slot for DEBUG outputs</DESCRIPTION>
|
|
</PARAMETER>
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<PARAMETER MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
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<DESCRIPTION>Select MI slot for DEBUG outputs</DESCRIPTION>
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</PARAMETER>
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<PARAMETER MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1">
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<DESCRIPTION>Thread depth of DEBUG signal</DESCRIPTION>
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</PARAMETER>
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</PARAMETERS>
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<PORTS>
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<PORT BUS="S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
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<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="sys_bus_reset_n"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="2" MSB="1" NAME="S_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_dma_mm_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARESETN" DIR="O" MPD_INDEX="3" NAME="M_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_dma_mm_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
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<PORT DEF_SIGNAME="sys_clk_s&sys_clk_s" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="5" MSB="1" NAME="S_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="sys_clk_s&sys_clk_s" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]">
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<SIGNALS>
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<SIGNAL NAME="sys_clk_s"/>
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<SIGNAL NAME="sys_clk_s"/>
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</SIGNALS>
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</PORT>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="6" MSB="1" NAME="S_AXI_AWID" RIGHT="0" SIGNAME="axi_dma_mm_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="7" MSB="63" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_dma_mm_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="8" MSB="15" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_dma_mm_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="9" MSB="5" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_dma_mm_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_dma_mm_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="11" MSB="3" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_dma_mm_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="12" MSB="7" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_dma_mm_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="13" MSB="5" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_dma_mm_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="14" MSB="7" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_dma_mm_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="15" MSB="1" NAME="S_AXI_AWUSER" RIGHT="0" SIGNAME="axi_dma_mm_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_AWVALID" RIGHT="0" SIGNAME="axi_dma_mm_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_AWREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_AWREADY" RIGHT="0" SIGNAME="axi_dma_mm_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="18" MSB="63" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_dma_mm_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_dma_mm_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_WLAST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_WLAST" RIGHT="0" SIGNAME="axi_dma_mm_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_WUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_WUSER" RIGHT="0" SIGNAME="axi_dma_mm_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_WVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="22" MSB="1" NAME="S_AXI_WVALID" RIGHT="0" SIGNAME="axi_dma_mm_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_WREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_WREADY" RIGHT="0" SIGNAME="axi_dma_mm_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_BID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="S_AXI_BID" RIGHT="0" SIGNAME="axi_dma_mm_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_dma_mm_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_BUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="26" MSB="1" NAME="S_AXI_BUSER" RIGHT="0" SIGNAME="axi_dma_mm_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_BVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_BVALID" RIGHT="0" SIGNAME="axi_dma_mm_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_BREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="28" MSB="1" NAME="S_AXI_BREADY" RIGHT="0" SIGNAME="axi_dma_mm_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="29" MSB="1" NAME="S_AXI_ARID" RIGHT="0" SIGNAME="axi_dma_mm_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="30" MSB="63" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_dma_mm_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="15" LSB="0" MPD_INDEX="31" MSB="15" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_dma_mm_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="32" MSB="5" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_dma_mm_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="33" MSB="3" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_dma_mm_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="34" MSB="3" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_dma_mm_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="35" MSB="7" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_dma_mm_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="5" LSB="0" MPD_INDEX="36" MSB="5" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_dma_mm_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="37" MSB="7" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_dma_mm_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARUSER" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="38" MSB="1" NAME="S_AXI_ARUSER" RIGHT="0" SIGNAME="axi_dma_mm_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARVALID" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="39" MSB="1" NAME="S_AXI_ARVALID" RIGHT="0" SIGNAME="axi_dma_mm_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_ARREADY" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="S_AXI_ARREADY" RIGHT="0" SIGNAME="axi_dma_mm_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_RID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="41" MSB="1" NAME="S_AXI_RID" RIGHT="0" SIGNAME="axi_dma_mm_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="63" LSB="0" MPD_INDEX="42" MSB="63" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_dma_mm_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="43" MSB="3" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_dma_mm_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_RLAST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_RLAST" RIGHT="0" SIGNAME="axi_dma_mm_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_RUSER" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_RUSER" RIGHT="0" SIGNAME="axi_dma_mm_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_RVALID" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="S_AXI_RVALID" RIGHT="0" SIGNAME="axi_dma_mm_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_S_RREADY" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="47" MSB="1" NAME="S_AXI_RREADY" RIGHT="0" SIGNAME="axi_dma_mm_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="sys_clk_s" DIR="I" MPD_INDEX="48" NAME="M_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWID" DIR="O" MPD_INDEX="49" NAME="M_AXI_AWID" SIGNAME="axi_dma_mm_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_dma_mm_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_dma_mm_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_dma_mm_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_dma_mm_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_dma_mm_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_dma_mm_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="56" MSB="2" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_dma_mm_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="57" MSB="3" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_dma_mm_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_dma_mm_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWUSER" DIR="O" MPD_INDEX="59" NAME="M_AXI_AWUSER" SIGNAME="axi_dma_mm_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWVALID" DIR="O" MPD_INDEX="60" NAME="M_AXI_AWVALID" SIGNAME="axi_dma_mm_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_AWREADY" DIR="I" MPD_INDEX="61" NAME="M_AXI_AWREADY" SIGNAME="axi_dma_mm_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_WID" DIR="O" MPD_INDEX="62" NAME="M_AXI_WID" SIGNAME="axi_dma_mm_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="63" MSB="31" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_dma_mm_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="64" MSB="3" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_dma_mm_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_WLAST" DIR="O" MPD_INDEX="65" NAME="M_AXI_WLAST" SIGNAME="axi_dma_mm_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_WUSER" DIR="O" MPD_INDEX="66" NAME="M_AXI_WUSER" SIGNAME="axi_dma_mm_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_WVALID" DIR="O" MPD_INDEX="67" NAME="M_AXI_WVALID" SIGNAME="axi_dma_mm_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_WREADY" DIR="I" MPD_INDEX="68" NAME="M_AXI_WREADY" SIGNAME="axi_dma_mm_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_BID" DIR="I" MPD_INDEX="69" NAME="M_AXI_BID" SIGNAME="axi_dma_mm_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_dma_mm_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_BUSER" DIR="I" MPD_INDEX="71" NAME="M_AXI_BUSER" SIGNAME="axi_dma_mm_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_BVALID" DIR="I" MPD_INDEX="72" NAME="M_AXI_BVALID" SIGNAME="axi_dma_mm_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_BREADY" DIR="O" MPD_INDEX="73" NAME="M_AXI_BREADY" SIGNAME="axi_dma_mm_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARID" DIR="O" MPD_INDEX="74" NAME="M_AXI_ARID" SIGNAME="axi_dma_mm_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_dma_mm_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_dma_mm_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_dma_mm_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_dma_mm_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="79" MSB="1" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_dma_mm_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_dma_mm_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="81" MSB="2" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_dma_mm_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="82" MSB="3" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_dma_mm_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="83" MSB="3" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_dma_mm_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARUSER" DIR="O" MPD_INDEX="84" NAME="M_AXI_ARUSER" SIGNAME="axi_dma_mm_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARVALID" DIR="O" MPD_INDEX="85" NAME="M_AXI_ARVALID" SIGNAME="axi_dma_mm_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_ARREADY" DIR="I" MPD_INDEX="86" NAME="M_AXI_ARREADY" SIGNAME="axi_dma_mm_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_RID" DIR="I" MPD_INDEX="87" NAME="M_AXI_RID" SIGNAME="axi_dma_mm_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="88" MSB="31" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_dma_mm_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="89" MSB="1" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_dma_mm_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_RLAST" DIR="I" MPD_INDEX="90" NAME="M_AXI_RLAST" SIGNAME="axi_dma_mm_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_RUSER" DIR="I" MPD_INDEX="91" NAME="M_AXI_RUSER" SIGNAME="axi_dma_mm_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_RVALID" DIR="I" MPD_INDEX="92" NAME="M_AXI_RVALID" SIGNAME="axi_dma_mm_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_dma_mm_M_RREADY" DIR="O" MPD_INDEX="93" NAME="M_AXI_RREADY" SIGNAME="axi_dma_mm_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
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<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="110" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="111" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="115" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="116" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="117" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="118" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="122" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="123" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="124" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="125" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
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|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="137" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="138" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="139" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="140" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
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|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="141" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="142" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="143" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="144" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="145" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="146" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="147" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="148" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="149" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="150" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="151" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="152" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="153" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="154" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="155" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="156" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="157" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="158" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="159" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="161" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="162" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="164" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="165" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="166" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="167" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="168" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="169" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="170" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="171" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="173" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="175" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="176" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="177" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="178" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="179" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="180" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="181" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="182" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="184" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="185" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="186" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="187" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="188" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="189" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="190" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="191" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="192" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="193" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="194" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="195" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="196" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="197" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="198" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="199" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="200" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="202" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE BUSSTD="AXI" BUSSTD_PSF="AXI" HWVERSION="1.03.a" INSTANCE="AXI_Lite" IPTYPE="BUS" MHS_INDEX="13" MODCLASS="BUS" MODTYPE="axi_interconnect">
|
|
<DESCRIPTION TYPE="SHORT">AXI Interconnect</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI4 Memory-Mapped Interconnect</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_interconnect_v1_03_a/doc/ds768_axi_interconnect.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_BASEFAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Base Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_NUM_SLAVE_SLOTS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Number of Slave Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_NUM_MASTER_SLOTS" TYPE="INTEGER" VALUE="12">
|
|
<DESCRIPTION>Number of Master Slots </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI ID Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Widgth </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_AXI_DATA_MAX_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Maximum Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_S_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Slave AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_M_AXI_DATA_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020">
|
|
<DESCRIPTION>Master AXI Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_INTERCONNECT_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Interconnect Crossbar Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002">
|
|
<DESCRIPTION>AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_M_AXI_PROTOCOL" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002">
|
|
<DESCRIPTION>Master AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_M_AXI_BASE_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000091800000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000086000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000080000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000081440000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000081400000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000081420000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000081600000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000083400000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000081800000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000083c00000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000084000000ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000084400000">
|
|
<DESCRIPTION>Master AXI Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="13" NAME="C_M_AXI_HIGH_ADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000009180ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008607ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008000ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008144ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008140ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008142ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008160ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008340ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008180ffff0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000083c0ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008400ffff000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008440ffff">
|
|
<DESCRIPTION>Master AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_S_AXI_BASE_ID" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Base ID</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_THREAD_ID_WIDTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Thread ID Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_S_AXI_IS_INTERCONNECT" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Is Interconnect</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100">
|
|
<DESCRIPTION>Slave AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_S_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slvave AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="19" NAME="C_M_AXI_ACLK_RATIO" TYPE="STD_LOGIC_VECTOR" VALUE="0x0000000100000001000000010000000102faf08002faf08002faf08002faf08002faf08002faf08002faf08002faf08002faf08002faf08002faf08002faf080">
|
|
<DESCRIPTION>Master AXI ACLK Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="20" NAME="C_M_AXI_IS_ACLK_ASYNC" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Is ACLK ASYNC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="21" NAME="C_INTERCONNECT_ACLK_RATIO" TYPE="INTEGER" VALUE="50000000">
|
|
<DESCRIPTION>Interconnect Crossbar ACLK Frequency Ratio</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_S_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_S_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_M_AXI_SUPPORTS_WRITE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Write</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_M_AXI_SUPPORTS_READ" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Read</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="26" NAME="C_AXI_SUPPORTS_USER_SIGNALS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Propagate USER Signals</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="27" NAME="C_AXI_AWUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AWUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="28" NAME="C_AXI_ARUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>ARUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_AXI_WUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>WUSER Signal Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_AXI_RUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>RUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_AXI_BUSER_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>BUSER Signal Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="32" NAME="C_AXI_CONNECTIVITY" TYPE="STD_LOGIC_VECTOR" VALUE="0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff">
|
|
<DESCRIPTION>AXI Connectivity</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_S_AXI_SINGLE_THREAD" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Single Thread</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_M_AXI_SUPPORTS_REORDERING" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Supports Reordering</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="35" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111110">
|
|
<DESCRIPTION>Master generates narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="36" NAME="C_M_AXI_SUPPORTS_NARROW_BURST" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave accepts narrow bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="37" NAME="C_S_AXI_WRITE_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Slave AXI Write Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="38" NAME="C_S_AXI_READ_ACCEPTANCE" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Slave AXI Read Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_M_AXI_WRITE_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Master AXI Write Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="40" NAME="C_M_AXI_READ_ISSUING" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001">
|
|
<DESCRIPTION>Master AXI Read Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_S_AXI_ARB_PRIORITY" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI ARB Priority</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_M_AXI_SECURE" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Secure</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="43" NAME="C_S_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_S_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_S_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_S_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_S_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Slave AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_S_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Slave AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_M_AXI_WRITE_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_M_AXI_WRITE_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Write FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_M_AXI_WRITE_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Write FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_M_AXI_READ_FIFO_DEPTH" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_M_AXI_READ_FIFO_TYPE" TYPE="STD_LOGIC_VECTOR" VALUE="0b1111111111111111">
|
|
<DESCRIPTION>Master AXI Read FIFO Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_M_AXI_READ_FIFO_DELAY" TYPE="STD_LOGIC_VECTOR" VALUE="0b0000000000000000">
|
|
<DESCRIPTION>Master AXI Read FIFO Delay</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="55" NAME="C_S_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="56" NAME="C_S_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_S_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI W Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="58" NAME="C_S_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_S_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Slave AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_M_AXI_AW_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI AW Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="61" NAME="C_M_AXI_AR_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI AR Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="62" NAME="C_M_AXI_W_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI W Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_M_AXI_R_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI R Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_M_AXI_B_REGISTER" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000">
|
|
<DESCRIPTION>Master AXI B Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="65" NAME="C_INTERCONNECT_R_REGISTER" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>C_INTERCONNECT_R_REGISTER</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="66" NAME="C_INTERCONNECT_CONNECTIVITY_MODE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Interconnect Architecture</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="67" NAME="C_USE_CTRL_PORT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Use Diagnostic Slave Port</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="68" NAME="C_USE_INTERRUPT" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Generate Interrupts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="69" NAME="C_RANGE_CHECK" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Check for transaction errors (DECERR)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="70" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>Slave AXI CTRL Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="71" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="72" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Slave AXI CTRL Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="73" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0xFFFFFFFF">
|
|
<DESCRIPTION>Diagnostic Slave Port Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="74" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x00000000">
|
|
<DESCRIPTION>Diagnostic Slave Port High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="75" NAME="C_DEBUG" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Simulation debug</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="76" NAME="C_S_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Select SI slot for DEBUG outputs</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="77" NAME="C_M_AXI_DEBUG_SLOT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Select MI slot for DEBUG outputs</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="78" NAME="C_MAX_DEBUG_THREADS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Thread depth of DEBUG signal</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI_CTRL" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="INTERCONNECT_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="INTERCONNECT_ARESETN" SIGIS="RST" SIGNAME="sys_bus_reset_n"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_ARESETN" DIR="O" MPD_INDEX="2" NAME="S_AXI_ARESET_OUT_N" SIGIS="RST" SIGNAME="axi_lite_S_ARESETN" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_M_ARESETN" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="3" MSB="11" NAME="M_AXI_ARESET_OUT_N" RIGHT="0" SIGIS="RST" SIGNAME="axi_lite_M_ARESETN" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="IRQ" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DEF_SIGNAME="sys_clk_s" DIR="I" MPD_INDEX="5" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWID" DIR="I" MPD_INDEX="6" NAME="S_AXI_AWID" SIGNAME="axi_lite_S_AWID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="axi_lite_S_AWADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="8" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="axi_lite_S_AWLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="9" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_lite_S_AWSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="axi_lite_S_AWBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_lite_S_AWLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="12" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_lite_S_AWCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="13" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="axi_lite_S_AWPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="14" MSB="3" NAME="S_AXI_AWQOS" RIGHT="0" SIGNAME="axi_lite_S_AWQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWUSER" DIR="I" MPD_INDEX="15" NAME="S_AXI_AWUSER" SIGNAME="axi_lite_S_AWUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWVALID" DIR="I" MPD_INDEX="16" NAME="S_AXI_AWVALID" SIGNAME="axi_lite_S_AWVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_AWREADY" DIR="O" MPD_INDEX="17" NAME="S_AXI_AWREADY" SIGNAME="axi_lite_S_AWREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="18" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="axi_lite_S_WDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="19" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="axi_lite_S_WSTRB" VECFORMULA="[(((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_WLAST" DIR="I" MPD_INDEX="20" NAME="S_AXI_WLAST" SIGNAME="axi_lite_S_WLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_WUSER" DIR="I" MPD_INDEX="21" NAME="S_AXI_WUSER" SIGNAME="axi_lite_S_WUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_WVALID" DIR="I" MPD_INDEX="22" NAME="S_AXI_WVALID" SIGNAME="axi_lite_S_WVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_WREADY" DIR="O" MPD_INDEX="23" NAME="S_AXI_WREADY" SIGNAME="axi_lite_S_WREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_BID" DIR="O" MPD_INDEX="24" NAME="S_AXI_BID" SIGNAME="axi_lite_S_BID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="25" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="axi_lite_S_BRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_BUSER" DIR="O" MPD_INDEX="26" NAME="S_AXI_BUSER" SIGNAME="axi_lite_S_BUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_BVALID" DIR="O" MPD_INDEX="27" NAME="S_AXI_BVALID" SIGNAME="axi_lite_S_BVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
|
|
<PORT DEF_SIGNAME="axi_lite_S_BREADY" DIR="I" MPD_INDEX="28" NAME="S_AXI_BREADY" SIGNAME="axi_lite_S_BREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARID" DIR="I" MPD_INDEX="29" NAME="S_AXI_ARID" SIGNAME="axi_lite_S_ARID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="30" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="axi_lite_S_ARADDR" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="31" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="axi_lite_S_ARLEN" VECFORMULA="[((C_NUM_SLAVE_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="32" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_lite_S_ARSIZE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="33" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="axi_lite_S_ARBURST" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARLOCK" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="S_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_lite_S_ARLOCK" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="35" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_lite_S_ARCACHE" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="36" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="axi_lite_S_ARPROT" VECFORMULA="[((C_NUM_SLAVE_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARQOS" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="37" MSB="3" NAME="S_AXI_ARQOS" RIGHT="0" SIGNAME="axi_lite_S_ARQOS" VECFORMULA="[((C_NUM_SLAVE_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARUSER" DIR="I" MPD_INDEX="38" NAME="S_AXI_ARUSER" SIGNAME="axi_lite_S_ARUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARVALID" DIR="I" MPD_INDEX="39" NAME="S_AXI_ARVALID" SIGNAME="axi_lite_S_ARVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_ARREADY" DIR="O" MPD_INDEX="40" NAME="S_AXI_ARREADY" SIGNAME="axi_lite_S_ARREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_RID" DIR="O" MPD_INDEX="41" NAME="S_AXI_RID" SIGNAME="axi_lite_S_RID" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="42" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="axi_lite_S_RDATA" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="43" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="axi_lite_S_RRESP" VECFORMULA="[((C_NUM_SLAVE_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_RLAST" DIR="O" MPD_INDEX="44" NAME="S_AXI_RLAST" SIGNAME="axi_lite_S_RLAST" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_RUSER" DIR="O" MPD_INDEX="45" NAME="S_AXI_RUSER" SIGNAME="axi_lite_S_RUSER" VECFORMULA="[((C_NUM_SLAVE_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_RVALID" DIR="O" MPD_INDEX="46" NAME="S_AXI_RVALID" SIGNAME="axi_lite_S_RVALID" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_S_RREADY" DIR="I" MPD_INDEX="47" NAME="S_AXI_RREADY" SIGNAME="axi_lite_S_RREADY" VECFORMULA="[(C_NUM_SLAVE_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="48" MSB="11" NAME="M_AXI_ACLK" RIGHT="0" SIGIS="CLK" SIGNAME="sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s&sys_clk_axilite_s" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]">
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<SIGNALS>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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<SIGNAL NAME="sys_clk_axilite_s"/>
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</SIGNALS>
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</PORT>
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<PORT DEF_SIGNAME="axi_lite_M_AWID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="49" MSB="11" NAME="M_AXI_AWID" RIGHT="0" SIGNAME="axi_lite_M_AWID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="50" MSB="383" NAME="M_AXI_AWADDR" RIGHT="0" SIGNAME="axi_lite_M_AWADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="51" MSB="95" NAME="M_AXI_AWLEN" RIGHT="0" SIGNAME="axi_lite_M_AWLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="52" MSB="35" NAME="M_AXI_AWSIZE" RIGHT="0" SIGNAME="axi_lite_M_AWSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="53" MSB="23" NAME="M_AXI_AWBURST" RIGHT="0" SIGNAME="axi_lite_M_AWBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWLOCK" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="54" MSB="23" NAME="M_AXI_AWLOCK" RIGHT="0" SIGNAME="axi_lite_M_AWLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="55" MSB="47" NAME="M_AXI_AWCACHE" RIGHT="0" SIGNAME="axi_lite_M_AWCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="56" MSB="35" NAME="M_AXI_AWPROT" RIGHT="0" SIGNAME="axi_lite_M_AWPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWREGION" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="57" MSB="47" NAME="M_AXI_AWREGION" RIGHT="0" SIGNAME="axi_lite_M_AWREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWQOS" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="58" MSB="47" NAME="M_AXI_AWQOS" RIGHT="0" SIGNAME="axi_lite_M_AWQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="59" MSB="11" NAME="M_AXI_AWUSER" RIGHT="0" SIGNAME="axi_lite_M_AWUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_AWUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="60" MSB="11" NAME="M_AXI_AWVALID" RIGHT="0" SIGNAME="axi_lite_M_AWVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_AWREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="61" MSB="11" NAME="M_AXI_AWREADY" RIGHT="0" SIGNAME="axi_lite_M_AWREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_WID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="62" MSB="11" NAME="M_AXI_WID" RIGHT="0" SIGNAME="axi_lite_M_WID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="63" MSB="383" NAME="M_AXI_WDATA" RIGHT="0" SIGNAME="axi_lite_M_WDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="64" MSB="47" NAME="M_AXI_WSTRB" RIGHT="0" SIGNAME="axi_lite_M_WSTRB" VECFORMULA="[(((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)/8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_WLAST" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="65" MSB="11" NAME="M_AXI_WLAST" RIGHT="0" SIGNAME="axi_lite_M_WLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_WUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="66" MSB="11" NAME="M_AXI_WUSER" RIGHT="0" SIGNAME="axi_lite_M_WUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_WUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_WVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="67" MSB="11" NAME="M_AXI_WVALID" RIGHT="0" SIGNAME="axi_lite_M_WVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_WREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="68" MSB="11" NAME="M_AXI_WREADY" RIGHT="0" SIGNAME="axi_lite_M_WREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_BID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="69" MSB="11" NAME="M_AXI_BID" RIGHT="0" SIGNAME="axi_lite_M_BID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="70" MSB="23" NAME="M_AXI_BRESP" RIGHT="0" SIGNAME="axi_lite_M_BRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_BUSER" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="71" MSB="11" NAME="M_AXI_BUSER" RIGHT="0" SIGNAME="axi_lite_M_BUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_BUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_BVALID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="72" MSB="11" NAME="M_AXI_BVALID" RIGHT="0" SIGNAME="axi_lite_M_BVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_BREADY" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="73" MSB="11" NAME="M_AXI_BREADY" RIGHT="0" SIGNAME="axi_lite_M_BREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="74" MSB="11" NAME="M_AXI_ARID" RIGHT="0" SIGNAME="axi_lite_M_ARID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="75" MSB="383" NAME="M_AXI_ARADDR" RIGHT="0" SIGNAME="axi_lite_M_ARADDR" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ADDR_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="95" LSB="0" MPD_INDEX="76" MSB="95" NAME="M_AXI_ARLEN" RIGHT="0" SIGNAME="axi_lite_M_ARLEN" VECFORMULA="[((C_NUM_MASTER_SLOTS*8)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="77" MSB="35" NAME="M_AXI_ARSIZE" RIGHT="0" SIGNAME="axi_lite_M_ARSIZE" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="78" MSB="23" NAME="M_AXI_ARBURST" RIGHT="0" SIGNAME="axi_lite_M_ARBURST" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARLOCK" DIR="O" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="79" MSB="23" NAME="M_AXI_ARLOCK" RIGHT="0" SIGNAME="axi_lite_M_ARLOCK" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="80" MSB="47" NAME="M_AXI_ARCACHE" RIGHT="0" SIGNAME="axi_lite_M_ARCACHE" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="35" LSB="0" MPD_INDEX="81" MSB="35" NAME="M_AXI_ARPROT" RIGHT="0" SIGNAME="axi_lite_M_ARPROT" VECFORMULA="[((C_NUM_MASTER_SLOTS*3)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARREGION" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="82" MSB="47" NAME="M_AXI_ARREGION" RIGHT="0" SIGNAME="axi_lite_M_ARREGION" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARQOS" DIR="O" ENDIAN="LITTLE" LEFT="47" LSB="0" MPD_INDEX="83" MSB="47" NAME="M_AXI_ARQOS" RIGHT="0" SIGNAME="axi_lite_M_ARQOS" VECFORMULA="[((C_NUM_MASTER_SLOTS*4)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARUSER" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="84" MSB="11" NAME="M_AXI_ARUSER" RIGHT="0" SIGNAME="axi_lite_M_ARUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ARUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARVALID" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="85" MSB="11" NAME="M_AXI_ARVALID" RIGHT="0" SIGNAME="axi_lite_M_ARVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_ARREADY" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="86" MSB="11" NAME="M_AXI_ARREADY" RIGHT="0" SIGNAME="axi_lite_M_ARREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_RID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="87" MSB="11" NAME="M_AXI_RID" RIGHT="0" SIGNAME="axi_lite_M_RID" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_ID_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="383" LSB="0" MPD_INDEX="88" MSB="383" NAME="M_AXI_RDATA" RIGHT="0" SIGNAME="axi_lite_M_RDATA" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_DATA_MAX_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="23" LSB="0" MPD_INDEX="89" MSB="23" NAME="M_AXI_RRESP" RIGHT="0" SIGNAME="axi_lite_M_RRESP" VECFORMULA="[((C_NUM_MASTER_SLOTS*2)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_RLAST" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="90" MSB="11" NAME="M_AXI_RLAST" RIGHT="0" SIGNAME="axi_lite_M_RLAST" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_RUSER" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="91" MSB="11" NAME="M_AXI_RUSER" RIGHT="0" SIGNAME="axi_lite_M_RUSER" VECFORMULA="[((C_NUM_MASTER_SLOTS*C_AXI_RUSER_WIDTH)-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_RVALID" DIR="I" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="92" MSB="11" NAME="M_AXI_RVALID" RIGHT="0" SIGNAME="axi_lite_M_RVALID" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT DEF_SIGNAME="axi_lite_M_RREADY" DIR="O" ENDIAN="LITTLE" LEFT="11" LSB="0" MPD_INDEX="93" MSB="11" NAME="M_AXI_RREADY" RIGHT="0" SIGNAME="axi_lite_M_RREADY" VECFORMULA="[(C_NUM_MASTER_SLOTS-1):0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="94" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
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<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="97" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
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|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="98" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="100" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="101" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="102" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="103" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_ADDR_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="104" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="105" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="106" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_CTRL_DATA_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="107" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="108" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="109" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="110" NAME="INTERCONNECT_ARESET_OUT_N" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="111" MSB="7" NAME="DEBUG_AW_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="112" MSB="7" NAME="DEBUG_AW_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="113" MSB="7" NAME="DEBUG_AR_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="114" MSB="7" NAME="DEBUG_AR_ARB_GRANT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="115" NAME="DEBUG_AW_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="116" MSB="7" NAME="DEBUG_AW_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="117" MSB="15" NAME="DEBUG_AW_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="118" MSB="7" NAME="DEBUG_AW_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="119" MSB="7" NAME="DEBUG_AW_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="120" MSB="7" NAME="DEBUG_AW_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="121" MSB="7" NAME="DEBUG_AW_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="122" NAME="DEBUG_AR_TRANS_QUAL" SIGNAME="__NOC__" VECFORMULA="[(C_MAX_DEBUG_THREADS-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="123" MSB="7" NAME="DEBUG_AR_ACCEPT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="15" LSB="0" MPD_INDEX="124" MSB="15" NAME="DEBUG_AR_ACTIVE_THREAD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(16-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="125" MSB="7" NAME="DEBUG_AR_ACTIVE_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="126" MSB="7" NAME="DEBUG_AR_ACTIVE_REGION" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="127" MSB="7" NAME="DEBUG_AR_ERROR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="128" MSB="7" NAME="DEBUG_AR_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="129" MSB="7" NAME="DEBUG_B_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="130" MSB="7" NAME="DEBUG_R_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="131" MSB="7" NAME="DEBUG_R_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_DEBUG_THREADS*8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="132" MSB="7" NAME="DEBUG_AW_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="133" MSB="7" NAME="DEBUG_AR_ISSUING_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="134" MSB="7" NAME="DEBUG_W_BEAT_CNT" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="135" MSB="7" NAME="DEBUG_W_TRANS_SEQ" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="136" MSB="7" NAME="DEBUG_BID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="137" NAME="DEBUG_BID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="7" LSB="0" MPD_INDEX="138" MSB="7" NAME="DEBUG_RID_TARGET" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(8-1):0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="139" NAME="DEBUG_RID_ERROR" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="140" MSB="31" NAME="DEBUG_SR_SC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="141" MSB="23" NAME="DEBUG_SR_SC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="142" MSB="31" NAME="DEBUG_SR_SC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="143" MSB="23" NAME="DEBUG_SR_SC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="144" MSB="4" NAME="DEBUG_SR_SC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="145" MSB="31" NAME="DEBUG_SR_SC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="146" MSB="5" NAME="DEBUG_SR_SC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="147" MSB="31" NAME="DEBUG_SR_SC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="148" MSB="6" NAME="DEBUG_SR_SC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="149" MSB="31" NAME="DEBUG_SC_SF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="150" MSB="23" NAME="DEBUG_SC_SF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="151" MSB="31" NAME="DEBUG_SC_SF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="152" MSB="23" NAME="DEBUG_SC_SF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="153" MSB="4" NAME="DEBUG_SC_SF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="154" MSB="31" NAME="DEBUG_SC_SF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="155" MSB="5" NAME="DEBUG_SC_SF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="156" MSB="31" NAME="DEBUG_SC_SF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="157" MSB="6" NAME="DEBUG_SC_SF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="158" MSB="31" NAME="DEBUG_SF_CB_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="159" MSB="23" NAME="DEBUG_SF_CB_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="160" MSB="31" NAME="DEBUG_SF_CB_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="161" MSB="23" NAME="DEBUG_SF_CB_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="162" MSB="4" NAME="DEBUG_SF_CB_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="163" MSB="31" NAME="DEBUG_SF_CB_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="164" MSB="5" NAME="DEBUG_SF_CB_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="165" MSB="31" NAME="DEBUG_SF_CB_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="166" MSB="6" NAME="DEBUG_SF_CB_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="167" MSB="31" NAME="DEBUG_CB_MF_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="168" MSB="23" NAME="DEBUG_CB_MF_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="169" MSB="31" NAME="DEBUG_CB_MF_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="170" MSB="23" NAME="DEBUG_CB_MF_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="171" MSB="4" NAME="DEBUG_CB_MF_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="172" MSB="31" NAME="DEBUG_CB_MF_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="173" MSB="5" NAME="DEBUG_CB_MF_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="174" MSB="31" NAME="DEBUG_CB_MF_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="175" MSB="6" NAME="DEBUG_CB_MF_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="176" MSB="31" NAME="DEBUG_MF_MC_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="177" MSB="23" NAME="DEBUG_MF_MC_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="178" MSB="31" NAME="DEBUG_MF_MC_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="179" MSB="23" NAME="DEBUG_MF_MC_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="180" MSB="4" NAME="DEBUG_MF_MC_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="181" MSB="31" NAME="DEBUG_MF_MC_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="182" MSB="5" NAME="DEBUG_MF_MC_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="183" MSB="31" NAME="DEBUG_MF_MC_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="184" MSB="6" NAME="DEBUG_MF_MC_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="185" MSB="31" NAME="DEBUG_MC_MP_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="186" MSB="23" NAME="DEBUG_MC_MP_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="187" MSB="31" NAME="DEBUG_MC_MP_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="188" MSB="23" NAME="DEBUG_MC_MP_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="189" MSB="4" NAME="DEBUG_MC_MP_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="190" MSB="31" NAME="DEBUG_MC_MP_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="191" MSB="5" NAME="DEBUG_MC_MP_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="192" MSB="31" NAME="DEBUG_MC_MP_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="193" MSB="6" NAME="DEBUG_MC_MP_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="194" MSB="31" NAME="DEBUG_MP_MR_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="195" MSB="23" NAME="DEBUG_MP_MR_ARADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="196" MSB="31" NAME="DEBUG_MP_MR_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="23" LSB="0" MPD_INDEX="197" MSB="23" NAME="DEBUG_MP_MR_AWADDRCONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((((((1+1)+8)+3)+2)+1)+4)+3)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="4" LSB="0" MPD_INDEX="198" MSB="4" NAME="DEBUG_MP_MR_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="199" MSB="31" NAME="DEBUG_MP_MR_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="5" LSB="0" MPD_INDEX="200" MSB="5" NAME="DEBUG_MP_MR_RDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(((((1+1)+1)+2)+C_AXI_ID_WIDTH)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="201" MSB="31" NAME="DEBUG_MP_MR_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_AXI_DATA_MAX_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="6" LSB="0" MPD_INDEX="202" MSB="6" NAME="DEBUG_MP_MR_WDATACONTROL" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((((1+1)+1)+(C_AXI_DATA_MAX_WIDTH/8))-1):0]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="0" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="INTERCONNECT_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_BASEADDR" BASEVALUE="0xFFFFFFFF" HIGHDECIMAL="0" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="RS232_Uart_1" IPTYPE="PERIPHERAL" MHS_INDEX="14" MODCLASS="PERIPHERAL" MODTYPE="axi_uart16550">
|
|
<DESCRIPTION TYPE="SHORT">AXI UART (16550-style)</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI 16550/450 UART (Universal Asynchronous Receiver/Transmitter)</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_uart16550_v1_01_a/doc/ds748_axi_uart16550.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
|
|
<DESCRIPTION>AXI Clock Frequency </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x84000000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8400ffff">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_IS_A_16550" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Uart Configuration </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_HAS_EXTERNAL_XIN" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>External XIN is Present</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_HAS_EXTERNAL_RCLK" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>External RCLK is Present</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_EXTERNAL_XIN_CLK_HZ" TYPE="INTEGER" VALUE="25000000">
|
|
<DESCRIPTION>XIN Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_USE_MODEM_PORTS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Include Modem Interface Ports</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_USE_USER_PORTS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Include User Interface Ports</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="I" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="33" NAME="Sin" SIGNAME="fpga_0_RS232_Uart_1_sin">
|
|
<DESCRIPTION>Serial Data Input</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="34" NAME="Sout" SIGNAME="fpga_0_RS232_Uart_1_sout">
|
|
<DESCRIPTION>Serial Data Output</DESCRIPTION>
|
|
</PORT>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="RS232_Uart_1_IP2INTC_Irpt"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="Freeze" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Freeze UART</DESCRIPTION>
|
|
</PORT>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="4" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="5" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="6" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="8" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="9" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="10" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="12" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="13" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="14" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="15" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="16" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="17" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="18" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="19" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="20" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT DIR="O" MPD_INDEX="21" NAME="BaudoutN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Transmitter Clock</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="22" NAME="CtsN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Clear To Send</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="23" NAME="DcdN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Data Carrier Detect</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="24" NAME="Ddis" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Driver disable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="25" NAME="DsrN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Data Set Ready</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="26" NAME="DtrN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Data Terminal Ready</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="27" NAME="Out1N" SIGNAME="__NOC__">
|
|
<DESCRIPTION>User Controlled Output</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="28" NAME="Out2N" SIGNAME="__NOC__">
|
|
<DESCRIPTION>User Controlled Output</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="29" NAME="Rclk" SIGIS="CLK" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Receiver 16x Clock</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="30" NAME="RiN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Ring Indicator</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="31" NAME="RtsN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Request To Send</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="32" NAME="RxrdyN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>DMA Control Signal</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="35" NAME="TxrdyN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>DMA Control Signal</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="36" NAME="Xin" SIGIS="CLK" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Baudrate Generator Reference Clock</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="uart_0" IS_VALID="FALSE" MPD_INDEX="37" NAME="Xout" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Inverted XIN</DESCRIPTION>
|
|
</PORT>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="uart_0" TYPE="XIL_UART_V1_hide">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="Sin"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sout"/>
|
|
<PORTMAP DIR="I" PHYSICAL="CtsN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DcdN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Ddis"/>
|
|
<PORTMAP DIR="I" PHYSICAL="DsrN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="DtrN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Out1N"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Out2N"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Rclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RiN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RtsN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RxrdyN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="TxrdyN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Xin"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Xout"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2214592512" BASENAME="C_BASEADDR" BASEVALUE="0x84000000" HIGHDECIMAL="2214658047" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8400ffff" MEMTYPE="REGISTER" MINSIZE="0x2000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<INTERRUPTINFO TYPE="SOURCE">
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="1"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.02.a" INSTANCE="Dual_Timer_Counter" IPTYPE="PERIPHERAL" MHS_INDEX="15" MODCLASS="PERIPHERAL" MODTYPE="axi_timer">
|
|
<DESCRIPTION TYPE="SHORT">AXI Timer/Counter</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Timer counter with AXI interface</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_timer_v1_02_a/doc/axi_timer_ds764.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_COUNT_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>The Width of Counter in Timer</DESCRIPTION>
|
|
<DESCRIPTION>Count Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_ONE_TIMER_ONLY" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Only One Timer is present</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_TRIG0_ASSERT" TYPE="std_logic" VALUE="1">
|
|
<DESCRIPTION>TRIG0 Active Level</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_TRIG1_ASSERT" TYPE="std_logic" VALUE="1">
|
|
<DESCRIPTION>TRIG1 Active Level</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_GEN0_ASSERT" TYPE="std_logic" VALUE="1">
|
|
<DESCRIPTION>GEN0 Active Level</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_GEN1_ASSERT" TYPE="std_logic" VALUE="1">
|
|
<DESCRIPTION>GEN1 Active Level</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="8" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x83c00000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="9" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x83c0ffff">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="7" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="5" NAME="Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Dual_Timer_Counter_Interrupt"/>
|
|
<PORT DIR="I" MPD_INDEX="0" NAME="CaptureTrig0" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Capture Trig 0</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" MPD_INDEX="1" NAME="CaptureTrig1" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Capture Trig 1</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" MPD_INDEX="2" NAME="GenerateOut0" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Generate Out 0</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" MPD_INDEX="3" NAME="GenerateOut1" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Generate Out 1</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" MPD_INDEX="4" NAME="PWM0" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Pulse Width Modulation 0</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" MPD_INDEX="6" NAME="Freeze" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="8" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="9" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="10" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="11" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="13" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="20" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="21" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="22" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="23" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="24" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="25" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2210398208" BASENAME="C_BASEADDR" BASEVALUE="0x83c00000" HIGHDECIMAL="2210463743" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x83c0ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<INTERRUPTINFO TYPE="SOURCE">
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="4"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="Interrupt_Cntlr" IPTYPE="PERIPHERAL" MHS_INDEX="16" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc">
|
|
<DESCRIPTION TYPE="SHORT">AXI Interrupt Controller</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">intc core attached to the AXI</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_intc_v1_01_a/doc/ds747_axi_intc.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81800000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8180ffff">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_NUM_INTR_INPUTS" TYPE="INTEGER" VALUE="8">
|
|
<DESCRIPTION>Number of Interrupt Inputs </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_KIND_OF_INTR" TYPE="std_logic_vector" VALUE="0b11111111111111111111111100000000">
|
|
<DESCRIPTION>Type of Interrupt for Each Input </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="7" NAME="C_KIND_OF_EDGE" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
|
|
<DESCRIPTION>Type of Each Edge Senstive Interrupt </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_KIND_OF_LVL" TYPE="std_logic_vector" VALUE="0b11111111111111111111111111111111">
|
|
<DESCRIPTION>Type of Each Level Sensitive Interrupt </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_HAS_IPR" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Support IPR </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_HAS_SIE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Support SIE </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_HAS_CIE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Support CIE </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_HAS_IVR" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Support IVR </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="13" NAME="C_IRQ_IS_LEVEL" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>IRQ Output Use Level </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_IRQ_ACTIVE" TYPE="std_logic" VALUE="1">
|
|
<DESCRIPTION>The Sense of IRQ Output </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="Irq" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="Interrupt">
|
|
<DESCRIPTION>Interrupt Request Output</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="2" MPD_INDEX="19" MSB="7" NAME="Intr" RIGHT="0" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT" SIGNAME="SysACE_CompactFlash_SysACE_IRQ & RS232_Uart_1_IP2INTC_Irpt & IIC_EEPROM_IIC2INTC_Irpt & SPI_FLASH_IP2INTC_Irpt & Dual_Timer_Counter_Interrupt & Soft_Ethernet_MAC_INTERRUPT & AXI_DMA_Ethernet_s2mm_introut & AXI_DMA_Ethernet_mm2s_introut" VECFORMULA="[(C_NUM_INTR_INPUTS-1):0]">
|
|
<SIGNALS>
|
|
<SIGNAL NAME="SysACE_CompactFlash_SysACE_IRQ"/>
|
|
<SIGNAL NAME="RS232_Uart_1_IP2INTC_Irpt"/>
|
|
<SIGNAL NAME="IIC_EEPROM_IIC2INTC_Irpt"/>
|
|
<SIGNAL NAME="SPI_FLASH_IP2INTC_Irpt"/>
|
|
<SIGNAL NAME="Dual_Timer_Counter_Interrupt"/>
|
|
<SIGNAL NAME="Soft_Ethernet_MAC_INTERRUPT"/>
|
|
<SIGNAL NAME="AXI_DMA_Ethernet_s2mm_introut"/>
|
|
<SIGNAL NAME="AXI_DMA_Ethernet_mm2s_introut"/>
|
|
</SIGNALS>
|
|
<DESCRIPTION>Interrupt Inputs</DESCRIPTION>
|
|
</PORT>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2172649472" BASENAME="C_BASEADDR" BASEVALUE="0x81800000" HIGHDECIMAL="2172715007" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8180ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<INTERRUPTINFO INTC_INDEX="0" TYPE="CONTROLLER">
|
|
<SOURCE INSTANCE="SysACE_CompactFlash" PRIORITY="0" SIGNAME="SysACE_CompactFlash_SysACE_IRQ"/>
|
|
<SOURCE INSTANCE="RS232_Uart_1" PRIORITY="1" SIGNAME="RS232_Uart_1_IP2INTC_Irpt"/>
|
|
<SOURCE INSTANCE="IIC_EEPROM" PRIORITY="2" SIGNAME="IIC_EEPROM_IIC2INTC_Irpt"/>
|
|
<SOURCE INSTANCE="SPI_FLASH" PRIORITY="3" SIGNAME="SPI_FLASH_IP2INTC_Irpt"/>
|
|
<SOURCE INSTANCE="Dual_Timer_Counter" PRIORITY="4" SIGNAME="Dual_Timer_Counter_Interrupt"/>
|
|
<SOURCE INSTANCE="Soft_Ethernet_MAC" PRIORITY="5" SIGNAME="Soft_Ethernet_MAC_INTERRUPT"/>
|
|
<SOURCE INSTANCE="AXI_DMA_Ethernet" PRIORITY="6" SIGNAME="AXI_DMA_Ethernet_s2mm_introut"/>
|
|
<SOURCE INSTANCE="AXI_DMA_Ethernet" PRIORITY="7" SIGNAME="AXI_DMA_Ethernet_mm2s_introut"/>
|
|
<TARGET INSTANCE="microblaze_0"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="SPI_FLASH" IPTYPE="PERIPHERAL" MHS_INDEX="17" MODCLASS="PERIPHERAL" MODTYPE="axi_spi">
|
|
<DESCRIPTION TYPE="SHORT">AXI SPI Interface</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI to Motorola Serial Peripheral Interface (SPI) adapter</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_spi_v1_01_a/doc/axi_spi_ds742.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x83400000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8340ffff">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_FIFO_EXIST" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include both Receiver and Transmitter FIFOs </DESCRIPTION>
|
|
<DESCRIPTION>Include Receive and Transmit FIFO</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_SCK_RATIO" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Ratio of AXI Clock Frequency To SCK Frequency </DESCRIPTION>
|
|
<DESCRIPTION>C_SCK_RATIO</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_NUM_SS_BITS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Total Number of Slave Select Bits in SS Vector </DESCRIPTION>
|
|
<DESCRIPTION>C_NUM_SS_BITS</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_NUM_TRANSFER_BITS" TYPE="INTEGER" VALUE="8">
|
|
<DESCRIPTION>Number of SPI transfer bits </DESCRIPTION>
|
|
<DESCRIPTION>C_NUM_TRANSFER_BITS</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="32" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="SPI_FLASH_IP2INTC_Irpt"/>
|
|
<PORT DIR="I" IOS="spi_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="28" NAME="SPISEL" SIGNAME="net_vcc">
|
|
<DESCRIPTION>Local SPI Slave Select Active LOW Input</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="spi_0" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="22" NAME="MISO_I" SIGNAME="fpga_0_SPI_FLASH_MISO_I"/>
|
|
<PORT DIR="O" IOS="spi_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="23" NAME="MISO_O" SIGNAME="fpga_0_SPI_FLASH_MISO_O"/>
|
|
<PORT DIR="O" IOS="spi_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="24" NAME="MISO_T" SIGNAME="fpga_0_SPI_FLASH_MISO_T"/>
|
|
<PORT DIR="IO" IOS="spi_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="5" MPD_INDEX="35" NAME="MOSI" SIGNAME="fpga_0_SPI_FLASH_MOSI" TRI_I="MOSI_I" TRI_O="MOSI_O" TRI_T="MOSI_T">
|
|
<DESCRIPTION>Master Out Slave In</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" IOS="spi_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="6" MPD_INDEX="33" NAME="SCK" SIGNAME="fpga_0_SPI_FLASH_SCK" TRI_I="SCK_I" TRI_O="SCK_O" TRI_T="SCK_T">
|
|
<DESCRIPTION>SPI Bus Clock</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" IOS="spi_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="7" MPD_INDEX="36" NAME="SS" SIGNAME="fpga_0_SPI_FLASH_SS" TRI_I="SS_I" TRI_O="SS_O" TRI_T="SS_T" VECFORMULA="[(C_NUM_SS_BITS-1):0]">
|
|
<DESCRIPTION>Slave Select Vector</DESCRIPTION>
|
|
</PORT>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT DIR="I" IOS="spi_0" MPD_INDEX="19" NAME="SCK_I" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="spi_0" MPD_INDEX="20" NAME="SCK_O" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="spi_0" MPD_INDEX="21" NAME="SCK_T" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="spi_0" MPD_INDEX="25" NAME="MOSI_I" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="spi_0" MPD_INDEX="26" NAME="MOSI_O" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="spi_0" MPD_INDEX="27" NAME="MOSI_T" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="spi_0" MPD_INDEX="29" NAME="SS_I" SIGNAME="__NOC__" VECFORMULA="[(C_NUM_SS_BITS-1):0]"/>
|
|
<PORT DIR="O" IOS="spi_0" MPD_INDEX="30" NAME="SS_O" SIGNAME="__NOC__" VECFORMULA="[(C_NUM_SS_BITS-1):0]"/>
|
|
<PORT DIR="O" IOS="spi_0" MPD_INDEX="31" NAME="SS_T" SIGNAME="__NOC__"/>
|
|
<PORT DIR="IO" IOS="spi_0" IS_THREE_STATE="TRUE" MPD_INDEX="34" NAME="MISO" SIGNAME="__NOC__" TRI_I="MISO_I" TRI_O="MISO_O" TRI_T="MISO_T">
|
|
<DESCRIPTION>Master In Slave Out</DESCRIPTION>
|
|
</PORT>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="spi_0" TYPE="XIL_SPI_V1_hide">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="SPISEL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MISO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MISO_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MISO_T"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="MOSI"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="SCK"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="SS"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SCK_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SCK_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SCK_T"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MOSI_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MOSI_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MOSI_T"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SS_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SS_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SS_T"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="MISO"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2202009600" BASENAME="C_BASEADDR" BASEVALUE="0x83400000" HIGHDECIMAL="2202075135" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8340ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<INTERRUPTINFO TYPE="SOURCE">
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="3"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.00.a" INSTANCE="util_io_mux_0" IPTYPE="PERIPHERAL" MHS_INDEX="18" MODCLASS="IP" MODTYPE="util_io_mux">
|
|
<DESCRIPTION TYPE="SHORT">Utility IO Multiplexor</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Utility IO multiplexor</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/util_io_mux_v1_00_a/doc/util_io_mux.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_SIZE" TYPE="INTEGER" VALUE="16">
|
|
<DESCRIPTION>Size of The Vector </DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S" SIGNAME="fpga_0_FLASH_Mem_CEN"/>
|
|
<PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="15" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="I0" RIGHT="15" SIGNAME="fpga_0_FLASH_Mem_DQ_I" VECFORMULA="[0:C_SIZE-1]"/>
|
|
<PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="15" MHS_INDEX="2" MPD_INDEX="2" MSB="0" NAME="O0" RIGHT="15" SIGNAME="fpga_0_FLASH_Mem_DQ_O" VECFORMULA="[0:C_SIZE-1]"/>
|
|
<PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="15" MHS_INDEX="3" MPD_INDEX="3" MSB="0" NAME="T0" RIGHT="15" SIGNAME="fpga_0_FLASH_Mem_DQ_T" VECFORMULA="[0:C_SIZE-1]"/>
|
|
<PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="15" MHS_INDEX="4" MPD_INDEX="4" MSB="0" NAME="I1" RIGHT="15" SIGNAME="0b000000000000000&fpga_0_SPI_FLASH_MISO_I" VECFORMULA="[0:C_SIZE-1]">
|
|
<SIGNALS>
|
|
<SIGNAL NAME="0b000000000000000"/>
|
|
<SIGNAL NAME="fpga_0_SPI_FLASH_MISO_I"/>
|
|
</SIGNALS>
|
|
</PORT>
|
|
<PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="15" MHS_INDEX="5" MPD_INDEX="5" MSB="0" NAME="O1" RIGHT="15" SIGNAME="0b111111111111111&fpga_0_SPI_FLASH_MISO_O" VECFORMULA="[0:C_SIZE-1]">
|
|
<SIGNALS>
|
|
<SIGNAL NAME="0b111111111111111"/>
|
|
<SIGNAL NAME="fpga_0_SPI_FLASH_MISO_O"/>
|
|
</SIGNALS>
|
|
</PORT>
|
|
<PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="15" MHS_INDEX="6" MPD_INDEX="6" MSB="0" NAME="T1" RIGHT="15" SIGNAME="0b111111111111111&fpga_0_SPI_FLASH_MISO_T" VECFORMULA="[0:C_SIZE-1]">
|
|
<SIGNALS>
|
|
<SIGNAL NAME="0b111111111111111"/>
|
|
<SIGNAL NAME="fpga_0_SPI_FLASH_MISO_T"/>
|
|
</SIGNALS>
|
|
</PORT>
|
|
<PORT DIR="IO" ENDIAN="BIG" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="0" LSB="15" MHS_INDEX="7" MPD_INDEX="10" MSB="0" NAME="IO" RIGHT="15" SIGNAME="fpga_0_FLASH_Mem_DQ_Shared" TRI_I="IO_I" TRI_O="IO_O" TRI_T="IO_T" VECFORMULA="[0:C_SIZE-1]"/>
|
|
<PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="7" MSB="0" NAME="IO_I" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:C_SIZE-1]"/>
|
|
<PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="8" MSB="0" NAME="IO_O" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:C_SIZE-1]"/>
|
|
<PORT DIR="O" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="9" MSB="0" NAME="IO_T" RIGHT="15" SIGNAME="__NOC__" VECFORMULA="[0:C_SIZE-1]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES/>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="IIC_EEPROM" IPTYPE="PERIPHERAL" MHS_INDEX="19" MODCLASS="PERIPHERAL" MODTYPE="axi_iic">
|
|
<DESCRIPTION TYPE="SHORT">AXI IIC Interface</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI interface to Philips I2C bus v2.1</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_iic_v1_01_a/doc/axi_iic_ds756.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81600000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8160ffff">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="5" NAME="C_IIC_FREQ" TYPE="INTEGER" VALUE="100000">
|
|
<DESCRIPTION>Output Frequency of SCL Signal</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="6" NAME="C_TEN_BIT_ADR" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Use 10-bit Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_GPO_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Width of GPIO</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
|
|
<DESCRIPTION>AXI Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_SCL_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Width of glitches removed on SCL input</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_SDA_INERTIAL_DELAY" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Width of glitches removed on SDA input</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_SDA_LEVEL" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>SDA level when Master transmit throttling occurs</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="1" MPD_INDEX="28" NAME="Scl" SIGNAME="fpga_0_IIC_EEPROM_Scl" TRI_I="Scl_I" TRI_O="Scl_O" TRI_T="Scl_T">
|
|
<DESCRIPTION>IIC Serial Clock</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" IOS="iic_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="2" MPD_INDEX="27" NAME="Sda" SIGNAME="fpga_0_IIC_EEPROM_Sda" TRI_I="Sda_I" TRI_O="Sda_O" TRI_T="Sda_T">
|
|
<DESCRIPTION>IIC Serial Data</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="IIC2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="IIC_EEPROM_IIC2INTC_Irpt"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT DIR="I" IOS="iic_0" MPD_INDEX="20" NAME="Sda_I" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="iic_0" MPD_INDEX="21" NAME="Sda_O" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="iic_0" MPD_INDEX="22" NAME="Sda_T" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="iic_0" MPD_INDEX="23" NAME="Scl_I" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="iic_0" MPD_INDEX="24" NAME="Scl_O" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="iic_0" MPD_INDEX="25" NAME="Scl_T" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="iic_0" MPD_INDEX="26" NAME="Gpo" SIGNAME="__NOC__" VECFORMULA="[(C_GPO_WIDTH-1):0]">
|
|
<DESCRIPTION>IIC General Purpose Output</DESCRIPTION>
|
|
</PORT>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="iic_0" TYPE="XIL_AXI_IIC_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="IO" PHYSICAL="Scl"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="Sda"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Sda_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sda_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Sda_T"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Scl_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Scl_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Scl_T"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Gpo"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2170552320" BASENAME="C_BASEADDR" BASEVALUE="0x81600000" HIGHDECIMAL="2170617855" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8160ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<INTERRUPTINFO TYPE="SOURCE">
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="2"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="LEDs_4Bit" IPTYPE="PERIPHERAL" MHS_INDEX="20" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
|
|
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81420000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8142FFFF">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
|
|
<DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
|
|
<DESCRIPTION>GPIO Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Enable Channel 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="fpga_0_LEDs_4Bit_GPIO_d_out" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
|
|
<DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
|
|
<DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
|
|
</PORT>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2168586240" BASENAME="C_BASEADDR" BASEVALUE="0x81420000" HIGHDECIMAL="2168651775" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8142FFFF" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="Push_Buttons_4Bit" IPTYPE="PERIPHERAL" MHS_INDEX="21" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
|
|
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81400000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8140ffff">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
|
|
<DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
|
|
<DESCRIPTION>GPIO Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Enable Channel 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="fpga_0_Push_Buttons_4Bit_GPIO_IO" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
|
|
<DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
|
|
</PORT>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
|
|
<DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
|
|
</PORT>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2168455168" BASENAME="C_BASEADDR" BASEVALUE="0x81400000" HIGHDECIMAL="2168520703" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8140ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="DIP_Switches_4Bit" IPTYPE="PERIPHERAL" MHS_INDEX="22" MODCLASS="PERIPHERAL" MODTYPE="axi_gpio">
|
|
<DESCRIPTION TYPE="SHORT">AXI General Purpose IO</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">General Purpose Input/Output (GPIO) core for the AXI bus.</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_gpio_v1_01_a/doc/ds744_axi_gpio.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="1" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x81440000">
|
|
<DESCRIPTION>AXI Base Address </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="2" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8144ffff">
|
|
<DESCRIPTION>AXI High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="5" NAME="C_GPIO_WIDTH" TYPE="INTEGER" VALUE="4">
|
|
<DESCRIPTION>GPIO Data Channel Width</DESCRIPTION>
|
|
<DESCRIPTION>GPIO Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_GPIO2_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>GPIO2 Data Channel Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="7" NAME="C_ALL_INPUTS" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Channel 1 is Input Only </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_ALL_INPUTS_2" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Channel 2 is Input Only </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_INTERRUPT_PRESENT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>GPIO Supports Interrupts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_DOUT_DEFAULT" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Channel 1 Data Out Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_TRI_DEFAULT" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Channel 1 Tri-state Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="12" NAME="C_IS_DUAL" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Enable Channel 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="13" NAME="C_DOUT_DEFAULT_2" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>Channel 2 Data Out Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_TRI_DEFAULT_2" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Channel 2 Tri-state Default Value </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4LITE protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_INSTANTIATED="TRUE" LEFT="3" LSB="0" MHS_INDEX="0" MPD_INDEX="20" MSB="3" NAME="GPIO_IO_I" RIGHT="0" SIGNAME="fpga_0_DIP_Switches_4Bit_GPIO_IO_I_pin" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="19" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="21" MSB="3" NAME="GPIO_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" LEFT="3" LSB="0" MPD_INDEX="22" MSB="3" NAME="GPIO_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO_WIDTH-1):0]"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="23" MSB="31" NAME="GPIO2_IO_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="GPIO2_IO_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="gpio_0" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="25" MSB="31" NAME="GPIO2_IO_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_GPIO2_WIDTH-1):0]"/>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="GPIO_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO_IO_I" TRI_O="GPIO_IO_O" TRI_T="GPIO_IO_T" VECFORMULA="[(C_GPIO_WIDTH-1):0]">
|
|
<DESCRIPTION>GPIO1 Data IO</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="gpio_0" IS_THREE_STATE="TRUE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="27" MSB="31" NAME="GPIO2_IO" RIGHT="0" SIGNAME="__NOC__" TRI_I="GPIO2_IO_I" TRI_O="GPIO2_IO_O" TRI_T="GPIO2_IO_T" VECFORMULA="[(C_GPIO2_WIDTH-1):0]">
|
|
<DESCRIPTION>GPIO2 Data IO</DESCRIPTION>
|
|
</PORT>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="gpio_0" TYPE="XIL_AXI_GPIO_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="GPIO_IO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO_IO_T"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GPIO2_IO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GPIO2_IO_T"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="GPIO_IO"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="GPIO2_IO"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2168717312" BASENAME="C_BASEADDR" BASEVALUE="0x81440000" HIGHDECIMAL="2168782847" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8144ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.02.a" INSTANCE="Internal_BRAM" IPTYPE="PERIPHERAL" MHS_INDEX="23" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_bram_ctrl">
|
|
<DESCRIPTION TYPE="SHORT">AXI BRAM Controller</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Attaches BRAM to the AXI</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_bram_ctrl_v1_02_a/doc/axi_bram_ctrl.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4">
|
|
<DESCRIPTION>AXI4 Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="C_S_AXI_BASEADDR" TYPE="std_logic_vector" VALUE="0x4A000000">
|
|
<DESCRIPTION>AXI Slave IP Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="C_S_AXI_HIGHADDR" TYPE="std_logic_vector" VALUE="0x4A00FFFF">
|
|
<DESCRIPTION>AXI Slave IP High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Slave IP Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Slave IP Data Width or BRAM Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="6" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI Slave IP ID Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="7" NAME="C_S_AXI_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Slave AXI Supports Narrow Bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_SINGLE_PORT_BRAM" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Slave Single Port BRAM</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="9" NAME="C_INTERCONNECT_S_AXI_AR_REGISTER" TYPE="INTEGER" VALUE="8">
|
|
<DESCRIPTION>Inteconnect Slave AXI Read Address Channel Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="10" NAME="C_INTERCONNECT_S_AXI_AW_REGISTER" TYPE="INTEGER" VALUE="8">
|
|
<DESCRIPTION>Inteconnect Slave AXI Write Address Channel Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_INTERCONNECT_S_AXI_B_REGISTER" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Inteconnect Slave AXI Write Back Channel Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_INTERCONNECT_S_AXI_R_REGISTER" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Inteconnect Slave AXI Read Data Channel Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="13" NAME="C_INTERCONNECT_S_AXI_W_REGISTER" TYPE="INTEGER" VALUE="8">
|
|
<DESCRIPTION>Inteconnect Slave AXI Write Data Channel Register</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Inteconnect Slave AXI Write Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_INTERCONNECT_S_AXI_READ_ACCEPTANCE" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Inteconnect Slave AXI Read Acceptance</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_S_AXI_CTRL_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI4-Lite Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="17" NAME="C_S_AXI_CTRL_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI4-Lite Slave IP Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_S_AXI_CTRL_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI4-Lite Slave Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="19" NAME="C_S_AXI_CTRL_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>AXI4-Lite Slave IP Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="20" NAME="C_S_AXI_CTRL_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>AXI4-Lite Slave IP High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="21" NAME="C_INTERCONNECT_S_AXI_CTRL_SUPPORTS_READ" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Inteconnect Slave AXI Control Read Support</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_INTERCONNECT_S_AXI_CTRL_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Inteconnect Slave AXI Control Write Support</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_ECC" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Enable ECC Functionality</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_FAULT_INJECT" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Enable AXI4-Lite ECC Fault Injection Registers</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_ECC_ONOFF_RESET_VALUE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Set ECC On/Off Reset Value</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" NAME="C_INTERCONNECT_S_AXI_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC"/>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI:S_AXI_CTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="2" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT DIR="O" MPD_INDEX="0" NAME="ECC_Interrupt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" MPD_INDEX="1" NAME="ECC_UE" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI:S_AXI_CTRL" DEF_SIGNAME="AXI_MM_M_ARESETN" DIR="I" MPD_INDEX="3" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_MM_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWID" SIGNAME="AXI_MM_M_AWID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_MM_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="6" MSB="7" NAME="S_AXI_AWLEN" RIGHT="0" SIGNAME="AXI_MM_M_AWLEN" VECFORMULA="[7 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="7" MSB="2" NAME="S_AXI_AWSIZE" RIGHT="0" SIGNAME="AXI_MM_M_AWSIZE" VECFORMULA="[2 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="8" MSB="1" NAME="S_AXI_AWBURST" RIGHT="0" SIGNAME="AXI_MM_M_AWBURST" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWLOCK" DIR="I" MPD_INDEX="9" NAME="S_AXI_AWLOCK" SIGNAME="AXI_MM_M_AWLOCK"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="10" MSB="3" NAME="S_AXI_AWCACHE" RIGHT="0" SIGNAME="AXI_MM_M_AWCACHE" VECFORMULA="[3 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="11" MSB="2" NAME="S_AXI_AWPROT" RIGHT="0" SIGNAME="AXI_MM_M_AWPROT" VECFORMULA="[2 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWVALID" DIR="I" MPD_INDEX="12" NAME="S_AXI_AWVALID" SIGNAME="AXI_MM_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_AWREADY" DIR="O" MPD_INDEX="13" NAME="S_AXI_AWREADY" SIGNAME="AXI_MM_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="14" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_MM_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="15" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_MM_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH / 8) - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_WLAST" DIR="I" MPD_INDEX="16" NAME="S_AXI_WLAST" SIGNAME="AXI_MM_M_WLAST"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_WVALID" DIR="I" MPD_INDEX="17" NAME="S_AXI_WVALID" SIGNAME="AXI_MM_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_WREADY" DIR="O" MPD_INDEX="18" NAME="S_AXI_WREADY" SIGNAME="AXI_MM_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_BID" DIR="O" MPD_INDEX="19" NAME="S_AXI_BID" SIGNAME="AXI_MM_M_BID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_MM_M_BRESP" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_BVALID" DIR="O" MPD_INDEX="21" NAME="S_AXI_BVALID" SIGNAME="AXI_MM_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_BREADY" DIR="I" MPD_INDEX="22" NAME="S_AXI_BREADY" SIGNAME="AXI_MM_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARID" DIR="I" MPD_INDEX="23" NAME="S_AXI_ARID" SIGNAME="AXI_MM_M_ARID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="24" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_MM_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="25" MSB="7" NAME="S_AXI_ARLEN" RIGHT="0" SIGNAME="AXI_MM_M_ARLEN" VECFORMULA="[7 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="26" MSB="2" NAME="S_AXI_ARSIZE" RIGHT="0" SIGNAME="AXI_MM_M_ARSIZE" VECFORMULA="[2 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="27" MSB="1" NAME="S_AXI_ARBURST" RIGHT="0" SIGNAME="AXI_MM_M_ARBURST" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARLOCK" DIR="I" MPD_INDEX="28" NAME="S_AXI_ARLOCK" SIGNAME="AXI_MM_M_ARLOCK"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="29" MSB="3" NAME="S_AXI_ARCACHE" RIGHT="0" SIGNAME="AXI_MM_M_ARCACHE" VECFORMULA="[3 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="30" MSB="2" NAME="S_AXI_ARPROT" RIGHT="0" SIGNAME="AXI_MM_M_ARPROT" VECFORMULA="[2 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARVALID" DIR="I" MPD_INDEX="31" NAME="S_AXI_ARVALID" SIGNAME="AXI_MM_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_ARREADY" DIR="O" MPD_INDEX="32" NAME="S_AXI_ARREADY" SIGNAME="AXI_MM_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_RID" DIR="O" MPD_INDEX="33" NAME="S_AXI_RID" SIGNAME="AXI_MM_M_RID" VECFORMULA="[(C_S_AXI_ID_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="34" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_MM_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="35" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_MM_M_RRESP" VECFORMULA="[1 : 0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_RVALID" DIR="O" MPD_INDEX="36" NAME="S_AXI_RVALID" SIGNAME="AXI_MM_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_RREADY" DIR="I" MPD_INDEX="37" NAME="S_AXI_RREADY" SIGNAME="AXI_MM_M_RREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_MM_M_RLAST" DIR="O" MPD_INDEX="38" NAME="S_AXI_RLAST" SIGNAME="AXI_MM_M_RLAST"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="39" NAME="S_AXI_CTRL_AWVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="40" NAME="S_AXI_CTRL_AWREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="41" MSB="31" NAME="S_AXI_CTRL_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_ADDR_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="42" NAME="S_AXI_CTRL_WVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="43" NAME="S_AXI_CTRL_WREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="44" MSB="31" NAME="S_AXI_CTRL_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="45" MSB="1" NAME="S_AXI_CTRL_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="46" NAME="S_AXI_CTRL_BVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="47" NAME="S_AXI_CTRL_BREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="48" NAME="S_AXI_CTRL_ARVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="49" NAME="S_AXI_CTRL_ARREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="S_AXI_CTRL_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_ADDR_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="51" NAME="S_AXI_CTRL_RVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="52" NAME="S_AXI_CTRL_RREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="53" MSB="31" NAME="S_AXI_CTRL_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[C_S_AXI_CTRL_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_CTRL" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="54" MSB="1" NAME="S_AXI_CTRL_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="BRAM_PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Rst" DIR="O" MPD_INDEX="55" NAME="BRAM_Rst_A" SIGNAME="Internal_BRAM_port_a_BRAM_Rst"/>
|
|
<PORT BUS="BRAM_PORTA" CLKFREQUENCY="100000000" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Clk" DIR="O" MPD_INDEX="56" NAME="BRAM_Clk_A" SIGNAME="Internal_BRAM_port_a_BRAM_Clk"/>
|
|
<PORT BUS="BRAM_PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_En" DIR="O" MPD_INDEX="57" NAME="BRAM_En_A" SIGNAME="Internal_BRAM_port_a_BRAM_En"/>
|
|
<PORT BUS="BRAM_PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_WEN" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="58" MSB="3" NAME="BRAM_WE_A" RIGHT="0" SIGNAME="Internal_BRAM_port_a_BRAM_WEN" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8 + C_ECC) - 1) : 0]"/>
|
|
<PORT BUS="BRAM_PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Addr" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="59" MSB="31" NAME="BRAM_Addr_A" RIGHT="0" SIGNAME="Internal_BRAM_port_a_BRAM_Addr" VECFORMULA="[(C_S_AXI_ADDR_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="BRAM_PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Dout" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="60" MSB="31" NAME="BRAM_WrData_A" RIGHT="0" SIGNAME="Internal_BRAM_port_a_BRAM_Dout" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
|
|
<PORT BUS="BRAM_PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Din" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="61" MSB="31" NAME="BRAM_RdData_A" RIGHT="0" SIGNAME="Internal_BRAM_port_a_BRAM_Din" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
|
|
<PORT BUS="BRAM_PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Rst" DIR="O" MPD_INDEX="62" NAME="BRAM_Rst_B" SIGNAME="Internal_BRAM_port_b_BRAM_Rst"/>
|
|
<PORT BUS="BRAM_PORTB" CLKFREQUENCY="100000000" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Clk" DIR="O" MPD_INDEX="63" NAME="BRAM_Clk_B" SIGNAME="Internal_BRAM_port_b_BRAM_Clk"/>
|
|
<PORT BUS="BRAM_PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_En" DIR="O" MPD_INDEX="64" NAME="BRAM_En_B" SIGNAME="Internal_BRAM_port_b_BRAM_En"/>
|
|
<PORT BUS="BRAM_PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_WEN" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="65" MSB="3" NAME="BRAM_WE_B" RIGHT="0" SIGNAME="Internal_BRAM_port_b_BRAM_WEN" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8 + C_ECC) - 1) : 0]"/>
|
|
<PORT BUS="BRAM_PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Addr" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="66" MSB="31" NAME="BRAM_Addr_B" RIGHT="0" SIGNAME="Internal_BRAM_port_b_BRAM_Addr" VECFORMULA="[(C_S_AXI_ADDR_WIDTH - 1) : 0]"/>
|
|
<PORT BUS="BRAM_PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Dout" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="67" MSB="31" NAME="BRAM_WrData_B" RIGHT="0" SIGNAME="Internal_BRAM_port_b_BRAM_Dout" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
|
|
<PORT BUS="BRAM_PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Din" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="68" MSB="31" NAME="BRAM_RdData_B" RIGHT="0" SIGNAME="Internal_BRAM_port_b_BRAM_Din" VECFORMULA="[(C_S_AXI_DATA_WIDTH + (8*C_ECC) - 1) : 0]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWLEN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWSIZE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWBURST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWLOCK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWCACHE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWPROT"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARLEN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARSIZE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARBURST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARLOCK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARCACHE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARPROT"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RLAST"/>
|
|
</PORTMAPS>
|
|
<MASTERS>
|
|
<MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
|
|
<MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
|
|
</MASTERS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S_AXI_CTRL" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_WREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_WDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_ARREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_ARADDR"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_CTRL_RREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_CTRL_RRESP"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="Internal_BRAM_port_a" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="2" NAME="BRAM_PORTA" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Rst_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Clk_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_En_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_WE_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Addr_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_WrData_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_RdData_A"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="Internal_BRAM_port_b" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="3" NAME="BRAM_PORTB" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Rst_B"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Clk_B"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_En_B"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_WE_B"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Addr_B"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_WrData_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_RdData_B"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="1241513984" BASENAME="C_S_AXI_BASEADDR" BASEVALUE="0x4A000000" HIGHDECIMAL="1241579519" HIGHNAME="C_S_AXI_HIGHADDR" HIGHVALUE="0x4A00FFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" MINSIZE="0xFFF" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_CTRL_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_CTRL_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="MEMORY" MINSIZE="0x3FF" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_CTRL"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.00.a" INSTANCE="axi_bram_0" IPTYPE="PERIPHERAL" MHS_INDEX="24" MODCLASS="MEMORY" MODTYPE="bram_block">
|
|
<DESCRIPTION TYPE="SHORT">Block RAM (BRAM) Block</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/bram_block_v1_00_a/doc/bram_block.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_MEMSIZE" TYPE="integer" VALUE="0x10000">
|
|
<DESCRIPTION>Size of BRAM(s) in Bytes</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="1" NAME="C_PORT_DWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>Data Width of Port A and B</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_PORT_AWIDTH" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>Address Width of Port A and B</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_NUM_WE" TYPE="integer" VALUE="4">
|
|
<DESCRIPTION>Number of Byte Write Enables</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_FAMILY" TYPE="string" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Rst" DIR="I" MPD_INDEX="0" NAME="BRAM_Rst_A" SIGNAME="Internal_BRAM_port_a_BRAM_Rst"/>
|
|
<PORT BUS="PORTA" CLKFREQUENCY="100000000" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Clk" DIR="I" MPD_INDEX="1" NAME="BRAM_Clk_A" SIGIS="CLK" SIGNAME="Internal_BRAM_port_a_BRAM_Clk"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_EN" DIR="I" MPD_INDEX="2" NAME="BRAM_EN_A" SIGNAME="Internal_BRAM_port_a_BRAM_EN"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="BRAM_WEN_A" RIGHT="3" SIGNAME="Internal_BRAM_port_a_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="4" MSB="0" NAME="BRAM_Addr_A" RIGHT="31" SIGNAME="Internal_BRAM_port_a_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="5" MSB="0" NAME="BRAM_Din_A" RIGHT="31" SIGNAME="Internal_BRAM_port_a_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
<PORT BUS="PORTA" DEF_SIGNAME="Internal_BRAM_port_a_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="BRAM_Dout_A" RIGHT="31" SIGNAME="Internal_BRAM_port_a_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Rst" DIR="I" MPD_INDEX="7" NAME="BRAM_Rst_B" SIGNAME="Internal_BRAM_port_b_BRAM_Rst"/>
|
|
<PORT BUS="PORTB" CLKFREQUENCY="100000000" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Clk" DIR="I" MPD_INDEX="8" NAME="BRAM_Clk_B" SIGIS="CLK" SIGNAME="Internal_BRAM_port_b_BRAM_Clk"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_EN" DIR="I" MPD_INDEX="9" NAME="BRAM_EN_B" SIGNAME="Internal_BRAM_port_b_BRAM_EN"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_WEN" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="10" MSB="0" NAME="BRAM_WEN_B" RIGHT="3" SIGNAME="Internal_BRAM_port_b_BRAM_WEN" VECFORMULA="[0:C_NUM_WE-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Addr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="11" MSB="0" NAME="BRAM_Addr_B" RIGHT="31" SIGNAME="Internal_BRAM_port_b_BRAM_Addr" VECFORMULA="[0:C_PORT_AWIDTH-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Din" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="12" MSB="0" NAME="BRAM_Din_B" RIGHT="31" SIGNAME="Internal_BRAM_port_b_BRAM_Din" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
<PORT BUS="PORTB" DEF_SIGNAME="Internal_BRAM_port_b_BRAM_Dout" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="13" MSB="0" NAME="BRAM_Dout_B" RIGHT="31" SIGNAME="Internal_BRAM_port_b_BRAM_Dout" VECFORMULA="[0:C_PORT_DWIDTH-1]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="Internal_BRAM_port_a" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PORTA" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Rst_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Clk_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_EN_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_WEN_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Addr_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Din_A"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Dout_A"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="Internal_BRAM_port_b" BUSSTD="XIL" BUSSTD_PSF="XIL_BRAM" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="PORTB" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Rst_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Clk_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_EN_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_WEN_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Addr_B"/>
|
|
<PORTMAP DIR="O" PHYSICAL="BRAM_Din_B"/>
|
|
<PORTMAP DIR="I" PHYSICAL="BRAM_Dout_B"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.00.a" INSTANCE="FLASH_util_bus_split_0" IPTYPE="PERIPHERAL" MHS_INDEX="25" MODCLASS="IP" MODTYPE="util_bus_split">
|
|
<DESCRIPTION TYPE="SHORT">Utility Bus Split</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Bus splitting primitive</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/util_bus_split_v1_00_a/doc/util_bus_split.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_SIZE_IN" TYPE="integer" VALUE="32">
|
|
<DESCRIPTION>Vector Size of Input Bus </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_LEFT_POS" TYPE="integer" VALUE="7">
|
|
<DESCRIPTION>The Left Bit Position of The Out1 Output Bus </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_SPLIT" TYPE="integer" VALUE="31">
|
|
<DESCRIPTION>First Bit of The Out2 Output Bus </DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="I" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="31" MHS_INDEX="0" MPD_INDEX="0" MSB="0" NAME="Sig" RIGHT="31" SIGNAME="fpga_0_FLASH_Mem_A_split" VECFORMULA="[0:C_SIZE_IN-1]"/>
|
|
<PORT DIR="O" ENDIAN="BIG" IS_INSTANTIATED="TRUE" LEFT="0" LSB="23" MHS_INDEX="1" MPD_INDEX="1" MSB="0" NAME="Out1" RIGHT="23" SIGNAME="fpga_0_FLASH_Mem_A" VECFORMULA="[C_LEFT_POS:C_SPLIT-1]"/>
|
|
<PORT DIR="O" MPD_INDEX="2" NAME="Out2" SIGNAME="__NOC__" VECFORMULA="[C_SPLIT:C_SIZE_IN-1]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES/>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="FLASH" IPTYPE="PERIPHERAL" MHS_INDEX="26" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_emc">
|
|
<DESCRIPTION TYPE="SHORT">AXI External Memory Controller (SRAM/Flash/Cellular RAM)</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI External Memory Controller (SRAM/Flash/Cellular RAM)</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_emc_v1_01_a/doc/ds762_axi_emc.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Family Supported </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_S_AXI_EN_REG" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>AXI Register Interface Enable </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_S_AXI_REG_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Register Interface Addresses Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_S_AXI_REG_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Register Interface Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_S_AXI_MEM_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI Memory Interface ID Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_S_AXI_MEM_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Memory Interface Addresses Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_S_AXI_MEM_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Memory Interface Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_S_AXI_MEM_PROTOCOL" VALUE="axi4">
|
|
<DESCRIPTION>AXI4 Memory Interface protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_S_AXI_REG_PROTOCOL" VALUE="axi4">
|
|
<DESCRIPTION>AXI4 Register Interface protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="9" NAME="C_AXI_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="10000">
|
|
<DESCRIPTION>axi clock period to calculate wait state pulse widths </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="10" NAME="C_NUM_BANKS_MEM" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Number of Banks </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_NEGEDGE_IOREGS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Include negative edge IO registers </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="12" NAME="C_MEM0_WIDTH" TYPE="INTEGER" VALUE="16">
|
|
<DESCRIPTION>Data Bus Width of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="13" NAME="C_MEM1_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Data Bus Width of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="14" NAME="C_MEM2_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Data Bus Width of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_MEM3_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>Data Bus Width of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="16" NAME="C_INCLUDE_DATAWIDTH_MATCHING_0" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Execute Multiple Memory Accesses To Match Bank 0 Data Bus Width To AXI Data Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="17" NAME="C_INCLUDE_DATAWIDTH_MATCHING_1" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 1 Data Bus Width To AXI Data Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_INCLUDE_DATAWIDTH_MATCHING_2" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 2 Data Bus Width To AXI Data Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="19" NAME="C_INCLUDE_DATAWIDTH_MATCHING_3" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION> Execute Multiple Memory Accesses To Match Bank 3 Data Bus Width To AXI Data Bus Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="20" NAME="C_MEM0_TYPE" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Memory type for Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="21" NAME="C_SYNCH_PIPEDELAY_0" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Pipeline Latency of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_PARITY_TYPE_MEM_0" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Type of parity of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="23" NAME="C_TCEDV_PS_MEM_0" TYPE="INTEGER" VALUE="130000">
|
|
<DESCRIPTION>TCEDV of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="24" NAME="C_TAVDV_PS_MEM_0" TYPE="INTEGER" VALUE="130000">
|
|
<DESCRIPTION>TAVDV of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="25" NAME="C_TPACC_PS_FLASH_0" TYPE="INTEGER" VALUE="25000">
|
|
<DESCRIPTION>TPACC of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="26" NAME="C_THZCE_PS_MEM_0" TYPE="INTEGER" VALUE="35000">
|
|
<DESCRIPTION>THZCE of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="27" NAME="C_THZOE_PS_MEM_0" TYPE="INTEGER" VALUE="7000">
|
|
<DESCRIPTION>THZOE of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="28" NAME="C_TWC_PS_MEM_0" TYPE="INTEGER" VALUE="13000">
|
|
<DESCRIPTION>TWC of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="29" NAME="C_TWP_PS_MEM_0" TYPE="INTEGER" VALUE="70000">
|
|
<DESCRIPTION>TWP of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_TWPH_PS_MEM_0" TYPE="INTEGER" VALUE="12000">
|
|
<DESCRIPTION>TWPH of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="31" NAME="C_TLZWE_PS_MEM_0" TYPE="INTEGER" VALUE="35000">
|
|
<DESCRIPTION>TLZWE of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="32" NAME="C_MEM1_TYPE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Memory type for Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_SYNCH_PIPEDELAY_1" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Pipeline Latency of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_PARITY_TYPE_MEM_1" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Type of parity of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="35" NAME="C_TCEDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TCEDV of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="36" NAME="C_TAVDV_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TAVDV of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="37" NAME="C_TPACC_PS_FLASH_1" TYPE="INTEGER" VALUE="25000">
|
|
<DESCRIPTION>TPACC of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="38" NAME="C_THZCE_PS_MEM_1" TYPE="INTEGER" VALUE="7000">
|
|
<DESCRIPTION>THZCE of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_THZOE_PS_MEM_1" TYPE="INTEGER" VALUE="7000">
|
|
<DESCRIPTION>THZOE of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="40" NAME="C_TWC_PS_MEM_1" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TWC of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_TWP_PS_MEM_1" TYPE="INTEGER" VALUE="12000">
|
|
<DESCRIPTION>TWP of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_TWPH_PS_MEM_1" TYPE="INTEGER" VALUE="12000">
|
|
<DESCRIPTION>TWPH of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="43" NAME="C_TLZWE_PS_MEM_1" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>TLZWE of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_MEM2_TYPE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Memory type for Bank 2</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_SYNCH_PIPEDELAY_2" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Pipeline Latency of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_PARITY_TYPE_MEM_2" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Type of parity of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_TCEDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TCEDV of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_TAVDV_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TAVDV of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_TPACC_PS_FLASH_2" TYPE="INTEGER" VALUE="25000">
|
|
<DESCRIPTION>TPACC of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_THZCE_PS_MEM_2" TYPE="INTEGER" VALUE="7000">
|
|
<DESCRIPTION>THZCE of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_THZOE_PS_MEM_2" TYPE="INTEGER" VALUE="7000">
|
|
<DESCRIPTION>THZOE of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_TWC_PS_MEM_2" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TWC of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_TWP_PS_MEM_2" TYPE="INTEGER" VALUE="12000">
|
|
<DESCRIPTION>TWP of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_TWPH_PS_MEM_2" TYPE="INTEGER" VALUE="12000">
|
|
<DESCRIPTION>TWPH of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="55" NAME="C_TLZWE_PS_MEM_2" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>TLZWE of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="56" NAME="C_MEM3_TYPE" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Memory type for Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_SYNCH_PIPEDELAY_3" TYPE="INTEGER" VALUE="2">
|
|
<DESCRIPTION>Pipeline Latency of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="58" NAME="C_PARITY_TYPE_MEM_3" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Type of parity of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_TCEDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TCEDV of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_TAVDV_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TAVDV of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="61" NAME="C_TPACC_PS_FLASH_3" TYPE="INTEGER" VALUE="25000">
|
|
<DESCRIPTION>TPACC of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="62" NAME="C_THZCE_PS_MEM_3" TYPE="INTEGER" VALUE="7000">
|
|
<DESCRIPTION>THZCE of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="63" NAME="C_THZOE_PS_MEM_3" TYPE="INTEGER" VALUE="7000">
|
|
<DESCRIPTION>THZOE of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="64" NAME="C_TWC_PS_MEM_3" TYPE="INTEGER" VALUE="15000">
|
|
<DESCRIPTION>TWC of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="65" NAME="C_TWP_PS_MEM_3" TYPE="INTEGER" VALUE="12000">
|
|
<DESCRIPTION>TWP of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="66" NAME="C_TWPH_PS_MEM_3" TYPE="INTEGER" VALUE="12000">
|
|
<DESCRIPTION>TWPH of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="67" NAME="C_TLZWE_PS_MEM_3" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>TLZWE of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="68" NAME="C_MAX_MEM_WIDTH" TYPE="INTEGER" VALUE="16">
|
|
<DESCRIPTION>Maximum data bus width of all memory banks</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" MPD_INDEX="69" NAME="C_S_AXI_REG_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Base Address of Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" MPD_INDEX="70" NAME="C_S_AXI_REG_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>High Address of Register </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="71" NAME="C_S_AXI_MEM0_BASEADDR" TYPE="std_logic_vector" VALUE="0x48000000">
|
|
<DESCRIPTION>Base Address of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="72" NAME="C_S_AXI_MEM0_HIGHADDR" TYPE="std_logic_vector" VALUE="0x49FFFFFF">
|
|
<DESCRIPTION>High Address of Bank 0 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="73" NAME="C_S_AXI_MEM1_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Base Address of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="74" NAME="C_S_AXI_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>High Address of Bank 1 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="75" NAME="C_S_AXI_MEM2_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Base Address of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="76" NAME="C_S_AXI_MEM2_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>High Address of Bank 2 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" MPD_INDEX="77" NAME="C_S_AXI_MEM3_BASEADDR" TYPE="std_logic_vector" VALUE="0xffffffff">
|
|
<DESCRIPTION>Base Address of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" MPD_INDEX="78" NAME="C_S_AXI_MEM3_HIGHADDR" TYPE="std_logic_vector" VALUE="0x00000000">
|
|
<DESCRIPTION>High Address of Bank 3 </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" NAME="C_INTERCONNECT_S_AXI_MEM_AW_REGISTER" VALUE="8"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" NAME="C_INTERCONNECT_S_AXI_MEM_AR_REGISTER" VALUE="8"/>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" NAME="C_INTERCONNECT_S_AXI_MEM_MASTERS" VALUE="microblaze_0.M_AXI_DC & microblaze_0.M_AXI_IC"/>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="emc_0" IS_INSTANTIATED="TRUE" LEFT="31" LSB="0" MHS_INDEX="0" MPD_INDEX="55" MSB="31" NAME="Mem_A" RIGHT="0" SIGNAME="fpga_0_FLASH_Mem_A_split" VECFORMULA="[(C_S_AXI_MEM_ADDR_WIDTH-1):0]">
|
|
<DESCRIPTION>Memory Address Bus</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="60" NAME="Mem_WEN" SIGNAME="fpga_0_FLASH_Mem_WEN">
|
|
<DESCRIPTION>Memory Write Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="emc_0" IS_INSTANTIATED="TRUE" LEFT="15" LSB="0" MHS_INDEX="2" MPD_INDEX="67" MSB="15" NAME="Mem_DQ_I" RIGHT="0" SIGNAME="fpga_0_FLASH_Mem_DQ_I" VECFORMULA="[(C_MAX_MEM_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="emc_0" IS_INSTANTIATED="TRUE" LEFT="15" LSB="0" MHS_INDEX="3" MPD_INDEX="68" MSB="15" NAME="Mem_DQ_O" RIGHT="0" SIGNAME="fpga_0_FLASH_Mem_DQ_O" VECFORMULA="[(C_MAX_MEM_WIDTH-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="emc_0" IS_INSTANTIATED="TRUE" LEFT="15" LSB="0" MHS_INDEX="4" MPD_INDEX="69" MSB="15" NAME="Mem_DQ_T" RIGHT="0" SIGNAME="fpga_0_FLASH_Mem_DQ_T" VECFORMULA="[(C_MAX_MEM_WIDTH-1):0]"/>
|
|
<PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="59" NAME="Mem_OEN" SIGNAME="fpga_0_FLASH_Mem_OEN" VECFORMULA="[(C_NUM_BANKS_MEM-1):0]">
|
|
<DESCRIPTION>Memory Output Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="58" NAME="Mem_CEN" SIGNAME="fpga_0_FLASH_Mem_CEN" VECFORMULA="[(C_NUM_BANKS_MEM-1):0]">
|
|
<DESCRIPTION>Memory Chip Enable Active Low</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="63" NAME="Mem_ADV_LDN" SIGNAME="fpga_0_FLASH_Mem_ADV_LDN">
|
|
<DESCRIPTION>Memory Advanced Burst Address/Load New Address</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="emc_0" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="56" NAME="Mem_RPN" SIGNAME="fpga_0_FLASH_Mem_RPN">
|
|
<DESCRIPTION>Memory Reset/Power Down</DESCRIPTION>
|
|
</PORT>
|
|
<PORT BUS="S_AXI_MEM:S_AXI_REG" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT CLKFREQUENCY="100000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="54" NAME="RdClk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="S_AXI_MEM:S_AXI_REG" DEF_SIGNAME="AXI_MM_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_MM_M_ARESETN"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_REG_AWADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_REG_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="3" NAME="S_AXI_REG_AWVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="4" NAME="S_AXI_REG_AWREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_REG_WDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_REG_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_REG_WSTRB" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_S_AXI_REG_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="7" NAME="S_AXI_REG_WVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="8" NAME="S_AXI_REG_WREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_REG_BRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="10" NAME="S_AXI_REG_BVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="11" NAME="S_AXI_REG_BREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_REG_ARADDR" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_REG_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="13" NAME="S_AXI_REG_ARVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="14" NAME="S_AXI_REG_ARREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_REG_RDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_S_AXI_REG_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_REG_RRESP" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="O" IS_VALID="FALSE" MPD_INDEX="17" NAME="S_AXI_REG_RVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_REG" DEF_SIGNAME="__BUS__" DIR="I" IS_VALID="FALSE" MPD_INDEX="18" NAME="S_AXI_REG_RREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="19" MSB="7" NAME="S_AXI_MEM_AWLEN" RIGHT="0" SIGNAME="AXI_MM_M_AWLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="20" MSB="2" NAME="S_AXI_MEM_AWSIZE" RIGHT="0" SIGNAME="AXI_MM_M_AWSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="21" MSB="1" NAME="S_AXI_MEM_AWBURST" RIGHT="0" SIGNAME="AXI_MM_M_AWBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWLOCK" DIR="I" MPD_INDEX="22" NAME="S_AXI_MEM_AWLOCK" SIGNAME="AXI_MM_M_AWLOCK"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="23" MSB="3" NAME="S_AXI_MEM_AWCACHE" RIGHT="0" SIGNAME="AXI_MM_M_AWCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="24" MSB="2" NAME="S_AXI_MEM_AWPROT" RIGHT="0" SIGNAME="AXI_MM_M_AWPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_WLAST" DIR="I" MPD_INDEX="25" NAME="S_AXI_MEM_WLAST" SIGNAME="AXI_MM_M_WLAST"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_BID" DIR="O" MPD_INDEX="26" NAME="S_AXI_MEM_BID" SIGNAME="AXI_MM_M_BID" VECFORMULA="[(C_S_AXI_MEM_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARID" DIR="I" MPD_INDEX="27" NAME="S_AXI_MEM_ARID" SIGNAME="AXI_MM_M_ARID" VECFORMULA="[(C_S_AXI_MEM_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARLEN" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="28" MSB="7" NAME="S_AXI_MEM_ARLEN" RIGHT="0" SIGNAME="AXI_MM_M_ARLEN" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARSIZE" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="29" MSB="2" NAME="S_AXI_MEM_ARSIZE" RIGHT="0" SIGNAME="AXI_MM_M_ARSIZE" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARBURST" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="30" MSB="1" NAME="S_AXI_MEM_ARBURST" RIGHT="0" SIGNAME="AXI_MM_M_ARBURST" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARLOCK" DIR="I" MPD_INDEX="31" NAME="S_AXI_MEM_ARLOCK" SIGNAME="AXI_MM_M_ARLOCK"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARCACHE" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="32" MSB="3" NAME="S_AXI_MEM_ARCACHE" RIGHT="0" SIGNAME="AXI_MM_M_ARCACHE" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARPROT" DIR="I" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="33" MSB="2" NAME="S_AXI_MEM_ARPROT" RIGHT="0" SIGNAME="AXI_MM_M_ARPROT" VECFORMULA="[2:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_RID" DIR="O" MPD_INDEX="34" NAME="S_AXI_MEM_RID" SIGNAME="AXI_MM_M_RID" VECFORMULA="[(C_S_AXI_MEM_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_RLAST" DIR="O" MPD_INDEX="35" NAME="S_AXI_MEM_RLAST" SIGNAME="AXI_MM_M_RLAST"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWID" DIR="I" MPD_INDEX="36" NAME="S_AXI_MEM_AWID" SIGNAME="AXI_MM_M_AWID" VECFORMULA="[(C_S_AXI_MEM_ID_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="37" MSB="31" NAME="S_AXI_MEM_AWADDR" RIGHT="0" SIGNAME="AXI_MM_M_AWADDR" VECFORMULA="[(C_S_AXI_MEM_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWVALID" DIR="I" MPD_INDEX="38" NAME="S_AXI_MEM_AWVALID" SIGNAME="AXI_MM_M_AWVALID"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_AWREADY" DIR="O" MPD_INDEX="39" NAME="S_AXI_MEM_AWREADY" SIGNAME="AXI_MM_M_AWREADY"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="S_AXI_MEM_WDATA" RIGHT="0" SIGNAME="AXI_MM_M_WDATA" VECFORMULA="[(C_S_AXI_MEM_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="41" MSB="3" NAME="S_AXI_MEM_WSTRB" RIGHT="0" SIGNAME="AXI_MM_M_WSTRB" VECFORMULA="[((C_S_AXI_MEM_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_WVALID" DIR="I" MPD_INDEX="42" NAME="S_AXI_MEM_WVALID" SIGNAME="AXI_MM_M_WVALID"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_WREADY" DIR="O" MPD_INDEX="43" NAME="S_AXI_MEM_WREADY" SIGNAME="AXI_MM_M_WREADY"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="44" MSB="1" NAME="S_AXI_MEM_BRESP" RIGHT="0" SIGNAME="AXI_MM_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_BVALID" DIR="O" MPD_INDEX="45" NAME="S_AXI_MEM_BVALID" SIGNAME="AXI_MM_M_BVALID"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_BREADY" DIR="I" MPD_INDEX="46" NAME="S_AXI_MEM_BREADY" SIGNAME="AXI_MM_M_BREADY"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="47" MSB="31" NAME="S_AXI_MEM_ARADDR" RIGHT="0" SIGNAME="AXI_MM_M_ARADDR" VECFORMULA="[(C_S_AXI_MEM_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARVALID" DIR="I" MPD_INDEX="48" NAME="S_AXI_MEM_ARVALID" SIGNAME="AXI_MM_M_ARVALID"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_ARREADY" DIR="O" MPD_INDEX="49" NAME="S_AXI_MEM_ARREADY" SIGNAME="AXI_MM_M_ARREADY"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="S_AXI_MEM_RDATA" RIGHT="0" SIGNAME="AXI_MM_M_RDATA" VECFORMULA="[(C_S_AXI_MEM_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="51" MSB="1" NAME="S_AXI_MEM_RRESP" RIGHT="0" SIGNAME="AXI_MM_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_RVALID" DIR="O" MPD_INDEX="52" NAME="S_AXI_MEM_RVALID" SIGNAME="AXI_MM_M_RVALID"/>
|
|
<PORT BUS="S_AXI_MEM" DEF_SIGNAME="AXI_MM_M_RREADY" DIR="I" MPD_INDEX="53" NAME="S_AXI_MEM_RREADY" SIGNAME="AXI_MM_M_RREADY"/>
|
|
<PORT DIR="O" IOS="emc_0" MPD_INDEX="57" NAME="Mem_CE" SIGNAME="__NOC__" VECFORMULA="[(C_NUM_BANKS_MEM-1):0]">
|
|
<DESCRIPTION>Memory Chip Enable Active High</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="emc_0" LEFT="1" LSB="0" MPD_INDEX="61" MSB="1" NAME="Mem_QWEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_MEM_WIDTH/8)-1):0]">
|
|
<DESCRIPTION>Memory Qualified Write Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="emc_0" LEFT="1" LSB="0" MPD_INDEX="62" MSB="1" NAME="Mem_BEN" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_MEM_WIDTH/8)-1):0]">
|
|
<DESCRIPTION>Memory Byte Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="emc_0" MPD_INDEX="64" NAME="Mem_LBON" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Memory Linear/Interleaved Burst Order</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="emc_0" MPD_INDEX="65" NAME="Mem_CKEN" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Memory Clock Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="emc_0" MPD_INDEX="66" NAME="Mem_RNW" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Memory Read Not Write</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="emc_0" LEFT="1" LSB="0" MPD_INDEX="70" MSB="1" NAME="MEM_DQ_PARITY_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_MEM_WIDTH/8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="emc_0" LEFT="1" LSB="0" MPD_INDEX="71" MSB="1" NAME="MEM_DQ_PARITY_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_MEM_WIDTH/8)-1):0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="emc_0" LEFT="1" LSB="0" MPD_INDEX="72" MSB="1" NAME="MEM_DQ_PARITY_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[((C_MAX_MEM_WIDTH/8)-1):0]"/>
|
|
<PORT DIR="O" IOS="emc_0" IS_VALID="FALSE" MPD_INDEX="73" NAME="Mem_CRE" SIGNAME="__NOC__">
|
|
<DESCRIPTION>Memory Clock Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="emc_0" IS_THREE_STATE="TRUE" LEFT="15" LSB="0" MPD_INDEX="74" MSB="15" NAME="Mem_DQ" RIGHT="0" SIGNAME="__NOC__" TRI_I="Mem_DQ_I" TRI_O="Mem_DQ_O" TRI_T="Mem_DQ_T" VECFORMULA="[(C_MAX_MEM_WIDTH-1):0]">
|
|
<DESCRIPTION>Memory Data Bus</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="emc_0" IS_THREE_STATE="TRUE" LEFT="1" LSB="0" MPD_INDEX="75" MSB="1" NAME="MEM_DQ_PARITY" RIGHT="0" SIGNAME="__NOC__" TRI_I="MEM_DQ_PARITY_I" TRI_O="MEM_DQ_PARITY_O" TRI_T="MEM_DQ_PARITY_T" VECFORMULA="[((C_MAX_MEM_WIDTH/8)-1):0]">
|
|
<DESCRIPTION>Memory Data Parity Bus</DESCRIPTION>
|
|
</PORT>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_MEM" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWLEN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWSIZE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWBURST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWLOCK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWCACHE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWPROT"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_WLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_BID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARLEN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARSIZE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARBURST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARLOCK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARCACHE"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARPROT"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_RID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_RLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_MEM_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_MEM_RREADY"/>
|
|
</PORTMAPS>
|
|
<MASTERS>
|
|
<MASTER BUSINTERFACE="M_AXI_DC" INSTANCE="microblaze_0"/>
|
|
<MASTER BUSINTERFACE="M_AXI_IC" INSTANCE="microblaze_0"/>
|
|
</MASTERS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_VALID="FALSE" MPD_INDEX="1" NAME="S_AXI_REG" PROTOCOL="AXI4" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_REG_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_REG_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="emc_0" TYPE="XIL_AXI_EMC_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_A"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_WEN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="Mem_DQ_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_DQ_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_DQ_T"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_OEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_CEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_ADV_LDN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_RPN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_CE"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_QWEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_BEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_LBON"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_CKEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_RNW"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MEM_DQ_PARITY_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MEM_DQ_PARITY_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MEM_DQ_PARITY_T"/>
|
|
<PORTMAP DIR="O" PHYSICAL="Mem_CRE"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="Mem_DQ"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="MEM_DQ_PARITY"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_REG_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_REG_HIGHADDR" HIGHVALUE="0x00000000" IS_VALID="FALSE" MEMTYPE="REGISTER" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_REG"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="1207959552" BASENAME="C_S_AXI_MEM0_BASEADDR" BASEVALUE="0x48000000" HIGHDECIMAL="1241513983" HIGHNAME="C_S_AXI_MEM0_HIGHADDR" HIGHVALUE="0x49FFFFFF" IS_CACHEABLE="TRUE" MEMTYPE="MEMORY" SIZE="33554432" SIZEABRV="32M">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_MEM"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_MEM1_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_MEM1_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_MEM"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_MEM2_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_MEM2_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_MEM"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
<MEMRANGE BASEDECIMAL="4294967295" BASENAME="C_S_AXI_MEM3_BASEADDR" BASEVALUE="0xffffffff" HIGHDECIMAL="0" HIGHNAME="C_S_AXI_MEM3_HIGHADDR" HIGHVALUE="0x00000000" IS_CACHEABLE="TRUE" IS_VALID="FALSE" MEMTYPE="MEMORY" SIZE="0" SIZEABRV="U">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_MEM"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
</MODULE>
|
|
<MODULE HWVERSION="4.00.a" INSTANCE="AXI_DMA_Ethernet" IPTYPE="PERIPHERAL" MHS_INDEX="27" MODCLASS="PERIPHERAL" MODTYPE="axi_dma">
|
|
<DESCRIPTION TYPE="SHORT">AXI DMA Engine</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">AXI MemoryMap to/from AXI Stream Direct Memory Access Engine</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_dma_v4_00_a/doc/axi_dma_ds781.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER MPD_INDEX="0" NAME="C_S_AXI_LITE_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Lite Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_S_AXI_LITE_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Lite Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="2" NAME="C_DLYTMR_RESOLUTION" TYPE="INTEGER" VALUE="1250">
|
|
<DESCRIPTION>Delay Timer Counter Resolution </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="3" NAME="C_PRMRY_IS_ACLK_ASYNC" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Primary clock Is Asynchronous </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_INCLUDE_SG" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include Scatter Gather Engine</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="5" NAME="C_SG_INCLUDE_DESC_QUEUE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include Scatter Gather Descriptor Queuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="6" NAME="C_SG_INCLUDE_STSCNTRL_STRM" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include AXI Status and Control Streams</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="7" NAME="C_SG_USE_STSAPP_LENGTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Use Status Stream App Length</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="8" NAME="C_SG_LENGTH_WIDTH" TYPE="INTEGER" VALUE="16">
|
|
<DESCRIPTION>Buffer Length Field Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_M_AXI_SG_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI SG Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_M_AXI_SG_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI SG Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="11" NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Control Stream Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="12" NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Status Stream Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="13" NAME="C_INCLUDE_MM2S" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include MM2S Channel</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="14" NAME="C_INCLUDE_MM2S_DRE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include MM2S Data Realignment Engine</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="15" NAME="C_MM2S_BURST_SIZE" TYPE="INTEGER" VALUE="16">
|
|
<DESCRIPTION>Maximum Memory Map Burst Size for MM2S</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_M_AXI_MM2S_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>MM2S Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="17" NAME="C_M_AXI_MM2S_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>MM2S Memory Map Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_M_AXIS_MM2S_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>MM2S Stream Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="19" NAME="C_INCLUDE_S2MM" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include S2MM Channel</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="20" NAME="C_INCLUDE_S2MM_DRE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include S2MM Data Realignment Engine</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="21" NAME="C_S2MM_BURST_SIZE" TYPE="INTEGER" VALUE="16">
|
|
<DESCRIPTION>Maximum Memory Map Burst Size for S2MM (data beats)</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="22" NAME="C_M_AXI_S2MM_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>S2MM Address Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="23" NAME="C_M_AXI_S2MM_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>S2MM Memory Map Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="24" NAME="C_S_AXIS_S2MM_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>S2MM Stream Data Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="25" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="26" NAME="C_BASEADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x80000000">
|
|
<DESCRIPTION>Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="27" NAME="C_HIGHADDR" TYPE="STD_LOGIC_VECTOR" VALUE="0x8000FFFF">
|
|
<DESCRIPTION>High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="28" NAME="C_S_AXI_LITE_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
|
|
<DESCRIPTION>AXI Lite Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="29" NAME="C_M_AXI_SG_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>AXI Scatter Gather Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="30" NAME="C_M_AXI_MM2S_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>AXI MM2S Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="31" NAME="C_M_AXI_S2MM_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>AXI S2MM Clock Frequency</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="32" NAME="C_S_AXI_LITE_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI Lite Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="33" NAME="C_S_AXI_LITE_SUPPORTS_READ" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI Lite Supports Read Access</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="34" NAME="C_S_AXI_LITE_SUPPORTS_WRITE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI Lite Supports Write Access</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="35" NAME="C_M_AXI_SG_PROTOCOL" TYPE="STRING" VALUE="AXI4">
|
|
<DESCRIPTION>AXI SG Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="36" NAME="C_M_AXI_SG_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>AXI SG Support Threads</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="37" NAME="C_M_AXI_SG_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="38" NAME="C_M_AXI_SG_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>AXI SG Supports Narrow Bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_M_AXI_SG_SUPPORTS_READ" TYPE="STRING" VALUE="1">
|
|
<DESCRIPTION>AXI SG Generates Read Accesses</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="40" NAME="C_M_AXI_SG_SUPPORTS_WRITE" TYPE="STRING" VALUE="1">
|
|
<DESCRIPTION>AXI SG Generates Write Accesses</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="41" NAME="C_M_AXI_MM2S_PROTOCOL" TYPE="STRING" VALUE="AXI4">
|
|
<DESCRIPTION>AXI MM2S Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="42" NAME="C_M_AXI_MM2S_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>AXI MM2S Support Threads</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="43" NAME="C_M_AXI_MM2S_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI MM2S Thread ID Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="44" NAME="C_M_AXI_MM2S_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>AXI MM2S Supports Narrow Bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="45" NAME="C_M_AXI_MM2S_SUPPORTS_READ" TYPE="STRING" VALUE="1">
|
|
<DESCRIPTION>AXI MM2S Generates Read Accesses</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="46" NAME="C_M_AXI_MM2S_SUPPORTS_WRITE" TYPE="STRING" VALUE="0">
|
|
<DESCRIPTION>AXI MM2S Generates Write Accesses</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="47" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING" TYPE="INTEGER" VALUE="4">
|
|
<DESCRIPTION>AXI MM2S Interface Read Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="48" NAME="C_INTERCONNECT_M_AXI_MM2S_READ_FIFO_DEPTH" TYPE="INTEGER" VALUE="512">
|
|
<DESCRIPTION>AXI MM2S Interface Read FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="49" NAME="C_M_AXI_S2MM_PROTOCOL" TYPE="STRING" VALUE="AXI4">
|
|
<DESCRIPTION>AXI S2MM Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="50" NAME="C_M_AXI_S2MM_SUPPORTS_THREADS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>AXI S2MM Support Threads</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="51" NAME="C_M_AXI_S2MM_THREAD_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI S2MM Thread ID Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="52" NAME="C_M_AXI_S2MM_SUPPORTS_NARROW_BURST" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>AXI S2MM Supports Narrow Bursts</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="53" NAME="C_M_AXI_S2MM_SUPPORTS_WRITE" TYPE="STRING" VALUE="1">
|
|
<DESCRIPTION>AXI S2MM Generates Write Accesses</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="54" NAME="C_M_AXI_S2MM_SUPPORTS_READ" TYPE="STRING" VALUE="0">
|
|
<DESCRIPTION>AXI S2MM Generates Read Accesses</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="55" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_ISSUING" TYPE="INTEGER" VALUE="4">
|
|
<DESCRIPTION>AXI S2MM Interface Write Issuing</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="56" NAME="C_INTERCONNECT_M_AXI_S2MM_WRITE_FIFO_DEPTH" TYPE="INTEGER" VALUE="512">
|
|
<DESCRIPTION>AXI S2MM Interface Write FIFO Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="57" NAME="C_M_AXIS_MM2S_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
|
|
<DESCRIPTION>AXI MM2S Stream Interface Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="58" NAME="C_S_AXIS_S2MM_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
|
|
<DESCRIPTION>AXI S2MM Stream Interface Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="59" NAME="C_M_AXIS_MM2S_CNTRL_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
|
|
<DESCRIPTION>AXI MM2S Control Stream Interface Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="60" NAME="C_S_AXIS_S2MM_STS_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
|
|
<DESCRIPTION>AXI S2MM Status Stream Interface Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI_LITE" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="s_axi_lite_aclk" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT BUS="M_AXI_SG" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="m_axi_sg_aclk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="M_AXI_MM2S:M_AXIS_MM2S_CNTRL" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="m_axi_mm2s_aclk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="M_AXI_S2MM:S_AXIS_S2MM_STS" CLKFREQUENCY="100000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="m_axi_s2mm_aclk" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="63" NAME="mm2s_prmry_reset_out_n" SIGNAME="AXI_STR_TXD_ARESETN"/>
|
|
<PORT BUS="M_AXIS_MM2S_CNTRL" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="69" NAME="mm2s_cntrl_reset_out_n" SIGNAME="AXI_STR_TXC_ARESETN"/>
|
|
<PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="91" NAME="s2mm_prmry_reset_out_n" SIGNAME="AXI_STR_RXD_ARESETN"/>
|
|
<PORT BUS="S_AXIS_S2MM_STS" DEF_SIGNAME="RESET_OUT_N" DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="97" NAME="s2mm_sts_reset_out_n" SIGNAME="AXI_STR_RXS_ARESETN"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="103" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="AXI_DMA_Ethernet_mm2s_introut"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="104" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="AXI_DMA_Ethernet_s2mm_introut"/>
|
|
<PORT BUS="S_AXI_LITE:M_AXI_SG:M_AXI_MM2S:M_AXI_S2MM:S_AXIS_S2MM_STS:M_AXIS_MM2S_CNTRL:M_AXIS_MM2S:S_AXIS_S2MM" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="4" NAME="axi_resetn" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="5" NAME="s_axi_lite_awvalid" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="6" NAME="s_axi_lite_awready" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="7" MSB="31" NAME="s_axi_lite_awaddr" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="8" NAME="s_axi_lite_wvalid" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="9" NAME="s_axi_lite_wready" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="10" MSB="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="11" MSB="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="12" NAME="s_axi_lite_bvalid" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="13" NAME="s_axi_lite_bready" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="s_axi_lite_arvalid" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="s_axi_lite_arready" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="s_axi_lite_araddr" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[C_S_AXI_LITE_ADDR_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="17" NAME="s_axi_lite_rvalid" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="18" NAME="s_axi_lite_rready" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="19" MSB="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[C_S_AXI_LITE_DATA_WIDTH-1:0]"/>
|
|
<PORT BUS="S_AXI_LITE" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="20" MSB="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="21" MSB="31" NAME="m_axi_sg_awaddr" RIGHT="0" SIGNAME="AXI_DMA_SG_S_AWADDR" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/>
|
|
<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="m_axi_sg_awlen" RIGHT="0" SIGNAME="AXI_DMA_SG_S_AWLEN" VECFORMULA="[7:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="23" MSB="2" NAME="m_axi_sg_awsize" RIGHT="0" SIGNAME="AXI_DMA_SG_S_AWSIZE" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="24" MSB="1" NAME="m_axi_sg_awburst" RIGHT="0" SIGNAME="AXI_DMA_SG_S_AWBURST" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="25" MSB="2" NAME="m_axi_sg_awprot" RIGHT="0" SIGNAME="AXI_DMA_SG_S_AWPROT" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="26" MSB="3" NAME="m_axi_sg_awcache" RIGHT="0" SIGNAME="AXI_DMA_SG_S_AWCACHE" VECFORMULA="[3:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWVALID" DIR="O" MPD_INDEX="27" NAME="m_axi_sg_awvalid" SIGNAME="AXI_DMA_SG_S_AWVALID"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_AWREADY" DIR="I" MPD_INDEX="28" NAME="m_axi_sg_awready" SIGNAME="AXI_DMA_SG_S_AWREADY"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="29" MSB="31" NAME="m_axi_sg_wdata" RIGHT="0" SIGNAME="AXI_DMA_SG_S_WDATA" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="30" MSB="3" NAME="m_axi_sg_wstrb" RIGHT="0" SIGNAME="AXI_DMA_SG_S_WSTRB" VECFORMULA="[(C_M_AXI_SG_DATA_WIDTH/8)-1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_WLAST" DIR="O" MPD_INDEX="31" NAME="m_axi_sg_wlast" SIGNAME="AXI_DMA_SG_S_WLAST"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_WVALID" DIR="O" MPD_INDEX="32" NAME="m_axi_sg_wvalid" SIGNAME="AXI_DMA_SG_S_WVALID"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_WREADY" DIR="I" MPD_INDEX="33" NAME="m_axi_sg_wready" SIGNAME="AXI_DMA_SG_S_WREADY"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="34" MSB="1" NAME="m_axi_sg_bresp" RIGHT="0" SIGNAME="AXI_DMA_SG_S_BRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_BVALID" DIR="I" MPD_INDEX="35" NAME="m_axi_sg_bvalid" SIGNAME="AXI_DMA_SG_S_BVALID"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_BREADY" DIR="O" MPD_INDEX="36" NAME="m_axi_sg_bready" SIGNAME="AXI_DMA_SG_S_BREADY"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="37" MSB="31" NAME="m_axi_sg_araddr" RIGHT="0" SIGNAME="AXI_DMA_SG_S_ARADDR" VECFORMULA="[C_M_AXI_SG_ADDR_WIDTH-1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="38" MSB="7" NAME="m_axi_sg_arlen" RIGHT="0" SIGNAME="AXI_DMA_SG_S_ARLEN" VECFORMULA="[7:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="39" MSB="2" NAME="m_axi_sg_arsize" RIGHT="0" SIGNAME="AXI_DMA_SG_S_ARSIZE" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="40" MSB="1" NAME="m_axi_sg_arburst" RIGHT="0" SIGNAME="AXI_DMA_SG_S_ARBURST" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="41" MSB="2" NAME="m_axi_sg_arprot" RIGHT="0" SIGNAME="AXI_DMA_SG_S_ARPROT" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="42" MSB="3" NAME="m_axi_sg_arcache" RIGHT="0" SIGNAME="AXI_DMA_SG_S_ARCACHE" VECFORMULA="[3:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARVALID" DIR="O" MPD_INDEX="43" NAME="m_axi_sg_arvalid" SIGNAME="AXI_DMA_SG_S_ARVALID"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_ARREADY" DIR="I" MPD_INDEX="44" NAME="m_axi_sg_arready" SIGNAME="AXI_DMA_SG_S_ARREADY"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="45" MSB="31" NAME="m_axi_sg_rdata" RIGHT="0" SIGNAME="AXI_DMA_SG_S_RDATA" VECFORMULA="[C_M_AXI_SG_DATA_WIDTH-1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="46" MSB="1" NAME="m_axi_sg_rresp" RIGHT="0" SIGNAME="AXI_DMA_SG_S_RRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_RLAST" DIR="I" MPD_INDEX="47" NAME="m_axi_sg_rlast" SIGNAME="AXI_DMA_SG_S_RLAST"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_RVALID" DIR="I" MPD_INDEX="48" NAME="m_axi_sg_rvalid" SIGNAME="AXI_DMA_SG_S_RVALID"/>
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<PORT BUS="M_AXI_SG" DEF_SIGNAME="AXI_DMA_SG_S_RREADY" DIR="O" MPD_INDEX="49" NAME="m_axi_sg_rready" SIGNAME="AXI_DMA_SG_S_RREADY"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="50" MSB="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGNAME="AXI_DMA_MM_S_ARADDR" VECFORMULA="[C_M_AXI_MM2S_ADDR_WIDTH-1:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="51" MSB="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGNAME="AXI_DMA_MM_S_ARLEN" VECFORMULA="[7:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="52" MSB="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGNAME="AXI_DMA_MM_S_ARSIZE" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="53" MSB="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGNAME="AXI_DMA_MM_S_ARBURST" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="54" MSB="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGNAME="AXI_DMA_MM_S_ARPROT" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="55" MSB="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGNAME="AXI_DMA_MM_S_ARCACHE" VECFORMULA="[3:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARVALID" DIR="O" MPD_INDEX="56" NAME="m_axi_mm2s_arvalid" SIGNAME="AXI_DMA_MM_S_ARVALID"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_ARREADY" DIR="I" MPD_INDEX="57" NAME="m_axi_mm2s_arready" SIGNAME="AXI_DMA_MM_S_ARREADY"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_RDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="58" MSB="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGNAME="AXI_DMA_MM_S_RDATA" VECFORMULA="[C_M_AXI_MM2S_DATA_WIDTH-1:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_RRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="59" MSB="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGNAME="AXI_DMA_MM_S_RRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_RLAST" DIR="I" MPD_INDEX="60" NAME="m_axi_mm2s_rlast" SIGNAME="AXI_DMA_MM_S_RLAST"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_RVALID" DIR="I" MPD_INDEX="61" NAME="m_axi_mm2s_rvalid" SIGNAME="AXI_DMA_MM_S_RVALID"/>
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<PORT BUS="M_AXI_MM2S" DEF_SIGNAME="AXI_DMA_MM_S_RREADY" DIR="O" MPD_INDEX="62" NAME="m_axi_mm2s_rready" SIGNAME="AXI_DMA_MM_S_RREADY"/>
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<PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="64" MSB="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TDATA" VECFORMULA="[C_M_AXIS_MM2S_TDATA_WIDTH-1:0]"/>
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<PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="65" MSB="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_TDATA_WIDTH/8)-1:0]"/>
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<PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TVALID" DIR="O" MPD_INDEX="66" NAME="m_axis_mm2s_tvalid" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TVALID"/>
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<PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TREADY" DIR="I" MPD_INDEX="67" NAME="m_axis_mm2s_tready" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TREADY"/>
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<PORT BUS="M_AXIS_MM2S" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TLAST" DIR="O" MPD_INDEX="68" NAME="m_axis_mm2s_tlast" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TLAST"/>
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<PORT BUS="M_AXIS_MM2S_CNTRL" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="70" MSB="31" NAME="m_axis_mm2s_cntrl_tdata" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TDATA" VECFORMULA="[C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1:0]"/>
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<PORT BUS="M_AXIS_MM2S_CNTRL" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="71" MSB="3" NAME="m_axis_mm2s_cntrl_tkeep" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TKEEP" VECFORMULA="[(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1:0]"/>
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<PORT BUS="M_AXIS_MM2S_CNTRL" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TVALID" DIR="O" MPD_INDEX="72" NAME="m_axis_mm2s_cntrl_tvalid" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TVALID"/>
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<PORT BUS="M_AXIS_MM2S_CNTRL" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TREADY" DIR="I" MPD_INDEX="73" NAME="m_axis_mm2s_cntrl_tready" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TREADY"/>
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<PORT BUS="M_AXIS_MM2S_CNTRL" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TLAST" DIR="O" MPD_INDEX="74" NAME="m_axis_mm2s_cntrl_tlast" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TLAST"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWADDR" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="75" MSB="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGNAME="AXI_DMA_MM_S_AWADDR" VECFORMULA="[C_M_AXI_S2MM_ADDR_WIDTH-1:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWLEN" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="76" MSB="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGNAME="AXI_DMA_MM_S_AWLEN" VECFORMULA="[7:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWSIZE" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="77" MSB="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGNAME="AXI_DMA_MM_S_AWSIZE" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWBURST" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="78" MSB="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGNAME="AXI_DMA_MM_S_AWBURST" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWPROT" DIR="O" ENDIAN="LITTLE" LEFT="2" LSB="0" MPD_INDEX="79" MSB="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGNAME="AXI_DMA_MM_S_AWPROT" VECFORMULA="[2:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWCACHE" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGNAME="AXI_DMA_MM_S_AWCACHE" VECFORMULA="[3:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWVALID" DIR="O" MPD_INDEX="81" NAME="m_axi_s2mm_awvalid" SIGNAME="AXI_DMA_MM_S_AWVALID"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_AWREADY" DIR="I" MPD_INDEX="82" NAME="m_axi_s2mm_awready" SIGNAME="AXI_DMA_MM_S_AWREADY"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_WDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="83" MSB="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGNAME="AXI_DMA_MM_S_WDATA" VECFORMULA="[C_M_AXI_S2MM_DATA_WIDTH-1:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_WSTRB" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="84" MSB="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGNAME="AXI_DMA_MM_S_WSTRB" VECFORMULA="[(C_M_AXI_S2MM_DATA_WIDTH/8)-1:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_WLAST" DIR="O" MPD_INDEX="85" NAME="m_axi_s2mm_wlast" SIGNAME="AXI_DMA_MM_S_WLAST"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_WVALID" DIR="O" MPD_INDEX="86" NAME="m_axi_s2mm_wvalid" SIGNAME="AXI_DMA_MM_S_WVALID"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_WREADY" DIR="I" MPD_INDEX="87" NAME="m_axi_s2mm_wready" SIGNAME="AXI_DMA_MM_S_WREADY"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_BRESP" DIR="I" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="88" MSB="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGNAME="AXI_DMA_MM_S_BRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_BVALID" DIR="I" MPD_INDEX="89" NAME="m_axi_s2mm_bvalid" SIGNAME="AXI_DMA_MM_S_BVALID"/>
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<PORT BUS="M_AXI_S2MM" DEF_SIGNAME="AXI_DMA_MM_S_BREADY" DIR="O" MPD_INDEX="90" NAME="m_axi_s2mm_bready" SIGNAME="AXI_DMA_MM_S_BREADY"/>
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<PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="92" MSB="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TDATA" VECFORMULA="[C_S_AXIS_S2MM_TDATA_WIDTH-1:0]"/>
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<PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="93" MSB="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TKEEP" VECFORMULA="[(C_S_AXIS_S2MM_TDATA_WIDTH/8)-1:0]"/>
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<PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TVALID" DIR="I" MPD_INDEX="94" NAME="s_axis_s2mm_tvalid" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TVALID"/>
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<PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TREADY" DIR="O" MPD_INDEX="95" NAME="s_axis_s2mm_tready" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TREADY"/>
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<PORT BUS="S_AXIS_S2MM" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TLAST" DIR="I" MPD_INDEX="96" NAME="s_axis_s2mm_tlast" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TLAST"/>
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<PORT BUS="S_AXIS_S2MM_STS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="98" MSB="31" NAME="s_axis_s2mm_sts_tdata" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TDATA" VECFORMULA="[C_S_AXIS_S2MM_STS_TDATA_WIDTH-1:0]"/>
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<PORT BUS="S_AXIS_S2MM_STS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="99" MSB="3" NAME="s_axis_s2mm_sts_tkeep" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TKEEP" VECFORMULA="[(C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1:0]"/>
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<PORT BUS="S_AXIS_S2MM_STS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TVALID" DIR="I" MPD_INDEX="100" NAME="s_axis_s2mm_sts_tvalid" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TVALID"/>
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<PORT BUS="S_AXIS_S2MM_STS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TREADY" DIR="O" MPD_INDEX="101" NAME="s_axis_s2mm_sts_tready" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TREADY"/>
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<PORT BUS="S_AXIS_S2MM_STS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TLAST" DIR="I" MPD_INDEX="102" NAME="s_axis_s2mm_sts_tlast" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TLAST"/>
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|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_LITE" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_awvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_awready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_awaddr"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_wvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_wready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_wdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_bresp"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_bvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_bready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_arvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_arready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_araddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axi_lite_rready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axi_lite_rresp"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_SG" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="M_AXI_SG" PROTOCOL="AXI4" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_awaddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_awlen"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_awsize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_awburst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_awprot"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_awcache"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_awvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_awready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_wdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_wstrb"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_wlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_wvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_wready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_bresp"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_bvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_bready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_araddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_arlen"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_arsize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_arburst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_arprot"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_arcache"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_arvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_arready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_rdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_rresp"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_rlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_sg_rvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_sg_rready"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="M_AXI_MM2S" PROTOCOL="AXI4" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_araddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arlen"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arsize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arburst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arprot"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arcache"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_arvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_arready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rresp"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rlast"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_rvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_mm2s_rready"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="6" NAME="M_AXIS_MM2S_CNTRL" PROTOCOL="XIL_AXI_STREAM_ETH_CTRL" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_mm2s_aclk"/>
|
|
<PORTMAP DIR="O" PHYSICAL="mm2s_cntrl_reset_out_n"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tkeep"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_cntrl_tready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_cntrl_tlast"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_MM" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="M_AXI_S2MM" PROTOCOL="AXI4" TYPE="MASTER">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awaddr"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awlen"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awsize"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awburst"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awprot"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awcache"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_awvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_awready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wstrb"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wlast"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_wvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_wready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bresp"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_bvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axi_s2mm_bready"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="Soft_Ethernet_MAC_AXI_STR_RXS" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="7" NAME="S_AXIS_S2MM_STS" PROTOCOL="XIL_AXI_STREAM_ETH_CTRL" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axi_s2mm_aclk"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s2mm_sts_reset_out_n"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tkeep"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_sts_tready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_sts_tlast"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_Ethernet_M_AXIS_MM2S" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="M_AXIS_MM2S" PROTOCOL="XIL_AXI_STREAM_ETH_DATA" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="mm2s_prmry_reset_out_n"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tdata"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tkeep"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tvalid"/>
|
|
<PORTMAP DIR="I" PHYSICAL="m_axis_mm2s_tready"/>
|
|
<PORTMAP DIR="O" PHYSICAL="m_axis_mm2s_tlast"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="Soft_Ethernet_MAC_AXI_STR_RXD" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="5" NAME="S_AXIS_S2MM" PROTOCOL="XIL_AXI_STREAM_ETH_DATA" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="s2mm_prmry_reset_out_n"/>
|
|
<PORTMAP DIR="I" PHYSICAL="axi_resetn"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tdata"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tkeep"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tvalid"/>
|
|
<PORTMAP DIR="O" PHYSICAL="s_axis_s2mm_tready"/>
|
|
<PORTMAP DIR="I" PHYSICAL="s_axis_s2mm_tlast"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2147483648" BASENAME="C_BASEADDR" BASEVALUE="0x80000000" HIGHDECIMAL="2147549183" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8000FFFF" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI_LITE"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<INTERRUPTINFO TYPE="SOURCE">
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="6"/>
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="7"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE HWVERSION="3.00.a" INSTANCE="Soft_Ethernet_MAC" IPTYPE="PERIPHERAL" MHS_INDEX="28" MODCLASS="PERIPHERAL" MODTYPE="axi_ethernet">
|
|
<DESCRIPTION TYPE="SHORT">AXI Ethernet Embedded IP</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Embedded Ethernet core that implements a Tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC to support MII/GMII/SGMII/RGMII/1000Base-X PHY types</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_ethernet_v3_00_a/doc/ds759_axi_ethernet.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO EXPIRESON="Does not expire" ICON_NAME="ps_pay_core_2" STATE="VALID" TYPE="Bought"/>
|
|
<PARAMETERS>
|
|
<PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" TYPE="STRING" VALUE="AXI4LITE">
|
|
<DESCRIPTION>AXI Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="1" NAME="C_AXI_STR_TXC_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="2" NAME="C_AXI_STR_TXD_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="3" NAME="C_AXI_STR_RXS_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_AXI_STR_RXD_TDATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Stream Bus Width</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_AXI_STR_TXC_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
|
|
<DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="6" NAME="C_AXI_STR_TXD_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
|
|
<DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="7" NAME="C_AXI_STR_RXS_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_CTRL">
|
|
<DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="8" NAME="C_AXI_STR_RXD_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_DATA">
|
|
<DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="9" NAME="C_AXI_STR_AVBTX_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_AVB_TX">
|
|
<DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="10" NAME="C_AXI_STR_AVBRX_PROTOCOL" TYPE="STRING" VALUE="XIL_AXI_STREAM_ETH_AVB_RX">
|
|
<DESCRIPTION>AXI Stream Protocol</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="11" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>Device Family</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="12" NAME="C_S_AXI_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="50000000">
|
|
<DESCRIPTION>AXI Clock Freq in HZ</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="13" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x86000000">
|
|
<DESCRIPTION>Base Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="14" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8607FFFF">
|
|
<DESCRIPTION>High Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="15" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Address Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="16" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>AXI Data Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="17" NAME="C_S_AXI_ID_WIDTH" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>AXI ID Width </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="18" NAME="C_TRANS" TYPE="STRING" VALUE="A">
|
|
<DESCRIPTION>Spartan 6 Transceiver Side</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="19" NAME="C_PHYADDR" TYPE="std_logic_vector" VALUE="0b00001">
|
|
<DESCRIPTION>PHY Address</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="20" NAME="C_INCLUDE_IO" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Include IO and BUFG as Needed for the PHY Interface Selected</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="21" NAME="C_TYPE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Type of TEMAC</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="22" NAME="C_PHY_TYPE" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Physical Interface Type</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="23" NAME="C_HALFDUP" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Enable Half Duplex mode</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="24" NAME="C_TXMEM" TYPE="INTEGER" VALUE="4096">
|
|
<DESCRIPTION>TX Memory Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="25" NAME="C_RXMEM" TYPE="INTEGER" VALUE="4096">
|
|
<DESCRIPTION>RX Memory Depth</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="26" NAME="C_TXCSUM" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Enable TX Checksum Offload</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="27" NAME="C_RXCSUM" TYPE="INTEGER" VALUE="1">
|
|
<DESCRIPTION>Enable RX Checksum Offload</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="14" MPD_INDEX="28" NAME="C_TXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Transmit VLAN translation</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="29" NAME="C_RXVLAN_TRAN" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Receive VLAN translation</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="30" NAME="C_TXVLAN_TAG" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Transmit VLAN tagging</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="31" NAME="C_RXVLAN_TAG" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Receive VLAN tagging</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="18" MPD_INDEX="32" NAME="C_TXVLAN_STRP" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Transmit VLAN stripping</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="33" NAME="C_RXVLAN_STRP" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Receive VLAN stripping</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="34" NAME="C_MCAST_EXTEND" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Receive Extended Multicast Address Filtering</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="35" NAME="C_STATS" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Statistics Counters</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="36" NAME="C_AVB" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Audio Video Bridging (AVB) - license required</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="37" NAME="C_SIMULATION" TYPE="INTEGER" VALUE="0">
|
|
<DESCRIPTION>Simulation Mode</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="38" NAME="C_STATS_WIDTH" TYPE="INTEGER" VALUE="64">
|
|
<DESCRIPTION>C_STATS_WIDTH</DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="39" NAME="C_AXI_STR_TXC_ACLK_FREQ_HZ" TYPE="INTEGER" VALUE="100000000">
|
|
<DESCRIPTION>AXI Stream Tx Clock Freq</DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT BUS="AXI_STR_TXD" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="AXI_STR_TXD_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="AXI_STR_TXC" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="27" NAME="AXI_STR_TXC_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="AXI_STR_RXD" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="34" NAME="AXI_STR_RXD_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="AXI_STR_RXS" CLKFREQUENCY="100000000" DEF_SIGNAME="ACLK" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="41" NAME="AXI_STR_RXS_ACLK" SIGIS="CLK" SIGNAME="sys_clk_s"/>
|
|
<PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="21" NAME="AXI_STR_TXD_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_TXD_ARESETN"/>
|
|
<PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="28" NAME="AXI_STR_TXC_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_TXC_ARESETN"/>
|
|
<PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="35" NAME="AXI_STR_RXD_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_RXD_ARESETN"/>
|
|
<PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="ARESETN" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="42" NAME="AXI_STR_RXS_ARESETN" SIGIS="RST" SIGNAME="AXI_STR_RXS_ARESETN"/>
|
|
<PORT CLKFREQUENCY="125000000" DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="9" MPD_INDEX="49" NAME="GTX_CLK" SIGIS="CLK" SIGNAME="ethernet_clk_s"/>
|
|
<PORT CLKFREQUENCY="200000000" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="10" MPD_INDEX="52" NAME="REF_CLK" SIGIS="CLK" SIGNAME="clk_ref"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="11" MPD_INDEX="48" NAME="PHY_RST_N" SIGNAME="Soft_Ethernet_MAC_RST_N"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="12" MPD_INDEX="2" NAME="INTERRUPT" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="Soft_Ethernet_MAC_INTERRUPT"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="13" MPD_INDEX="60" NAME="MII_TX_CLK" SIGNAME="Soft_Ethernet_MAC_MII_TX_CLK"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="14" MPD_INDEX="63" MSB="7" NAME="GMII_TXD" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_GMII_TXD" VECFORMULA="[7:0]"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="15" MPD_INDEX="64" NAME="GMII_TX_EN" SIGNAME="Soft_Ethernet_MAC_GMII_TX_EN"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="16" MPD_INDEX="65" NAME="GMII_TX_ER" SIGNAME="Soft_Ethernet_MAC_GMII_TX_ER"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="17" MPD_INDEX="66" NAME="GMII_TX_CLK" SIGNAME="Soft_Ethernet_MAC_GMII_TX_CLK"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" LEFT="7" LSB="0" MHS_INDEX="18" MPD_INDEX="67" MSB="7" NAME="GMII_RXD" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_GMII_RXD" VECFORMULA="[7:0]"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="19" MPD_INDEX="68" NAME="GMII_RX_DV" SIGNAME="Soft_Ethernet_MAC_GMII_RX_DV"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="20" MPD_INDEX="69" NAME="GMII_RX_ER" SIGNAME="Soft_Ethernet_MAC_GMII_RX_ER"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="21" MPD_INDEX="70" NAME="GMII_RX_CLK" SIGNAME="Soft_Ethernet_MAC_GMII_RX_CLK"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="22" MPD_INDEX="71" NAME="GMII_COL" SIGNAME="Soft_Ethernet_MAC_GMII_COL"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="23" MPD_INDEX="72" NAME="GMII_CRS" SIGNAME="Soft_Ethernet_MAC_GMII_CRS"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" MHS_INDEX="24" MPD_INDEX="83" NAME="MDC" SIGNAME="Soft_Ethernet_MAC_MDC"/>
|
|
<PORT DIR="IO" IOS="AXIETHERNETIF" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" MHS_INDEX="25" MPD_INDEX="108" NAME="MDIO" SIGNAME="Soft_Ethernet_MAC_MDIO" TRI_I="MDIO_I" TRI_O="MDIO_O" TRI_T="MDIO_T"/>
|
|
<PORT BUS="S_AXI:AXI_STR_TXC:AXI_STR_TXD:AXI_STR_RXS:AXI_STR_RXD" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="3" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="4" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="5" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="6" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="7" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="8" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="9" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="10" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="11" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="12" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="13" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="14" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="15" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="16" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="17" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="18" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
|
|
<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="19" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
|
|
<PORT BUS="AXI_STR_TXD" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TVALID" DIR="I" MPD_INDEX="22" NAME="AXI_STR_TXD_TVALID" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TVALID"/>
|
|
<PORT BUS="AXI_STR_TXD" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TREADY" DIR="O" MPD_INDEX="23" NAME="AXI_STR_TXD_TREADY" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TREADY"/>
|
|
<PORT BUS="AXI_STR_TXD" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TLAST" DIR="I" MPD_INDEX="24" NAME="AXI_STR_TXD_TLAST" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TLAST"/>
|
|
<PORT BUS="AXI_STR_TXD" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="25" MSB="3" NAME="AXI_STR_TXD_TKEEP" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TKEEP" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="AXI_STR_TXD" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="26" MSB="31" NAME="AXI_STR_TXD_TDATA" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_MM2S_TDATA" VECFORMULA="[31:0]"/>
|
|
<PORT BUS="AXI_STR_TXC" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TVALID" DIR="I" MPD_INDEX="29" NAME="AXI_STR_TXC_TVALID" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TVALID"/>
|
|
<PORT BUS="AXI_STR_TXC" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TREADY" DIR="O" MPD_INDEX="30" NAME="AXI_STR_TXC_TREADY" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TREADY"/>
|
|
<PORT BUS="AXI_STR_TXC" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TLAST" DIR="I" MPD_INDEX="31" NAME="AXI_STR_TXC_TLAST" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TLAST"/>
|
|
<PORT BUS="AXI_STR_TXC" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TKEEP" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="32" MSB="3" NAME="AXI_STR_TXC_TKEEP" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TKEEP" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="AXI_STR_TXC" DEF_SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="33" MSB="31" NAME="AXI_STR_TXC_TDATA" RIGHT="0" SIGNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL_TDATA" VECFORMULA="[31:0]"/>
|
|
<PORT BUS="AXI_STR_RXD" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TVALID" DIR="O" MPD_INDEX="36" NAME="AXI_STR_RXD_TVALID" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TVALID"/>
|
|
<PORT BUS="AXI_STR_RXD" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TREADY" DIR="I" MPD_INDEX="37" NAME="AXI_STR_RXD_TREADY" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TREADY"/>
|
|
<PORT BUS="AXI_STR_RXD" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TLAST" DIR="O" MPD_INDEX="38" NAME="AXI_STR_RXD_TLAST" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TLAST"/>
|
|
<PORT BUS="AXI_STR_RXD" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="39" MSB="3" NAME="AXI_STR_RXD_TKEEP" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TKEEP" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="AXI_STR_RXD" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="40" MSB="31" NAME="AXI_STR_RXD_TDATA" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXD_TDATA" VECFORMULA="[31:0]"/>
|
|
<PORT BUS="AXI_STR_RXS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TVALID" DIR="O" MPD_INDEX="43" NAME="AXI_STR_RXS_TVALID" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TVALID"/>
|
|
<PORT BUS="AXI_STR_RXS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TREADY" DIR="I" MPD_INDEX="44" NAME="AXI_STR_RXS_TREADY" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TREADY"/>
|
|
<PORT BUS="AXI_STR_RXS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TLAST" DIR="O" MPD_INDEX="45" NAME="AXI_STR_RXS_TLAST" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TLAST"/>
|
|
<PORT BUS="AXI_STR_RXS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TKEEP" DIR="O" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="46" MSB="3" NAME="AXI_STR_RXS_TKEEP" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TKEEP" VECFORMULA="[3:0]"/>
|
|
<PORT BUS="AXI_STR_RXS" DEF_SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="47" MSB="31" NAME="AXI_STR_RXS_TDATA" RIGHT="0" SIGNAME="Soft_Ethernet_MAC_AXI_STR_RXS_TDATA" VECFORMULA="[31:0]"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="50" NAME="MGT_CLK_P" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="51" NAME="MGT_CLK_N" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="53" MSB="3" NAME="MII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="54" NAME="MII_TX_EN" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="55" NAME="MII_TX_ER" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="56" MSB="3" NAME="MII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="57" NAME="MII_RX_DV" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="58" NAME="MII_RX_ER" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="59" NAME="MII_RX_CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="61" NAME="MII_COL" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="62" NAME="MII_CRS" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="73" NAME="TXP" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="74" NAME="TXN" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="75" NAME="RXP" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="76" NAME="RXN" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="77" MSB="3" NAME="RGMII_TXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="78" NAME="RGMII_TX_CTL" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="79" NAME="RGMII_TXC" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" ENDIAN="LITTLE" IOS="AXIETHERNETIF" IS_VALID="FALSE" LEFT="3" LSB="0" MPD_INDEX="80" MSB="3" NAME="RGMII_RXD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[3:0]"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="81" NAME="RGMII_RX_CTL" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" IS_VALID="FALSE" MPD_INDEX="82" NAME="RGMII_RXC" SIGNAME="__NOC__"/>
|
|
<PORT DIR="I" IOS="AXIETHERNETIF" MPD_INDEX="84" NAME="MDIO_I" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" MPD_INDEX="85" NAME="MDIO_O" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IOS="AXIETHERNETIF" MPD_INDEX="86" NAME="MDIO_T" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="87" NAME="AXI_STR_AVBTX_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="88" NAME="AXI_STR_AVBTX_ARESETN" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="89" NAME="AXI_STR_AVBTX_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="90" NAME="AXI_STR_AVBTX_TREADY" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="91" NAME="AXI_STR_AVBTX_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="92" MSB="7" NAME="AXI_STR_AVBTX_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="AXI_STR_AVBTX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="93" NAME="AXI_STR_AVBTX_TUSER" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
|
|
<PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="94" NAME="AXI_STR_AVBRX_ACLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="I" MPD_INDEX="95" NAME="AXI_STR_AVBRX_ARESETN" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="96" NAME="AXI_STR_AVBRX_TVALID" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="97" NAME="AXI_STR_AVBRX_TLAST" SIGNAME="__NOC__"/>
|
|
<PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="LITTLE" LEFT="7" LSB="0" MPD_INDEX="98" MSB="7" NAME="AXI_STR_AVBRX_TDATA" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[7:0]"/>
|
|
<PORT BUS="AXI_STR_AVBRX" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="99" NAME="AXI_STR_AVBRX_TUSER" SIGNAME="__NOC__" VECFORMULA="[0:0]"/>
|
|
<PORT DIR="I" IS_VALID="FALSE" MPD_INDEX="100" NAME="RTC_CLK" SIGIS="CLK" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="101" NAME="AV_INTERRUPT_10MS" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="102" NAME="AV_INTERRUPT_PTP_TX" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="103" NAME="AV_INTERRUPT_PTP_RX" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="104" MSB="31" NAME="AV_RTC_NANOSECFIELD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="47" LSB="0" MPD_INDEX="105" MSB="47" NAME="AV_RTC_SECFIELD" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[47:0]"/>
|
|
<PORT DIR="O" IS_VALID="FALSE" MPD_INDEX="106" NAME="AV_CLK_8K" SIGNAME="__NOC__"/>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IS_VALID="FALSE" LEFT="31" LSB="0" MPD_INDEX="107" MSB="31" NAME="AV_RTC_NANOSECFIELD_1722" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[31:0]"/>
|
|
</PORTS>
|
|
<BUSINTERFACES>
|
|
<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_Ethernet_M_AXIS_MM2S" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="AXI_STR_TXD" PROTOCOL="XIL_AXI_STREAM_ETH_DATA" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_TXD_TREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TKEEP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_TDATA"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="AXI_DMA_Ethernet_M_AXIS_CNTRL" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="AXI_STR_TXC" PROTOCOL="XIL_AXI_STREAM_ETH_CTRL" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_TXC_TREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TKEEP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_TDATA"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="Soft_Ethernet_MAC_AXI_STR_RXD" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="4" NAME="AXI_STR_RXD" PROTOCOL="XIL_AXI_STREAM_ETH_DATA" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_TREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TKEEP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXD_TDATA"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="Soft_Ethernet_MAC_AXI_STR_RXS" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="AXI_STR_RXS" PROTOCOL="XIL_AXI_STREAM_ETH_CTRL" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_TXC_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXD_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TVALID"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_RXS_TREADY"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TKEEP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_RXS_TDATA"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="5" NAME="AXI_STR_AVBTX" PROTOCOL="XIL_AXI_STREAM_ETH_AVB_TX" TYPE="TARGET">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBTX_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_ARESETN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBTX_TREADY"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TLAST"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TDATA"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBTX_TUSER"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
<BUSINTERFACE BUSNAME="__NOC__" BUSSTD="AXIS" BUSSTD_PSF="AXIS" IS_VALID="FALSE" MPD_INDEX="6" NAME="AXI_STR_AVBRX" PROTOCOL="XIL_AXI_STREAM_ETH_AVB_RX" TYPE="INITIATOR">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_ACLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="AXI_STR_AVBRX_ARESETN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TVALID"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TLAST"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TDATA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="AXI_STR_AVBRX_TUSER"/>
|
|
</PORTMAPS>
|
|
</BUSINTERFACE>
|
|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="AXIETHERNETIF" TYPE="XIL_AXIETHERNET_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="GTX_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="PHY_RST_N"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MII_TX_CLK"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GMII_TXD"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GMII_TX_EN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GMII_TX_ER"/>
|
|
<PORTMAP DIR="O" PHYSICAL="GMII_TX_CLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GMII_RXD"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GMII_RX_DV"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GMII_RX_ER"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GMII_RX_CLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GMII_COL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="GMII_CRS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MDC"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="MDIO"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MGT_CLK_P"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MGT_CLK_N"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MII_TXD"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MII_TX_EN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MII_TX_ER"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MII_RXD"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MII_RX_DV"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MII_RX_ER"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MII_RX_CLK"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MII_COL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MII_CRS"/>
|
|
<PORTMAP DIR="O" PHYSICAL="TXP"/>
|
|
<PORTMAP DIR="O" PHYSICAL="TXN"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RXP"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RXN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RGMII_TXD"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RGMII_TX_CTL"/>
|
|
<PORTMAP DIR="O" PHYSICAL="RGMII_TXC"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RGMII_RXD"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RGMII_RX_CTL"/>
|
|
<PORTMAP DIR="I" PHYSICAL="RGMII_RXC"/>
|
|
<PORTMAP DIR="I" PHYSICAL="MDIO_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MDIO_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="MDIO_T"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2248146944" BASENAME="C_BASEADDR" BASEVALUE="0x86000000" HIGHDECIMAL="2248671231" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8607FFFF" MEMTYPE="REGISTER" MINSIZE="0x40000" SIZE="524288" SIZEABRV="512K">
|
|
<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
|
</MEMRANGE>
|
|
</MEMORYMAP>
|
|
<INTERRUPTINFO TYPE="SOURCE">
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="5"/>
|
|
</INTERRUPTINFO>
|
|
</MODULE>
|
|
<MODULE HWVERSION="1.01.a" INSTANCE="SysACE_CompactFlash" IPTYPE="PERIPHERAL" MHS_INDEX="29" MODCLASS="PERIPHERAL" MODTYPE="axi_sysace">
|
|
<DESCRIPTION TYPE="SHORT">AXI System ACE Interface Controller(Compact Flash)</DESCRIPTION>
|
|
<DESCRIPTION TYPE="LONG">Interface between the AXI and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral</DESCRIPTION>
|
|
<DOCUMENTATION>
|
|
<DOCUMENT SOURCE="/proj/xbuilds/ids_13.2_O.61xd.0.0/lin/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/axi_sysace_v1_01_a/doc/ds789_axi_sysace.pdf" TYPE="IP"/>
|
|
</DOCUMENTATION>
|
|
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
|
|
<PARAMETERS>
|
|
<PARAMETER MPD_INDEX="0" NAME="C_S_AXI_PROTOCOL" VALUE="AXI4LITE">
|
|
<DESCRIPTION>C_S_AXI_PROTOCOL </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6">
|
|
<DESCRIPTION>C_FAMILY </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="2" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x91800000">
|
|
<DESCRIPTION>C_BASEADDR </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="3" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x9180ffff">
|
|
<DESCRIPTION>C_HIGHADDR </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="4" NAME="C_S_AXI_ADDR_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>C_S_AXI_ADDR_WIDTH </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER MPD_INDEX="5" NAME="C_S_AXI_DATA_WIDTH" TYPE="INTEGER" VALUE="32">
|
|
<DESCRIPTION>C_S_AXI_DATA_WIDTH </DESCRIPTION>
|
|
</PARAMETER>
|
|
<PARAMETER CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="6" NAME="C_MEM_WIDTH" TYPE="INTEGER" VALUE="8">
|
|
<DESCRIPTION>C_MEM_WIDTH </DESCRIPTION>
|
|
</PARAMETER>
|
|
</PARAMETERS>
|
|
<PORTS>
|
|
<PORT DIR="I" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="19" NAME="SysACE_CLK" SIGNAME="SysACE_CLK">
|
|
<DESCRIPTION>Clock Input</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="I" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="20" NAME="SysACE_MPIRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="SysACE_MPIRQ">
|
|
<DESCRIPTION>Active high Interrupt Output</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" ENDIAN="LITTLE" IOS="sysace_0" IS_INSTANTIATED="TRUE" LEFT="6" LSB="0" MHS_INDEX="2" MPD_INDEX="24" MSB="6" NAME="SysACE_MPA" RIGHT="0" SIGNAME="SysACE_MPA" VECFORMULA="[6:0]">
|
|
<DESCRIPTION>Address Input</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="25" NAME="SysACE_CEN" SIGNAME="SysACE_CEN">
|
|
<DESCRIPTION>Active LOW Chip Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="26" NAME="SysACE_OEN" SIGNAME="SysACE_OEN">
|
|
<DESCRIPTION>Active LOW Output Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="O" IOS="sysace_0" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="27" NAME="SysACE_WEN" SIGNAME="SysACE_WEN">
|
|
<DESCRIPTION>Active LOW Write Enable</DESCRIPTION>
|
|
</PORT>
|
|
<PORT DIR="IO" ENDIAN="LITTLE" IOS="sysace_0" IS_INSTANTIATED="TRUE" IS_THREE_STATE="TRUE" LEFT="7" LSB="0" MHS_INDEX="6" MPD_INDEX="29" MSB="7" NAME="SysACE_MPD" RIGHT="0" SIGNAME="SysACE_MPD" TRI_I="SysACE_MPD_I" TRI_O="SysACE_MPD_O" TRI_T="SysACE_MPD_T" VECFORMULA="[(C_MEM_WIDTH-1):0]">
|
|
<DESCRIPTION>Data Input/Output</DESCRIPTION>
|
|
</PORT>
|
|
<PORT BUS="S_AXI" CLKFREQUENCY="50000000" DEF_SIGNAME="__BUS__" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="0" NAME="S_AXI_ACLK" SIGIS="CLK" SIGNAME="sys_clk_axilite_s"/>
|
|
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="8" MPD_INDEX="28" NAME="SysACE_IRQ" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="SysACE_CompactFlash_SysACE_IRQ"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARESETN" DIR="I" MPD_INDEX="1" NAME="S_AXI_ARESETN" SIGIS="RST" SIGNAME="AXI_Lite_M_ARESETN"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="2" MSB="31" NAME="S_AXI_AWADDR" RIGHT="0" SIGNAME="AXI_Lite_M_AWADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWVALID" DIR="I" MPD_INDEX="3" NAME="S_AXI_AWVALID" SIGNAME="AXI_Lite_M_AWVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_AWREADY" DIR="O" MPD_INDEX="4" NAME="S_AXI_AWREADY" SIGNAME="AXI_Lite_M_AWREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WDATA" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="5" MSB="31" NAME="S_AXI_WDATA" RIGHT="0" SIGNAME="AXI_Lite_M_WDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WSTRB" DIR="I" ENDIAN="LITTLE" LEFT="3" LSB="0" MPD_INDEX="6" MSB="3" NAME="S_AXI_WSTRB" RIGHT="0" SIGNAME="AXI_Lite_M_WSTRB" VECFORMULA="[((C_S_AXI_DATA_WIDTH/8)-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WVALID" DIR="I" MPD_INDEX="7" NAME="S_AXI_WVALID" SIGNAME="AXI_Lite_M_WVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_WREADY" DIR="O" MPD_INDEX="8" NAME="S_AXI_WREADY" SIGNAME="AXI_Lite_M_WREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="9" MSB="1" NAME="S_AXI_BRESP" RIGHT="0" SIGNAME="AXI_Lite_M_BRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BVALID" DIR="O" MPD_INDEX="10" NAME="S_AXI_BVALID" SIGNAME="AXI_Lite_M_BVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_BREADY" DIR="I" MPD_INDEX="11" NAME="S_AXI_BREADY" SIGNAME="AXI_Lite_M_BREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARADDR" DIR="I" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="12" MSB="31" NAME="S_AXI_ARADDR" RIGHT="0" SIGNAME="AXI_Lite_M_ARADDR" VECFORMULA="[(C_S_AXI_ADDR_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARVALID" DIR="I" MPD_INDEX="13" NAME="S_AXI_ARVALID" SIGNAME="AXI_Lite_M_ARVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_ARREADY" DIR="O" MPD_INDEX="14" NAME="S_AXI_ARREADY" SIGNAME="AXI_Lite_M_ARREADY"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RDATA" DIR="O" ENDIAN="LITTLE" LEFT="31" LSB="0" MPD_INDEX="15" MSB="31" NAME="S_AXI_RDATA" RIGHT="0" SIGNAME="AXI_Lite_M_RDATA" VECFORMULA="[(C_S_AXI_DATA_WIDTH-1):0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RRESP" DIR="O" ENDIAN="LITTLE" LEFT="1" LSB="0" MPD_INDEX="16" MSB="1" NAME="S_AXI_RRESP" RIGHT="0" SIGNAME="AXI_Lite_M_RRESP" VECFORMULA="[1:0]"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RVALID" DIR="O" MPD_INDEX="17" NAME="S_AXI_RVALID" SIGNAME="AXI_Lite_M_RVALID"/>
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<PORT BUS="S_AXI" DEF_SIGNAME="AXI_Lite_M_RREADY" DIR="I" MPD_INDEX="18" NAME="S_AXI_RREADY" SIGNAME="AXI_Lite_M_RREADY"/>
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<PORT DIR="I" ENDIAN="LITTLE" IOS="sysace_0" LEFT="7" LSB="0" MPD_INDEX="21" MSB="7" NAME="SysACE_MPD_I" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IOS="sysace_0" LEFT="7" LSB="0" MPD_INDEX="22" MSB="7" NAME="SysACE_MPD_O" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/>
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<PORT DIR="O" ENDIAN="LITTLE" IOS="sysace_0" LEFT="7" LSB="0" MPD_INDEX="23" MSB="7" NAME="SysACE_MPD_T" RIGHT="0" SIGNAME="__NOC__" VECFORMULA="[(C_MEM_WIDTH-1):0]"/>
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</PORTS>
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<BUSINTERFACES>
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<BUSINTERFACE BUSNAME="AXI_Lite" BUSSTD="AXI" BUSSTD_PSF="AXI" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="S_AXI" PROTOCOL="AXI4LITE" TYPE="SLAVE">
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<PORTMAPS>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_ACLK"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_ARESETN"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_AWADDR"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_AWVALID"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_AWREADY"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_WDATA"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_WSTRB"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_WVALID"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_WREADY"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_BRESP"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_BVALID"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_BREADY"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_ARADDR"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_ARVALID"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_ARREADY"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_RDATA"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_RRESP"/>
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<PORTMAP DIR="O" PHYSICAL="S_AXI_RVALID"/>
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<PORTMAP DIR="I" PHYSICAL="S_AXI_RREADY"/>
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</PORTMAPS>
|
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</BUSINTERFACE>
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|
</BUSINTERFACES>
|
|
<IOINTERFACES>
|
|
<IOINTERFACE MPD_INDEX="0" NAME="sysace_0" TYPE="XIL_AXI_SYSACE_V1">
|
|
<PORTMAPS>
|
|
<PORTMAP DIR="I" PHYSICAL="SysACE_CLK"/>
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|
<PORTMAP DIR="I" PHYSICAL="SysACE_MPIRQ"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SysACE_MPA"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SysACE_CEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SysACE_OEN"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SysACE_WEN"/>
|
|
<PORTMAP DIR="IO" PHYSICAL="SysACE_MPD"/>
|
|
<PORTMAP DIR="I" PHYSICAL="SysACE_MPD_I"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SysACE_MPD_O"/>
|
|
<PORTMAP DIR="O" PHYSICAL="SysACE_MPD_T"/>
|
|
</PORTMAPS>
|
|
</IOINTERFACE>
|
|
</IOINTERFACES>
|
|
<MEMORYMAP>
|
|
<MEMRANGE BASEDECIMAL="2441084928" BASENAME="C_BASEADDR" BASEVALUE="0x91800000" HIGHDECIMAL="2441150463" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x9180ffff" MEMTYPE="REGISTER" MINSIZE="0x1000" SIZE="65536" SIZEABRV="64K">
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<SLAVES>
|
|
<SLAVE BUSINTERFACE="S_AXI"/>
|
|
</SLAVES>
|
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</MEMRANGE>
|
|
</MEMORYMAP>
|
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<INTERRUPTINFO TYPE="SOURCE">
|
|
<TARGET INSTANCE="Interrupt_Cntlr" INTC_INDEX="0" PRIORITY="0"/>
|
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</INTERRUPTINFO>
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</MODULE>
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</MODULES>
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</EDKSYSTEM> |