MicroBlaze Debug Module (MDM) Debug module for MicroBlaze Soft Processor. Device Family Specifies the JTAG user-defined register used Specifies the Bus Interface for the JTAG UART Base Address High Address PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters Native Data Bus Width of PLB Slave PLB Slave is Capable of Bursts Number of MicroBlaze debug ports Enable JTAG UART AXI Address Width AXI Data Width AXI4LITE protocal MicroBlaze The MicroBlaze 32 bit soft processor Enable Fault Tolerance Support Select implementation to optimize area (with lower instruction throughput) Select Bus Interfaces Select Stream Interfaces Enable Additional Machine Status Register Instructions Enable Pattern Comparator Enable Barrel Shifter Enable Integer Divider Enable Integer Multiplier Enable Floating Point Unit Enable Unaligned Data Exception Enable Illegal Instruction Exception Enable Instruction-side AXI Exception Enable Data-side AXI Exception Enable Instruction-side PLB Exception Enable Data-side PLB Exception Enable Integer Divide Exception Enable Floating Point Unit Exceptions Enable Stream Exception <qt>Enable stack protection</qt> Specifies Processor Version Register Specify USER1 Bits in Processor Version Register Specify USER2 Bits in Processor Version Registers Enable MicroBlaze Debug Module Interface Number of PC Breakpoints Number of Read Address Watchpoints Number of Write Address Watchpoints Sense Interrupt on Edge vs. Level Sense Interrupt on Rising vs. Falling Edge Specify Reset Value for Select MSR Bits <qt>Generate Illegal Instruction Exception for NULL Instruction</qt> Number of Stream Links Enable Additional Stream Instructions Base Address High Address Enable Instruction Cache Enable Writes Size in Bytes Line Length Use Cache Links for All Memory Accesses Number of Victims Number of Streams Use Distributed RAM for Tags Data Width Base Address High Address Enable Data Cache Enable Writes Size in Bytes Line Length Use Cache Links for All Memory Accesses Enable Write-back Storage Policy Number of Victims Use Distributed RAM for Tags Data Width Memory Management Data Shadow Translation Look-Aside Buffer Size Instruction Shadow Translation Look-Aside Buffer Size Enable Access to Memory Management Special Registers Number of Memory Protection Zones Privileged Instructions Enable Branch Target Cache Branch Target Cache Size Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External Reset Local Memory Bus (LMB) 1.0 'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM' Number of Bus Slaves LMB Address Bus Width LMB Data Bus Width Active High External Reset LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus LMB BRAM Base Address LMB BRAM High Address LMB Address Decode Mask LMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register Width Write Access setting Base Address for PLB Interface High Address for PLB Interface PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters PLB Slave is Capable of Bursts Native Data Bus Width of PLB Slave Frequency of PLB Slave S_AXI_CTRL Clock Frequency S_AXI_CTRL Base Address S_AXI_CTRL High Address S_AXI_CTRL Address Width S_AXI_CTRL Data Width S_AXI_CTRL Protocol LMB BRAM Controller Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus LMB BRAM Base Address LMB BRAM High Address LMB Address Decode Mask LMB Address Bus Width LMB Data Bus Width Error Correction Code Select Interconnect Fault Inject Registers Correctable Error First Failing Register Uncorrectable Error First Failing Register ECC Status and Control Register ECC On/Off Register ECC On/Off Reset Value Correctable Error Counter Register Width Write Access setting Base Address for PLB Interface High Address for PLB Interface PLB Address Bus Width PLB Data Bus Width PLB Slave Uses P2P Topology Master ID Bus Width of PLB Number of PLB Masters PLB Slave is Capable of Bursts Native Data Bus Width of PLB Slave Frequency of PLB Slave S_AXI_CTRL Clock Frequency S_AXI_CTRL Base Address S_AXI_CTRL High Address S_AXI_CTRL Address Width S_AXI_CTRL Data Width S_AXI_CTRL Protocol Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. Size of BRAM(s) in Bytes Data Width of Port A and B Address Width of Port A and B Number of Byte Write Enables Device Family AXI S6 Memory Controller(DDR/DDR2/DDR3) Spartan-6 memory controller Clock Generator Clock generator for processor system. Family Device Package Speed Grade Input Clock Frequency (Hz) Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Varaible Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Varaible Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Required Frequency (Hz) Clock Deskew Required Frequency (Hz) Required Phase Required Group Buffered Variable Phase Shift Clock Primitive Feedback Buffer Processor System Reset Module Reset management module Device Subfamily Number of Clocks Before Input Change is Recognized On The External Reset Input Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input External Reset Active High Auxiliary Reset Active High Number of Bus Structure Reset Registered Outputs Number of Peripheral Reset Registered Outputs Number of Active Low Interconnect Reset Registered Outputs Number of Active Low Peripheral Reset Registered Outputs Device Family AXI Interconnect AXI4 Memory-Mapped Interconnect Family Base Family Number of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data Width Master AXI Data Width Interconnect Crossbar Data Width AXI Protocol Master AXI Protocol Master AXI Base Address Master AXI High Address Slave AXI Base ID Slave AXI Thread ID Width Slave AXI Is Interconnect Slave AXI ACLK Ratio Slvave AXI Is ACLK ASYNC Master AXI ACLK Ratio Master AXI Is ACLK ASYNC Interconnect Crossbar ACLK Frequency Ratio Slave AXI Supports Write Slave AXI Supports Read Master AXI Supports Write Master AXI Supports Read Propagate USER Signals AWUSER Signal Width ARUSER Signal Width WUSER Signal Width RUSER Signal Width BUSER Signal Width AXI Connectivity Slave AXI Single Thread Master AXI Supports Reordering Master generates narrow bursts Slave accepts narrow bursts Slave AXI Write Acceptance Slave AXI Read Acceptance Master AXI Write Issuing Master AXI Read Issuing Slave AXI ARB Priority Master AXI Secure Master AXI Write FIFO Depth Slave AXI Write FIFO Type Slave AXI Write FIFO Delay Slave AXI Read FIFO Depth Slave AXI Read FIFO Type Slave AXI Read FIFO Delay Master AXI Write FIFO Depth Master AXI Write FIFO Type Master AXI Write FIFO Delay Master AXI Read FIFO Depth Master AXI Read FIFO Type Master AXI Read FIFO Delay Slave AXI AW Register Slave AXI AR Register Slave AXI W Register Slave AXI R Register Slave AXI B Register Master AXI AW Register Master AXI AR Register Master AXI W Register Master AXI R Register Master AXI B Register C_INTERCONNECT_R_REGISTER Interconnect Architecture Use Diagnostic Slave Port Generate Interrupts Check for transaction errors (DECERR) Slave AXI CTRL Protocol Slave AXI CTRL Address Width Slave AXI CTRL Data Width Diagnostic Slave Port Base Address Diagnostic Slave Port High Address Simulation debug Select SI slot for DEBUG outputs Select MI slot for DEBUG outputs Thread depth of DEBUG signal AXI Interconnect AXI4 Memory-Mapped Interconnect Family Base Family Number of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data Width Master AXI Data Width Interconnect Crossbar Data Width AXI Protocol Master AXI Protocol Master AXI Base Address Master AXI High Address Slave AXI Base ID Slave AXI Thread ID Width Slave AXI Is Interconnect Slave AXI ACLK Ratio Slvave AXI Is ACLK ASYNC Master AXI ACLK Ratio Master AXI Is ACLK ASYNC Interconnect Crossbar ACLK Frequency Ratio Slave AXI Supports Write Slave AXI Supports Read Master AXI Supports Write Master AXI Supports Read Propagate USER Signals AWUSER Signal Width ARUSER Signal Width WUSER Signal Width RUSER Signal Width BUSER Signal Width AXI Connectivity Slave AXI Single Thread Master AXI Supports Reordering Master generates narrow bursts Slave accepts narrow bursts Slave AXI Write Acceptance Slave AXI Read Acceptance Master AXI Write Issuing Master AXI Read Issuing Slave AXI ARB Priority Master AXI Secure Master AXI Write FIFO Depth Slave AXI Write FIFO Type Slave AXI Write FIFO Delay Slave AXI Read FIFO Depth Slave AXI Read FIFO Type Slave AXI Read FIFO Delay Master AXI Write FIFO Depth Master AXI Write FIFO Type Master AXI Write FIFO Delay Master AXI Read FIFO Depth Master AXI Read FIFO Type Master AXI Read FIFO Delay Slave AXI AW Register Slave AXI AR Register Slave AXI W Register Slave AXI R Register Slave AXI B Register Master AXI AW Register Master AXI AR Register Master AXI W Register Master AXI R Register Master AXI B Register C_INTERCONNECT_R_REGISTER Interconnect Architecture Use Diagnostic Slave Port Generate Interrupts Check for transaction errors (DECERR) Slave AXI CTRL Protocol Slave AXI CTRL Address Width Slave AXI CTRL Data Width Diagnostic Slave Port Base Address Diagnostic Slave Port High Address Simulation debug Select SI slot for DEBUG outputs Select MI slot for DEBUG outputs Thread depth of DEBUG signal AXI Interconnect AXI4 Memory-Mapped Interconnect Family Base Family Number of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data Width Master AXI Data Width Interconnect Crossbar Data Width AXI Protocol Master AXI Protocol Master AXI Base Address Master AXI High Address Slave AXI Base ID Slave AXI Thread ID Width Slave AXI Is Interconnect Slave AXI ACLK Ratio Slvave AXI Is ACLK ASYNC Master AXI ACLK Ratio Master AXI Is ACLK ASYNC Interconnect Crossbar ACLK Frequency Ratio Slave AXI Supports Write Slave AXI Supports Read Master AXI Supports Write Master AXI Supports Read Propagate USER Signals AWUSER Signal Width ARUSER Signal Width WUSER Signal Width RUSER Signal Width BUSER Signal Width AXI Connectivity Slave AXI Single Thread Master AXI Supports Reordering Master generates narrow bursts Slave accepts narrow bursts Slave AXI Write Acceptance Slave AXI Read Acceptance Master AXI Write Issuing Master AXI Read Issuing Slave AXI ARB Priority Master AXI Secure Master AXI Write FIFO Depth Slave AXI Write FIFO Type Slave AXI Write FIFO Delay Slave AXI Read FIFO Depth Slave AXI Read FIFO Type Slave AXI Read FIFO Delay Master AXI Write FIFO Depth Master AXI Write FIFO Type Master AXI Write FIFO Delay Master AXI Read FIFO Depth Master AXI Read FIFO Type Master AXI Read FIFO Delay Slave AXI AW Register Slave AXI AR Register Slave AXI W Register Slave AXI R Register Slave AXI B Register Master AXI AW Register Master AXI AR Register Master AXI W Register Master AXI R Register Master AXI B Register C_INTERCONNECT_R_REGISTER Interconnect Architecture Use Diagnostic Slave Port Generate Interrupts Check for transaction errors (DECERR) Slave AXI CTRL Protocol Slave AXI CTRL Address Width Slave AXI CTRL Data Width Diagnostic Slave Port Base Address Diagnostic Slave Port High Address Simulation debug Select SI slot for DEBUG outputs Select MI slot for DEBUG outputs Thread depth of DEBUG signal AXI Interconnect AXI4 Memory-Mapped Interconnect Family Base Family Number of Slave Slots Number of Master Slots AXI ID Widgth AXI Address Widgth AXI Data Maximum Width Slave AXI Data Width Master AXI Data Width Interconnect Crossbar Data Width AXI Protocol Master AXI Protocol Master AXI Base Address Master AXI High Address Slave AXI Base ID Slave AXI Thread ID Width Slave AXI Is Interconnect Slave AXI ACLK Ratio Slvave AXI Is ACLK ASYNC Master AXI ACLK Ratio Master AXI Is ACLK ASYNC Interconnect Crossbar ACLK Frequency Ratio Slave AXI Supports Write Slave AXI Supports Read Master AXI Supports Write Master AXI Supports Read Propagate USER Signals AWUSER Signal Width ARUSER Signal Width WUSER Signal Width RUSER Signal Width BUSER Signal Width AXI Connectivity Slave AXI Single Thread Master AXI Supports Reordering Master generates narrow bursts Slave accepts narrow bursts Slave AXI Write Acceptance Slave AXI Read Acceptance Master AXI Write Issuing Master AXI Read Issuing Slave AXI ARB Priority Master AXI Secure Master AXI Write FIFO Depth Slave AXI Write FIFO Type Slave AXI Write FIFO Delay Slave AXI Read FIFO Depth Slave AXI Read FIFO Type Slave AXI Read FIFO Delay Master AXI Write FIFO Depth Master AXI Write FIFO Type Master AXI Write FIFO Delay Master AXI Read FIFO Depth Master AXI Read FIFO Type Master AXI Read FIFO Delay Slave AXI AW Register Slave AXI AR Register Slave AXI W Register Slave AXI R Register Slave AXI B Register Master AXI AW Register Master AXI AR Register Master AXI W Register Master AXI R Register Master AXI B Register C_INTERCONNECT_R_REGISTER Interconnect Architecture Use Diagnostic Slave Port Generate Interrupts Check for transaction errors (DECERR) Slave AXI CTRL Protocol Slave AXI CTRL Address Width Slave AXI CTRL Data Width Diagnostic Slave Port Base Address Diagnostic Slave Port High Address Simulation debug Select SI slot for DEBUG outputs Select MI slot for DEBUG outputs Thread depth of DEBUG signal AXI UART (16550-style) AXI 16550/450 UART (Universal Asynchronous Receiver/Transmitter) Device Family AXI Clock Frequency AXI Base Address AXI High Address AXI Address Width AXI Data Width Uart Configuration External XIN is Present External RCLK is Present XIN Clock Frequency AXI4LITE protocol Include Modem Interface Ports Include User Interface Ports Serial Data Input Serial Data Output Freeze UART Transmitter Clock Clear To Send Data Carrier Detect Driver disable Data Set Ready Data Terminal Ready User Controlled Output User Controlled Output Receiver 16x Clock Ring Indicator Request To Send DMA Control Signal DMA Control Signal Baudrate Generator Reference Clock Inverted XIN AXI Timer/Counter Timer counter with AXI interface AXI4LITE protocol Device Family The Width of Counter in Timer Count Width Only One Timer is present TRIG0 Active Level TRIG1 Active Level GEN0 Active Level GEN1 Active Level AXI Base Address AXI High Address AXI Address Width AXI Data Width Capture Trig 0 Capture Trig 1 Generate Out 0 Generate Out 1 Pulse Width Modulation 0 AXI Interrupt Controller intc core attached to the AXI Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width Number of Interrupt Inputs Type of Interrupt for Each Input Type of Each Edge Senstive Interrupt Type of Each Level Sensitive Interrupt Support IPR Support SIE Support CIE Support IVR IRQ Output Use Level The Sense of IRQ Output AXI4LITE protocol Interrupt Request Output Interrupt Inputs AXI SPI Interface AXI to Motorola Serial Peripheral Interface (SPI) adapter Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width Include both Receiver and Transmitter FIFOs Include Receive and Transmit FIFO Ratio of AXI Clock Frequency To SCK Frequency C_SCK_RATIO Total Number of Slave Select Bits in SS Vector C_NUM_SS_BITS Number of SPI transfer bits C_NUM_TRANSFER_BITS AXI4LITE protocol Local SPI Slave Select Active LOW Input Master Out Slave In SPI Bus Clock Slave Select Vector Master In Slave Out Utility IO Multiplexor Utility IO multiplexor Size of The Vector AXI IIC Interface AXI interface to Philips I2C bus v2.1 Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width Output Frequency of SCL Signal Use 10-bit Address Width of GPIO AXI Clock Frequency Width of glitches removed on SCL input Width of glitches removed on SDA input SDA level when Master transmit throttling occurs AXI4LITE protocol IIC Serial Clock IIC Serial Data IIC General Purpose Output AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus. Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width Channel 1 is Input Only Channel 2 is Input Only GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value AXI4LITE protocol GPIO1 Data IO GPIO2 Data IO AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus. Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width Channel 1 is Input Only Channel 2 is Input Only GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value AXI4LITE protocol GPIO1 Data IO GPIO2 Data IO AXI General Purpose IO General Purpose Input/Output (GPIO) core for the AXI bus. Device Family AXI Base Address AXI High Address AXI Address Width AXI Data Width GPIO Data Channel Width GPIO Data Width GPIO2 Data Channel Width Channel 1 is Input Only Channel 2 is Input Only GPIO Supports Interrupts Channel 1 Data Out Default Value Channel 1 Tri-state Default Value Enable Channel 2 Channel 2 Data Out Default Value Channel 2 Tri-state Default Value AXI4LITE protocol GPIO1 Data IO GPIO2 Data IO AXI BRAM Controller Attaches BRAM to the AXI Device Family AXI4 Protocol AXI Slave IP Base Address AXI Slave IP High Address AXI Slave IP Address Width AXI Slave IP Data Width or BRAM Data Width AXI Slave IP ID Width Slave AXI Supports Narrow Bursts Slave Single Port BRAM Inteconnect Slave AXI Read Address Channel Register Inteconnect Slave AXI Write Address Channel Register Inteconnect Slave AXI Write Back Channel Register Inteconnect Slave AXI Read Data Channel Register Inteconnect Slave AXI Write Data Channel Register Inteconnect Slave AXI Write Acceptance Inteconnect Slave AXI Read Acceptance AXI4-Lite Protocol AXI4-Lite Slave IP Address Width AXI4-Lite Slave Data Width AXI4-Lite Slave IP Base Address AXI4-Lite Slave IP High Address Inteconnect Slave AXI Control Read Support Inteconnect Slave AXI Control Write Support Enable ECC Functionality Enable AXI4-Lite ECC Fault Injection Registers Set ECC On/Off Reset Value Block RAM (BRAM) Block The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers. Size of BRAM(s) in Bytes Data Width of Port A and B Address Width of Port A and B Number of Byte Write Enables Device Family Utility Bus Split Bus splitting primitive Vector Size of Input Bus The Left Bit Position of The Out1 Output Bus First Bit of The Out2 Output Bus AXI External Memory Controller (SRAM/Flash/Cellular RAM) AXI External Memory Controller (SRAM/Flash/Cellular RAM) Family Supported AXI Register Interface Enable AXI Register Interface Addresses Width AXI Register Interface Data Width AXI Memory Interface ID Width AXI Memory Interface Addresses Width AXI Memory Interface Data Width AXI4 Memory Interface protocol AXI4 Register Interface protocol axi clock period to calculate wait state pulse widths Number of Banks Include negative edge IO registers Data Bus Width of Bank 0 Data Bus Width of Bank 1 Data Bus Width of Bank 2 Data Bus Width of Bank 3 Execute Multiple Memory Accesses To Match Bank 0 Data Bus Width To AXI Data Bus Width Execute Multiple Memory Accesses To Match Bank 1 Data Bus Width To AXI Data Bus Width Execute Multiple Memory Accesses To Match Bank 2 Data Bus Width To AXI Data Bus Width Execute Multiple Memory Accesses To Match Bank 3 Data Bus Width To AXI Data Bus Width Memory type for Bank 0 Pipeline Latency of Bank 0 Type of parity of Bank 0 TCEDV of Bank 0 TAVDV of Bank 0 TPACC of Bank 0 THZCE of Bank 0 THZOE of Bank 0 TWC of Bank 0 TWP of Bank 0 TWPH of Bank 0 TLZWE of Bank 0 Memory type for Bank 1 Pipeline Latency of Bank 1 Type of parity of Bank 1 TCEDV of Bank 1 TAVDV of Bank 1 TPACC of Bank 1 THZCE of Bank 1 THZOE of Bank 1 TWC of Bank 1 TWP of Bank 1 TWPH of Bank 1 TLZWE of Bank 1 Memory type for Bank 2 Pipeline Latency of Bank 2 Type of parity of Bank 2 TCEDV of Bank 2 TAVDV of Bank 2 TPACC of Bank 2 THZCE of Bank 2 THZOE of Bank 2 TWC of Bank 2 TWP of Bank 2 TWPH of Bank 2 TLZWE of Bank 2 Memory type for Bank 3 Pipeline Latency of Bank 3 Type of parity of Bank 3 TCEDV of Bank 3 TAVDV of Bank 3 TPACC of Bank 3 THZCE of Bank 3 THZOE of Bank 3 TWC of Bank 3 TWP of Bank 3 TWPH of Bank 3 TLZWE of Bank 3 Maximum data bus width of all memory banks Base Address of Register High Address of Register Base Address of Bank 0 High Address of Bank 0 Base Address of Bank 1 High Address of Bank 1 Base Address of Bank 2 High Address of Bank 2 Base Address of Bank 3 High Address of Bank 3 Memory Address Bus Memory Write Enable Memory Output Enable Memory Chip Enable Active Low Memory Advanced Burst Address/Load New Address Memory Reset/Power Down Memory Chip Enable Active High Memory Qualified Write Enable Memory Byte Enable Memory Linear/Interleaved Burst Order Memory Clock Enable Memory Read Not Write Memory Clock Enable Memory Data Bus Memory Data Parity Bus AXI DMA Engine AXI MemoryMap to/from AXI Stream Direct Memory Access Engine AXI Lite Address Width AXI Lite Data Width Delay Timer Counter Resolution Primary clock Is Asynchronous Include Scatter Gather Engine Include Scatter Gather Descriptor Queuing Include AXI Status and Control Streams Use Status Stream App Length Buffer Length Field Width AXI SG Address Width AXI SG Data Width AXI Control Stream Width AXI Status Stream Width Include MM2S Channel Include MM2S Data Realignment Engine Maximum Memory Map Burst Size for MM2S MM2S Address Width MM2S Memory Map Data Width MM2S Stream Data Width Include S2MM Channel Include S2MM Data Realignment Engine Maximum Memory Map Burst Size for S2MM (data beats) S2MM Address Width S2MM Memory Map Data Width S2MM Stream Data Width Device Family Base Address High Address AXI Lite Clock Frequency AXI Scatter Gather Clock Frequency AXI MM2S Clock Frequency AXI S2MM Clock Frequency AXI Lite Protocol AXI Lite Supports Read Access AXI Lite Supports Write Access AXI SG Protocol AXI SG Support Threads Base Address AXI SG Supports Narrow Bursts AXI SG Generates Read Accesses AXI SG Generates Write Accesses AXI MM2S Protocol AXI MM2S Support Threads AXI MM2S Thread ID Width AXI MM2S Supports Narrow Bursts AXI MM2S Generates Read Accesses AXI MM2S Generates Write Accesses AXI MM2S Interface Read Issuing AXI MM2S Interface Read FIFO Depth AXI S2MM Protocol AXI S2MM Support Threads AXI S2MM Thread ID Width AXI S2MM Supports Narrow Bursts AXI S2MM Generates Write Accesses AXI S2MM Generates Read Accesses AXI S2MM Interface Write Issuing AXI S2MM Interface Write FIFO Depth AXI MM2S Stream Interface Protocol AXI S2MM Stream Interface Protocol AXI MM2S Control Stream Interface Protocol AXI S2MM Status Stream Interface Protocol AXI Ethernet Embedded IP Embedded Ethernet core that implements a Tri-mode (10/100/1000 Mbps) Ethernet MAC or a 10/100 Mbps Ethernet MAC to support MII/GMII/SGMII/RGMII/1000Base-X PHY types AXI Protocol AXI Stream Bus Width AXI Stream Bus Width AXI Stream Bus Width AXI Stream Bus Width AXI Stream Protocol AXI Stream Protocol AXI Stream Protocol AXI Stream Protocol AXI Stream Protocol AXI Stream Protocol Device Family AXI Clock Freq in HZ Base Address High Address AXI Address Width AXI Data Width AXI ID Width Spartan 6 Transceiver Side PHY Address Include IO and BUFG as Needed for the PHY Interface Selected Type of TEMAC Physical Interface Type Enable Half Duplex mode TX Memory Depth RX Memory Depth Enable TX Checksum Offload Enable RX Checksum Offload Transmit VLAN translation Receive VLAN translation Transmit VLAN tagging Receive VLAN tagging Transmit VLAN stripping Receive VLAN stripping Receive Extended Multicast Address Filtering Statistics Counters Audio Video Bridging (AVB) - license required Simulation Mode C_STATS_WIDTH AXI Stream Tx Clock Freq AXI System ACE Interface Controller(Compact Flash) Interface between the AXI and the Microprocessor Interface (MPU) of the System ACE Compact Flash solution peripheral C_S_AXI_PROTOCOL C_FAMILY C_BASEADDR C_HIGHADDR C_S_AXI_ADDR_WIDTH C_S_AXI_DATA_WIDTH C_MEM_WIDTH Clock Input Active high Interrupt Output Address Input Active LOW Chip Enable Active LOW Output Enable Active LOW Write Enable Data Input/Output