The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the memory type, and where necessary the cacheable and shareable properties of the memory region. The default values for these bits, as configured in our MPU ports, are sometimes not suitable for application. One such example is when the MCU has a cache, the application writer may not want to mark the memory as shareable to avoid disabling the cache. This change allows the application writer to override default vales for TEX, S C and B bits for Flash and RAM in their FreeRTOSConfig.h. The following two new configurations are introduced: - configTEX_S_C_B_FLASH - configTEX_S_C_B_SRAM If undefined, the default values for the above configurations are TEX=000, S=1, C=1, B=1. This ensures backward compatibility. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
773 lines
34 KiB
C
773 lines
34 KiB
C
/*
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* FreeRTOS Kernel V10.3.1
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the ARM CM4F MPU port.
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*----------------------------------------------------------*/
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/* IAR includes. */
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#include <intrinsics.h>
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/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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* all the API functions to use the MPU wrappers. That should only be done when
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* task.h is included from an application file. */
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#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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#ifndef __ARMVFP__
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#error This port can only be used when the project options are configured to enable hardware floating point support.
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#endif
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#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
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#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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#endif
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#ifndef configSYSTICK_CLOCK_HZ
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#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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/* Ensure the SysTick is clocked at the same frequency as the core. */
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#define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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#else
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/* The way the SysTick is clocked is not modified in case it is not the same
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* as the core. */
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#define portNVIC_SYSTICK_CLK_BIT ( 0 )
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#endif
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/* Constants required to manipulate the core. Registers first... */
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#define portNVIC_SYSTICK_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000e010 ) )
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#define portNVIC_SYSTICK_LOAD_REG ( *( ( volatile uint32_t * ) 0xe000e014 ) )
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#define portNVIC_SYSTICK_CURRENT_VALUE_REG ( *( ( volatile uint32_t * ) 0xe000e018 ) )
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#define portNVIC_SHPR3_REG ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
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#define portNVIC_SHPR2_REG ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
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#define portNVIC_SYS_CTRL_STATE_REG ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
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#define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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/* Constants required to access and manipulate the MPU. */
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#define portMPU_TYPE_REG ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
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#define portMPU_REGION_BASE_ADDRESS_REG ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
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#define portMPU_REGION_ATTRIBUTE_REG ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
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#define portMPU_CTRL_REG ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
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#define portEXPECTED_MPU_TYPE_VALUE ( portTOTAL_NUM_REGIONS << 8UL )
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#define portMPU_ENABLE ( 0x01UL )
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#define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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#define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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#define portMPU_REGION_VALID ( 0x10UL )
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#define portMPU_REGION_ENABLE ( 0x01UL )
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#define portPERIPHERALS_START_ADDRESS 0x40000000UL
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#define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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/* ...then bits in the registers. */
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#define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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#define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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#define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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#define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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#define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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* r0p1 port. */
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#define portCPUID ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
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#define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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#define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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#define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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#define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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#define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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/* Constants required to check the validity of an interrupt priority. */
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#define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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#define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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#define portAIRCR_REG ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
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#define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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#define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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#define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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#define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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#define portPRIGROUP_SHIFT ( 8UL )
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/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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#define portVECTACTIVE_MASK ( 0xFFUL )
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/* Constants required to manipulate the VFP. */
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#define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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#define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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/* Constants required to set up the initial stack. */
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#define portINITIAL_XPSR ( 0x01000000 )
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#define portINITIAL_EXC_RETURN ( 0xfffffffd )
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#define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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#define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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/* Offsets in the stack to the parameters when inside the SVC handler. */
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#define portOFFSET_TO_PC ( 6 )
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/* The systick is a 24-bit counter. */
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#define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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/* A fiddle factor to estimate the number of SysTick counts that would have
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* occurred while the SysTick counter is stopped during tickless idle
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* calculations. */
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#define portMISSED_COUNTS_FACTOR ( 45UL )
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/* For strict compliance with the Cortex-M spec the task start address should
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* have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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#define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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/*
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* Configure a number of standard MPU regions that are used by all tasks.
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*/
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static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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/*
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* Return the smallest MPU region size that a given number of bytes will fit
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* into. The region size is returned as the value that should be programmed
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* into the region attribute register for that region.
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*/
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static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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/*
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* Setup the timer to generate the tick interrupts. The implementation in this
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* file is weak to allow application writers to change the timer used to
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* generate the tick interrupt.
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*/
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void vPortSetupTimerInterrupt( void );
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/*
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* Exception handlers.
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*/
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void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
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/*
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* Start first task is a separate function so it can be tested in isolation.
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*/
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extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
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/*
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* Turn the VFP on.
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*/
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extern void vPortEnableVFP( void );
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/*
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* The C portion of the SVC handler.
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*/
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void vPortSVCHandler_C( uint32_t * pulParam );
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/*
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* Called from the SVC handler used to start the scheduler.
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*/
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extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
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/**
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* @brief Calls the port specific code to raise the privilege.
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*
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* @return pdFALSE if privilege was raised, pdTRUE otherwise.
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*/
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extern BaseType_t xPortRaisePrivilege( void );
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/**
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* @brief If xRunningPrivileged is not pdTRUE, calls the port specific
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* code to reset the privilege, otherwise does nothing.
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*/
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extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
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/*-----------------------------------------------------------*/
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/* Each task maintains its own interrupt status in the critical nesting
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* variable. */
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static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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/*
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* Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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* FreeRTOS API functions are not called from interrupts that have been assigned
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* a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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*/
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#if ( configASSERT_DEFINED == 1 )
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static uint8_t ucMaxSysCallPriority = 0;
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static uint32_t ulMaxPRIGROUPValue = 0;
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static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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#endif /* configASSERT_DEFINED */
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
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TaskFunction_t pxCode,
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void * pvParameters,
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BaseType_t xRunPrivileged )
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{
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/* Simulate the stack frame as it would be created by a context switch
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* interrupt. */
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/* Offset added to account for the way the MCU uses the stack on entry/exit
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* of interrupts, and to ensure alignment. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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pxTopOfStack--;
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*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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pxTopOfStack--;
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*pxTopOfStack = ( StackType_t ) 0; /* LR */
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/* Save code space by skipping register initialisation. */
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pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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/* A save method is being used that requires each task to maintain its
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* own exec return value. */
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pxTopOfStack--;
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*pxTopOfStack = portINITIAL_EXC_RETURN;
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pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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if( xRunPrivileged == pdTRUE )
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{
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*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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}
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else
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{
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*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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}
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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void vPortSVCHandler_C( uint32_t * pulParam )
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{
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uint8_t ucSVCNumber;
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uint32_t ulPC;
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#if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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extern uint32_t __syscalls_flash_start__[];
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extern uint32_t __syscalls_flash_end__[];
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#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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/* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
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* argument (r0) is pulParam[ 0 ]. */
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ulPC = pulParam[ portOFFSET_TO_PC ];
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ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
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switch( ucSVCNumber )
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{
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case portSVC_START_SCHEDULER:
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portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
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vPortRestoreContextOfFirstTask();
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break;
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case portSVC_YIELD:
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portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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/* Barriers are normally not required
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* but do ensure the code is completely
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* within the specified behaviour for the
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* architecture. */
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__asm volatile ( "dsb" ::: "memory" );
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__asm volatile ( "isb" );
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break;
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#if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
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case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
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* svc was raised from any of the
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* system calls. */
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if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
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( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
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{
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__asm volatile
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(
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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::: "r1", "memory"
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);
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}
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break;
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#else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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case portSVC_RAISE_PRIVILEGE:
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__asm volatile
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(
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" mrs r1, control \n"/* Obtain current control value. */
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" bic r1, r1, #1 \n"/* Set privilege bit. */
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" msr control, r1 \n"/* Write back new control value. */
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::: "r1", "memory"
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);
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break;
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#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
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default: /* Unknown SVC call. */
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break;
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}
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}
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/*-----------------------------------------------------------*/
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/*
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* See header file for description.
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*/
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BaseType_t xPortStartScheduler( void )
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{
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/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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* See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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/* This port can be used on all revisions of the Cortex-M7 core other than
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* the r0p1 parts. r0p1 parts should use the port from the
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* /source/portable/GCC/ARM_CM7/r0p1 directory. */
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configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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#if ( configASSERT_DEFINED == 1 )
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{
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volatile uint32_t ulOriginalPriority;
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volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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volatile uint8_t ucMaxPriorityValue;
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/* Determine the maximum priority from which ISR safe FreeRTOS API
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* functions can be called. ISR safe functions are those that end in
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* "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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* ensure interrupt entry is as fast and simple as possible.
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*
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* Save the interrupt priority value that is about to be clobbered. */
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ulOriginalPriority = *pucFirstUserPriorityRegister;
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/* Determine the number of priority bits available. First write to all
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* possible bits. */
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*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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/* Read the value back to see how many bits stuck. */
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ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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/* Use the same mask on the maximum system call priority. */
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ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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/* Calculate the maximum acceptable priority group value for the number
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* of bits read back. */
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ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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{
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ulMaxPRIGROUPValue--;
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ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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}
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#ifdef __NVIC_PRIO_BITS
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{
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/* Check the CMSIS configuration that defines the number of
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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}
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#endif
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#ifdef configPRIO_BITS
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{
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/* Check the FreeRTOS configuration that defines the number of
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* priority bits matches the number of priority bits actually queried
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* from the hardware. */
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configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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}
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#endif
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/* Shift the priority group value back to its position within the AIRCR
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* register. */
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ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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/* Restore the clobbered interrupt priority register to its original
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* value. */
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*pucFirstUserPriorityRegister = ulOriginalPriority;
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}
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#endif /* conifgASSERT_DEFINED */
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/* Make PendSV and SysTick the lowest priority interrupts. */
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portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
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portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
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/* Configure the regions in the MPU that are common to all tasks. */
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prvSetupMPU();
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/* Start the timer that generates the tick ISR. Interrupts are disabled
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* here already. */
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vPortSetupTimerInterrupt();
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/* Initialise the critical nesting count ready for the first task. */
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uxCriticalNesting = 0;
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/* Ensure the VFP is enabled - it should be anyway. */
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vPortEnableVFP();
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/* Lazy save always. */
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*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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/* Start the first task. */
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vPortStartFirstTask();
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/* Should not get here! */
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return 0;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
|
|
/* Not implemented in ports where there is nothing to return to.
|
|
* Artificially force an assert. */
|
|
configASSERT( uxCriticalNesting == 1000UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortEnterCritical( void )
|
|
{
|
|
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
|
|
|
|
portDISABLE_INTERRUPTS();
|
|
uxCriticalNesting++;
|
|
|
|
vPortResetPrivilege( xRunningPrivileged );
|
|
|
|
/* This is not the interrupt safe version of the enter critical function so
|
|
* assert() if it is being called from an interrupt context. Only API
|
|
* functions that end in "FromISR" can be used in an interrupt. Only assert if
|
|
* the critical nesting count is 1 to protect against recursive calls if the
|
|
* assert function also uses a critical section. */
|
|
if( uxCriticalNesting == 1 )
|
|
{
|
|
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortExitCritical( void )
|
|
{
|
|
BaseType_t xRunningPrivileged = xPortRaisePrivilege();
|
|
|
|
configASSERT( uxCriticalNesting );
|
|
|
|
uxCriticalNesting--;
|
|
|
|
if( uxCriticalNesting == 0 )
|
|
{
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
|
|
vPortResetPrivilege( xRunningPrivileged );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void xPortSysTickHandler( void )
|
|
{
|
|
/* The SysTick runs at the lowest interrupt priority, so when this interrupt
|
|
* executes all interrupts must be unmasked. There is therefore no need to
|
|
* save and then restore the interrupt mask value as its value is already
|
|
* known. */
|
|
portDISABLE_INTERRUPTS();
|
|
{
|
|
/* Increment the RTOS tick. */
|
|
if( xTaskIncrementTick() != pdFALSE )
|
|
{
|
|
/* A context switch is required. Context switching is performed in
|
|
* the PendSV interrupt. Pend the PendSV interrupt. */
|
|
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
|
|
}
|
|
}
|
|
portENABLE_INTERRUPTS();
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
/*
|
|
* Setup the systick timer to generate the tick interrupts at the required
|
|
* frequency.
|
|
*/
|
|
__weak void vPortSetupTimerInterrupt( void )
|
|
{
|
|
/* Stop and clear the SysTick. */
|
|
portNVIC_SYSTICK_CTRL_REG = 0UL;
|
|
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
|
|
|
|
/* Configure SysTick to interrupt at the requested rate. */
|
|
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
|
|
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static void prvSetupMPU( void )
|
|
{
|
|
extern uint32_t __privileged_functions_start__[];
|
|
extern uint32_t __privileged_functions_end__[];
|
|
extern uint32_t __FLASH_segment_start__[];
|
|
extern uint32_t __FLASH_segment_end__[];
|
|
extern uint32_t __privileged_data_start__[];
|
|
extern uint32_t __privileged_data_end__[];
|
|
|
|
/* The only permitted number of regions are 8 or 16. */
|
|
configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
|
|
|
|
/* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
|
|
configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
|
|
|
|
/* Check the expected MPU is present. */
|
|
if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
|
|
{
|
|
/* First setup the unprivileged flash for unprivileged read only access. */
|
|
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
|
|
( portMPU_REGION_VALID ) |
|
|
( portUNPRIVILEGED_FLASH_REGION );
|
|
|
|
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
|
|
( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
|
|
( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
|
|
( portMPU_REGION_ENABLE );
|
|
|
|
/* Setup the privileged flash for privileged only access. This is where
|
|
* the kernel code is placed. */
|
|
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
|
|
( portMPU_REGION_VALID ) |
|
|
( portPRIVILEGED_FLASH_REGION );
|
|
|
|
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
|
|
( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
|
|
( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
|
|
( portMPU_REGION_ENABLE );
|
|
|
|
/* Setup the privileged data RAM region. This is where the kernel data
|
|
* is placed. */
|
|
portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
|
|
( portMPU_REGION_VALID ) |
|
|
( portPRIVILEGED_RAM_REGION );
|
|
|
|
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
|
|
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
|
|
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
|
|
( portMPU_REGION_ENABLE );
|
|
|
|
/* By default allow everything to access the general peripherals. The
|
|
* system peripherals and registers are protected. */
|
|
portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
|
|
( portMPU_REGION_VALID ) |
|
|
( portGENERAL_PERIPHERALS_REGION );
|
|
|
|
portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
|
|
( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
|
|
( portMPU_REGION_ENABLE );
|
|
|
|
/* Enable the memory fault exception. */
|
|
portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
|
|
|
|
/* Enable the MPU with the background region configured. */
|
|
portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
|
|
{
|
|
uint32_t ulRegionSize, ulReturnValue = 4;
|
|
|
|
/* 32 is the smallest region size, 31 is the largest valid value for
|
|
* ulReturnValue. */
|
|
for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
|
|
{
|
|
if( ulActualSizeInBytes <= ulRegionSize )
|
|
{
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
ulReturnValue++;
|
|
}
|
|
}
|
|
|
|
/* Shift the code by one before returning so it can be written directly
|
|
* into the the correct bit position of the attribute register. */
|
|
return( ulReturnValue << 1UL );
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
|
|
const struct xMEMORY_REGION * const xRegions,
|
|
StackType_t * pxBottomOfStack,
|
|
uint32_t ulStackDepth )
|
|
{
|
|
extern uint32_t __SRAM_segment_start__[];
|
|
extern uint32_t __SRAM_segment_end__[];
|
|
extern uint32_t __privileged_data_start__[];
|
|
extern uint32_t __privileged_data_end__[];
|
|
int32_t lIndex;
|
|
uint32_t ul;
|
|
|
|
if( xRegions == NULL )
|
|
{
|
|
/* No MPU regions are specified so allow access to all RAM. */
|
|
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
|
|
( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
|
|
( portMPU_REGION_VALID ) |
|
|
( portSTACK_REGION );
|
|
|
|
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
|
|
( portMPU_REGION_READ_WRITE ) |
|
|
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
|
|
( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
|
|
( portMPU_REGION_ENABLE );
|
|
|
|
/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
|
|
* just removed the privileged only parameters. */
|
|
xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
|
|
( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
|
|
( portMPU_REGION_VALID ) |
|
|
( portSTACK_REGION + 1 );
|
|
|
|
xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
|
|
( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
|
|
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
|
|
prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
|
|
( portMPU_REGION_ENABLE );
|
|
|
|
/* Invalidate all other regions. */
|
|
for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
|
|
{
|
|
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
|
|
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* This function is called automatically when the task is created - in
|
|
* which case the stack region parameters will be valid. At all other
|
|
* times the stack parameters will not be valid and it is assumed that the
|
|
* stack region has already been configured. */
|
|
if( ulStackDepth > 0 )
|
|
{
|
|
/* Define the region that allows access to the stack. */
|
|
xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
|
|
( ( uint32_t ) pxBottomOfStack ) |
|
|
( portMPU_REGION_VALID ) |
|
|
( portSTACK_REGION ); /* Region number. */
|
|
|
|
xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
|
|
( portMPU_REGION_READ_WRITE ) | /* Read and write. */
|
|
( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
|
|
( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
|
|
( portMPU_REGION_ENABLE );
|
|
}
|
|
|
|
lIndex = 0;
|
|
|
|
for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
|
|
{
|
|
if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
|
|
{
|
|
/* Translate the generic region definition contained in
|
|
* xRegions into the CM4 specific MPU settings that are then
|
|
* stored in xMPUSettings. */
|
|
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
|
|
( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
|
|
( portMPU_REGION_VALID ) |
|
|
( portSTACK_REGION + ul ); /* Region number. */
|
|
|
|
xMPUSettings->xRegion[ ul ].ulRegionAttribute =
|
|
( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
|
|
( xRegions[ lIndex ].ulParameters ) |
|
|
( portMPU_REGION_ENABLE );
|
|
}
|
|
else
|
|
{
|
|
/* Invalidate the region. */
|
|
xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
|
|
xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
|
|
}
|
|
|
|
lIndex++;
|
|
}
|
|
}
|
|
}
|
|
/*-----------------------------------------------------------*/
|
|
|
|
#if ( configASSERT_DEFINED == 1 )
|
|
|
|
void vPortValidateInterruptPriority( void )
|
|
{
|
|
uint32_t ulCurrentInterrupt;
|
|
uint8_t ucCurrentPriority;
|
|
|
|
/* Obtain the number of the currently executing interrupt. */
|
|
__asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
|
|
|
|
/* Is the interrupt number a user defined interrupt? */
|
|
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
|
|
{
|
|
/* Look up the interrupt's priority. */
|
|
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
|
|
|
|
/* The following assertion will fail if a service routine (ISR) for
|
|
* an interrupt that has been assigned a priority above
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
|
|
* function. ISR safe FreeRTOS API functions must *only* be called
|
|
* from interrupts that have been assigned a priority at or below
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* Numerically low interrupt priority numbers represent logically high
|
|
* interrupt priorities, therefore the priority of the interrupt must
|
|
* be set to a value equal to or numerically *higher* than
|
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
|
*
|
|
* Interrupts that use the FreeRTOS API must not be left at their
|
|
* default priority of zero as that is the highest possible priority,
|
|
* which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
|
|
* and therefore also guaranteed to be invalid.
|
|
*
|
|
* FreeRTOS maintains separate thread and ISR API functions to ensure
|
|
* interrupt entry is as fast and simple as possible.
|
|
*
|
|
* The following links provide detailed information:
|
|
* http://www.freertos.org/RTOS-Cortex-M3-M4.html
|
|
* http://www.freertos.org/FAQHelp.html */
|
|
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
|
|
}
|
|
|
|
/* Priority grouping: The interrupt controller (NVIC) allows the bits
|
|
* that define each interrupt's priority to be split between bits that
|
|
* define the interrupt's pre-emption priority bits and bits that define
|
|
* the interrupt's sub-priority. For simplicity all bits must be defined
|
|
* to be pre-emption priority bits. The following assertion will fail if
|
|
* this is not the case (if some bits represent a sub-priority).
|
|
*
|
|
* If the application only uses CMSIS libraries for interrupt
|
|
* configuration then the correct setting can be achieved on all Cortex-M
|
|
* devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
|
|
* scheduler. Note however that some vendor specific peripheral libraries
|
|
* assume a non-zero priority group setting, in which cases using a value
|
|
* of zero will result in unpredictable behaviour. */
|
|
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
|
|
}
|
|
|
|
#endif /* configASSERT_DEFINED */
|
|
/*-----------------------------------------------------------*/
|