287361091b
The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the memory type, and where necessary the cacheable and shareable properties of the memory region. The default values for these bits, as configured in our MPU ports, are sometimes not suitable for application. One such example is when the MCU has a cache, the application writer may not want to mark the memory as shareable to avoid disabling the cache. This change allows the application writer to override default vales for TEX, S C and B bits for Flash and RAM in their FreeRTOSConfig.h. The following two new configurations are introduced: - configTEX_S_C_B_FLASH - configTEX_S_C_B_SRAM If undefined, the default values for the above configurations are TEX=000, S=1, C=1, B=1. This ensures backward compatibility. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> |
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| .. | ||
| 78K0R | ||
| ARM_CA5_No_GIC | ||
| ARM_CA9 | ||
| ARM_CM0 | ||
| ARM_CM3 | ||
| ARM_CM4F | ||
| ARM_CM4F_MPU | ||
| ARM_CM7 | ||
| ARM_CM23 | ||
| ARM_CM23_NTZ/non_secure | ||
| ARM_CM33 | ||
| ARM_CM33_NTZ/non_secure | ||
| ARM_CRx_No_GIC | ||
| ATMega323 | ||
| AtmelSAM7S64 | ||
| AtmelSAM9XE | ||
| AVR32_UC3 | ||
| AVR_AVRDx | ||
| AVR_Mega0 | ||
| LPC2000 | ||
| MSP430 | ||
| MSP430X | ||
| RISC-V | ||
| RL78 | ||
| RX100 | ||
| RX600 | ||
| RXv2 | ||
| STR71x | ||
| STR75x | ||
| STR91x | ||
| V850ES | ||